Varilog lab#1

AO221 Program:

module AO221(f,a,b,c,d,e);

input a,b,c,d,e;

output f;

wire w1,w2;

and g1(w1,a,b);

and g2(w2,c,d);

or g3(w1,w2);

endmodule

module stimulus();

wire W1,W2;

reg A,B,C,D,E;

AO221 my_circuit (F,A,B,C,D,E);

initial begin

$monitor ("F=%b A=%b B=%b C=%b D=%b E=%b",F,A,B,C,D,E );

end

endmodule

Output
 Varilog lab#2

Half adder Program:

module half_adder (s,c,a,b);

input a,b;

output c,s;

xor g1 (s,a,b);

and g2 (c,a,b);

endmodule

module stimulus ();

reg A,B;

wire C,S;

half_adder EE8 (S,C,A,B);

initial begin

A=1'b0; //here 1 is for assigning single bit in registor and 0 is the value

B=1'b1; //here 1 is for assigning single bit in registor and 1 is the value

$monitor("half adder ckt: A=%b, B=%b, S=%b, C=%b",A,B,S,C);

end

endmodule
\Output:

Full adder Program:

module Full_adder (s,cout,cin,a,b);

input a,b,cin;

output cout,s, w1,w2,w3;

xor g1 (w1,a,b);

and g2 (w2,a,b);

and g3 (w3,cin,w1);

xor g4 (s,w1,cin);

or (cout,w2,w3);

endmodule

module stimulus ();

reg A,B,Cin;
wire Cout,S,W1,W2,W3;

Full_adder EE8 (S,Cout,Cin,A,B);

initial begin

A=1'b0; //here 1 is for assigning single bit in registor and 0 is the value

B=1'b1; //here 1 is for assigning single bit in registor and 1 is the value

Cin=1'b1;

$monitor("Full adder ckt: A=%b, B=%b,Cin=%b, S=%b, Cout=%b",A,B,Cin,S,Cout);

end

endmodule

Output:

With 4 bits
module Full_adder (s,cout,cin,a,b);

input a,b,cin;

output cout,s, w1,w2,w3;

xor g1 (w1,a,b);

and g2 (w2,a,b);

and g3 (w3,cin,w1);

xor g4 (s,w1,cin);

or (cout,w2,w3);

endmodule

module stimulus ();

reg [3:0] A,B;

reg Cin;

wire [3:0] S,W1,W2,W3;

wire cout;

Full_adder EE8 (S,Cout,Cin,A,B);

initial begin

A=4'b0011; //here 1 is for assigning single bit in registor and 0 is the value

B=4'b1111; //here 1 is for assigning single bit in registor and 1 is the value

Cin=1'b1;

$monitor("Full adder ckt: A=%b, B=%b,Cin=%b, S=%b, Cout=%b",A,B,Cin,S,Cout);

end

endmodule
output: