Balochistan University of Information Technology, Engineering and

Management Sciences

VLSI DESIGN
Laboratory Manual
___________________________________
Prepared By
Engr. Umer Iftikhar Mir

umer.iftikhar@buitms.edu.pk

Supervised By
Dr. Yousuf Khan

yousuf.khan@buitms.edu.pk

Submitted by
Student Name Ikramullah Khan
CMS ID 29450
Program Electronic Engineering

Signature

DEPARTMENT OF ELECTRONIC ENGINEERING

FACULTY OF INFORMATION AND COMMUNICATION TECHNOLOGY
BALOCHISTAN UNIVERSITY OF INFORMATION TECHNOLOGY ENGINEERING AND MANAGEMENT SCIENCES
 LAB #1: Introduction to DSCH and Microwind with the design of CMOS
inverter

Objective

Part 1

In this lab students will be introduced to a schematic based Electronic Design Automation (EDA) tool
“DSCH” and the introduction will be accompanied with an implementation of simple Gate at Gate level.
The tool used in this lab is DSCH.

The goals for this Lab are:

 Familiarity and Hands on Example using the tool.

 Gate Level Design using the tool.
 Design Verification.
 Simulation of the design instill
Part 2

In this lab students will be introduced to a Layout based EDA tool “Microwind” and the introduction will
be accompanied with analysis of MOS transistors. The tool used in this lab is Microwind. The goals for
this Lab are:

 Familiarity and Hands on Example using the tool.

 Layout Design using the tool.
 Study of MOSFET Characteristics.
 Analog Simulation of MOSFETs.
Pre-Lab

A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-
down network (PDN) (Figure 1). The figure shows a generic N input logic gate where all inputs are
distributed to both the pull-up and pull-down networks. The function of the PUN is to provide a
connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on
the inputs). Similarly, the function of the PDN is to connect the output to VSS when the output of the
logic gate is meant to be 0. The PUN and PDN networks are constructed in a mutually exclusive fashion
such that one and only one of the networks is conducting in steady state.

In this way, once the transients have settled, a path always exists between VDD and the output F,
realizing a high output (“one”), or, alternatively, between VSS and F for a low output (“zero”). This is
equivalent to stating that the output node is always a low-impedance node in steady state. In this section,
you will learn how to design an inverter using complementary CMOS family in DSCH and Microwind
softwares.
The Inverter

An Inverter can be implemented using two MOSFETS i.e. one PMOS and one NMOS. Both MOSFETS
are connected as shown in figure. VDD is supplied to PMOS while the NMOS is grounded. Input is
applied to the gate terminals of MOSFETs, and the output “F” is obtained from common junctions as
illustrated in the Inverter Circuit:

Inputs Output

A B

0 1
1 0

Table 1 Truth Table of Inverter

Figure 1 Transistor Level Inverter

In-Lab

Part A

The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the logic
circuit before the microelectronics design is started. DSCH provides a user-friendly environment for
hierarchical logic design, and simulation with delay analysis, which allows the design and validation of
complex logic structures. A key innovative feature is the possibility to estimate the power consumption of
the circuit.
Implement the function of inverter x= x’ by using NMOS and PMOS and then implement it on
DSCH.

1. Turn on your PC and click on the DSCH icon.

2. DSCH will bring up two windows-the schematic drawing board and the symbol library.
3. The drawing board should be blank. The symbol library window presents you with choices for
using predefined devices, such as basic gates, MOSFETS, LED and buttons.
 Icon Description
Cut
Copy
Move
Rotate to Left
Rotate to Right
Flip
Add text
Add a line
Add a connector between lines
Run Simulation
Timing diagram
Actual Size
Zoom In
Zoom Out
View electrical net
View symbol library

Table 2 DSCH Symbols

4. To select the foundry, use the command File > Select Foundry.

Figure 2 Select Foundry Window

5. We will be using 0.25-micron process. For this, we will be selecting “cmos025.tec” file.

Figure 3 Select Foundry File

6. To create a new schematic. Delete the existing diagram (if any) by selecting the Cut command
button from the icon menu bar and then select the whole diagram.
7. Choose the NMOS AND PMOS from the symbol library and arrange it as given in point.

Figure 4 Symbol Library

Figure 5 Schematic of Inverter

Figure 6 Timing Diagram of Inverter

Part B

Main screen of Microwind

Figure 7 Microwind Mainscreen

Icon Description
Cut

Copy Element

Stretch and move

View All

View electrical node

Measure Distance

Add text

2-D Vertical cross section

Process 3-D step

Design rule checker

Connect layers

Simulate MOS characteristics

Run Simulation

Timing diagram

Zoom In

Zoom Out

View electrical node

Show Palette

Table 3 Microwind Symbol Details

To select the foundry using the command File > Select Foundry

Figure 8 Select Foundry Window

We will be using 0.25-micron process by selecting “cmos025.tec” file. Click Open tab to continue.

Figure 9 Foundry Selection in Microwind

To create an nMOS by using the nMOS generator button in the Palate

Figure 10 Layout Generator

You can set the width and length of MOS by typing in the fields Width MOS and Length MOS either in
micron or in lambda units as indicated in the above figure.

Figure 11 NMOS Signal in Microwind

Apply the voltages and output node using the symbol buttons VDD, Gnd, Add a Pulse, and Visible node in
the Palate menu, as indicated in the following figure. You can use the Stretch/Move command button for
these actions.

Now apply the VDD to the n+ diffusion or drain terminal instead of Vss, run the Simulation again

Figure 12 Applying Potential to NMOS

 Figure 13 Analysis of NMOS in Microwind

Tasks

(a) Design the CMOS inverter in Microwind using 0.25um CMOS technology
(b) Show the timing diagram.

CMOS Inverter Layout:

Figure: CMOS inverter Layout in Micro wind using 0.25um CMOS technology
Timing Diagram:

Figure: CMOS inverter timing diagram in Micro wind using 0.25um CMOS technology

Post Lab

Performance Viva
Total/15
(12 Marks) (3 Marks)

Performance /2

Results /2

Pre-Lab /2

In Lab /2

Lab Report /4
Comments