Mixed-Signal ASIC Design for Digital RF Memory

Applications

Michael J. Groden James R. Mann

LNX Corporation Mann VLSI Research
8B Industrial Way Hudson NH 03079
Salem NH 03079 1 603-594-8668
1 603-898-6800 jmann@mannvlsi.com
mikeg@lnxcorp.com

ABSTRACT (see Figure 1). Filters (not shown) remove unwanted mixer
Mixed Signal ASIC Design for Digital RF Memory Applications products and band-limit the signal before sampling by analog
comparators.

Categories and Subject Descriptors Fast Tuning

Analog Design – Mixed Signal Design, Military Synthesizer

General Terms I
A Digital D I
ASIC, Mixed Signal, DRFM, Digital Receivers, Algorithms, D A
DSP, Electronic Design Automation RF
Processor RF
C C
Input Q Q Output
Keywords
Algorithms, ASIC, DSP, DRFM, Digital Receivers, Electronic Memory FPGA
Design Automation, Electronic Warfare, Signal Processors Controller DSP

Introduction
Digital RF Memories (DRFM) are used for the reproduction of
complex, coherent signals usually associated with modern pulse
compression radars. They replace historical techniques allowing Figure 1 Block diagram of a double sideband Digital RF
the digital storage and reproduction of detected radar signals. Memory.
Other applications include SIGINT operations, deception of
covert communications, simulators, and test equipment. A block
diagram of a typical DRFM system appears in Figure 1. The signal of interest can be represented as a rotating vector
whose components are represented by the in phase and quadrature
There are many different implementations of DRFM systems.
outputs (Figure 2). The phase is measured by comparing the
They include amplitude sampled systems, single sideband
relative amplitudes of the in phase (I) and quadrature (Q)
systems, dual sideband systems, and phase sampled systems.
components. This information is sampled and stored and/or
Significant features include the instantaneous bandwidth,
delayed and reproduced; in radar jamming applications, the
resolution, spurious response, and the external memory interface.
delayed waveform causes the transmitting radar to place the target
The design described here is for a double sideband, 4-bit, phase
at the wrong location. The DRFM can also add noise or generate
sampled system with 500 MHz of instantaneous bandwidth.
other signals typically found in an EW environment. Signals
A custom mixed signal ASIC was designed and fabricated in 0.18 from multiple radars may need to be recorded and stored, and the
micron CMOS, that implements the baseband component of the phase coherency of each signal must be maintained.
system including the phase-sampling circuit, digital processing,
LNX DRFM ASIC Design
signal reconstruction and digital to analog outputs. This paper
describes the design of the mixed-signal ASIC, some of the A block diagram of the LNX DRFM ASIC appears in Figure 3. A
challenges faced, and results from the fabricated device. pre-amplifier stage amplifies, buffers, and level shifts the input to
facilitate the interface to the digital logic circuitry. Input
Phase Sampled Double Sideband DRFM
bandwidth is 250 MHz providing 500 MHz of instantaneous
In a phase sampled DRFM system, the detected RF pulse is first bandwidth using the I and Q inputs. High speed comparators are
down converted to a convenient IF. Amplitude information is used to sample the I and Q inputs at up to 640 MHz; a look-up
removed with a limiting amplifier and quadrature down converted table is used for error correction and encoding into a 4-bit phase
to baseband, generating both in phase and quadrature components value representing 22.5 degrees of resolution. Data is then stored
for processing or playback. The signal is reconstructed using the
phase data and sine/cosine look-up tables. Further information on
implementing phase-sampled DRFM systems can be found in the
literature [1].
Q Q
s(t)
θ I
Figure 2 Amplitude limited signal can be represented as a
rotating vector with in phase and quadrature components.
After encoding, the data enters a demultiplexing block where it is
distributed over a 20-bit bus that runs at one quarter the sample
rate, facilitating storage in an external memory. Alternatively, the
data is fed to the next delay line block. The delay line block
implements two functions; it can either delay the digitized signal
in fixed increments or it can re-circulate the data for head to tail
reconstruction. Head to tail reconstruction or recirculation allows
a CW signal to be replayed with the correct phase and frequency
characteristics of the recorded signal. The minimum throughput
time with no delay is < 25 nsecs.
The external memory interface operates at 160 MHz and performs
the demultiplexing for data storage and playback. Full duplex
operation allows signals to be sampled and stored simultaneous
with the playback and transmission of a previously stored signal.
Data signal levels are 3.3V CMOS, the clocks are differential
LVDS. The ASIC supplies all of the timing and control for
external storage. An external memory, FPGA or DSP processing
system can be used to store and/or process the recorded
waveforms.
The ASIC contains all of the timing necessary to maintain phase
coherency for signals that are re-circulated. Timing is also
provided to external circuitry to maintain the coherence of
recorded signals. The timing circuitry can also be used for Range
Gate Pull Off (RGPO) in radar jamming applications. In this
scenario, the jammer can “walk” the range gate of the radar off
the target [1].
There are other auxiliary circuits such as a pseudo-random noise
generator and frequency measurement function. The PN noise
generator can be used to add pseudo-random noise to the output
signal. The frequency measurement block can measure the
frequency of the input signal with up to 10-bit accuracy using
accumulated delta phase measurements; the resolution of the
frequency measurement can be automatically adjusted depending
on pulse length.
Re-circulate
A/D D/A
Correction D
Mux
Network E I
I &
& M
Pipe- Q
Encoding U line Coding
X
Timing
&
Control
160
MHz
20-bit
Detection External Memory
Interface
Figure 3 Simplified block diagram of the LNX DRFM ASIC.
A microprocessor interface is provided for configuration and test.
For example, data can be written to, or read from the external
memory interface from the microprocessor bus. Status and
control registers are also provided.
The back-end of the ASIC implements a quadrature modulator.
Independent sine/cosine look-up tables convert the 4-bit phase
values to sine/cosine outputs. Two on-board digital to analog
converters convert the look-up table outputs to analog outputs for
signal reconstruction and up conversion. The update rate of the
D/A is 640 MHz, consistent with the sampling rate and is capable
of driving +/- 0.5 volts into 50 ohms.
Mixed Signal Design Challenges
As described, the mixed-signal ASIC included the preamplifiers,
phase measurement circuitry including high-speed comparators,
high speed digital logic, and the digital to analog converter.
Different technologies were evaluated for implementation,
including SiGe and submicron CMOS technologies like TSMC’s
0.18 micron mixed-signal/RF process. It was determined through
some preliminary numerical simulations that the 0.18 micron
CMOS process could meet the speed requirements. TSMC’s 0.18
micron CMOS process is thoroughly established, well
characterized, and sure to be available for a considerable time to
come. These were important factors for this implementation
however it did present some unique challenges.
One of the challenges was achieving the wide bandwidth and high
accuracy in the preamplifier chain. A 250 MHz full power
bandwidth was required and the inputs needed to be DC coupled
to provide full frequency coverage on the I and Q inputs.
Sampling at 640 MHz required the comparators to have a
response time of less than 1.6 nanoseconds.
The 0.18 micron process supports a maximum supply voltage of
1.8 V for the high speed, small geometry transistors. This
complicated the design of the analog circuits that needed to
handle signals up to +/- 450 millivolts. In addition the system
required +3.3V CMOS and LVDS I/Os so an architectural
decision was made to level shift the analog input signals to a
common mode voltage of 0.9V internally and run all of the high
speed analog and digital circuitry at +1.8 volts.
An additional challenge was meeting the 640 MHz clock speed
using a standard cell design. Differential, current mode logic was
considered, however a standard cell design reduced the
requirement to design custom logic cells and allowed traditional generated from the look-up table. The performance of the state
synthesis and place and route tools to be used. machines was significantly enhanced by carefully selecting
default conditions and explicitly defining transitions between
Design Approach states.
The analog I/O was implemented using custom designed cells.
Even given these steps, the initial design did not meet
The preamplifier design consisted of a differential amplifier stage
performance goals, so two enhancements were made to the
followed by a common source amplifier. This stage provided a
standard cell library. First, cell geometries were increased to
constant 2 dB of gain out to 250 MHz when connected with
improve the drive strength of the cells minimizing wire delays.
feedback (see Fig. 9). The gain setting was limited by the
Second, a new flip-flop design was implemented (see Figure 5)
dynamic range of the input and the maximum allowed signal
[3]. The new flip-flop design was almost twice as fast as the
within the +1.8 volt chip. The differential input stage was also
original standard cell. These two enhancements boosted the
used to level shift the inputs.
overall performance of the design by almost a factor of two.
The high-speed comparator design was implemented using a
wide-range constant-gm preamplifier followed by a low-power,
low-voltage track and latch comparator (see Figure 4) [2]. This
was in turn followed by a transparent latch providing a stable
output level for both clock phases.

The structure of the digital to analog converter is known as a

Figure 4 Low voltage, low power latching comparator.

single-valued-current DAC and operates by each bit steering a
constant current through a resistor ladder network. Cross-coupled
NAND gates on each digital input guarantees that the current
steering signals do not overlap in a break before make fashion.
This reduces switching noise in the D/A. The output of the D/A
is driven through a source follower, capable of driving a 50 ohm
load.
The digital design was captured in VHDL using Mentor Graphics
HDL design tools. It was designed in VHDL for portability and
to facilitate system level simulation. The HDL Designer tools
allow the design to be capture graphically; the tool automatically
generates the VHDL. The design was then synthesized and
placed and routed using standard cells.
In order to meet the performance goals, the architecture of the
system was designed to minimize logic levels and maximize
performance. For example, the data flow and register placement
were analyzed to minimize logic levels. The state machines were
implemented using one-hot encoding; this technique traded speed
for the number of registers required to encode the states. The
VHDL generated by the tool and timing reports were analyzed for
high speed performance; in many cases the graphical design was
modified to enhance the generation of the VHDL. For example,
in some cases, describing a look up table as gates generated fewer
levels of logic and fewer gates, than the VHDL automatically
Figure 5 Sense-amp flip-flop was significant faster.
Each of the major blocks were synthesized, placed, routed, and
then simulated with SPICE to verify the performance of the
individual blocks. These blocks were then placed based on a chip
floor plan and the relationship between the digital blocks and the
analog blocks. The analog cells are placed along one side of the
device with separate power and ground connections. The digital
blocks are placed in the center (see Figure 6).
Clock Distribution
The digital design is fully synchronous; however a critical aspect
of any high speed digital design is clock distribution. This was
further complicated by the block place and route approach
chosen. One common approach to clock distribution is an RC
matched tree assuring that all clock paths have the exact same
delay. This must take into account the resistance and capacitance
of the wire, the delays from the clock buffers, and the number of
loads on each buffer.
 the layout of the cells themselves to minimize DC offset effects,
performance was affected by the chip level layout including input
and ground connections. The parasitic extractions used for post
layout SPICE simulations only included parasitic capacitance, not
resistance.

Figure 6 Layout of DRFM ASIC with the analog cells

on the left side and digital blocks with clock
distribution grid in the center. Figure 8 Prototype Digital RF Memory Chip designed by
LNX Corporation.

A simpler and equally effective approach is to use a clock grid

driven from two sides by a large distributed clock buffer (Figure
7) [3] incurring some additional cost in power. The grid appears
as a large, low resistance, high capacitance load with minimal
skew across the grid. Using the grid approach, connections are
made directly from each cell or sub-cell to the grid.
DC Amplifier Analysis
Figure 9 shows the basic topology and ideal equations that govern
the operation of the preamplifier circuit.

Figure 7 Clock distribution grid and distributed buffers.

The final design was verified over process, voltage, and

temperature using a “fast” SPICE simulation engine. This
allowed full mixed-signal spice simulation of the chip for final
verification.
Figure 9 Ideal Differencing Amplifier.
Prototype Chip Test Results
A prototype chip was fabricated to verify the performance of the
new analog circuits (see Figure 8). DC performance of the pre-
amplifier and comparator chain was degraded due to layout In our specific case, the voltage V2 is set at 0.9 V by an internal
considerations. Although careful consideration had been given to voltage reference generator circuit. The preamplifier V1 is the “I”
(or Q) input. By correctly setting the resistor values, the input delay is only 23.7 nsecs. Plot includes internal test points and
signal’s common mode level can be shifted to the reference external memory outputs.
voltage at the output of the preamplifier.
A study of the actual physical implementation showed a
significant amount of parasitic resistance between the input pin (I
or Q in) and the V1 pin of the Pre-Amplifier. In addition, the
parasitic resistance between R4 and “ground” was also
significant. It was both the significant value (relative to the
absolute values of R1-R4) as well as the (significant) difference
between the parasitic values that caused the offset voltage errors.
A simple analysis and SPICE simulations showed that using the
estimated parasitic resistance values (hand measured from the
layout), that we would expect to see an offset of 25-50mV (at the
output). This value corresponded well to the measured values.
Another issue uncovered was higher than expected ringing in the
D/A converter output due to higher than expected parasitic
inductance in the bond wires and package. Both issues were
addressed in a full-chip design fabricated in the spring of 2004.
Full-Chip Fabrication and Test
A new design was submitted for fabrication in February of 2004
(the layout appears in Figure 5). Characterization of the new chip
is still being performed, but performance has met or exceeded all
requirements. Significant characteristics of the new chip include:
Figure 11 Simulation of inphase and quadrature inputs
Input Offset < 5 Millivolts and D/A outputs for 100 nsec pulse, 25 MHz modulation.
Input Bandwidth - > 250 MHz
Clock Frequency - > 700 MHz Conclusion
Figure 10 shows signal reconstruction and playback of a 2 MHz LNX has developed a mixed-signal ASIC for Digital RF Memory
input signal sampled at 730 MHz. The device is operating in re- applications. The device includes preamplifiers, phase sampling,
circulate mode where a sampled pulse is being reconstructed in a an external memory interface, and signal reconstruction.
head to tail fashion, with no phase discontinuity. Implemented in 0.18 micron CMOS, the instantaneous input
bandwidth exceeds 500 MHz and phase data is sampled at 640
MHz. The ASIC includes all of the timing and control for phase
coherent external data storage and signal reconstruction, signal
delay and recirculation, pseudo-random noise generation, and
frequency measurement. The architecture of the device has been
described as it applies to DRFM applications, challenges faced in
the design of the chip, and test results.
Acknowledgements
The author would like to acknowledge Geoff Dawe, and Stefano
Tanzini for their efforts in the design of the ASIC and their
contributions to this paper.
References
[1] P.E. Pace, Advanced Techniques for Digital Receivers, Artech
House, Inc. Norwood, MA, 2000.
[2] C.J.B. Fayomi, G.W. Roberts & M Sawan, Low-Power/Low-
Voltage High Speed CMOS Differential Comparator with Rail-to-
Rail Input, 2000 IEEE ISCAS, v. 5, pg. 28-31, May 2000.
Figure 10 Reconstruction of a 2 MHz signal sampled at [3] V.G. Oklobdzija, V.M. Stojanovic, D.M. Markovic & N.M.
730 MHz in re-circulate mode. Nedovic, Digital System Clocking: High-Performance and Low-
Power Aspects, pg. 40, John Wiley & Sons, Inc. Hoboken, NJ,
2003.
Figure 11 shows a simulation of a 100 nanosecond pulse with 25
MHz modulation. The D/A outputs demonstrate re-circulation, or
head to tail reconstruction with phase coherency. Throughput