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47
F1
library ieee;
use ieee.std_legic_1164.all;
ENTITV problena IS
PORT(
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
END problena;
F2
library ieee;
use ieee.std_logic_1164.all;
EHTITY problemA IS
PORT(
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
END problemaA;
PROBLEMA 4.38
library ieee;
use ieee.std_logic_1164.all;
entity problema1 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema1;
PROBLEMA 4.39
library ieee;
use ieee.std_logic_1164.all;
entity problema2 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema2;
library ieee;
use ieee.std_logic_1164.all;
entity problema3 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema3;
PROBLEMA 4.41
library ieee;
use ieee.std_logic_1164.all;
entity problema4 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema4;
library ieee;
use ieee.std_logic_1164.all;
use work.fulladd.package.all;
entity CircuitComp is
port (
x,y : in std_logic.vector (3 downto 0);
v,n,z : out std_logic);
end CircuitComp;
F1
library ieee;
use ieee.std_legic_1164.all;
entity problema5 is
port (x1,x2,x3,x4 : in std_logic;
f : out std_logic};
end problema5;
F2
library ieee;
use ieee.std_logic_1164.all;
entity problem6 is
port (x1,x2,x3,x4 : in std_logic;
f2 : out std_logic);
end problem6;