772 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.

4, APRIL 2010

Subcircuit Compact Model for Dopant-Segregated

Schottky Gate-All-Around Si-Nanowire MOSFETs
Guojun Zhu, Student Member, IEEE, Xing Zhou, Senior Member, IEEE, Yoke-King Chin,
Kin Leong Pey, Senior Member, IEEE, Junbin Zhang, Guan Huei See,
Shihuan Lin, Yafei Yan, and Zuhui Chen, Member, IEEE

Abstract—In this paper, we demonstrate analytical device mod-

els and a unique subcircuit approach to physically and accurately
model the dopant-segregated Schottky (DSS) gate-all-around
(GAA) Si-nanowire (SiNW) MOSFETs. The direct current char-
acteristics of the DSS GAA SiNW MOSFETs are investigated
through numerical simulations and fabricated devices. Transport
mechanisms are studied and explained with numerical devices
from ambipolar thermionic tunneling to unipolar drift–diffusion
and a combination of both as the dopant segregation doping
and thickness are varied. The convex curvature in the Ids –Vds
characteristics is accurately reproduced by the subcircuit compact
model, and it is shown for the first time that such a unique gds –Vds
characteristic in DSS devices is only feasible to be modeled by the
subcircuit approach.
Fig. 1. Schematic of an ideal DSS GAA SiNW MOSFET: cross sections (left)
Index Terms—Ambipolar, compact model, dopant-segregated along S/D and (upper right) along radial. The n-channel DSS subcircuit model
Schottky (DSS), drift–diffusion (DD), gate-all-around (GAA), is shown in the lower right side. The nominal device parameters are Lg =
gate-induced drain leakage (GIDL), MOSFET, Schottky barrier 100 nm, R = 10 nm, Tox = 2 nm, Nseg = 1020 cm−3 , and Lseg = 10 nm,
(SB), subcircuit, thermionic tunneling (TT), unipolar. which are the default physical parameters values, unless otherwise stated. The
work function ΦM at S/D is 4.7 eV, corresponding to a barrier height ΦB of
0.53 eV for electrons.
I. I NTRODUCTION
terparts, and the OFF-state leakage current is larger due to
A S CONVENTIONAL bulk MOSFETs are approaching
the end of the technology roadmap, various alternatives
are being explored. MOSFETs with Schottky barrier (SB)
hole injection from the drain-side SB junction. To improve
the performance of SB MOSFETs, various methods have been
proposed, e.g., the use of thin interfacial layers [8], [9] or
source/drain (S/D) are viewed as very promising candidates due
group VI valence-mending adsorbates [10]–[14] and dopant
to their low parasitic S/D resistance and superior scalability [1],
segregation (DS) techniques [15]–[25], among which the
with additional advantages such as low thermal budget since
DS technique is most widely used.
metal silicides are formed at low temperatures and the high-
The concept of DS technique, which employs a very thin
temperature activation of S/D dopants is eliminated. In recent
but high dopant concentration layer at the metal/Si interface,
years, SB MOSFETs with various kinds of structures have been
is shown in Fig. 1. In this paper, we assume that the S/D is
fabricated, e.g., SB silicon-on-insulator (SOI) [2], SB-FinFET
perfectly aligned with the gate without any overlap/underlap.
[3], and SB Si-nanowire (SiNW) MOSFETs [4]–[7]. However,
Experimental studies [22] have shown that the DS changes the
due to the existence of the SB at the S/D junctions, the ON-state
leakage mechanism from SB tunneling (SBT) to gate-induced
current of SB MOSFETs is lower than its conventional coun-
drain leakage (GIDL) current due to band-to-band tunneling
(BTBT); at the same time, the ON-state transport changes from
Manuscript received September 21, 2009; revised January 4, 2010. First the ambipolar thermionic tunneling (TT) current to the unipo-
published February 22, 2010; current version published April 2, 2010. This lar drift–diffusion (DD) current. From numerical simulations,
work was supported in part by the Institute for Sustainable Nanoelectronics,
Nanyang Technological University, and in part by Semiconductor Research
we find that the characteristics of dopant-segregated Schottky
Corporation under Contract 2004-VJ-1166G. The review of this paper was (DSS) MOSFETs are very sensitive to the physical parameters
arranged by Editor M. Reed. such as the length and dopant concentration in the segregation
G. Zhu, X. Zhou, Y.-K. Chin, K. L. Pey, J. Zhang, S. Lin,
Y. Yan, and Z. Chen are with the School of Electrical and Electronic region. Carrier transport could be DD or TT dominant, or a
Engineering, Nanyang Technological University, Singapore 639798 (e-mail: combination of both, which depends on the DS-related parame-
zhug0002@ntu.edu.sg; exzhou@ntu.edu.sg; chin0102@ntu.edu.sg; eklpey@ ters. For either DD- or TT-dominant carrier transport, compact
ntu.edu.sg; e070054@ntu.edu.sg; lins0026@ntu.edu.sg; yanyf@ntu.edu.sg;
zhchen@ntu.edu.sg). models have been developed, respectively, by the authors to
G. H. See is with GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore fully characterize the corresponding devices [26], [27]. For
738406 (e-mail: seegh@globalfoundries.com). DSS devices whose carrier transport is coupled with both DD
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. and TT mechanisms, formulation of analytical device models
Digital Object Identifier 10.1109/TED.2010.2041513 is nontrivial. Analytical formulations to solve the coupled
0018-9383/$26.00 © 2010 IEEE
ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 773

Fig. 2. Measured Ids –Vgs characteristics of both SB (triangles) and DSS

(circles) SiNW MOSFETs at (solid) Vds = −0.05 V and (open) −1 V. The
inset shows the p-channel DSS subcircuit model conceptualized as a Schottky
diode in conjunction with the intrinsic Si channel MOSFET and a resistor at the
drain end.

equations were shown in [28] to model the SB MOSFET, which

is only possible when very simple equations are used, and
therefore, it is not able to include major short-channel effects.
Moreover, for SB MOSFETs, the carrier transport is dominated
by TT, and the DD inside the channel actually plays a neg-
ligible role.
In this paper, the characteristics of DSS gate-all-around
(GAA) SiNW MOSFETs are first investigated through 2-D nu-
merical simulations and fabricated devices. For devices whose
carrier transport involves both DD and TT mechanisms, we
demonstrate analytical device models and a unique subcircuit
approach, which shows very good agreement with both numer-
ical simulations and experimental data and is able to accurately
reproduce the convex curvature in the Ids –Vds characteristics Fig. 3. Extracted energy-band diagrams from Medici simulations for
[29]. There is no attempt to calibrate Medici to match experi- (a) conventional MOSFET, (b) SB MOSFET, and (c) DSS MOSFET at various
Vgs from −0.4 to 2 V with a step of 0.2 V and Vds = 1.2 V. The subcircuit
mental device characteristics. components for each structure are indicated by the corresponding subcircuit
symbols.

II. D EVICE FABRICATION AND N UMERICAL S IMULATION
Experimental DSS SiNW MOSFETs have been fabricated
on 200-mm p-type (100) SOI wafers. The detailed fabrication
process has been reported in [30]. A sample result for the
p-channel DSS device (with BF2 implant at 1 × 1015 cm−2
dose and 10 keV energy for the DS layer) and the SB device
(without BF2 implant) is shown in Fig. 2 [29], which shows that
DSS devices have superior performance. Due to the existence
of the SB at S/D sides, SB MOSFETs suffer from low ON-state
current and high OFF-state leakage current. With ultrathin DS,
the carrier transport demonstrates DD-like behaviors, and the
leakage current becomes GIDL-like.
Recently, we have used pulsed excimer laser anneal (ELA),
prior to silicidation, to achieve diffusion-less activation and
improved segregation as an approach to further reduce the
effective Schottky barrier height (SBH) in GAA DSS SiNW
transistors [31]. ELA-DSS MOSFETs outperform DSS coun-
terparts in both drive currents and short-channel effects.
Three numerical GAA n-channel MOSFETs (with the nom-
inal parameters shown in Fig. 1) are simulated by Medici,
each representing the conventional, SB, and DSS MOSFET,
respectively. Energy-band diagrams (from the intrinsic band
at the SiNW surface from source to drain) are extracted for
gate voltages ranging from −0.4 to 2 V (with a 0.2-V step), as
shown in Fig. 3. From the potential profiles across the channel,
transport mechanisms for each device can be identified. For the
p-n junction S/D MOSFET in Fig. 3(a), conventional diffusion
and drift currents at low and high gate biases, respectively, are
apparent from the potential gradients. For the SB MOSFET
without DS in Fig. 3(b), the potential distributions inside the
channel are very flat for all gate biases, indicating no drift cur-
rent, and the carrier transport is dominated by TT current. For
the DSS MOSFET in Fig. 3(c), the channel potential profiles are
similar to conventional DD counterparts while carrier injection
into the channel from the source is obviously due to TT, similar
to the SB counterpart. The drain side, however, is different from
that in Fig. 3(b) without hole injection from the SB, which can
be modeled by a resistor (Rd ) as a first-order approximation.
It may have BTBT due to the high gate field in the drain-side
DS region, which is modeled by the GIDL current.
III. M ODEL F ORMULATION
The DSS device has two types, namely, n-channel and
p-channel, depending on the type of dopant in the DS layer.
774 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

For model formulations, we follow the nMOS convention, B. Schottky Diode Model
and pMOS equations can be readily available by terminal-
The Schottky diode at the source end, which plays a very
bias polarity changes. The n-channel DSS MOSFET can be
important role in DSS MOSFETs, must be physically modeled.
conceptually separated into three components, namely, a gated
The diode current consists of both thermionic (Ith ) and tunnel-
Schottky diode (GSD) at the source junction whose anode
ing (Itun ) currents.
potential (Vs ) is dependent on the gate voltage Vg , an intrin-
The thermionic current is given as [36]
sic Si channel, and a resistor at the drain end, as shown in     
the lower right of Fig. 1 as well as in Fig. 3(c) for n-type ΦB,s VA − Rs Ith
Ith = AA∗n T 2 exp − exp −1
DSS devices. The polarity of the GSD is forward biased, vth nvth
different from the normal SB diode, since the electrons are (4)
injecting from the silicide to the (n-type) semiconductor in nor-
where VA = Vs − Vs is the voltage drop across the GSD. A is
mal operations. Internal nodes are introduced, whose voltages
the area of the SB/intrinsic-channel interface. A∗n is the electron
(Vs and Vd ) can be solved by a circuit simulator in the subcircuit
Richardson constant. ΦB,s is the effective SBH at the source
model. The key model formulations for the current components
junction. n is the ideality factor, which is an adjustable model
will be given in the ensuing sections.
parameter. Vs is the internal node voltage between the source
SB junction and intrinsic Si channel. For more accurate model-
A. DD Model ing, an internal resistor Rs for the GSD is included in the right-
hand side of (4), which is the underestimated approximation
The DD current in conventional nMOSFETs is given as known as the “Bethe diode” equation [37]. Ith can be further
[32], [33] expressed using the L{w} function based on (4)
L {Ath Bth exp(−Bth Is )}
Ids = Idrift + Idiff Ith = Is − (5)
Bth
dφs dQi (y)
= − μs W Qi (y) + μs W vth . (1) where
dy dy
 
∗ ΦB,s
In the case of SiNW MOSFETs, following the DD formu- Is = AA T exp −
2
(5a)
vth
lation, the surface-potential-based drain current model for the  
Vs − Vs
intrinsic Si channel is given by [26], [34], [35] Ath = Is exp − (5b)
nvth
πR Rs
Ids = 2μCox (Vgf − φs + 2vth )Δφs Bth =
nvth
. (5c)
L

≈ 2μCox
πR
(Vgf − φs + 2vth )Vds,eff (2) At low currents when Rs Ith  (Vs − Vs ), Ith has the diode
L exponential form. At high currents, Ith becomes linear and
behaves like a resistor.
where μ is the carrier mobility, Vgf ≡ Vg − VFB is the flatband- The tunneling current is given as [28]
shifted gate voltage, Cox = εox /[R ln(1 + Tox /R)] is the cylin-  

drical gate capacitance, and vth = kB T /q is the thermal q 2 Fs2 8π
Itun = A exp − 2m∗n (qΦB,s )3 (6)
voltage. Vds,eff is the effective terminal drain–source voltage 8πhΦB,s 3hq|Fs |
including velocity saturation/overshoot effects. φs in (2) is the
Vg -dependent surface potential without the lateral-field effect, where h is the Planck constant. m∗n is the electron ef-
which is given as fective mass. Fs is the electric field at the source-end
metal/semiconductor interface, which is expressed as
 
φs = Vgf − 2vth L
Υi (Vgf −Vc (y))/2vth
√ e (3) Vs − Vs
2 vth Fs = (7)
λdep,s

where Υi = (2qεSi ni )1/2 /Cox is the intrinsic body factor. in which λdep,s is the depletion width induced by the source-
Vc (y) is the channel voltage, which equals the internal Vs at end SB and is approximately given by
the source end and Vd at the drain end. L{w} is the Lambert W 
function. λdep,s = 2εSi ΦB,s /qNseg,s (8)
All major second-order effects, such as S/D series resistance,
where Nseg,s is the dopant concentration in the source-end
channel-length modulation, drain-induced barrier lowering, ve-
segregation region.
locity saturation/overshoot, and vertical/lateral-field mobility
The current-continuity condition requires that the total GSD
degradation, have been built into the core model as given in [26]
TT current, given by
and [34]. The detailed model validation with experimental data
can be found in [35], which shows that the unified model can Isb = Ith + Itun (9)
excellently match the drain current as well as its higher order
derivatives. be equal to the transistor DD current (Ids ) in (2).
ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs
For DSS MOSFETs, the DS layer creates a very narrow
tunneling width due to the high concentration, which leads to a
high tunneling current. At the same time, the ultrahigh electric
field induced by the DS layer causes a large Schottky barrier
lowering (SBL) effect due to the image force [38] and leads to a
larger thermionic current. Physical modeling of the SBL effect
usually requires self-consistent iterations [23]. For simplicity,
we did not include the SBL effect in the model. The inaccuracy
can be compensated by the adjustable model parameters (e.g.,
ΦB ) during actual data fitting. Ith usually dominates over Itun
in the subthreshold (low Vgs ) and linear (low Vds ) regions
since the barrier width is relatively wide. This can be justified
from Fig. 2, which shows that the subthreshold region of a
DSS MOSFET is very similar to the diffusion transport in
conventional MOSFETs. In the strong-inversion and saturation
regions, channel drift current plays a more important role in
DSS devices. In this study, we adopt a subcircuit approach
rather than pursuing analytical derivations for the coupled TT
and DD solutions. Both the GSD TT and intrinsic-channel DD
models are separately implemented in Hspice using Verilog-A,
which is simulated to obtain the internal node voltage Vs .
C. GIDL
When Nseg,d is high or Lseg,d is long in the drain-end
segregation region, a high electric field is induced by the gate
in the gate-to-drain overlap region, leading to GIDL, which can
be due to BTBT or trap-assisted tunneling. Normally, BTBT is
assumed to be dominant. The BTBT current in the drain-end
overlap region can be approximated by [39]
 
BGIDL
IGIDL ∝ 2πRLseg,d Eseg,d
2
exp − (10)
Eseg,d
where BGIDL is a physics-based parameter with a theoretical
value of 21.3 MV/cm. Eseg,d is the electric field in the drain
overlap region, given as
Cox  2
Eseg,d = Vseg,d + (CGIDL Vds )2 (11)
εSi
in which CGIDL is a fitting parameter. Vseg,d is the gate–drain
voltage across the oxide, given by
Vseg,d = Vg − VFB_seg,d − φs_seg,d (12)
where VFB_seg,d and φs_seg,d are the flatband voltage and
surface potential, respectively, in the drain overlap region; the
latter can be obtained using the unified regional approach [40].
The final expression for the GIDL current is written as
 
BGIDL
2
IGIDL = AGIDL Vds Eseg,d exp − (13)
Eseg,d
where AGIDL is a model parameter proportional to 2πRLseg,d .
The above analytical equations clearly show the relationship
between IGIDL and Nseg,d and Lseg,d . A longer segregation
length gives a larger overlap region, which increases the GIDL
current. A higher Nseg,d leads to a larger electric field, which
can also increase the GIDL current.
775
The aforementioned GIDL model can quite accurately repro-
duce the measured GIDL current in DSS MOSFETs, as shown
in Fig. 2. Models for SBT-induced leakage can be found in [27]
and will not be discussed in detail.
IV. R ESULTS AND D ISCUSSION
In this section, we show the compact subcircuit model
(Xsim) results in comparison with both (Medici) numerical
simulations and experimental data. Numerical investigation on
the leakage mechanism of DSS MOSFETs is also presented.
For SB MOSFETs without DS, the carrier transport is dom-
inated by TT current, which is evident from the energy-band
diagram shown in Fig. 3(b) and the drain current has been
very well modeled by the quasi-2-D compact model [27].
Electron tunneling occurs from source-side SB for positive
Vgs , whereas hole tunneling occurs from drain-side SB for
negative Vgs . After introducing the DS, the dc characteristic
is changed from ambipolar to unipolar transport, as shown
in Fig. 2. Fig. 3(b) shows the extracted energy-band diagram
of a DSS device with Lseg,s(d) = 10 nm and Nseg,s(d) =
1 × 1020 cm−3 . Electrons first tunnel from source-side SB
into the intrinsic Si channel, where the carrier transport is
dominated by DD. Hole injection from drain-side SB is ba-
sically blocked, and the leakage is mainly due to BTBT in
the gate–drain overlap region. Therefore, the carrier transport
of the DSS device can be viewed as a combination of TT
from the source-side SB and DD inside the intrinsic Si chan-
nel, together with a drain-side resistor to model the drain-end
DS region.
To understand the leakage mechanism of DSS MOSFETs so
as to optimize the device performance, numerical simulations
are performed, and the results are shown in Figs. 4 and 5.
The physical parameters for the source-side segregation layer
(Nseg,s and Lseg,s ) are fixed at relatively large values to ensure
partial depletion and therefore maintain high ON-state current.
Nseg,d and Lseg,d at the drain side are varied separately to study
their impact on the leakage current. The BTBT model used by
Medici has the form of Kane’s model [41]. The effective masses
used in the SBT model have the following values: 0.22m0
for electrons and 0.35m0 for holes, where m0 is the electron
rest mass.
Fig. 4 shows the effect of Nseg,d on the leakage current.
For Nseg,d greater than 5 × 1019 cm−3 , the segregation layer
is partially depleted, hole injection from drain-side SB is
blocked, and the leakage current is mainly due to BTBT. For
BTBT-dominated leakage, it is undesirable to have a very high
Nseg,d since higher Nseg,d induces larger electric field, which
leads to larger leakage (GIDL) current. Nseg,d can neither be
too small, which will make the segregation layer fully depleted,
and the leakage current will be dominated by the hole injection
from the SB. As shown in Fig. 4(b), once Nseg,d is below
1 × 1018 cm−3 , the energy-band diagram becomes independent
of Nseg,d . Because of the dual role of the segregation layer,
which requires higher dopant concentration to improve drive
current and slightly lower dopant concentration to suppress
leakage, asymmetric structure [22] could be advantageous for
practical applications.
776
Fig. 4. (a) Leakage current characteristics of DSS MOSFETs with various
dopant concentrations in the drain-side segregation region. (b) Corresponding
energy-band diagrams, which explains the transition from BTBT-induced GIDL
current to SBT-induced leakage current.
Fig. 5. (a) Leakage current characteristics of DSS MOSFETs with various DS
lengths in the drain-side segregation region. (b) Corresponding energy-band
diagrams, which explains the gradual transition from BTBT-induced GIDL
current to SBT-induced leakage current.
Fig. 5 shows the effects of Lseg,d on the leakage current.
For Lseg,d longer than 4 nm (with Nseg,d = 1 × 1020 cm−3 ),
the segregation layer is partially depleted, hole injection from
drain-side SB is blocked, and the leakage current is contributed
by BTBT. For BTBT-dominated leakage, it is undesirable to
have a long Lseg,d since longer Lseg,d gives a larger overlap
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
Fig. 6. Model (lines) comparison with numerical (symbols) simulation
for DSS nMOSFET (Lg = 100 nm, R = 10 nm, Tox = 2 nm, Nseg =
1020 cm−3 , and Lseg = 10 nm). Output conductance at Vgs = 1.2 V is given
in the inset, which shows the convex curvature.
region, which leads to a higher GIDL current. Lseg,d can
neither be too short, which will make the segregation layer
fully depleted, and the leakage current will be dominated by
hole injection from the drain-side SB. These observations can
be further supported by the extracted energy-band transitions at
different Lseg,d , as shown in Fig. 5(b). For DSS devices with
different SBH at S/D, although the optimal values for Nseg,d
and Lseg,d could be different since the onset of partial depletion
is changed, the aforementioned analysis still holds.
Although the Ids –Vgs characteristic of a DSS MOSFET
behaves similarly to the conventional counterpart, as shown in
the previous figures, its Ids –Vds characteristic shows a convex
curvature in the linear region while resembling the conventional
MOSFETs in the saturation region, as shown in Fig. 6. Similar
convex curvature can also be observed in SB MOSFET due
to Schottky diode at the source end, which can be accurately
reproduced by the quasi-2-D model [27]. For DSS MOSFETs,
such characteristics cannot be captured by either the conven-
tional DD-MOSFET model [26] or SB-MOSFET model [27],
but it can be very well reproduced by the subcircuit model pre-
sented in this paper. Fig. 6 shows the subcircuit model in com-
parison with the numerical device. The calibrated subcircuit
model shows good agreement with the numerical simulation,
in particular, the convex curvature, as shown in the inset by the
output-conductance characteristic.
To gain deeper insights into the convex curvature, we play
back the individual components of the subcircuit model, as
shown in Fig. 7(a), with the same parameters and bias con-
ditions as the one in Fig. 6 at Vgs = 1.2 V. The analysis is
similar to the 2-D numerical study [42] for the investigation of
the potential distribution inside the SB MOSFETs. The result
from the complete subcircuit model (schematic in Fig. 1) is
shown by the circles. Each component of the subcircuit is
calculated with the other two short circuited, all plotted as a
function of Vds . At any given current level, the sum of the
voltage drops across the drain resistance (Vd − Vd , diamonds),
intrinsic channel (Vd − Vs , triangles), and SB diode (Vs − Vs ,
squares) is always equal to Vds , the total voltage across the three
subcircuit elements. This is further confirmed by the zoomed-
in plot in Fig. 7(b), as indicated at two current levels. The dc
resistance (Vds /Ids ) for each component is calculated, and their
sum is shown by the dashed line in Fig. 7(c), which tallies with
ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs
Fig. 7. (a) Model playback of the (circle) subcircuit model and the individual
components: (square) Schottky diode including internal Rs ; (triangle) intrin-
sic channel; and (diamond) drain-end resistance Rd . (b) Zoomed-in plot at
low Vds < 0.6 V, showing that the total voltage drop across the subcircuit
model (Vds ) is the sum of the voltage drops across the drain resistance
(Vd − Vd ), intrinsic channel (Vd − Vs ), and GSD (Vs − Vs ) at any given
drain current (two indicated), as calculated by the circuit simulator. (c) DC
resistance (Vds /Ids ) of the individual components in (a). (d) AC (differential)
conductance (dIds /dVds ) of the individual components in (a). (e) Thermionic
(Ith ) and tunneling (Itun ) components of the GSD total current (Isb ).
N-DSS: Lg = 100 nm, R = 10 nm, Tox = 2 nm, Nseg = 1020 cm−3 , and
Lseg = 10 nm.
the dc resistance from the subcircuit model (circle). It can be
seen that the DSS terminal current is dominated by the SB diode
at low Vds and by the intrinsic-channel MOSFET at high Vds .
This is a unique feature of DSS devices [as in Fig. 3(c)], which
gives rise to the unique convex curvature in Ids at low Vds
and high Vgs , not observable in conventional MOSFETs
[as in Fig. 3(a)].
The small-signal ac conductance for each component is
shown in Fig. 7(d), which explains the observed convex curva-
ture at very low Vds . At low Vds and high Vgs , the current is low
and the intrinsic channel is linear, and most of the applied bias
Vds is dropped across the SB diode, which takes the exponential
form since the voltage drop across its internal resistor (Rs ) is
also small. This gives rise to the convex curvature in Ids or the
decreasing gds as Vds approaches zero. The exact shape of gds
should also depend on the drain-side DSS layer, which may not
be fully captured by our simple Rd subcircuit model.
777
Fig. 8. Internal voltage distribution (a) Vs − Vs , (b) Vd − Vd , and
(c) Vd − Vs versus terminal Vds from the subcircuit model at different Vgs ,
as indicated. (d) Voltage distribution across the whole channel at Vgs = 0.3 V.
As Vds increases, the internal resistance Rs starts to dominate
the thermionic current Ith , modeled by the Lambert W function
(5), as shown by the circle in Fig. 7(e). With a further increase in
Vds , the tunneling current Itun from (6), shown by the triangle
in Fig. 7(e), starts to contribute to the GSD current Isb , which
may have a minor influence on the total ac output resistance
but no effect on the dc current and dc resistance as the intrinsic
channel is pinched off. Fig. 7(e) clearly shows three distinct
regions of the GSD current (square), namely, exponential or
thermionic dominant at low Vds , resistive at medium Vds , and
tunneling dominant at high Vds .
The internal voltage distributions, Vs − Vs , Vd − Vd , and
Vd − Vs , obtained from the circuit simulator, are shown in

Fig. 8(a)–(c), respectively. The source-side internal Vs in-
creases initially when the intrinsic channel is in the linear region
with a small voltage drop, and it saturates once the channel
is pinched off and the current starts to be controlled by the
intrinsic channel. Similarly, the drain-side voltage drop Vd − Vd
across the resistor increases initially when the intrinsic channel
is in the linear region and it saturates once the channel is
pinched off. Fig. 8(c) shows the voltage drop across the intrinsic
channel. At low Vds , most of the voltage drops across the GSD
at the source side due to its large differential resistance com-
pared to the intrinsic-channel MOSFET, as shown in Fig. 8(d).
Finally, the subcircuit model is verified with the experimental
short-channel devices, as shown in Fig. 9. Two devices from
the same wafer are selected. The first one shows the con-
ventional behavior, whereas the second one shows a convex
curvature at low Vds and high Vgs . The saturation currents for
both devices have the same magnitude, which rules out the
possibility that the second device is a pure SB MOSFET whose
saturation current is usually much smaller than its conventional
counterparts. Neither the SB-MOSFET model [27] nor the
conventional MOSFET model [26] is able to capture such
behaviors. However, by using the subcircuit approach, the drain
778
Fig. 9. (Lines) Model comparison with (symbols) measurement data for two
DSS devices in (a) and (b), respectively. Output conductance of the two devices
is given in (c).
current as well as the convex curvature for the second device
can be accurately reproduced, which is further justified from the
characteristics of the output conductances of the two devices,
as shown in Fig. 9(c). This interesting difference between the
two devices is believed to be due to process variations, which
are normally very severe in SB/DSS MOSFETs. One major
source of fluctuations is the SBH, which is highly sensitive
to the interface states/traps at the silicide/silicon junction. Due
to the exponential dependence on the SBH, even a very small
variation in the SBH can lead to a huge variation in reverse
saturation current Is . In practice and model calibration, since
the SBH and electron effective mass can hardly be determined,
the reverse saturation current Is is considered as an adjustable
fitting parameter for flexibility, which can be related to the SBH
by (5a) if other parameters are known. The ideality factor n is
another source of variation that would distort the I–V behavior
of DSS MOSFETs. Fluctuations in these model parameters
could have great impact on the dc characteristics, as shown
in Fig. 10 from the model playback of a long-channel device.
The effect of saturation current Is (and the corresponding
SBH ΦB,s ) is shown in Fig. 10(a), which shows that the larger
Is is, the less convex the curvature becomes. According to (5a),
a larger Is corresponds to a smaller SBH, which is expected to
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
Fig. 10. Model playback of a long-channel device (Lg = 1 μm). (a) Impact
of the saturation current Is on the dc characteristics of DSS MOSFETs. The
smaller the value of Is is, the more convex the curvature becomes, as can be
justified from the output conductance shown in the inset. (b) Impact of ideality
factor n on the dc characteristics of DSS MOSFETs. The larger the value of n
is, the more convex the curvature becomes, as can be justified from the output
conductance shown in the inset.
make the curvature less convex. It indicates that close-to-zero
SBH would greatly boost the device performance. However,
in practice, due to Fermi-level pinning, the SBH is always
quite large regardless of the metal or silicide work function
[43]–[48]. Similarly, Fig. 10(b) shows that for larger ideality
factor n, the curvature in the linear region turns out to be
more convex. As n approaches zero, the curvature gradually
returns to the conventional (concave) behavior. This can also
be justified from the output conductance shown in the inset.
The practical value of the ideality factor is usually between 1
and 2. Therefore, the fluctuation of SBH at the S/D junction is
believed to be the dominant cause for the device performance
variations. During model calibration, n and Is can be tuned
together to better fit the data and to compensate for other
possible process fluctuations, such as variations in the length
and doping concentration in the segregation region.
The presented subcircuit modeling approach is, however, not
limited to DSS MOSFETs and can be readily applied to model
the convex curvature observed in some FinFET devices [49],
[50], which is believed to be caused by the nonideal ohmic
contact at the S/D junctions.
V. C ONCLUSION
In conclusion, we have demonstrated analytical device mod-
els and a unique subcircuit approach to physically and accu-
rately model the DSS GAA SiNW MOSFETs. The proposed
subcircuit device model shows very good agreement with both
numerical simulations and experimental data with physical
parameter scalability. The convex curvature in the Ids –Vds
ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs
characteristics at low drain and high gate biases has been
explained and accurately reproduced via the subcircuit compact
model. Although the detailed curvature in that region, which
has not been physically modeled so far to the best of our
knowledge, may not have practical importance for analog and
digital circuits, its physical modeling is of paramount impor-
tance. Without the subcircuit model to solve for the coupled TT
and DD carrier transport, the conventional DD model would
overestimate saturation current (that has to be tuned unphysi-
cally to match the actual data), whereas the ambipolar TT model
would give incorrect tunneling-dominant current in strong-
inversion and saturation regions. The proposed subcircuit com-
pact modeling approach represents a unique way for solving
coupled equations and a trend for future transistor compact
modeling.
R EFERENCES
[1] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky
barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53,
no. 5, pp. 1048–1058, May 2006.
[2] J. Knoch, M. Zhang, S. Mantl, and J. Appenzeller, “On the performance
of single-gated ultrathin-body SOI Schottky-barrier MOSFETs,” IEEE
Trans. Electron Devices, vol. 53, no. 7, pp. 1669–1674, Jul. 2006.
[3] T. P. Lee, E. J. Lim, K. M. Tan, T. Y. Liow, G. Q. Lo, G. S. Samudra,
D. Z. Chi, and Y. C. Yeo, “N-channel FinFETs with 25-nm gate length
and Schottky-barrier source and drain featuring ytterbium silicide,” IEEE
Electron Device Lett., vol. 28, no. 2, pp. 164–167, Feb. 2007.
[4] Y. K. Chin, K. L. Pey, N. Singh, G. Q. Lo, L. Chan, L. H. Tan, and
E. J. Tan, “Effect of nickel silicide intrusion on Schottky barrier nanowire
MOSFET fabricated using top-down technology,” in Proc. SSDM, 2008,
pp. 436–437.
[5] J. W. Peng, S. J. Lee, G. C. A. Liang, N. Singh, S. Y. Zhu, G. Q. Lo, and
D. L. Kwong, “Improved carrier injection in gate-all-around Schottky
barrier silicon nanowire field-effect transistors,” Appl. Phys. Lett., vol. 93,
no. 7, p. 073 503, Aug. 2008.
[6] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, K. M. Hoe,
G. Cui, and P. S. Lee, “Demonstration of Schottky barrier NMOS tran-
sistors with erbium silicided source/drain and silicon nanowire channel,”
IEEE Electron Device Lett., vol. 29, no. 10, pp. 1167–1170, Oct. 2008.
[7] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, L. J. Tang,
P. S. Lee, and C. K. F. Ho, “Nickel-silicided Schottky junction CMOS
transistors with gate-all-around nanowire channels,” IEEE Electron De-
vice Lett., vol. 29, no. 8, pp. 902–905, Aug. 2008.
[8] D. Connelly, C. Faulkner, D. E. Grupp, and D. J. S. Harris, “A new route
to zero-barrier metal source/drain MOSFETs,” IEEE Trans. Nanotechnol.,
vol. 3, no. 1, pp. 98–104, Mar. 2004.
[9] D. Connelly, C. Faulkner, P. A. Clifton, and D. E. Grupp, “Fermi-level
depinning for low-barrier Schottky source/drain transistors,” Appl. Phys.
Lett., vol. 88, no. 1, pp. 012 105–012 108, Jan. 2006.
[10] Q. T. Zhao, E. Rije, U. Bruer, S. Lenk, and S. Mantl, “Tuning of
silicide SBHs by segregation of sulfur atoms,” in Proc. ICSICT, 2004,
pp. 456–459.
[11] M. Tao, D. Udeshi, N. Basti, E. Maldonado, and W. P. Kirk, “Removal of
dangling bonds and surface states on silicon (001) with a monolayer of
selenium,” Appl. Phys. Lett., vol. 82, no. 10, pp. 1559–1561, May 2003.
[12] M. Tao, S. Agarwal, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk,
“Low Schottky barriers on n-type silicon (001),” Appl. Phys. Lett., vol. 83,
no. 13, pp. 2593–2595, Sep. 2003.
[13] G. Song, M. Y. Ali, and M. Tao, “A high Schottky-barrier of 1.1 eV
between AL and S-passivated p-type Si (100) surface,” IEEE Electron
Device Lett., vol. 28, no. 1, pp. 71–73, Jan. 2007.
[14] R. Saiz-Pardo, R. Perez, F. J. Garcia-Vidal, R. Whittle, and F. Flores, “Sys-
tematic theoretical studies of the Schottky barrier control by passivating
atomic intralayers,” Surf. Sci., vol. 426, no. 1, pp. 26–37, May 1999.
[15] S. J. Choi, J. W. Han, S. H. Kim, M. G. Jang, J. S. Kim, K. H. Kim,
G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y. K. Choi,
“Enhancement of program speed in dopant-segregated Schottky-barrier
(DSSB) FinFET SONOS for NAND-type Flash memory,” IEEE Electron
Device Lett., vol. 30, no. 1, pp. 78–81, Jan. 2009.
[16] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution
for high performance Schottky-source/drain MOSFETs: Schottky barrier
779
engineering with dopant segregation technique,” in VLSI Symp. Tech.
Dig., 2004, pp. 168–169.
[17] A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, “High-performance
50 nm-gate-length Schottky-source/drain MOSFETs with dopant-
segregation junctions,” in VLSI Symp. Tech. Dig., 2005, pp. 158–159.
[18] M. Zhang, J. Knoch, Q. T. Zhao, S. Lenk, U. Breuer, and
S. Mantl, “Schottky barrier height modulation using dopant
segregation in Schottky-barrier SOI-MOSFET,” in Proc. ESSDERC,
2005, pp. 457–460.
[19] B. Y. Tsui and C. Lin, “Process and characteristics of modified
Schottky barrier (MSB) p-channel FinFETs,” IEEE Trans. Electron De-
vices, vol. 52, no. 11, pp. 2455–2462, Nov. 2005.
[20] Z. Qiu, Z. Zhang, M. Östling, and S. L. Zhang, “A comparative study
of two different schemes to dopant segregation at NiSi/Si and PtSi/Si
interfaces for Schottky barrier height lowering,” IEEE Trans. Electron
Devices, vol. 55, no. 1, pp. 396–403, Jan. 2008.
[21] S. Matsumoto, M. Nishisaka, and T. Asano, “CMOS application of Schot-
tky source/drain SOI MOSFET with shallow doped extension,” Jpn. J.
Appl. Phys., vol. 43, no. 4B, pp. 2170–2175, Apr. 2004.
[22] T. Hoffmann, G. Doornbos, I. Ferain, N. Collaert, P. Zimmerman,
M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit,
K. De Meyer, M. Jurczak, and S. Biesemans, “GIDL (gate-induced
drain leakage) and parasitic Schottky barrier leakage elimination in ag-
gressively scaled HfO2 /TiN FinFET devices,” in IEDM Tech. Dig., 2005,
pp. 725–728.
[23] R. A. Vega and T.-J. K. Liu, “A comparative study of dopant-
segregated Schottky and raised source/drain double-gate MOSFETs,”
IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665–2677,
Oct. 2008.
[24] F. F. Huang and B. Y. Tsui, “Short-channel metal-gate TFTs with modified
Schottky-barrier source/drain,” IEEE Electron Device Lett., vol. 27, no. 1,
pp. 43–45, Jan. 2006.
[25] Z. Zhang, Z. J. Qiu, P. E. Hellstrom, G. Malm, J. Olsson, J. Lu, M. Östling,
and S. L. Zhang, “SB-MOSFETs in UTB-SOI featuring PtSi source/drain
with dopant segregation,” IEEE Electron Device Lett., vol. 29, no. 1,
pp. 125–127, Jan. 2008.
[26] G. J. Zhu, G. H. See, S. H. Lin, and X. Zhou, ““Ground-referenced” model
for three-terminal symmetric double-gate MOSFETs with source/drain
symmetry,” IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2526–2530,
Sep. 2008.
[27] G. J. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, S. H. Lin,
Y. K. Chin, and K. L. Pey, “A compact model for undoped silicon
nanowire MOSFETs with Schottky barrier source/drain,” IEEE Trans.
Electron Devices, vol. 56, no. 5, pp. 1100–1109, May 2009.
[28] M. Jang, K. Kang, S. Lee, and K. Park, “Simulation of Schottky barrier
tunneling transistor using simple boundary condition,” Appl. Phys. Lett.,
vol. 2, no. 16, pp. 2718–2720, Apr. 2003.
[29] G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, G. H. See, S. H. Lin,
J. B. Zhang, and Z. H. Chen, “Subcircuit compact model for dopant-
segregated Schottky silicon-nanowire MOSFETs,” in Proc. SSDM, 2009,
pp. 402–403.
[30] Y. K. Chin, K.-L. Pey, N. Singh, G.-Q. Lo, K. H. Tan, C.-Y. Ong, and
L. H. Tan, “Dopant-segregated Schottky silicon-nanowire MOSFETs with
gate-all-around channels,” IEEE Electron Device Lett., vol. 30, no. 8,
pp. 843–845, Aug. 2009.
[31] Y. K. Chin, K. L. Pey, N. Singh, G. Q. Lo, G. Zhu, X. Zhou,
X. C. Wang, H. Y. Zheng, and L. H. Tan, “Excimer laser-annealed dopant
segregated Schottky Si nanowire gate-all-around pFET with near zero
effective Schottky barrier height (SBH),” in IEDM Tech. Dig., 2009,
pp. 935–938.
[32] H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of
metal–oxide (insulator)–semiconductor transistors,” Solid State Electron.,
vol. 9, no. 10, pp. 927–937, Oct. 1966.
[33] J. R. Brews, “A charge-sheet model of the MOSFET,” Solid State Elec-
tron., vol. 21, no. 2, pp. 345–355, Feb. 1978.
[34] G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. M. Zhu,
C. Q. Wei, S. H. Lin, G. J. Zhu, and G. H. Lim, “A compact model
satisfying Gummel symmetry in higher order derivatives and applicable
to asymmetric MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2,
pp. 624–631, Feb. 2008.
[35] G. J. Zhu, X. Zhou, G. H. See, S. H. Lin, C. Q. Wei, and J. B. Zhang, “A
unified compact model for FinFET and silicon nanowire MOSFETs,” in
Proc. NSTI Nanotech, 2009, pp. 588–591.
[36] D. A. Neamen, Semiconductor Physics and Devices—Basic Principles.
New York: McGraw-Hill, 2003, p. 338.
[37] C.-T. Sah, Fundamentals of Solid-State Electronics. Singapore: World
Scientific, 1991, p. 495.
780
[38] R. F. Pierret, Semiconductor Device Fundamentals. Reading, MA:
Addison-Wesley, 1996, p. 492.
[39] R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, Physical
Background of MOS Model 11, p. 44, Apr. 2003. [Online]. Available:
http://www.nxpcom/acrobat_download/other/philipsmodels/nl_tn2003_
00239.pdf
[40] X. Zhou, G. H. See, G. J. Zhu, S. H. Lin, C. Q. Wei, and J. B. Zhang,
“Unified regional modeling approach to emerging multiple-gate/nanowire
MOSFETs,” in Proc. ICSICT, 2008, pp. 262–267.
[41] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solids,
vol. 12, no. 2, pp. 181–188, 1959.
[42] J. P. Snyder, C. R. Helms, and Y. Nishi, “Analysis of the potential distribu-
tion in the channel region of a platinum silicided source/drain metal oxide
semiconductor field effect transistor,” Appl. Phys. Lett., vol. 74, no. 22,
pp. 3407–3409, May 1999.
[43] S. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee,
M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh,
A. Chin, and D. L. Kwong, “Schottky-barrier S/D MOSFETs with
high-k gate dielectrics and metal-gate electrode,” IEEE Electron Device
Lett., vol. 25, no. 5, pp. 268–270, May 2004.
[44] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du,
C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier
source/drain MOSFET using ytterbium silicide,” IEEE Electron Device
Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004.
[45] J. Kedzaerski, P. Xuan, H. Anderson, J. Bokor, T. J. King, and C. Hu,
“Complementary silicide source/drain thin-body MOSFETs for the 20 nm
gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60.
[46] L. E. Calvet, H. Leubben, M. A. Reed, C. Wang, J. P. Snyder,
and J. R. Tucker, “Suppression of leakage current in Schottky bar-
rier metal–oxide–semiconductor field-effect transistors,” J. Appl. Phys.,
vol. 91, no. 2, pp. 757–759, Jan. 2002.
[47] M. Fritze, L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast,
J. Snyder, and J. Larson, “High-speed Schottky-barrier pMOSFET with
fT = 280 GHz,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 220–222,
Apr. 2004.
[48] G. Larrieu and E. Dubois, “Schottky-barrier source/drain MOSFETs on
ultrathin SOI body with a tungsten metallic midgap gate,” IEEE Electron
Device Lett., vol. 25, no. 12, pp. 801–803, Dec. 2004.
[49] H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, “A low-power, highly
scalable, vertical double-gate MOSFET using novel processes,” IEEE
Trans. Electron Devices, vol. 55, no. 2, pp. 632–639, Feb. 2008.
[50] H.-S. P. Wong, K. K. Chan, and T. Yuan, “Self-aligned (top and bottom)
double-gate MOSFET with a 25 nm thick silicon channel,” in IEDM Tech.
Dig., 1997, pp. 427–430.
Guojun Zhu (S’08) was born in China in 1984.
He received the B.E.(Hons.) degree in electrical and
electronic engineering in 2007 from the Nanyang
Technological University, Singapore, where he is
currently working toward the Ph.D. degree at the
School of Electrical and Electronic Engineering.
From July to December 2005, he was an Intern
with Chartered Semiconductor Manufacturing Ltd.,
Singapore, where he worked on electrical testing.
His current research interests include unified com-
pact modeling of bulk/SOI/DG/GAA and Schottky-
barrier MOSFETs.
Xing Zhou (S’88–M’91–SM’99) received the B.E.
degree in semiconductor physics from Tsinghua Uni-
versity, Beijing, China, in 1983, and the M.S. and
Ph.D. degrees in electrical engineering from the Uni-
versity of Rochester, Rochester, NY, in 1987 and
1990, respectively.
From 1990 to 1991, he was a Research Associate
with the Department of Electrical Engineering, Uni-
versity of Rochester, where he worked on hot-carrier
injection phenomena in MOS devices and on the
development of computer-aided design (CAD) tools
for mixed-signal circuit simulation. From 1992 to 1995, he was a Research
Fellow with the School of Electrical and Electronic Engineering, Nanyang
Technological University, Singapore, where he worked on Monte Carlo and
numerical modeling of semiconductor and optoelectronic devices as well as
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
mixed-signal circuit modeling and simulation. In November and December
of 1997 as well as in February and March 2001, he was a Visiting Fellow
with the Center for Integrated Systems, Stanford University, Stanford, CA.
In January 2003, he was a Visiting Professor with Hiroshima University,
Hiroshima, Japan. In May 2007, he was a Visiting Professor with Universiti
Teknologi Malaysia, Johor Bahru, Malaysia. He is currently with the School
of Electrical and Electronic Engineering, Nanyang Technological University as
a tenured Associate Professor, teaching and researching deep-submicrometer
CMOS technology and device modeling. His current research interests include
the area of semiconductor device physics and modeling, novel device struc-
tures, compact model development for advanced devices, technology modeling
and simulation, mixed-signal CAD tools, hot-carrier transport, and ultrafast
phenomena.
Dr. Zhou is an Elected Member of the IEEE Electron Devices Society (EDS)
Administrative Committee, the Chair of the EDS Asia Pacific Subcommittee
for Regions/Chapters, a Member of the EDS Compact Modeling Technical
Committee as well as the Educational Activities, Publications, and Membership
Committees, an EDS Distinguished Lecturer, and an Editor of the IEEE E LEC -
TRON D EVICE L ETTERS . He received the 2006 Nano Science and Technology
Institute (NSTI) Fellowship Award. He is listed in the Marquis Who’s Who in
the World and Who’s Who in Science and Engineering. Since 2002, he has been
the Founding Chair of the Workshop on Compact Modeling in association with
the NSTI Nanotech Conference.
Yoke-King Chin received the B.E. degree in elec-
trical and electronics engineering in 2006 from
the Nanyang Technological University, Singapore,
where he is currently working toward the Ph.D.
degree in the Division of Microelectronics, School
of Electrical and Electronic Engineering.
His research interests include the fabrication
and characterization of silicon-nanowire transistors,
Schottky MOSFETs, advanced junction engineer-
ing, and channel engineering for future CMOS
applications.
Kin Leong Pey (S’86–M’95–SM’02) received the
B.Eng. and Ph.D. degrees in electrical engineer-
ing from the National University of Singapore,
Singapore, 1989 and 1994, respectively.
He has held various research positions in the Insti-
tute of Microelectronics, Chartered Semiconductor
Manufacturing, Agilent Technologies, and National
University of Singapore. He is currently a Professor,
the Head of the Microelectronics Division, and the
Director of the Nanyang Nanofabrication Center at
the School of Electrical and Electronic Engineering,
College of Engineering, Nanyang Technological University, and holds a con-
current Fellowship appointment in the Singapore—MIT Alliance (SMA).
Dr. Pey is an IEEE Electron Devices Society Distinguished Lecturer and has
been the Organizing Committee Member of the International Symposium on
the Physical and Failure Analysis of Integrated Circuits (IPFA) since 1995. He
was the General Chair of IPFA 2001, Singapore, and a Co-General Chair of
IPFA 2004, Hsinchu, Taiwan. He was an Editor of the IEEE T RANSACTIONS
ON D EVICES AND M ATERIALS R ELIABILITY and the Chair of the Singapore
Chapter of the IEEE Reliability Society, the IEEE Components, Packaging, and
Manufacturing Technology Society, and the IEEE Electron Devices Society
in 2004/2005 and 2009. He served on the 2006–2009 International Reliability
Physics Symposium Technical Subcommittee, the IPFA 2002–2006 and 2008
Technical Committee, and the 2007 International Electron Devices Meeting
(IEDM) CMOS and Interconnect Reliability and the 2008 IEDM Characteri-
zation, Reliability and Yield Subcommittees.
Junbin Zhang received the B.E.(Hons.) degree in
electrical and electronic engineering in 2007 from
the Nanyang Technological University, Singapore,
where he is currently working toward the Ph.D.
degree at the School of Electrical and Electronic
Engineering.
His current research interests include compact
modeling and device physics of next-generation de-
vices such as SOI, double-gate, and LD MOS.
ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 781

Guan Huei See received the B.E. degree in Yafei Yan received the B.S. and M.S. degrees
electrical/telecommunication engineering and the in electrical engineering from Tsinghua University,
M.Eng. degree in electrical engineering from Beijing, China, in 2000 and 2003, respectively.
the Universiti Teknologi Malaysia, Johor Bahru, From 2003 to 2008, he was with Cadence. He
Malaysia, in 2002 and 2004, respectively, and the is currently a Research Associate with the School
Ph.D. degree in electrical and electronic engineer- of Electrical and Electronic Engineering, Nanyang
ing from the Nanyang Technological University, Technological University, Singapore. His research
Singapore, in 2009. interests include semiconductors and physics, mainly
He was a Postgraduate Intern at Silterra Malaysia focusing on compact modeling.
from 2002 to 2003, where he was responsible for
developing RF SPICE model for on-chip passive
devices, i.e., inductors, capacitors and resistors. He is currently a Senior
Integration Engineer for mixed-signal/RFCMOS with GLOBALFOUNDRIES
Singapore Pte. Ltd., Singapore. His current research interests include compact
modeling of CMOS transistors.
Zuhui Chen (S’05–M’06) received the B.S. degree
in physics from Fujian Normal University, Fujian,
China, the M.S. degree in solid-state physics from
Shihuan Lin received the B.Sc. degree in electronic
Xiamen University, Fujian, and the Ph.D. degree in
engineering from the Beijing Institute of Technology,
engineering science from the University of Florida,
Beijing, China, in 2001 and the M.Sc. degree in
Gainesville, in 1998, 2001, and 2005, respectively.
microelectronics from the Nanyang Technological
In 2006, he joined the Pen-Tung Sah MEMS Re-
University, Singapore, in 2006, where he is currently
search Center of Xiamen University as an Instruc-
working toward the Ph.D. degree at the School of
tor. In 2007, under the Lee Kuan Yew Postdoctoral
Electrical and Electronic Engineering.
Fellowship, he joined Nanyang Technological Uni-
His current research interests include nanoscale
versity, Singapore, as a Research Fellow, where he is
device modeling.
currently with the School of Electrical and Electronic Engineering. His current
interests include NBTIs and interface-trap modeling in silicon MOSFETs.