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WCDMA Library

Accelerating Wireless Design Productivity For 3G Cellular System Design

H I G H L I G H T S
Overview ■ Transmitter modeling functions including
■ Supports the design of 3GPP Wideband CDMA
Code-division multiple access, or CDMA, tech- variable rate data generation, channel coding
nology is the foundation for many modern (both convolutional and turbo), rate (WCDMA) products
matching single or multicarrier spreading, ■ Includes a rich set of libraries of fundamental
wireless communications systems. To assist
engineers designing Wideband CDMA scrambling, and transmit filtering CDMA functions such as sequence generation,
(WCDMA) systems, CoWare has developed a spreading and despreading operations
■ Channel/environment modeling functions
■ Provides several CDMA and WCDMA system
WCDMA library for Signal Processing including a Wideband Rayleigh fading
Designer. Use of SPD’s WCDMA library can test benches
channel model (up to six paths) with log-
expedite your design of WCDMA systems by ■ Includes fixed-point algorithmic design
normal shadow fading and additive white
facilitating algorithmic exploration and Gaussian noise (AWGN) capture and datapath performance analysis
shortening development and design verifica- ■ Enables simulation of C, C++, and/or HDL
■ Receiver modeling functions including
tion times. It also can increase your chance blocks in a single simulation process
receiver filtering, rake receiver (up to six
of first-time design success. You can also ■ Conforms to current standards for 3GPP WCDMA
fingers), descrambling, despreading, de-
combine WCDMA library models with other ■ Accelerates complete design of a 3G wireless
rate-matching and channel decoding
Signal Processing Designer models. For personal device when used with optional
(both Viterbi for convolutional codes and
example, by combining WCDMA models Signal Processing Designer libraries such as the
Maximum A-Posteriori (MAP) for turbo
with models from SPD’s multimedia library, a WLAN library for IEEE802.11, and Bluetooth
codes)
designer can quickly build advanced 3G ■ Compatible with the Signal Processing Designer
wireless system level designs which include
■ Performance analysis functions including
Multimedia Library for the development of 3G
multimedia (video) features. bit error rate (BER) and frame error rate systems that incorporate imaging/video sub-
(FER) counting systems such as a digital camera, video
History The Signal Processing Designer environment compression routines, and/or video display
The Signal Processing Designer team has allows users to replace parts of these system
been producing end-to-end physical layer models with their own hardware or software
baseband simulation models of third genera- implementations and then simulate their WCDMA Verification Systems
tion WCDMA standards since December implementation in the context of the entire The WCDMA library includes a number of
1997. This effort started with UMTS and system. This provides a powerful environ- system reference models. The testbench
ARIB WCDMA and was followed by 3GPP ment to rapidly develop, debug, and validate models can be used for algorithmic explo-
and 3GPP2 models. CoWare continues to an implementation. ration of an end-to-end WCDMA system.
track the evolving standards and uses infor- These reference systems model all aspects
The 3GPP models provide both ideal receivers of a CDMA system, including sequence
mation from the standards committees to
(with perfect knowledge of the channel) and generation, acquisition, tracking, channel
build the system level models. The models, in
non-ideal receivers (which must estimate the estimation, and interference cancellation.
turn, provide a framework and a testbench
channel characteristics). The ideal receiver Each modeled system is configurable,
for users interested in hardware and/or soft-
gives a best case scenario for comparison enabling users to make rapid modifications
ware implementation of all or parts of a 3G
against your real and non-ideal receiver design. to support modeling their particular
design.
The WCDMA library covers the Frequency WCDMA system design decisions.
The WCDMA Library Division Duplex (FDD) of the 3GPP standard. The 3GPP WCDMA reference systems
The system level models provided by the CoWare’s strategy is to rapidly update the included in the library are as follows:
WCDMA library include many baseband pro- libraries as the recommendations evolve and
cessing functions. The following lists several become standards. We are committed to the Downlink Channel
functions available in the library. continued updating of these models until This system models an end to end single
they reach their final maturity. code 3GPP downlink system with two trans-
port channels in its standard configuration,
WCDMA Library 2

but is flexible enough to allow as many or as ■ Viterbi decoder ■ MACK/NACK generation


few transport channels as wanted. This refer- ■ Turbo decoder ■ HS-DSCH throughput measured
ence system can be used to verify the DCH ■ Rate de-matcher
demodulation performance requirements in Downlink Practical Rake Receiver
3GPP TS 25.101 sections 8.2, 8.3, 8.4 and 8.5.
■ Block error rate and bit error rate measured The downlink Practical Rake receiver system
The standard 12.2kbps, 64kbps, 144kbps and is the same as the Downlink Channel refer-
Downlink HSDPA
384kbps measurement channels can easily be ence system, with the exception of the Ideal
This model implements the High Speed
simulated by changing a single parameter. Receiver which has been replaced by a
Downlink Packet Access channel introduced
The receiver model is ideal. A similar system Practical Receiver model. The Practical
in Release 5 of the 3GPP standard. It has QPSK
supporting Space Time Transmit Diversity is Receiver model has the following features:
and 16QAM modulation modes and can be
also available. used to verify the HS-DSCH Fixed Reference ■ Pilot-based rake receiver integrated with
Transmitter Model Details Channel performance requirements in 3GPP full downlink system
■ Transport channel generation and coding TS 25.101 section 9.2.1. Both the HS-DSCH ■ Four rake fingers modeled with support of
and the HS-SCCH channels are implemented
■ Primary and secondary synchronization up to six fingers
and the receiver uses information from the
channels ■ Maximum ratio combining
HS-SCCH to decode the data on the HS-DSCH.
■ Common pilot channel It models the HARQ protocol with ACK/NACK ■ Channel delay tracking loop
■ Primary common control physical channel feedback and soft combining. Turbo coding ■ Coherent tracking using Common Pilot
■ Page indication channel (HS-DSCH) and convolutional coding (HS- Channel (CPICH)
SCCH) are fully supported.
■ 16 channel orthogonal channel ■ Fully polymorphic for fixed-point
noise simulator Transmitter Model Details exploration
■ Compressed mode with puncturing, ■ Transport block generation with support ■ Fixed point RTL version available as well
spreading factor reduction, higher layer for up to 8 HARQ processes and changeable
scheduling modes transmit pattern Downlink Practical Rake Receiver—
RTL Implementation
■ Both A and B compressed mode frame ■ HS-DSCH bit scrambling This is same as the above system except that
structures ■ Turbo coding with support for multiple the Practical Rake Receiver has been refined
■ Fixed and flexible frame positions code blocks (HS-DSCH) for Fixed-Point simulation and Hardware
■ Transport format combination ■ Convolutional coding (HS-SCCH) (RTL) generation. It is implemented using
indicator coding ■ Rate matching (HS-DSCH and HS-SCCH) HDS, Advanced HDS and CDMA RTL library
■ Pilot symbol generation blocks. The RTL Implementation of Practical
■ HS-DSCH interleaving and constellation
Rake Receiver design has the following features:
■ Turbo and convolutional coding rearrangement
■ CRC generation ■ HS-SCCH frame generation ■ Fixed-point refinement (bitwidths and
■ First and second interleaver ■ HS-DSCH multi-code transmitter supporting modes) of the design
■ Scrambling code generation both 16QAM and QPSK modulation ■ Fixed-point simulation functionally
Channel Model Details matches the floating-point design
■ OVSF code generation
■ Standard 3GPP model with PA3, PB3, VA30 ■ Hardware refinement of the design by
Channel Model Details
and VA120 as preset propagation conditions adding clocks, adjusting delays, removing
■ Static, fading cases 1 through 6, moving
Receiver Model Details multirate blocks and adding extra control
and birth-death channel conditions
■ HS-SCCH ideal receiver circuitry
Receiver Model Details
■ HS-DSCH ideal multi-code receiver ■ Hardware generation from the design
■ Ideal receiver model
model supporting both 16QAM and QPSK outputting synthesizable Verilog and VHDL
■ Compressed mode support which can map to both ASICs and FPGAs
modulation
■ First and second deinterleaver (synthesizable by Cadence-BuildGates,
■ HS-DSCH deinterleaving and rate
■ CRC checking Synopsys Design Compiler, Synplicity
dematching
Synplify-Pro)
■ Transport format combination ■ HARQ soft combining
indicator decoding ■ Generated hardware optimized for data-
■ Turbo (HS-DSCH) and Viterbi (HS-SCCH) path-synthesis tools (BG with datapath
■ Turbo code scaling decoding option and DC-Ultra)
WCDMA Library 3

■ The design can be simulated in pure C or as ■ Primary Control Physical Channel ■ CRC generation
a mix of C and generated HDL by using the (PCCPCH) ■ Pilot symbol generation
Signal Processing Designer HDS option and ■ Paging Indicator Channel (PICH) ■ First and second interleaver
the BER results can be verified. ■ 16 channel Orthogonal Channel Noise ■ Fixed and flexible frame positions
Downlink STTD Channel Simulator (OCNS) ■ OVSF code generation
This reference system is the same as the ■ Long and short scrambling code generation
Channel Model Details
Downlink Channel, except that it imple- ■ Dynamic runtime control of scrambling ■ Static, fading cases 1 through 4, moving
ments Space Time Transmit Diversity in the code group and number and birth-death channel conditions
transmitter and receiver models. The system
Channel Model Details Receiver Model Details
can be used to verify the DCH demodulation ■ Static, fading cases 1 through 4, moving ■ Ideal diversity receiver model
performance requirements in 3GPP TS
and birth-death channel conditions
25.101 section 8.6.1. ■ Compressed mode supported
Receiver Model Details
■ First and second deinterleaver
■ Slot alignment through weighted multi-slot
Downlink Searcher ■ CRC checking
averaged matched filter output
This reference system has the same transmitter
■ Group indicator codes (GIC) through weight- ■ Transport format combination
and channel model as the Downlink Channel,
ed Hadamard transform peak detection indicator decoding
but the receiver is replaced with a searcher.
The searcher is a practical model that uses a ■ Frame alignment and group code through ■ Turbo code scaling
matched filter to find and sort the strongest table matched group indicator codes ■ Viterbi decoder
received signal paths. The searcher model ■ Scrambling code selection through short ■ Turbo decoder supporting two
can find up to six simultaneous signal paths. term correlation different algorithms
■ Rate de-matcher
Fast Cell Search Uplink Channel
The Uplink Channel reference system models ■ Block error rate and bit error rate
The Fast Cell Search reference system models
single, high bandwidth data link from the user is calculated
the procedure a mobile must perform to
synchronize itself with the basestation. The terminal to the base station. In its standard Uplink HSUPA
cell search is done in three phases. First the configuration the uplink reference system The Uplink HSUPA reference system models
primary synchronization channel (PSCH) is multiplexes two transport channels, DTCH the E-DCH (Enhanced Dedicated Channel)
used to obtain slot synchronization. Second, and DCCH, onto a single physical channel for and E-DPCCH (Enhanced Physical Control
the secondary synchronization channel transmission. However just like the downlink Channel) as described in 3GPP Release 6. It
(SSCH) is used to obtain frame synchroniza- the number of transport channels can easily supports all UE Categories and is configured
tion and to discern the code group for the be modified. The uplink uses two channel to run the performance requirements
basestation’s scrambling code. Finally the models to simulate a basestation using an described in TS 25.104 section 8.11. The
scrambling code is selected from the 8 possi- ideal diversity receiver. The standard measure- system includes transmitters for all Uplink
ble long codes in the long code group. ment channels 12.2kbps, 64kbps 144kbps and channels and diversity receivers for E-DPDCH
384kbps can easily be simulated by using and E-DPCCH. The system configuration can
An interactive display shows the slot and parameter presets. This reference system easily be changed by disabling HS-DPCCH
frame offset, the code group and the selected can be used to verify the DCH demodulation and/or DPDCH and turning off diversity. The
scrambling code. The interactive display also performance requirements in 3GPP TS E-DCH uses information from the E-DPCCH
allows the code group, code number and 25.104 sections 8.2, 8.3, 8.4 and 8.5. receiver for reception and decoding. The
channel delay to be altered while the simula-
Transmitter Model Details HARQ protocol is implemented and used to
tion is running to observe how quickly the
■ Transport channel generation and coding decode the E-DCH using incremental redun-
fast cell search algorithm reacquires synchro-
dancy combining. After decoding the E-DCH
nization and the scrambling code number. ■ Compressed mode with spreading factor
data is verified through CRC and used to
reduction, higher layer scheduling modes
Basestation Model Details measure the data throughput. As part of the
■ Long and short scrambling code generation HARQ protocol an ACK or NACK is signaled
■ Primary and Secondary Synchronization
Channels (SCH) ■ Transport format combination indicator to the transmitter data source.
coding
■ Common Pilot Channel (CPICH) ■ System includes E-DCH, E-DPCCH, HS-
■ Turbo and convolutional coding
DPCCH, DPCCH and DPDCH uplink channels
WCDMA Library 4

■ Simulation scripts covers 3GPP performance Uplink HSDPA 3GPP standard. The TD-SCDMA reference
requirement tests in TS 25.104 section 8.11 The Uplink HSDPA reference system models systems included in the library are as follows:
■ All Fixed Reference Channels, FRC1-FRC7, in HS-DPCCH (High Speed Dedicated Physical
TD-SCDMA Downlink System
TS 25.104 Annexes A.9 to A.11 parametrised Control Channel) that transmits feedback
information for an associated HS-DSCH
■ Uses same channel encoder/decoder as
■ E-DCH and E-DPCCH models support 2 3GPP uplink system
channel from the user terminal to the base
or 10 ms TTI
station. ■ Uses same set TFC block as 3GPP downlink
■ Included DPDCH and HS-DPCCH transmit- system
ter models can be turned on or off ■ HS-DPCCH implementation including CQI ■ Frame processing includes bit scrambling
■ Receiver diversity can be enabled or disabled and HARQ-ACK
■ Second interleaver can operate over frames
■ Compressed Mode supported in both 2 ■ Ideal HS-DPCCH diversity receiver model
or timeslots
and 10 ms TTI mode ■ CQI encoding and decoding models ■ Modulation using QPSK, 8-PSK or 16-QAM
■ HSUPA Category 6 UE:s with 5.76 Mbps ■ HS-DPCCH mapping to I or Q branch is (only QPSK and 8-PSK used in normative
max bitrate supported configurable channels)
■ Hybrid-ARQ protocol with retransmissions ■ Full downlink DPDCH and DPCCH coding ■ 1–16 Physical channels, all with the same
and combining implemented and transmission included in system spreading factor
■ E-DCH Turbo and E-DPCCH Reed-Muller ■ Uplink DPDCH transmitter supports ■ OVSF channelization codes are phase
encoding and decoding included dynamic multi-code shifted based on length and code number.
■ E-DPDCH models support 1,2 or 4 physical ■ Compressed Mode is supported ■ Spread data is scrambled before inserting
channels midamble
Uplink RACH Message Reception
■ E-DPDCH models supports spreading ■ Normative channels for 12.2, 64, 144, 384
The Random Access Channel Message
factors 256 to 2 and 2048 kbps
Reception reference system consists of message
■ E-DPDCH IQ branch mapping using frame generator, a transmitter, a channel model ■ 0–16 Channels of other users, DPCHo
Nmax-dpdch and HS-DSCH configuration and an ideal receiver that measures the block TD-SCDMA Uplink System
parameters error rate. The RACH message frames are con- ■ Uses same channel encoder/decoder as
■ E-DPCCH E-TFCI, Retransmission Sequence volutionally coded and a combined with a con- 3GPP uplink system
Number and happy fields implemented trol frame consisting of pilot and TFCI symbols. ■ Uses same set TFC block as 3GPP
■ 3GPP Channel Model with five presets, The receiver model uses diversity to increase
downlink system
Pedestrian A, Pedestrian B, Vehicular 30, performance. The system supports all the test
cases in the 3GPP TS 25.104 section 8.7.2 per-
■ Frame processing includes bit scrambling
Vehicular 120 or AWGN
formance requirements. ■ Second interleaver can operate over frames
■ Selectable channel model oversampling
or timeslots
rate (1x, 2x, 4x or 8x)
Uplink RACH Preamble Detection ■ Modulation using QPSK, 8-PSK or 16-QAM
■ Transmitter data source supports E-DCH
This verification system models the detection (only QPSK used in normative channels)
frame retransmissions
of transmitted RACH preamble sequences. ■ OVSF channelization codes are phase
■ Data throughput collected and calculated The preamble sequences are generated and shifted based on length and code number.
■ ACK/NACK or DTX generated and signalled transmitted over the standard 3GPP channel ■ Spread data is scrambled before inserting
to transmitter with optional channel model. A non-ideal diversity receiver uses
midamble
degeneration matched filters to detect the sequence. Only
a predetermined preamble signature can be
■ 1 or 2 physical channels with different
■ Models allow Transport Block Size,
detected. This system can be used to verify spreading factors
Redundancy Version, Spreading Factor and
number of physical channels to change the RACH performance requirements in ■ Normative channels for 12.2, 64, 144,
during simulation 3GPP TS 25.104 section 8.7.1. 384 kbps
■ Ideal E-DCH and E-DPCCH diversity
■ 0–8 Independent transmitters (other
receiver models The Signal Processing Designer TD-SCDMA Library users), DPCHo.
The Time Division— Synchronous CDMA
■ Uplink DPDCH transmitter supports
(TD-SCDMA) library covers the Low Chip
dynamic multi-code
Rate (LCR) Time Division Duplex (TDD) of the
WCDMA Library 5

Key Library Blocks Partial list of HSDPA blocks ■ Uplink DPCCH Frame Format
Partial list of downlink blocks ■ HARQ Combiner ■ Uplink DPDCH Frame Format
■ Compressed Mode Gain ■ HARQ Interleaver Partial list of HSUPA blocks
■ Downlink Common Channels ■ HARQ Transport Block Source ■ HSUPA Data Source
■ Downlink Common Channels STTD ■ HSDPA Channel Coefficient Estimation ■ HSUPA Redundancy Version Generator
■ Downlink Demodulation ■ HSDPA Rate Dematch Stage 1 ■ E-DCH Encoder
■ Downlink Frame Deformat ■ HSDPA Rate Dematch Stage 2 ■ E-DCH Interleaver and Deinterleaver
■ Downlink Frame Format ■ HS-DSCH Rate Match ■ E-DCH Rate Dematch
■ Downlink Frame Processing ■ HS-DSCH Bit Scramble ■ E-DCH Rate Match
■ Downlink Ideal Receiver ■ HS-DSCH Constellation Rearrangement ■ E-DCH TBS Calculation
■ Downlink Ideal Receiver and Deformatting ■ HS-DSCH CRC Check ■ E-DPCCH Decoder
■ Downlink Ideal STTD Receiver and ■ HS-DSCH Decoder ■ E-DPCCH Encoder
Deformatting HS-DSCH Demodulator
■ ■ E-DPCCH Receiver
■ Downlink Rate Match HS-DSCH De-scrambler
■ ■ E-DPCCH Transmitter
■ Downlink Scramble HS-DSCH Encoder
■ ■ E-DPDCH Decoder
■ Downlink Scramble and Filter HS-DSCH Interleaver
■ ■ E-DPDCH Frame Deformat
■ Downlink Single Code Spreading HS-DSCH Modulator
■ ■ E-DPDCH Frame Format
■ Downlink Single Code STTD Transmit HS-DSCH Multicode Demodulator
■ ■ E-DPDCH Receiver
■ Downlink Single Code Transmit HS-DSCH Multicode Spreader
■ ■ E-DPDCH Transmitter
■ Downlink Symbol Derepeat HS-DSCH Receiver
■ ■ HARQ Combiner
■ Downlink Symbol Repeat HS-DSCH Scrambler
■ ■ HSPA Data Throughput
■ Downlink TrCH Decode HS-DSCH Transmitter
■ ■ Multi Channel Despreader
■ Downlink TrCH Encode HS-SCCH CRC Check
■ ■ Single Channel Despreader
■ Downlink Turbo Scaling HS-SCCH Decoder
■ ■ ACK/NACK/DTX Generator
■ First Interleaver HS-SCCH Demodulator
■ Partial list of uplink blocks
■ Hierarchical Golay Seqeunce ■ HS-SCCH Encoder ■ Uplink Demodulator
■ OVSF Code Generator ■ HS-SCCH Rate Match 1 ■ Uplink Frame Deformat
■ Paging Indicator Channel ■ HS-SCCH Rate Match 2 ■ Uplink Frame Derepeat
■ PN Sequence Generator ■ HS-SCCH Receiver ■ Uplink Frame Format
■ Primary Common Control Physical ■ HS-SCCH Spreader ■ Uplink Frame Processing
Channel
■ HS-SCCH Transmitter ■ Uplink Gain Calculation
■ Primary Synchronization Channel
■ HS-SCCH UE Specific Demasking ■ Uplink Ideal Receiver
■ Second Interleaver
■ HS-SCCH UE Specific Masking ■ Uplink Ideal Receiver and Deformat
■ Secondary Synchronization Channel
■ Multicode Demodulator ■ Uplink Long Code Generator
Downlink Searcher
■ Multicode Slot Deformat ■ Uplink Rate Match
■ Secondary Synchronization Code Decoder
■ Multicode Slot Format ■ Uplink Scramble and Filter
■ STTD Encode
■ Multicode Spreading ■ Uplink Scrambling Code
■ STTD Frame Encode
■ HS-DPCCH CQI decoder ■ Uplink Single Code Spreading
■ TFCI Decode
■ HS-DPCCH CQI encoder ■ Uplink Single Code Transmit
■ TFCI Encode
■ HS-DPCCH Receiver ■ Uplink Symbol Derepeat
■ HS-DPCCH Transmitter ■ Uplink Symbol Repeat
WCDMA Library 6

■ Uplink TrCH Decode Partial list of propagation model blocks Customer Focus
■ Uplink TrCH Encode ■ 3GPP Channel CoWare provides a complete range of training,
Channel Delays support, design methodology consulting, and
■ Uplink Turbo Scaling ■
integration services. Technical support
Partial list of RACH blocks ■ Channel Weights and Filter
requests are handled directly by experienced
■ Pilot Generator ■ Complex Gaussian Noise design engineers who are fully familiar with
■ Preamble Generator ■ Compressed Mode Control Block the application of CoWare tools and method-
■ RACH Preamble Diversity Detector ■ OCNS Generator ologies to real-world designs. Training courses
are available at CoWare offices or at the cus-
■ RACH Uplink Control Format ■ STTD OCNS Generator
tomer site and can be tailored to meet the
■ RACH Uplink FFT Detector Partial list of channel coding blocks specific needs of the design team.
■ RACH Uplink Ideal STTD Receiver ■ Convolutional Encoder
■ RACH Uplink Ideal STTD Receiver and ■ MAP Decoder Sales Offices
Deformat ■ Recursive Convolutional Encoder CoWare has sales offices in the U.S., Europe,
■ RACH Uplink Preamble Detector Asia Pacific and Japan. For a complete
■ Turbo Decoder
listing with contact information visit
■ RACH Uplink Transmit ■ Turbo Demultiplex www.coware.com. For technical or sales
Partial list of practical receiver blocks ■ Turbo Interleaver information call 1-888-CoWare8 or email
■ Comparator and Chip Adjustment ■ Turbo Multiplex info@coware.com.
■ Correlate and Dump ■ Vector CRC
■ Golay Sequence Match Filter ■ Viterbi Decoder
■ Loop Filter ■ Signal creation
■ Practical Rake Receiver and Slot Deformat The SIgnal Processing Designer WCDMA
■ Practical Rake Receiver Finger library offers the designer a faster way to
Partial list of practical receiver RTL blocks market with improved opportunity for first-
time success. The library enables a design
■ Practical Rake Receiver Combiner
team to quickly build complete system mod-
■ Coherent Delay Locked loop els including all the major systems of a net-
■ Practical Rake Receiver Finger work or personal communications device.
■ Pilot Power Estimation Appropriate portions of the system model
can be refined to generate RTL and the test-
■ Downlink Scrambler-long Code Generator
bench shared with other team members. As
■ OVSF Code Gen-Short Code Generator we move forward, CoWare will continue to
■ Rake Signal Combiner track standards changes and offer the best
■ DLL Control libraries for your development efforts.
■ Rake Finger Control
■ Pilot Power Control

The ESL Design Leader


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