Sensitivity and PSRR Enhancement of RF Amplifiers https://www.highfrequencyelectronics.com/index.php?option=com_co...

Sensitivity and PSRR Enhancement of RF Amplifiers

Parent Category: 2018 HFE

By Michael Hopkins

High sensitivity performance in amplifier design, in the presence of noise, has traditionally been a sought-after design goal since the early days of
electronics design. Typically, the SNR struggle has focused on the reduction of the effects of classical noise sources, enabling increased sensitivity
in amplifier systems.

With the advent of the embedding of Digital Signal Processing (DSP) in amplifier systems, a new source of noise distortion has been introduced into
sensitive Analog and RF Amplifier systems. This noise is high in frequency in nature, and propagates not only through traditional supply and
ground lines, but also through the substrate in chip designs.

This high frequency noise is the result of the logic action and overlap current generated by CMOS logic circuits in DSP blocks, and is a significant
source of sensitivity decreases in modern RF amplifier systems.

Figure 1 shows an RF Amplifier with high gain, bandwidth, and sensitivity. As with all high performance analog and RF amplifiers and systems,
PSRR is critical in enhancing and maintaining spectral output performance. In High Speed and RF amplifiers that are resident with digital circuits
and processing, design efforts are generally focused initially on obtaining the highest performance in a pure supply environment, with PSRR
concerns of secondary importance. It is always assumed that analog/RF and digital supply separation, bypassing, current mode techniques, etc. will
mitigate any output signal corruption due to system supply and ground line non-idealities.

Figure 1 • Typical RF Amplifier with Embedded DSP.

High Sensitivity

For highly sensitive amplifiers, the common supply isolation techniques mentioned above work only to a point. Figure 2 shows the effects of
digitally induced noise on system outputs utilizing the common noise mitigation, supply isolation techniques. Given a perfect simulation supply, the
top output plot in Figure 2 shows the time domain result of a -146 dBm sine wave signal at 990Mhz, input into a LNA/RF Amplifier and
Subsampling Track and Hold (not shown). The clean output waveform is what one would expect in a pure simulation environment.

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Figure 2 • The effect of Digital Noise on Amplifier Outputs with and without Silicon Super Cap IP.

Given a -143dBm sine wave RF input at 990Mhz and a realistic power grid model shown in Figures 1, 6, and 7, coupled with Silicon Super Caps
used as bypass caps, one obtains a time domain waveform as seen in the middle output plot of Figure 2. It should be noted that without the Silicon
Super Caps, the output waveform degrades to the waveform shown in the lower output plot of Figure 2.

Figure 3 • Typical on Chip DCAP performance vs Silicon Super Cap IP.

Dropping the magnitude of the sine wave RF input signal to -146dBm, using the supply grid in Figures 1, 6, and 7, and Super Cap IP, as shown in
Figures 6 and 7, the RF amplifier and Track and Hold produce a plot similar to the lower output plot in Figure 2. The remaining waveforms (RF
signal and current sources in the lower plots in Figure 2) show noise contamination that contributes to the noise distortion in the lower output
waveform of Figure 2.

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Figure 4 • Supply Noise Spectrum Without the Silicon Super Caps Engaged.

Thus, a -3 dBm increase in RF Amplifier performance is seen utilizing the Silicon Super Cap IP in conjunction with common on-chip Power Supply
isolation techniques shown in Figures 1, 6, and 7. Figure 3 shows, as a point of reference, the difference in supply power draw given typical on-chip
DCAPs verses the Silicon Super Capacitor IP.

Figure 5 • Supply Noise Spectrum With the Silicon Super Caps Engaged.

Real World Measurements

With typical noise levels set to a maximum limit of 50mVpp or -22dBm of supply signal power (see Figure 4), and if amplifier circuits have almost
zero PSRR at the highest noise peak frequency induced on the system supply line, amplifier output signal corruption will occur. In reality, PSRR is
rarely zero, but generally does approach zero as one moves up in supply line frequency. At high frequencies, MOSFET device capacitances override
the gm of each device, thus creating a system PSRR that would not be acceptable in most applications.

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Figure 6 • Typical RF Amplifier with Embedded DSP and the IC form of the Silicon Super Cap IP.

Using analog/RF and digital supply separation, bypassing, and current mode techniques, improvement RF Amplifier and system sensitivity will be
obtained. On chip, however, one has limited space and must use capacitive components with relatively low capacitance density when compared to
off chip capacitive components.

The Silicon Super Capacitor IP, shown in Figures 6 and 7, features at least a 2X improvement in effective capacitance per unit area with respect to
typical on-chip MOS decoupling capacitors, with an added 25% reduction in capacitor effective series inductance (ESL). The IP feeds back a
portion (nominally 20%) of the bypass current flowing through on chip decoupling capacitors onto the chip power grid, thus reducing overall chip
dynamic power draw. These effects substantially reduce RF Emissions from chip power grids making systems less vulnerable to cyber hacking and
more secure. The IP draws no DC current , thus maximizing block efficiency.

Figure 7 • Typical RF Amplifier with Embedded DSP and the on-chip IP form of the Silicon Super Cap IP.

The IP block shown in figure 7 is meant to replace on chip decoupling capacitors, thus can be shaped into various aspect ratios and sizes to fit on-
chip “white space,” the area under power grids, etc. in the same fashion as typical on-chip decoupling capacitors. In similar fashion to typical
decoupling capacitors, the IP blocks can be connected in parallel to increase overall RF emission reduction, reservoir capability, and effective
capacitance.

Using a single Silicon Super Cap device, the supply noise reduction shown in the top spectral plot of Figure 5, results in a 20% reduction in system
dynamic power draw, and the induced digital supply noise reduces by 11 dBm with respect to the spectrum of the disabled Silicon Super CapIP
(operating with just the nominal input capacitance), shown in the Figure 4 plot.

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Figure 8 • Silicon Super Cap IP S11 Disengaged Input Return Loss-Lowest Impedance Point: 370Mhz.

Using multiple Silicon Super Capacitor devices (3 in this case), yields the same dynamic power reduction as with a single device, but produces an
additional 3 dBm noise power reduction magnitude to -36dBm and a noise spectrum decrease from 650 Mhz (the single device case) to 500 Mhz
(the 3x device case) as seen in the lower plot in Figure 5.

Figure 9: Silicon Super Cap IP S11 Engaged Return Loss-Lowest Impedance Point: 170Mhz.

Figures 6 and 7 show Silicon Super Capacitor Implementations in the power grids of highly sensitive RF amplifiers both on and off chip. Figure 6
shows the off chip, Silicon Super Capacitor Test Chip implemented on IBM (Global Foundries) GF_018RF, a 180nm manufacturing process. In this
implementation, the base input capacitance is 11uF and the effective capacitance increase is 11uF, yielding a total device capacitance of
approximately 22uF for the device.

One can see this capacitance increase on the Silicon Super Capacitor Test Chip with the results of the S11 plots in Figures 8 and 9.

In Figure 8, with the Silicon Super Cap IP disengaged, looking exclusively into the 11uF input base capacitance, the best return loss/SWR and the
lowest impedance point occurs at 370Mhz (-64dB) and corresponds to a capacitive low impedance magnitude of 39 Micro Ohms. A short math
proof is as follows.

Equation 1:

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Using the Silicon Super Cap IP data, the lowest impedance point frequency in the figure 8 plot, as well as the “Best” return loss and SWR numbers
from the Network Analyzer, gives

Solving yields

Which, within measurement and error tolerances, the results are essentially equal.

Using the same base input capacitance, 11uF, and engaging the Silicon Super Capacitor IP, the best return loss/SWR the transfer function lowest
impedance point is translated down to 170Mhz (-56.3dB), as seen in Figure 9. Accounting for a +7 dBm scaling with respect to the Figure 8 plot,
this due to return currents flowing from the Silicon Super Capacitor IP output into the Network Analyzer detectors, the low impedance point
corresponds to a capacitive low impedance of 42 Micro Ohms. This low impedance dip in Figure 9 fits the impedance and frequency characteristic
that would be seen utilizing a standard 22uF capacitance. This measurement confirms the effective capacitance increase generated by the action of
the Silicon Super Capacitance IP. The math for this condition as follows.

Equation 2:

Using the Silicon Super Cap IP data, the lowest impedance point frequency in the Figure 9 plot, as well as the “Best” return loss and SWR numbers
from the Network Analyzer gives

Solving yields

Which, within measurement and error tolerances, the results are essentially equal.

Referring back to Figure 7, the Silicon Super Capacitor IP cell is implemented on the IBM (Global Foundries) GF_018RF 180nm manufacturing
process. In this implementation, the base input capacitance is 16pF and the effective capacitance increase is 16pf, yielding a total capacitance of
approximately 32pF for the IP cell. The Silicon Super Capacitor IP cell is the same architecture as is in the Silicon Super Capacitor Test Chip, the
only difference is the IP cell has the input and output capacitors included on chip. The IP cell can be paralleled for increased overall capacitance,
like any other standard DCAP.

Conclusions

Utilizing the Silicon Super Capacitor IP demonstrates a substantial improvement in Analog and RF circuit sensitivity and signal cleanliness due to
the additional effective capacitance the device and IP cell provide. With the increased effective capacitance per unit area with respect to standard
DCAPs and the higher levels of noise immunity, increased amplifier sensitivity and spectral cleanliness can be achieved, and dynamic current flow
from the supply minimized. The Silicon Super Capacitor IP effective capacitance increase can be seen in supply line noise reduction, output signal
cleanliness, input signal sensitivity increases, and movement of low impedance points in the S11 return loss/transfer function plots with and without
the Silicon Super Capacitor devices engaged.

About the Author

Michael Hopkins is the CEO and founder of CurrentRF, a California based research and development company, founded in 2002.
Through activities with CurrentRF, Michael developed the RFDAC methodology and Current Reuse Mixer (the CRF2101) in
2002, and more recently, the PowerOptimizer (PowerOp) and Silicon Supercapacitor methodologies and technologies
(subsystems, chips, IP) the company is currently marketing.

Michael is also an RF/Analog IC design engineer with 20 years of RFIC and Mixed Signal/Analog design experience with

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companies such as Analog Devices, Northrop Grumman, Intersil, Teledyne Scientific, and Cypress Semiconductor (Amplifiers,DACs, ADCs,
Mixers, Switch Mode Regulators, High Efficiency Charge Pumps, DLLs/PLLs, Energy Harvesting Circuits, etc.). His unique and wide experience
across the Communications, Analog/Mixed Signal, RF, Power Management, and Energy Harvesting disciplines in the semiconductor industry has
enabled the latest CurrentRF development, the CC-100 IC and IP PowerOptimizer (PowerOp), the Silicon Super Capacitor, and its derivative
products.

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