Lovely Professional University, Punjab

Course Code Course Title Course Planner Lectures Tutorials Practicals Credits
CAP208 COMPUTER ORGANIZATION AND DESIGN 11111::Rishi Chopra 4 0 0 4
Course Weightage ATT: 5 CA: 25 MTT: 20 ETT: 50 Exam Category: 13: Mid Term Exam: All MCQ – End Term Exam: MCQ +
Subjective
Course Orientation KNOWLEDGE ENHANCEMENT

TextBooks ( T )
Sr No Title Author Publisher Name
T-1 COMPUTER SYSTEM MORRIS MANO PEARSON
ARCHITECTURE
Reference Books ( R )
Sr No Title Author Publisher Name
R-1 COMPUTER ORGANIZATION V RAJARAMAN PRENTICE HALL
AND ARCHITECTURE
R-2 COMPUTER ARCHITECTURE A DAVID A PATTERSON PRENTICE HALL
QUANTITATIVE APPROACH
R-3 COMPUTER ORGANIZATION WILLIAM STALLINGS PEARSON
AND ARCHITECTURE:
DESIGNING AND PERFORMANCE
R-4 COMPUTER ORGANIZATION V. CARL HAMACHER, MCGRAW HILL EDUCATION
SAFWAT G. ZAKY AND
ZVONKO G. VRANESIC
Other Reading ( OR )

Sr No Journals articles as Compulsary reading (specific articles, complete reference)

OR-1 http://jes.eurasipjournals.com/content/2009/1/758480 ,

Relevant Websites ( RW )
Sr No (Web address) (only if relevant to the course) Salient Features
RW-1 http://www.cs.iastate.edu/~prabhu/Tutorial/title.html Brief introduction about addressing Modes and Instruction formats

RW-2 http://www.tutorialspoint.com/computer_logical_organization/ Practical examples on Number System and gates

RW-3 http://www.labri.fr/perso/strandh/Teaching/AMP/Common/Strandh-Tutorial/Dir.html Explanation of Registers and Multiplexers

RW-4 http://bottomupcs.sourceforge.net/csbu/c1453.htm Components of CPU explained

RW-5 http://www.personal.kent.edu/~rmuhamma/ComArchitec/comArchitec.html Explanation of Pipeline Processing

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
 Audio Visual Aids ( AV )
Sr No (AV aids) (only if relevant to the course) Salient Features
AV-1 http://nptel.ac.in/video.php?subjectId=106102062 Explanation of Instruction sets, Memory Hierarchy and Input output
subsystems
AV-2 http://freevideolectures.com/Course/2274/Computer-Architecture# Introduction to computer architecture
AV-3 https://www.youtube.com/watch?v=BJ87rZCGWU0 Basics of computer architecture

LTP week distribution: (LTP Weeks)

Weeks before MTE 7
Weeks After MTE 7
Spill Over (Lecture) 8

Detailed Plan For Lectures

Week Lecture Broad Topic(Sub Topic) Chapters/Sections of Other Readings, Lecture Description Learning Outcomes Pedagogical Tool Live Examples
Number Number Text/reference Relevant Websites, Demonstration/
books Audio Visual Aids, Case Study /
software and Virtual Images /
Labs animation / ppt
etc. Planned
Week 1 Lecture 1 Register Transfer and T-1 L1:Introductory lecture L1:As a result of this Blend of
Microoperations(Number R-1 L0: Lecture 0 lecture student will powerpoint
System) understand the presentation with
importance of AV
computer architecture
its design and
organization
Lecture 2 Register Transfer and T-1 L2: Detailed explanation L2: As a result of this Demonstration 1's complement
Microoperations of Number System lecture student will using board or of 1100 is 0011
(Compliments) including understand that how presentation 2's complement
Binary,Decimal, Octal users in different of 1100 is
and Hexadecimal langauge can interact 0011+1=0100
L3: Complements of with computers in
number like 1's binary form.
complement,2's L3:Students will
complement,9's learn to do the
complement,10's complements of the
complement etc. any given number

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 1 Lecture 3 Register Transfer and T-1 L2: Detailed explanation L2: As a result of this Demonstration 1's complement
Microoperations of Number System lecture student will using board or of 1100 is 0011
(Compliments) including understand that how presentation 2's complement
Binary,Decimal, Octal users in different of 1100 is
and Hexadecimal langauge can interact 0011+1=0100
L3: Complements of with computers in
number like 1's binary form.
complement,2's L3:Students will
complement,9's learn to do the
complement,10's complements of the
complement etc. any given number
Lecture 4 Register Transfer and T-1 L4: Floating point L4: Student will learn Demonstration on 10.0111 to
Microoperations(Fixed point R-2 numbers and its the conversion of white board decimal:
and floating point explanation floating point
representation) L5: Fixed Point numbers into other
representation that number systems
includes arithmetic L5: Student will learn
addition and subtraction the difference
between fixed point
representation and its
error detection
Week 2 Lecture 5 Register Transfer and T-1 L4: Floating point L4: Student will learn Demonstration on 10.0111 to
Microoperations(Fixed point R-2 numbers and its the conversion of white board decimal:
and floating point explanation floating point
representation) L5: Fixed Point numbers into other
representation that number systems
includes arithmetic L5: Student will learn
addition and subtraction the difference
between fixed point
representation and its
error detection
Lecture 6 Register Transfer and T-1 RW-1 Implementation of half As a result of this Demonstration Addition of 2
Microoperations(Register RW-2 adder and full adder lecture students will using presentation bits or 3 bits
Transfer) come to know the using with or
implementation of without carry
logic gates in
designing the circuits
Lecture 7 Register Transfer and T-1 RW-2 Basic of Register Student will learn Blend of R3<- R1+R2 i.e.
Microoperations(Register R-3 RW-3 Transfer Language about the powerpoint adding the
Transfer Language) communication of presentation with contents of
registers and their AV register 2 and
communication register 3 and
language then transfer the
result into
register 1

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 2 Lecture 8 Register Transfer and T-1 Implementation of 3 Student will learn the Demonstration on Connectivity of
Microoperations(Bus and state bus buffers and transferring of white board 4 bit register
Memory Transfer) memory transfer information from one that includes
register to another mesh
using bus system of 4 connectivity by
registers connecting each
bit of register
with each bit of
multiplexer
Week 3 Lecture 9 Register Transfer and T-1 L9: Arithmetic micro L9: Students will Demonstration on Increment,Decre
Microoperations(Arithmetic operations in detail understand different white board ment, Binary
Microoperations) L10: Implementation of micro operation Addition, Binary
arithmetic operations along with symbolic Subtract, 1s
using circuit diagram structure complement,2s
L10: As a result of complement.
this lecture students
will be able to
understand the
implementation of all
the arithmetic micro
operations using
single circuit
Lecture 10 Register Transfer and T-1 L9: Arithmetic micro L9: Students will Demonstration on Increment,Decre
Microoperations(Arithmetic operations in detail understand different white board ment, Binary
Microoperations) L10: Implementation of micro operation Addition, Binary
arithmetic operations along with symbolic Subtract, 1s
using circuit diagram structure complement,2s
L10: As a result of complement.
this lecture students
will be able to
understand the
implementation of all
the arithmetic micro
operations using
single circuit
Lecture 11 Register Transfer and T-1 RW-3 Logic Micro operations As a result of this Powerpoint 1100 AND 0101
Microoperations(Logic and its applications lecture student will presentation will give 0100
microoperations) come to know how to
apply different logic
micro operations
Lecture 12 Register Transfer and T-1 RW-2 Implementation and Students will be able Powerpoint Logical shift left
Microoperations(Shift detailed explanation of to understand the presentation on 1100 will
Microoperations) shift micro operations difference between give 1000
logical shift left and
right or circular shift
left and right

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 4 Lecture 13 Instruction Codes and T-1 AV-1 Explanation of As a result of this Demonstration Size of memory
Instruction Cycle(Instruction Instruction codes, lecture students will using white board in basic
codes) illustration of stored come to know the computer is
program organization size of basic 4096 * 16 which
and difference of direct computer's memory, states that
and indirect addressing its addressing and memory consists
difference between of 4096 words
direct and indirect and each word is
addressing 16 bits in length
Lecture 14 Instruction Codes and T-1 AV-1 L14: Brief introduction L14: Students will Blend of L14: PC is used
Instruction Cycle(Common of all the registers being come to know the powerpoint to store the
Bus System) used in basic computer size and functionality presentation with address of next
L15: Implementation of of each register used AV instruction like
common bus system to L15: Students will we used to
ensure the efficient understand how implement one
communication different registers counter outside
between registers used to communicate the classroom
by having less which denotes
circuitry involved that the next
students who
entered the class
will sit on which
particular seat
Lecture 15 Instruction Codes and T-1 AV-1 L14: Brief introduction L14: Students will Blend of L14: PC is used
Instruction Cycle(Common of all the registers being come to know the powerpoint to store the
Bus System) used in basic computer size and functionality presentation with address of next
L15: Implementation of of each register used AV instruction like
common bus system to L15: Students will we used to
ensure the efficient understand how implement one
communication different registers counter outside
between registers used to communicate the classroom
by having less which denotes
circuitry involved that the next
students who
entered the class
will sit on which
particular seat
Lecture 16 Instruction Codes and T-1 Detailed explanation of As a result of this Demonstration
Instruction Cycle(Types of different types of lecture students will using white board
instructions) instruction using their understand the
formats representation of 3
different types of
instructions in
memory

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 5 Lecture 17 Instruction Codes and T-1 AV-3 L17: Timing and control Students will learn Demonstration Instruction1 will
Instruction Cycle(Timing structure representation the timing sequence using white board be completed in
and control) L18: Timing and control of instructions in 3 sec and
plus Allocation of test which they execute Instruction 2
will be
completed in 4
secs, then
calculate the
total time taken
to execute the
instruction
Lecture 18 Instruction Codes and T-1 AV-3 L17: Timing and control Students will learn Demonstration Instruction1 will
Instruction Cycle(Timing structure representation the timing sequence using white board be completed in
and control) L18: Timing and control of instructions in 3 sec and
plus Allocation of test which they execute Instruction 2
will be
completed in 4
secs, then
calculate the
total time taken
to execute the
instruction
Lecture 19 Instruction Codes and T-1 RW-3 L19: Four steps of L19: As a result of Demonstration L19: Fetch,
Instruction Cycle(Instruction R-4 AV-1 instruction cycle along this lecture student using white board decode, read an
Cycle) with Flowchart learn how an effective address
L20: Detailed instruction executes and execute the
explanation of each L20: Students will instruction
memory reference and learn the L20:
register reference functionality of each Add,sub,mul,div
instruction instruction ,mov
instructions
Lecture 20 Instruction Codes and T-1 RW-3 L19: Four steps of L19: As a result of Demonstration L19: Fetch,
Instruction Cycle(Instruction R-4 AV-1 instruction cycle along this lecture student using white board decode, read an
Cycle) with Flowchart learn how an effective address
L20: Detailed instruction executes and execute the
explanation of each L20: Students will instruction
memory reference and learn the L20:
register reference functionality of each Add,sub,mul,div
instruction instruction ,mov
instructions
Week 6 Lecture 21 Machine Language and T-1 OR-1 Machine language and As a result of this Blend of ORG, END,
Programming(Introduction assembly language lecture students will powerpoint MACRO,
of Machine Language) difference along with understand the presentation with MEND are
elements of assembly programmatic AV pseudo
language structure of assembly instructions and
language. cannot be
converted to
machine

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 6 Lecture 21 Machine Language and T-1 OR-1 Machine language and As a result of this Blend of ORG, END,
Programming(Assembly assembly language lecture students will powerpoint MACRO,
Language Basics) difference along with understand the presentation with MEND are
elements of assembly programmatic AV pseudo
language structure of assembly instructions and
language. cannot be
converted to
machine
Lecture 22 Machine Language and T-1 RW-1 Assembler first pass and Students will Powerpoint Source code
Programming(Assembler AV-2 second pass understand how presentation (assembly
Basics) assembler converts language) ->
assembly language Assembler ->
program to machine Machine Code
code
Lecture 23 Machine Language and T-1 RW-1 Circuit explaining As a result of this Demonstration P: R1<- R2,
Programming(Arithmetic arithmetic and logic lecture students will using white board (3 + 5) \times 2
and Logic Operation micro programming understand the
programming) implementation of
ALU tasks
Lecture 24 Test 1
Week 7 Lecture 25 Machine Language and T-1 Implementation of Students will learn Powerpoint Language
Programming(program subroutines and program the difference presentation support,
loops) loops between functions Selfmodifying
and subroutines and code,
the use of program Subroutine
loops libraries, Return
by indirect jump
Machine Language and T-1 Implementation of Students will learn Powerpoint Language
Programming(Subroutines) subroutines and program the difference presentation support,
loops between functions Selfmodifying
and subroutines and code,
the use of program Subroutine
loops libraries, Return
by indirect jump
Machine Language and T-1 Implementation of Students will learn Powerpoint Language
Programming(Programming subroutines and program the difference presentation support,
loops) loops between functions Selfmodifying
and subroutines and code,
the use of program Subroutine
loops libraries, Return
by indirect jump
Lecture 26 Machine Language and T-1 AV-1 Input output interfacing Students should learn Discussion and Channel I/O and
Programming(Input-Output AV-2 in Demonstration Port-mapped I/O
programming) AV-3 the lecture about the using white board
programming
examples

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
 SPILL OVER
Week 7 Lecture 27 Spill Over
Lecture 28 Spill Over

MID-TERM
Week 8 Lecture 29 Central Processing Unit T-1 RW-4 L29: Components of L29: Students will Discussion and LC4/MIPS/x86
(General Register CPU, Control word come to know the demonstration Registers
Organization) L30: CPU organizations basic parts of CPU using white board
and micro operations L30: Students will
come to know the
different ways of
organization of a
computer
Lecture 30 Central Processing Unit T-1 RW-4 L29: Components of L29: Students will Discussion and LC4/MIPS/x86
(General Register CPU, Control word come to know the demonstration Registers
Organization) L30: CPU organizations basic parts of CPU using white board
and micro operations L30: Students will
come to know the
different ways of
organization of a
computer
Lecture 31 Central Processing Unit T-1 RW-4 L31: Basics of control L31: Students will Discussion and STACK-> LIFO
(Organization of stacks) word, stacks and learn the basic data demonstration PUSH-> Insert
operations on stacks structure stack before using powerpoint new element
L32: Register stack staring its presentation POP-> Remove
organization along with implementation from TOS
PUSH, POP L32: Students will
L33: Memory stack understand the
organization along with representation of
PUSH,POP stacks in registers
L33: Students will
come to know the
memory
representation of
stacks

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 8 Lecture 32 Central Processing Unit T-1 RW-4 L31: Basics of control L31: Students will Discussion and STACK-> LIFO
(Organization of stacks) word, stacks and learn the basic data demonstration PUSH-> Insert
operations on stacks structure stack before using powerpoint new element
L32: Register stack staring its presentation POP-> Remove
organization along with implementation from TOS
PUSH, POP L32: Students will
L33: Memory stack understand the
organization along with representation of
PUSH,POP stacks in registers
L33: Students will
come to know the
memory
representation of
stacks
Week 9 Lecture 33 Central Processing Unit T-1 RW-4 L31: Basics of control L31: Students will Discussion and STACK-> LIFO
(Organization of stacks) word, stacks and learn the basic data demonstration PUSH-> Insert
operations on stacks structure stack before using powerpoint new element
L32: Register stack staring its presentation POP-> Remove
organization along with implementation from TOS
PUSH, POP L32: Students will
L33: Memory stack understand the
organization along with representation of
PUSH,POP stacks in registers
L33: Students will
come to know the
memory
representation of
stacks
Lecture 34 Central Processing Unit T-1 RW-1 Infix, prefix and post fix Learn about different Discussion and 5 1 2 + 4 × +
(Reverse Polish Notation) RW-4 notations types of notations Demonstration of 3
AV-3 Animation -.The expression
is evaluated left
toright
Lecture 35 Central Processing Unit(One T-1 RW-1 Implementation of zero Learn about three Demonstration Addition of R2
Address Instructions) RW-4 address and one address address instruction using white board AND R3 and
instructions with the help of transfer the
example same to R1
Central Processing Unit T-1 RW-1 Implementation of zero Learn about three Demonstration Addition of R2
(Zero Address Instructions) RW-4 address and one address address instruction using white board AND R3 and
instructions with the help of transfer the
example same to R1
Lecture 36 Central Processing Unit T-1 RW-1 Implementation of three Student will learn its Demonstration on Add R1,R2,R3
(Three address Instructions) AND two implementation white board
address instruction
Central Processing Unit T-1 RW-1 Implementation of three Student will learn its Demonstration on Add R1,R2,R3
(Two Address Instructions) AND two implementation white board
address instruction

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 10 Lecture 37 Central Processing Unit T-1 RW-1 L37:Discussion of L37: Students will Demonstration L37: Register
(Addressing Modes) addressing modes learn the types of using white board Direct and
L38: Implementation of addressing in Indirect like
modes using numerical memory finding address
L38: Practical by using
exposure will be correspondance
gained through or permanent
numerical address L38:
One numerical
will discuss the
detail of each
addressing mode
Lecture 38 Central Processing Unit T-1 RW-1 L37:Discussion of L37: Students will Demonstration L37: Register
(Addressing Modes) addressing modes learn the types of using white board Direct and
L38: Implementation of addressing in Indirect like
modes using numerical memory finding address
L38: Practical by using
exposure will be correspondance
gained through or permanent
numerical address L38:
One numerical
will discuss the
detail of each
addressing mode
Lecture 39 Central Processing Unit T-1 RW-4 RISC and CISC Students will learn Demonstration Computers using
(RISC Instructions) characteristics the difference using powerpoint
between RISC and presentation RISC and
CISC processors computers using
CISC
Lecture 40 Pipeline processing(Parallel T-1 RW-5 L40: Parallel processing L40: Students will Blend of Execute 5
processing) L41: Pipeline come to know about powerpoint instructions
Processing parallel processing presentation with simultaneously
and ways to improve AV and calculate the
the efficiency of efficiency
system
L41: Learn that how
pipeline helps to
improve the
efficiency of system
Week 11 Lecture 41 Pipeline processing(Parallel T-1 RW-5 L40: Parallel processing L40: Students will Blend of Execute 5
processing) L41: Pipeline come to know about powerpoint instructions
Processing parallel processing presentation with simultaneously
and ways to improve AV and calculate the
the efficiency of efficiency
system
L41: Learn that how
pipeline helps to
improve the
efficiency of system

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 11 Lecture 42 Pipeline processing T-1 RW-5 L42: implementation of L42: Learn about the Discussion and Addition of
(Instruction and arithmetic arithmetic pipeline addition or demonstration 0.9504 and
pipeline) L43: Implementation of subtraction of two using white board 0.8200
instruction pipeline floating point
numbers
L43: Learn about
how interrupt hinders
the normal flow of
execution
Lecture 43 Pipeline processing T-1 RW-5 L42: implementation of L42: Learn about the Discussion and Addition of
(Instruction and arithmetic arithmetic pipeline addition or demonstration 0.9504 and
pipeline) L43: Implementation of subtraction of two using white board 0.8200
instruction pipeline floating point
numbers
L43: Learn about
how interrupt hinders
the normal flow of
execution
Lecture 44 Pipeline processing(Pipeline T-1 RW-5 Pipeline hazards that Students will learn Powerpoint Data
hazards and their resolution) includes resource that by the use of presentation dependency
conflicts, data conflicts pipeline there are conflict:
and control conflicts certain parameters ADD: R1,R2,R3
that hinders its SUB: R4,R1,R5
execution SUB instruction
is dependent on
the execution of
ADD instruction
Week 12 Lecture 45 I/O subsystems(Input-output T-1 Peripheral Devices and Learn about the use Powerpoint Magnetic tape ,
devices) its implementation of various I/O presentation magnetic disk
devices etc
Lecture 46 I/O subsystems(Interfacing T-1 Interfacing of I/O bus Learn about the Demonstration on Connection of
with IO devices) and Interface modules interface of I/O white board one bus using
systems various devices
Lecture 47 I/O subsystems T-1 AV-1 Asynchronous data Learn about various Powerpoint
(Asynchronous data transfer) AV-2 transfer mechanism transfer mechanisms presentation

Lecture 48 Test 2
Week 13 Lecture 49 I/O subsystems(Concept of T-1 Implementation details Learn about the use Powerpoint CPU-IOP
handshaking) of direct memory of DMA ,its presentation communication
access, Handshaking functions and
handshaking
I/O subsystems(DMA data T-1 Implementation details Learn about the use Powerpoint CPU-IOP
transfer) of direct memory of DMA ,its presentation communication
access, Handshaking functions and
handshaking

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 13 Lecture 50 Memory technology T-1 Hierarchy of memories Learn about the Powerpoint Main memory,
(Memory hierarchy) available different types of presentation Auxiliary
memory present memory, static
and dynamic
Lecture 51 Memory technology(Cache T-1 RAM and Cache Learn about the Powerpoint Selection of
memory and memory difference difference between presentation books from
hierarchy) RAM and cache and Library is
its use MAIN memory
and placing the
selected books
on your book
shelf at your
home is Cache
memory
Memory technology(Cache T-1 RAM and Cache Learn about the Powerpoint Selection of
memory) difference difference between presentation books from
RAM and cache and Library is
its use MAIN memory
and placing the
selected books
on your book
shelf at your
home is Cache
memory
Lecture 52 Memory technology T-1 Implementation and Learn about the use Powerpoint
(Associative memory) components of auxiliary of associative and presentation
memory and associative auxiliary memory
memory
Week 14 Lecture 53 Memory technology(Virtual T-1 Logical and physical Learn about the Discussion and Paging and
memory and memory address space hardware used for demonstration segmentation
management unit) virtual memory using animation hardware can be
management discussed
Lecture 54 Memory technology(Virtual T-1 Logical and physical Learn about the Discussion and Paging and
memory and memory address space hardware used for demonstration segmentation
management unit) virtual memory using animation hardware can be
management discussed

SPILL OVER
Week 14 Lecture 55 Spill Over
Lecture 56 Spill Over
Week 15 Lecture 57 Spill Over
Lecture 58 Spill Over
Lecture 59 Spill Over
Lecture 60 Spill Over

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
 Scheme for CA:

CA Category of this Course Code is:A0203 (2 best out of 3)

Component Weightage
Term paper 50
Test 50
Test 50

Details of Academic Task(s)

Academic Task Objective Detail of Academic Task Nature of Academic Academic Task Marks Allottment /
Task Mode submission
(group/individuals) Week
Term paper To evaluate the As per assigned topics Individual Online 30 3 / 10
performance of
students
Test 1 To test the Basic organization of computers : Block level description of Individual Offline 30 5 / 6
performance of the
students based on functional units,Fetch cycle, Decode and execute
classroom cycle,Machine
teaching instructions : Instruction set architectures, Assembly
language
programming, Addressing modes, Instruction cycles,
Registers
and storage, Inside a CPU ,Information representation :
Floating point representation,Computer arithmetic and their
implementation, Fixed-point arithmetic, Arithmetic addition
and subtraction, Multiplication and Number system
Test 2 To test the Memory technology : Static and dynamic memory,Random Individual Offline 30 11 / 12
performance of access and serial access memories, Cache memory and
students based on memory
classroom hierarchy, Address mapping, Virtual memory and memory
teaching management unit, Cache updation schemes,I/O subsystems :
Input-output devices, Interfacing with IO,devices, Addressing
modes, Instruction formats and pipeline processing

List of suggested topics for term paper[at least 15] (Student to spend about 15 hrs on any one specified term paper)

Sr. No. Topic

1 Cache Coherence

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
 2 Distributed Shared Memory Systems
3 Integrated Memory circuits
4 Memory system organization and architecture
5 Distributed System arhitecture
6 Pipelined processor Architecture
7 Shared Memory MIMD Architecture
8 Distributed Memory MIMD Architecture
9 Study of various RISC & CISC Processors
10 Parallel processing and pipelining
11 Neural Architecture
12 VLSI System Design
13 Memory Hierarchy techniques
14 Energy efficient caching
15 Client server design issues

An instruction plan is a tentative plan only and a teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.