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9. Which of the following is the most widely used alphanumeric code for computer input and output?
A. Gray
B. ASCII
C. Parity
D. EBCDIC
Answer: Option B
10 If a typical PC uses a 20-bit address code, how much memory can the CPU address?
. A. 20 MB
B. 10 MB
C. 1 MB
D. 580 MB
Answer: Option C
27 A binary number's value changes most drastically when the ________ is changed.
. A. MSB
B. frequency
C. LSB
D. duty cycle
Answer: Option A
42 An analog signal has a range from 0 V to 5 V. What is the total number of analog possibilities within this
. range?
A. 5
B. 50
C. 250
D. infinite
Answer: Option D
43 Hexadecimal letters A through F are used for decimal equivalent values from:
. A. 1 through 6
B. 9 through 14
C. 10 through 15
D. 11 through 17
Answer: Option C
55 Determine the decimal equivalent of the signed binary number 11110100 in 1's complement.
. A. 116
B. –12
C. 11
D. 128
Answer: Option C
66 3428 is the decimal value for which of the following binary-coded decimal (BCD) groupings?
. A. 11010001001000
B. 11010000101000
C. 011010010000010
D. 110100001101010
Answer: Option B
67 The binary-coded decimal (BCD) system can be used to represent each of the 10 decimal digits as a(n):
. A. 4-bit binary code
B. 8-bit binary code
C. 16-bit binary code
D. ASCII code
Answer: Option A
88 The American Standard Code for Information Interchange (ASCII) uses how many individual pulses for any
. given character?
A. 1
B. 2
C. 7
D. 8
Answer: Option C
96 Select one of the following statements that best describes the parity method of error detection.
. A. Parity checking is best suited for detecting single-bit errors in transmitted codes.
B. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
C. Parity checking is capable of detecting and correcting errors in transmitted codes.
D. Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes
from one location to another.
Answer: Option A
97 Which of the following is the primary advantage of using the BCD code instead of straight binary coding?
. A. Fewer bits are required to represent a decimal number with the BCD code.
B. The relative ease of converting to and from decimal.
C. BCD codes are easily converted to hexadecimal codes.
D. BCD codes are easily converted to straight binary codes.
Answer: Option B
98 How many BCD code bits and how many straight binary bits would be required to represent the decimal
. number 643?
A. 12 BCD, 12 binary
B. 12 BCD, 10 binary
C. 12 BCD, 9 binary
D. 16 BCD, 9 binary
Answer: Option B
When using the repeated division by 2 method of converting from decimal to binary, one must write the first
remainder as the:
A. MSB
B. MSB, provided the following sequence of remainders are written in descending order until the final
remainder is achieved.
C. LSB
D. LSB, provided the final remainder is used to replace the original LSB, which is then moved to the MSB
position.
Answer: Option A
2. Determine the values of A, B, C, and D that make the sum term equal to zero.
A.A = 1, B = 0, C = 0, D = 0
B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0
D. A = 1, B = 0, C = 1, D = 1
Answer: Option B
4. Derive the Boolean expression for the logic circuit shown below:
A.
B.
C.
D.
Answer: Option A
5. From the truth table below, determine the standard SOP expression.
A.
B.
C.
D.
Answer: Option D
6. One of De Morgan's theorems states that . Simply stated, this means that logically there is no
difference between:
A.a NOR and an AND gate with inverted inputs
B. a NAND and an OR gate with inverted inputs
C. an AND and a NOR gate with inverted inputs
D. a NOR and a NAND gate with inverted inputs
Answer: Option A
12. For the SOP expression , how many 1s are in the truth table's output column?
A.1
B. 2
C. 3
D. 5
Answer: Option C
13. A truth table for the SOP expression has how many input combinations?
A.1
B. 2
C. 4
D. 8
Answer: Option D
14. How many gates would be required to implement the following Boolean expression before simplification?
XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D. 5
Answer: Option D
15. Determine the values of A, B, C, and D that make the product term equal to 1.
A.A = 0, B = 1, C = 0, D = 1
B. A = 0, B = 0, C = 0, D = 1
C. A = 1, B = 1, C = 1, D = 1
D. A = 0, B = 0, C = 1, D = 0
Answer: Option A
16. What is the primary motivation for using Boolean algebra to simplify logic expressions?
A.It may make it easier to understand the overall function of the circuit.
B. It may reduce the number of gates.
C. It may reduce the number of inputs required.
D. all of the above
Answer: Option D
17. How many gates would be required to implement the following Boolean expression after simplification?
XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D. 5
Answer: Option B
18. AC + ABC = AC
A.True
B. False
Answer: Option A
19. When are the inputs to a NAND gate, according to De Morgan's theorem, the output expression
could be:
A.X = A + B
B.
C. X = (A)(B)
D.
Answer: Option A
20. Which Boolean algebra property allows us to group operands in an expression in any order without
affecting the results of the operation [for example, A + B= B + A]?
A.associative
B. commutative
C. Boolean
D. distributive
Answer: Option B
22. When grouping cells within a K-map, the cells must be combined in groups of ________.
A.2s
B. 1, 2, 4, 8, etc.
C. 4s
D. 3s
Answer: Option B
23. Use Boolean algebra to find the most simplified SOP expression
for F = ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B. F = CD + AD
C. F = BC + AB
D. F = AC + AD
Answer: Option A
24. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as a
BCD-to-decimal converter. These result in ________terms in the K-map and can be treated as either ________ or
________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B. spurious, ANDs, ORs, eliminate
C. duplicate, 1s, 0s, verify
D. spurious, 1s, 0s, simplify
Answer: Option A
25. The NAND or NOR gates are referred to as "universal" gates because either:
A.can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D. were the first gates to be integrated
Answer: Option B
26. The truth table for the SOP expression has how many input combinations?
A.1
B. 2
C. 4
D. 8
Answer: Option D
27. Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get ________.
A.LM + MNOPQ
B. L + MNO + MPQ
C. LM + M + NO + MPQ
D. LM + MNO + MPQ
Answer: Option D
A.
B.
C.
D.
Answer: Option D
31. Mapping the SOP expression , we get ________.
A.(A)
B. (B)
C. (C)
D. (D)
Answer: Option B
32. Derive the Boolean expression for the logic circuit shown below:
A.
B.
C.
D.
Answer: Option C
33. Which is the correct logic function for this PAL diagram?
A.
B.
C.
D.
Answer: Option C
34. For the SOP expression , how many 0s are in the truth table's output column?
A.zero
B. 1
C. 4
D. 5
Answer: Option C
38. Which of the examples below expresses the distributive law of Boolean algebra?
A.(A + B) + C = A + (B + C)
B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
D. A(BC) = (AB) + C
Answer: Option B
40. Which of the following is an important feature of the sum-of-products (SOP) form of expression?
A.All logic circuits are reduced to nothing more than simple AND and OR gates.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer: Option C
41. An OR gate with schematic "bubbles" on its inputs performs the same functions as a(n)________ gate.
A.NOR
B. OR
C. NOT
D. NAND
Answer: Option D
42. Which of the examples below expresses the commutative law of multiplication?
A.A + B = B + A
B. AB = B + A
C. AB = BA
D. AB = A × B
Answer: Option C
43. Determine the binary values of the variables for which the following standard POS expression is equal to
0.
A.(0 + 1 + 0)(1 + 0 + 1)
B. (1 + 1 + 1)(0 + 0 + 0)
C. (0 + 0 + 0)(1 + 0 + 1)
D. (1 + 1 + 0)(1 + 0 + 0)
Answer: Option A
44. The expression W(X + YZ) can be converted to SOP form by applying which law?
A.associative law
B. commutative law
C. distributive law
D. none of the above
Answer: Option C
A.a
B. b
C. c
D. d
A.a
B. b
C. c
D. d
4. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW.
What is the status of the Y output?
A.LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A
5. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH.
What is the status of the Y output?
A.LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A
6. Convert BCD 0001 0010 0110 to binary.
A.1111110
B. 1111101
C. 1111000
D. 1111111
Answer: Option A
7. A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the
state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
A.
B.
C.
D.
Answer: Option A
8. Convert BCD 0001 0111 to binary.
A.10101
B. 10010
C. 10001
D. 11000
Answer: Option C
A.a
B. b
C. c
D. d
Answer: Option B
10. How many data select lines are required for selecting eight inputs?
A.1
B. 2
C. 3
D. 4
Answer: Option C
11. The simplest equation which implements the K-map shown below is:
A.
B.
C.
D.
Answer: Option A
12. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A.5
B. 6
C. 7
D. 8
Answer: Option D
13. Which of the following logic expressions represents the logic diagram shown?
A.
B.
C.
D.
Answer: Option D
14. The implementation of simplified sum-of-products expressions may be easily implemented into actual logic
circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for
the blank space that will BEST make the statement true.)
A.AND/OR
B. NAND
C. NOR
D. OR/AND
Answer: Option B
15. Which of the following statements accurately represents the two BEST methods of logic circuit
simplification?
A.Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis
C. Actual circuit trial and error evaluation and waveform analysis
D. Boolean algebra and actual circuit trial and error evaluation
Answer: Option A
16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is
HIGH. What is the status of the outputs?
17. Which of the following combinations cannot be combined into K-map groups?
A.Corners in the same row
B. Corners in the same column
C. Diagonal corners
D. Overlapping combinations
Answer: Option C
18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken
several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the
possible faults listed, select the one that most probably is causing the problem.
A.A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to Vcc
Answer: Option C
A.comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option C
21. In VHDL, macrofunctions is/are:
A.digital circuits.
B. analog circuits.
C. a set of bit vectors.
D. preprogrammed TTL devices.
Answer: Option D
23. Which of the following is an important feature of the sum-of-products form of expressions?
A.All logic circuits are reduced to nothing more than simple AND and OR operations.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer: Option A
24. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW.
What is the status of the outputs?
25. An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the
DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the
interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help
isolate the problem?
A.Current tracer
B. Logic probe
C. Oscilloscope
D. Logic analyzer
Answer: Option A
26. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output
levels?
A.A > B = 1, A < B = 0, A < B = 1
B. A > B = 0, A < B = 1, A = B = 0
C. A > B = 1, A < B = 0, A = B = 0
D. A > B = 0, A < B = 1, A = B = 1
Answer: Option C
27. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of
the input terminals, but the output indication does not change. What is wrong?
A.The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.
Answer: Option A
28. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What
are the values for the sum and carry output?
A. 4 3 2 1 = 0111, Cout = 0
B. 4 3 2 1 = 1111, Cout = 1
C. 4 3 2 1 = 1011, Cout = 1
D. 4 3 2 1 = 1100, Cout = 1
Answer: Option C
29. Each "1" entry in a K-map square represents:
A.a HIGH for each input truth table condition that produces a HIGH output.
B. a HIGH output on the truth table for all LOW input combinations.
C. a LOW output for all possible HIGH input conditions.
D. a DON'T CARE condition for all possible input truth table combinations.
Answer: Option A
30. Looping on a K-map always results in the elimination of:
A.variables within the loop that appear only in their complemented form.
B. variables that remain unchanged within the loop.
C. variables within the loop that appear in both complemented and uncomplemented form.
D. variables within the loop that appear only in their uncomplemented form.
Answer: Option C
31. What will a design engineer do after he/she is satisfied that the design will work?
A.Put it in a flow chart
B. Program a chip and test it
C. Give the design to a technician to verify the design
D. Perform a vector test
Answer: Option B
32. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?
A.The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the
technician to the problem.
B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.
C. The output appears to be LOW, but is being pulsed by the pulser.
D. Nothing appears to be wrong at that point.
Answer: Option D
33. What is the indication of a short on the input of a load gate?
A.Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.
D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.
Answer: Option D
34. In HDL, LITERALS is/are:
A.digital systems.
B. scalars.
C. binary coded decimals.
D. a numbering system.
Answer: Option B
35. Which of the following expressions is in the sum-of-products form?
A.(A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD
Answer: Option D
36. The carry propagation can be expressed as ________.
A.Cp = AB
B. Cp = A + B
C.
D.
Answer: Option B
37. Which of the K-maps given below represents the expression X = AC + BC + B?
A.a
B. b
C. c
D. d
Answer: Option C
38. A decoder can be used as a demultiplexer by ________.
A.tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input
Answer: Option D
39. How many 4-bit parallel adders would be required to add two binary numbers each representing decimal
numbers up through 30010?
A.1
B. 2
C. 3
D. 4
Answer: Option C
40. Which statement below best describes a Karnaugh map?
A.A Karnaugh map can be used to replace Boolean rules.
B. The Karnaugh map eliminates the need for using NAND and NOR gates.
C. Variable complements can be eliminated by using Karnaugh maps.
D. Karnaugh maps provide a visual approach to simplifying Boolean expressions.
Answer: Option D
41. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
A.a
B. b
C. c
D. d
Answer: Option D
42. A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes
LOW when the inputs are 1001?
A.0
B. 3
C. 9
D. None. All outputs are HIGH.
Answer: Option C
43. Solve the network in the figure given below for X.
A.A + BC + D
B. ((A + B)C) + D
C. D(A + B + C)
D. (AC + BC)D
Answer: Option B
44. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?
A. = 0, Cout = 0
B. = 0, Cout = 1
C. = 1, Cout = 0
D. = 1, Cout = 1
Answer: Option B
45. What type of logic circuit is represented by the figure shown below?
A.XOR
B. XNOR
C. XAND
D. XNAND
Answer: Option B
46. The device shown here is most likely a ________.
A.comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option B
47. The design concept of using building blocks of circuits in a PLD program is called a(n):
A.hierarchical design.
B. architectural design.
C. digital design.
D. verilog.
Answer: Option A
48. When adding an even parity bit to the code 110010, the result is ________.
A.1110010
B. 1111001
C. 110010
D. 001101
Answer: Option A
49. Which of the following combinations of logic gates can decode binary 1101?
A.One 4-input AND gate
B. One 4-input AND gate, one OR gate
C. One 4-input NAND gate, one inverter
D. One 4-input AND gate, one inverter
Answer: Option D
50. What is the indication of a short to ground in the output of a driving gate?
A.Only the output of the defective gate is affected.
B. There is a signal loss to all load gates.
C. The node may be stuck in either the HIGH or the LOW state.
D. The affected node will be stuck in the HIGH state.
Answer: Option B
51. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?
A.3
B. 4
C. 5
D. 6
Answer: Option B
Sequential Logic Circuits - General Questions
B
all flip-flops and gates
.
C
the flip-flops only with gates
.
D
only circuit gates
.
Answer: Option A
To operate correctly, starting a ring counter requires:
A
clearing all the flip-flops
.
B
presetting one flip-flop and clearing all the others
.
C
clearing one flip-flop and presetting all the others
.
D
presetting all the flip-flops
.
Answer: Option B
What type of register would shift a complete binary number in one bit at a time and shift all the
stored bits out one bit at a time?
A
PIPO
.
B
SISO
.
C
SIPO
.
D
PISO
.
Answer: Option B
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
counters because the:
A
input clock pulses are applied only to the first and last stages
.
B
input clock pulses are applied only to the last stage
.
C
input clock pulses are not used to activate any of the counter stages
.
D
input clock pulses are applied simultaneously to each stage
.
Answer: Option D
One of the major drawbacks to the use of asynchronous counters is that:
A
low-frequency applications are limited because of internal propagation delays
.
B
high-frequency applications are limited because of internal propagation delays
.
C Asynchronous counters do not have major drawbacks and are suitable for use in high-
. and low-frequency counting applications.
D Asynchronous counters do not have propagation delays, which limits their use in high-
. frequency applications.
Answer: Option B
Which type of device may be used to interface a parallel data format with external equipment's
serial format?
A
key matrix
.
B
UART
.
C
memory chip
.
D serial-in, parallel-out
.
Answer: Option B
When the output of a tri-state shift register is disabled, the output level is placed in a:
A
float state
.
B
LOW state
.
C
high impedance state
.
D
float state and a high impedance state
.
Answer: Option D
A comparison between ring and johnson counters indicates that:
A
a ring counter has fewer flip-flops but requires more decoding circuitry
.
B
a ring counter has an inverted feedback path
.
C
a johnson counter has more flip-flops but less decoding circuitry
.
D
a johnson counter has an inverted feedback path
.
Answer: Option D
A sequence of equally spaced timing pulses may be easily generated by which type of counter
circuit?
A
shift register sequencer
.
B
clock
.
C
johnson
.
D
binary
.
Answer: Option A
What is meant by parallel-loading the register?
A
Shifting the data in all flip-flops simultaneously
.
B
Loading data in two of the flip-flops
.
D
Momentarily disabling the synchronous SET and RESET inputs
.
Answer: Option C
What is a shift register that will accept a parallel input and can shift data left or right called?
A
tri-state
.
B
end around
.
C
bidirectional universal
.
D
conversion
.
Answer: Option C
What happens to the parallel output word in an asynchronous binary down counter whenever a
clock pulse occurs?
A
The output word decreases by 1.
.
B
The output word decreases by 2.
.
C
The output word increases by 1.
.
D
The output word increases by 2.
.
Answer: Option A
Mod-6 and mod-12 counters are most commonly used in:
A
frequency counters
.
B
multiplexed displays
.
C
digital clocks
.
D
power consumption meters
.
Answer: Option C
MCQ. The switch which clears the flip-flop to its initial state is called
A. clock
B. invert
C. hold
D. clear
MCQ. The don't care condition in a table is represented by
A. a
B. b
C. c
D. x
MCQ. How many types a sequential circuits have?
A. 2
B. 5
C. 6
D. None
A MCQ. Master-slave flip-flop consists of
A. 2 flip-flops
B. 3 flip-flops
C. 4 flip-flops
D. 5 flip-flops
MCQ. In Moore models, output are the function of only
A. present state
B. input state
C. next state
D. both a and b
MCQ. Memory elements in clocked sequential circuits are called
A. latches
B. flip-flop
C. signals
D. gates
The design procedure of sequential circuit is based on
A. 7steps
B. 8steps
C. 9steps
D. 10steps
ns MCQ. The state of flip-flop can be switched by changing its
A. input signal
B. output signal
C. momentary signals
D. all signals
w MCQ. The major difference between various types of flip-flops are
A. output that they generate
B. input that they posses
C. gates
D. both a and b
MCQ. The flip-flops can be constructed with two
A. NAND gates
B. XOR gates
C. AND gates
D. NOT gates
MCQ. Unused states are treated as Don't cares conditions during the
A. Design of a circuit
B. Execution
C. Pulse trigger
D. None
e MCQ. The momentary change in the state of flip-flop is called
A. feedback path
B. tri state
C. signals
D. trigger
MCQ. The positive transition in flip-flops is referred as
A. clock
B. negative edge
C. positive edge
D. both a and b
MCQ. Feedback among logic gates make asynchronous system
A. stable
B. unstable
C. complex
D. combinational
MCQ. Clocked flip-flops are triggered by
A. feedback path
B. pulses
C. signals
D. clear
MCQ. Direct coupled RS flip-flops are also called
A. RS latch
B. SR latch
C. TS latch
D. ST latch
MCQ. Sequential circuits are
A. Synchronous
B. Asynchronous
C. signals
D. both a and b
MCQ. The behavior of sequential circuits are determined by the state of their
A. clock
B. pulses
C. flip-flops
D. trigger
MCQ. The definite time in a flip-flop is called
A. clear time
B. pulse time
C. hold time
D. reset time
MCQ. JK Master-slave flip-flops are constructed with
A. NAND gates
B. OR gates
C. AND gates
D. NOT gates
MCQ. The operation of basic flip-flop can be changed by providing some additional control
A. Input
B. Output
C. Inverter
D. None
MCQ. M flip-flops produces
A. 2^m-1 states
B. 2-1 states
C. 2^m+1 states
D. 2^m states
MCQ. The state of flip-flops are initialized with
A. reset input
B. master input
C. master reset input
D. both a and b
MCQ. A counter that flows the binary sequence is called
A. ripple counter
B. edge counter
C. binary counter
D. level counter
MCQ. The next state of B(t) will be
A. B(t-1)
B. B(t+1)
C. B(t-2)
D. B(t+2)
MCQ. In Mealy models output are the functions of both
A. present state
B. input state
C. next state
D. both a and b
In T flip-flop when state of the T flip-flop has to be complemented the T must be
A. 0
B. 1
C. t
D. t+1
MCQ. A synchronous sequential circuit is made up of
A. combinational gates
B. flip-flops
C. latches
D. both a and b
MCQ. The next state of the D flip-flop is dependent on
A. state diagram
B. present state
C. input state
D. D state
MCQ. The time sequence for flip-flop can be enumerated by
A. state table
B. map
C. truth table
D. graph
MCQ. Synchronous sequential circuits that uses clock are called
A. clocked sequential circuits
B. sequential circuits
C. logic circuits
D. complex circuits
MCQ. Two states are said to be equal if they have exactly same
A. inputs
B. next state
C. output
D. both a and b
MCQ. The implication table consists of
A. squares
B. triangles
C. cubes
D. circles
MCQ. Table that lists the inputs for required change of states is called
A. truth table
B. excitation table
C. state table
D. clock table
MCQ. A circuit that goes through prescribed sequence of state is called
A. flip-flops
B. truth tables
C. latches
D. counters
MCQ. Classification of sequential circuits depends upon their timing of
A. feedback path
B. gates
C. signals
D. complex circuits
MCQ. Which state a flip-flop circuits can maintain as long as a power is delivered to the circuit?
A. n states
B. tri state
C. binary state
D. octa state
MCQ. The negative transition in flip-flops are referred as
A. clock
B. negative edge
C. positive edge
D. both a and b
MCQ. Clock generator, generates periodic train of
A. feedback path
B. gates
C. clock pulses
D. both a and b
MCQ. Flip-flops are sensitive to
A. feedback path
B. pulses
C. signals
D. pulse transition
MCQ. A flip-flop circuit can be constructed by two NAND gates or
A. with Two AND gates
B. with Two OR Gates
C. with Two NOR gates
D. None
MCQ. One that is not stated in a state table is
A. present state
B. next state
C. input state
D. clock state
MCQ. In the last step of design procedure we
A. draw map
B. draw circuit
C. draw table
D. draw a logic diagra
MCQ. The state diagram provides the same information as the
A. flip-flops provides
B. State table provides
C. truth table provides
D. both a and b
1. Memory is a/an
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
View Answer
Answer: c
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems.
2. The instruction used in a program for executing them, is stored in the
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
View Answer
Answer: c
Explanation: All of the program and the instructions are stored in the memory.
3. A flip flop stores
a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) None of the Mentioned
View Answer
Answer: b
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous
information.
4. A register is able to hold
a) Data
b) Word
c) Nibble
d) Both data and word
View Answer
Answer: b
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word.
5. A register file holds
a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
View Answer
Answer: d
Explanation: A register file is different from a simple register because of capability to hold a modest number of
words of information.
6. The very first computer memory consisted of
a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) None of the Mentioned
View Answer
Answer: b
Explanation: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky
circuit boards stored in large cabinates.
7. A minute magnetic toroid is also called as
a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
View Answer
Answer: c
Explanation: A minute magnetic toroid is also called as core memory which is made up of a semiconductor.
8. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) None of the Mentioned
View Answer
Answer: c
Explanation: Semiconductor has capability to store data in extremely high densities.
9. A large memory is compressed into a small one by using
a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) None of the Mentioned
View Answer
Answer: b
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of
memory.
10. VLSI chip utilizes
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
View Answer
Answer: d
Explanation: VLSI is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS.
11. CD-ROM refers to
a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) None of the Mentioned
View Answer
Answer: b
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.
12. Data stored in an electronic memory cell can be accessed at random and on demand using
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
View Answer
Answer: b
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the desired
data word.
13. The full form of PLD is
a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) None of the Mentioned
View Answer
Answer: c
Explanation: The full form of PLD is Programmable Logic Device.
14. The evolution of PLD began with
a) EROM
b) RAM
c) PROM
d) EEPROM
View Answer
Answer: a
Explanation: The evolution of PLD began with Programmable Read Only Memory (i.e. PROM).
15. A ROM is defined as
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) None of the Mentioned
View Answer
Answer: c
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.
This set of Discrete Mathematics Questions and Answers for Aptitude test focuses on “Cardinality of Sets”.
This set of Discrete Mathematics Multiple Choice Questions & Answers (MCQs) focuses on “Types of Set”.
This set of Discrete Mathematics Multiple Choice Questions & Answers (MCQs) focuses on “Sets”.
1. The union of the sets {1, 2, 5} and {1, 2, 6} is the set _______________
a) {1, 2, 6, 1}
b) {1, 2, 5, 6}
c) {1, 2, 1, 2}
d) {1, 5, 6, 3}
View Answer
Answer: b
Explanation: The union of the sets A and B, is the set that contains those elements that are either in A or in B.
2. The intersection of the sets {1, 2, 5} and {1, 2, 6} is the set _____________
a) {1, 2}
b) {5, 6}
c) {2, 5}
d) {1, 6}
View Answer
Answer: a
Explanation: The intersection of the sets A and B, is the set containing those elements that are in both A and B.
3. Two sets are called disjoint if there _____________ is the empty set.
a) Union
b) Difference
c) Intersection
d) Complement
View Answer
Answer: c
Explanation: By the definition of the disjoint set.
4. Which of the following two sets are disjoint?
a) {1, 3, 5} and {1, 3, 6}
b) {1, 2, 3} and {1, 2, 3}
c) {1, 3, 5} and {2, 3, 4}
d) {1, 3, 5} and {2, 4, 6}
View Answer
Answer: d
Explanation: Two sets are disjoint if the intersection of two sets is the empty set.
5. The difference of {1, 2, 3} and {1, 2, 5} is the set ____________
a) {1}
b) {5}
c) {3}
d) {2}
View Answer
Answer: c
Explanation: The difference of the sets A and B denoted by A-B, is the set containing those elements that are in A
not in B.
6. The complement of the set A is _____________
a) A – B
b) U – A
c) A – U
d) B – A
View Answer
Answer: b
Explanation: The complement of the set A is the complement of A with respect to U.
7. The bit string for the set {2, 4, 6, 8, 10} (with universal set of natural numbers less than or equal to 10) is
____________________
a) 0101010101
b) 1010101010
c) 1010010101
d) 0010010101
View Answer
Answer: a
Explanation: The bit string for the set has a one bit in second, fourth, sixth, eighth, tenth positions, and a zero
elsewhere.
8. Let Ai = {i, i+1, i+2, …..}. Then set {n, n+1, n+2, n+3, …..} is the _________ of the set Ai.
a) Union
b) Intersection
c) Set Difference
d) Disjoint
View Answer
Answer: b
Explanation: By the definition of the generalized intersection of the set.
9. The bit strings for the sets are 1111100000 and 1010101010. The union of these sets is ___________
a) 1010100000
b) 1010101101
c) 1111111100
d) 1111101010
View Answer
Answer: d
Explanation: The bit string for the union is the bitwise OR of the bit strings.
10. The set difference of the set A with null set is __________
a) A
b) null
c) U
d) B
View Answer
Answer: a
Explanation: The set difference of the set A by null set denoted by A – {null} is A.
This set of Discrete Mathematics Interview Questions and Answers focuses on “Set Operations – 2”.
1. Let the set A is {1, 2, 3} and B is {2, 3, 4}. Then number of elements in A U B is
a) 4
b) 5
c) 6
d) 7
View Answer
Answer: a
Explanation: AUB is {1, 2, 3, 4}.
2. Let the set A is {1, 2, 3} and B is { 2, 3, 4}. Then number of elements in A ∩ B is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: A ∩ B is {2, 3}.
3. Let the set A is {1, 2, 3} and B is {2, 3, 4}. Then the set A – B is
a) {1, -4}
b) {1, 2, 3}
c) {1}
d) {2, 3}
View Answer
Answer: c
Explanation: In A – B the common elements get cancelled.
4. In which of the following sets A- B is equal to B – A
a) A= {1, 2, 3}, B ={2, 3, 4}
b) A= {1, 2, 3}, B ={1, 2, 3, 4}
c) A={1, 2, 3}, B ={2, 3, 1}
d) A={1, 2, 3, 4, 5, 6}, B ={2, 3, 4, 5, 1}
View Answer
Answer: c
Explanation: A- B= B-A = Empty set.
5. Let A be set of all prime numbers, B be the set of all even prime numbers, C be the set of all odd prime numbers,
then which of the following is true?
a) A ≡ B U C
b) B is a singleton set.
c) A ≡ C U {2}
d) All of the mentioned
View Answer
Answer: d
Explanation: 2 is the only even prime number.
6. If A has 4 elements B has 8 elements then the minimum and maximum number of elements in A U B are
respectively
a) 4, 8
b) 8, 12
c) 4, 12
d) None of the mentioned
View Answer
Answer: b
Explanation: Minimum would be when 4 elements are same as in 8, maximum would be when all are distinct.
7. If A is {{Φ}, {Φ, {Φ}}, then the power set of A has how many element?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: b
Explanation: The set A has got 2 elements so n(P(A))=4.
8. Two sets A and B contains a and b elements respectively .If power set of A contains 16 more elements than that of
B, value of ‘b’ and ‘a’ are respectively
a) 4, 5
b) 6, 7
c) 2, 3
d) None of the mentioned
View Answer
Answer: a
Explanation: 32-16=16, hence a=5, b=4.
9. Let A be {1, 2, 3, 4}, U be set of all natural numbers, then U-A’(complement of A) is given by set.
a) {1, 2, 3, 4, 5, 6, ….}
b) {5, 6, 7, 8, 9, ……}
c) {1, 2, 3, 4}
d) All of the mentioned
View Answer
Answer: c
Explanation: U – A’ ≡ A.
10. Which sets are not empty?
a) {x: x is a even prime greater than 3}
b) {x : x is a multiple of 2 and is odd}
c) {x: x is an even number and x+3 is even}
d) { x: x is a prime number less than 5 and is odd}
View Answer
Answer: d
Explanation: Because the set is {3}.