Computer Architecture and Organization

Introduction :
Over the past decades the computing technology has made tremendous progress. The computing
power of computers have grown by leaps and bounds, the size of the computers have got reduced
from that of a big hall to palm size, and the cost of computers have become more affordable. The
result is – it has invaded every walk of our lives. This tremendous progress in computers has
come from the advances in the technologies used to build computers as well as from the
innovations made in computer design. However the basic principles on which a computer is built
have essentially remained the same. In this chapter we will take an overview of these basic
principles.

Architecture and Organization are two terms with meanings that are context dependent and are
relative in nature. In the context of a computer also experts have defined these terms somewhat
differently. However, broadly, we can say that the terms- Computer Architecture and Computer
Organization – are used to define two levels of abstractions that are used for designing or
understanding a computer system.

The term Computer Architecture refers to those aspects of a computer system that are
visible to a programmer or those parameters that have a direct impact on the logical execution of
a program. Examples of architectural attributes include the instruction set, the specification of
the data, the number of bits used to represent different data types, Input/Output mechanisms, and
the mechanisms used for addressing memory.

The term Computer Organization refers to the functional units of a computer, their
interconnection and interaction processes so as to realize the architectural specifications.
Examples of organizational attributes include those hardware details that are apparent to the
programmer, such as the functional units like the arithmetic and logical units, control signals,
interfaces between the computer and peripherals, the instruction execution processes etc.

This course deals with the architectural elements of computers as well as the aspects of
computer organization and discusses how a computer, the bare machine, is built.
 Basic Computer Model

A computer consists of four basic modules:

o Central Processing Unit (CPU)

o Input Unit

o Output Unit

o Memory Unit

Data
Flow
CPU Control/
Signal

INPUT MEMORY OUTPUT

Basic Computer Model

A. Central Processing Unit (CPU):

The job of the Central Processing Unit or the Processor is to control the operation of all the
functional units of the computer to execute a program. It consists of two basic modules:

o The Decoder and Control Unit (DCU) that interprets the instructions of a program
and emits control signals to the different functional units within the CPU and also the rest
of the computer for execution of the individual instructions.
o The Arithmetic and Logic Unit (ALU) that performs the arithmetic and logical
operations required for execution of the instructions.

In addition, the CPU generally has a set of registers for temporary storage of data and to maintain
the state information of the computer and the data paths that interconnect the different
components of the processor.
B. Input Unit:

Through the Input Unit data and instructions can be fed to memory unit of the computer under
the control of the CPU.

Examples of input devices: Keyboard, Mouse, Track ball, Joystick, Scanner, Digitizer etc.

C. Output Unit:

Through the Output Unit results of the computation are provided to the user from the memory
unit under the control of the CPU.

Examples of output devices: Printer, CRT/LCD monitor, Plotter etc.

D. Memory Unit:

The Memory Unit is used to store the data and the program fed through the input unit. The CPU
processes the data as per the instructions in the program. The results produced are stored back in
the memory unit to be finally transferred to the output unit.

The memory can be categorized into two types:

1. Primary or Main Memory
2. Secondary Memory or Storage
The Primary Memory holds the program currently under execution and its data. It is of Random
Access type. The locations in the primary memory can be specified at the Byte level and these
can be accessed at random, i.e. any memory location (any byte of data) in the main memory can
be accessed at any moment in time without maintaining any order. These are usually
semiconductor devices.
In Secondary Memory data are organized in blocks of certain size and are accessed in blocks, not
in individual bytes. They are of two types depending upon the access mechanism used. The two
access mechanisms used are-
1. Serial or Sequential Access
2. Direct Access
In direct access devices blocks of data can be specified at random and can be transferred. In
serial access devices the data blocks are accessed in a serial order and cannot be picked-up at
random. The Direct Access Devices such as Hard Disk are used as Online Storage and Serial
Access Devices, such as Magnetic Tape are used as Back-up or Offline storage. There are
however exceptions to this. Many direct access devices, such as CDs, Flash Memory (Pen
Drives) etc. are also used as back-up devices due to convenience of small size and detachability
from the system.
Primary Memory Organization:

The Primary Memory can be thought to be an array of data slots each capable of holding a byte
of data. These slots are called memory locations. Each of these memory locations is identified by
a number. This identifying number is called its address.

Address Memory Locations

0
1
2
3
4
5

. .
. .
. .

N-2
N-1

To access any of the memory locations one has to specify the address and the operation (i.e. read
or write) to be performed. There are address lines through which the address is specified.
Through the command lines the operation is specified. Data lines are provided to input/output the
data. In case of a write operation the data to be written is fed through the data lines. On
completion of the operation the memory unit emits Memory Function Complete (MFC) signal
for information of the operation initiator.

Primary Memory Unit

Decoder Memory Locations

0
1
2 Address Data
3

. Command
.

N-1 MFC
 Working Principle of a Computer

A computer understands a set of instructions. Any task that needs to be performed by the
computer is specified in terms of the instructions within this set. This specification of the task
therefore takes the form of an ordered set of instructions that is called a Computer Program or
just a Program. The information to be processed and the variable parameters of the task are
specified in terms of Data.

The model of a computer that we discuss here is known as the Von Neumann Stored
Program Computer. This model was developed by Von Neumann in 1946 while building a
computer at the Institute of Advanced Studies (IAS) at Princeton University. In this model of a
computer the program under execution and its data are stored in the primary memory of the
computer. The instructions in the program are stored in the memory unit in the order in which
they are to be executed.

The essential components in a processor are-

- A register called the Program Counter(PC) or Instruction Pointer(IP) that maintains

the address of the next instruction to be executed.
- A register called the Instruction Register(IR) that holds the instruction currently under
execution.
- A register called the Memory Address Register(MAR) that holds the address of the
memory location that is to be accessed next or currently being accessed.
- A register called the Memory Data Register(MDR) or Memory Buffer Register(MBR)
that holds the data to be transferred to the memory unit through a memory write
operation or transferred from the memory unit through a memory read operation.
- A Decoder and Control Unit(DCU) that decodes the instruction in the IR and emits
the necessary signals to the various units within the processor as well as the memory
and the input and output units for execution of the instruction at hand.
- An Arithmetic and Logic Unit(ALU) that performs arithmetic and logical operations
on data as instructed by the DCU.
- A set of General purpose Registers(GPR) that are used for holding temporary data
and addresses during the execution of a program.
- A Status Register(SR) that maintenance certain information on the current status of
the program under execution as well as the processor.
- A register called the Stack Pointer(SP) that points to the location of operation in a
data structure that works with the Last-In-First-Out(LIFO) discipline.

For execution of a program the Program Counter (PC) is loaded with the address of the
first instruction of the program. The processor then follows the steps below:

1. Transfer the address in the PC to the MAR. ( MAR ← PC )

2. Increment PC to point to the next instruction in memory. (PC++)
3. Initiate a read operation in the memory. As a result the memory (Read)
transfers the content of the location specified in the MAR to the MDR.
4. Transfer the content of MDR to the IR. ( IR ← MDR )
5. The DCU decodes the instruction in the IR and accordingly issues (Execute IR)
controls signals to the various units within the processor as well as
the memory, input and output units to perform the desired operation.
6. Repeat the steps 1 to 5 until a Halt instruction is encountered.
 Address
PC MAR To Memory
Unit
Data
IR MDR

Decoder &
Control Unit
(DCU)

GPR
Arithmetic &
Logic Unit
(ALU)

SR

SP

Central Processing Unit (CPU)

In a Register Transfer Language (RTL) the above process can be described as-
Repeat
MAR ← PC
PC++
Read
IR ← MDR
Execute
Until IR = Halt

The first four steps in the process above constitute the Instruction Fetch Cycle while the fifth
step constitutes the Instruction Execution Cycle. The instruction execution cycle can be further
divided into following sub cycles-
1. Operand Fetch Cycle: During this the operands of the instruction are fetched into
the processor from the memory unit.
2. Execution Cycle: Perform the desired operation.
3. Operand Store Cycle: During this cycle transfer the result(s) of the instruction to
desired location.
Activities during these sub cycles vary from instruction to instruction while the Instruction Fetch
Cycle remains the same for every instruction.
 Instruction Set Architecture

A. Instruction Types:
a. Data Manipulation Instructions:
i. Arithmetic: For arithmetic operations such as- Add, Subtract, Multiply,
Divide etc.
ii. Logical: Logical operations such as- AND, OR, NOT, etc.
iii. Bit Manipulation: Binary operations such as- Shift, Rotate, Set, Clear etc.
iv. Compare & Test: Performing operations such as- Compare, Test etc.

b. Data Transfer Instructions:

To perform frequently required data transfers from one location to another such as-
i. Transfer between registers: Move etc.
ii. Transfer between memory locations: Move etc.
iii. Transfer between register and memory locations: Load, Store etc.
iv. Transfer between registers/ memory locations and Input/ Output devices:
Input, Output etc.

c. Program Control Instructions:

To enable implementation of non-sequential execution of instructions such as program
loops, if-then-else conditional execution, subroutine/ function execution, etc. These are
of two categories-
i. Branch or Jump Instructions:
- Unconditional Branch: Branch, Jump etc.
- Conditional Branch: Branch if Equal, Branch if Greater Than etc.
ii. Subroutine Instructions: Call Subroutine, Return from Subroutine etc.

B. Instruction Format: Representation of instructions as a string of bits.

a. Components of an Instruction
i. Operation - Operation Code (Opcode)
ii. Operand(s)- Addresses
iii. Next Instruction Address

Opcode Opr1 Opr2 Opr3 Next Address

b. Addressing Format – Number of Operand Addresses Specified in the Instruction
i. Three Address: General Purpose Register (GPR) Based Machine(m/c)
- Two addresses specify the two input operands and the third address
specifies the location for the result to be stored. Three GPRs can be used
for this purpose.
ii. Two Address: General Purpose Register (GPR) Based m/c
- Two addresses specify the two input operands. One of these addresses is
also used as the location for the result to be stored. In this case one of the
source operands gets overwritten. Two GPRs can be used for the two
operand locations.
iii. One/ Single Address: Accumulator Based m/c
- Only one address is provided to specify one of the operands. The second
operand location has to be implied. A special purpose register called
Accumulator is used for the purpose. The accumulator is also used to
store the result.

GPRs
GPRs

ALU
ALU

Accumulator

GPRS Based m/c Accumulator Based m/c

iv. Zero/ No Address: Stack Based m/c

- In this format the instruction does not specify any of the operand
addresses. Therefore all the addresses have to be implied. The top of a
stack is assumed to hold the source operands and the result is placed at
the top of the stack.

ALU
Stack
 Stack Based m/c

Example Evaluation of Arithmetic Expressions for Different Addressing Formats:

Let the expression to evaluate be:

R=(A+B)*C/D-E

Three address format:

T1  A+B; T2  T1*C; T3  T2/D; R  T3-E;

Two address format:

T1A; T1T1+B; T1T1*C; T1T1/D; T1T1-E; RT1;

Single address format:

AccA; AccAcc+B; AccAcc*C; AccAcc/D; AccAcc-E; RAcc;

Zero address format:

Push(A), Push(B), add, Push(C), mult, push(D), div, Push(E), sub, pop(R)

:: SA, SB, Spop()+pop(), SC, Spop()*pop(), SD,

Spop()/pop(), SE, Spop()-pop(), Rpop()

:: SA,SB,SS1+S2,SC,SS1*S2,SD,SS2/S1, SE,SS2-S1,RS1
 Addressing Modes:
i. Immediate:
Instruction
The operand is specified
Opcode Operand
as part of the instruction.

ii. Absolute or Direct:

Instruction

Opcode Address Memory

Operand

The address of the operand in memory

is specified as a part of the instruction.

iii. Register:
Instruction

Opcode Register No. GPRS

A register holds the Operand

operand. The register is
specified in the instruction.

iv. Register Indirect:

Instruction

Opcode Register No.

Memory

GPRs

The operand is placed

in a memory location.
Its address is stored in Address Operand
a register. This
register is specified in
the instruction.
 v. Displacement
- Relative
Instruction
Memory
Opcode Displacement

Instruction

Displacement
PC
Operand
+

The operand is placed in a memory location.

A displacement relative to the location of the
instruction specifies in the location of the operand.
- Indexed
Instruction

Opcode Index Register Displacement

Memory

GPRS

The operand is placed in a

memory location.
A displacement w.r.t. an
Address + Operand
address given in an index
register specifies in the
location of the operand.

- Base Register
Instruction

Opcode Index Base

Register Register

Memory

GPRS

The operand is
placed in a
memory location. Base
The sum of the
Address
contents of an
index register and + Operand
a base register
gives the location Index
of the operand.
 Program Control Instructions:
. Branch/ Jump Instructions:
i. Unconditional Branch: Branch, Jump etc.
ii. Conditional Branch: Branch if Equal (BEQ), Branch if Not Equal (BNE) Branch if
Greater Than (BGT) etc.
The format of a typical branch instruction is-

Branch Code Branch Address

In case of an unconditional branch on execution of the instruction the control of the

processor is transferred to the instruction located at the branch address. This is achieved by
simply modifying the PC content to the branch address, i.e. by performing the operation
PC ← Branch Address.
In case of a conditional branch instruction it is also necessary to evaluate the
condition and based on its result the branch may or may not be taken. For example, say the
branch instruction is required to implement an if statement-
if (x==y)
then
Statement Block1
else
Statement Block2
To achieve this, the processor uses a set of Flags maintained in a Status Register
(SR). Some of these flags are- Negative(N), Zero(Z), Overflow(V), Carry(C). The processor
sets or resets these flags based on the result of an operation involving the ALU. If the result
of an ALU operation is negative, the N bit is set, otherwise it is reset. Similarly, if the result
is zero, the Z bit is set, otherwise reset. The setting or resetting of the V and C bits depend
upon whether an overflow or carry occurs as a result of an ALU operation.
The conditional branching is achieved through two m/c instructions. First, instruction
for evaluation of the condition and setting or resetting the flag bits. Second, the conditional
branch instruction for which the processor checks the relevant flag bit(s) and decides on
whether to modify or not to modify the PC. The case above may be implemented as-
com x, y ; Compare x and y.
bne branch_address ; Branch if not equal to.
For the com x, y instruction the processor performs a subtraction operation and sets or resets
the N and Z bits as follows:
x and y are equal : N=0, Z=1;
x is greater than y : N=0, Z=0;
x is less than y : N=1, Z=0;
Following this instruction when the bne instruction is executed, the processor checks the Z
bit. If it finds the Z bit set to 1, it modifies the PC content with the branch_address,
otherwise it leaves the PC unchanged. The other conditional branch instructions are executed
in a similar manner.
. Subroutine: Call Subroutine, Return from Subroutine etc.
The format of a typical subroutine call instruction is -

Subroutine Call Code Subroutine Address

and that for a return instruction is-

Return Code

The return instruction does not specify any return address. This address is
remembered by the processor by saving it in the processor stack while executing the
subroutine call instruction. The use of the stack for saving the return address allows deep
nesting of subroutines as the stack is a Last-In-First-Out (LIFO) structure.
The Call Subroutine instruction performs a Push(PC) operation to save the current
PC in the Stack and then modify the PC to point to the called subroutine. The Return
instruction placed at the end of a subroutine performs a Pop operation to restore the last PC
saved in the Stack. The resulting effect in case of a set of nested subroutines is as depicted in
the figure below:

Main
----------- Sub1 Sub2 Sub3 Sub4
----------- ----------- ----------- ----------- -----------

----------- ----------- ----------- ----------- -----------

Call Sub1 ----------- ----------- ----------- -----------

P1 ----------- Call Sub2 Call Sub3 Call Sub4 ----------

----------- P2 ----------- P3 ----------- P ----------- -----------

4

----------- ----------- ----------- ----------- -----------

----------- Return Return Return Return

-----------

Nested of Subroutines

    P4
P3 P3
  P2  P2  P2
P1 P1 P1 P1
At Main At Sub1 At Sub2 At Sub3 At Sub4

Content of the Stack at different stages of nesting of the Subroutines above.

In practice, the processor also saves the Status Register (SR) content along with the PC on
execution of a Call Subroutine instruction and restores it while executing the Return instruction.
This is done to ensure that the status of the processor within a program segment is not affected
by the execution of a Subroutine.
PDP-11 instruction set
The instruction set of the PDP-11 was designed towards a clean, general, symmetric
instruction set. It can be used as a register-based, stack-based, or memory-based machine,
depending on the programmer's preferences. 3

Word length is 16 bits with the leftmost, most significant bit (MSB) being bit 15. There
are eight general registers of 16 bits each. Register 7 is the program counter (PC) and Register 6
is the stack pointer (SP). There is also a Processor Status Register/Word (PSW) which indicates
the 4 condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt priority, and 4 bits
for current and previous operating modes.

Addressing on the PDP-11 is linear from memory address 0 through 177777(octal).

Memory management allows access to physical memory with addresses of up to 22 bits
(17777777). All I/O devices, registers etc are addressed as if they were part of memory. These
are in the 4KW of reserved memory space at the top of the address space. All word memory
addresses are even. In byte operations, an even address specifies the least-significant byte and an
odd address specifies the most-significant byte. Specifying an odd byte in a word operation will
return an odd address trap. Memory addresses from 0 to 400 octal are reserved for various
exception traps such as timeouts, reserved instructions, parity, etc., and device interrupts.

Addressing for the Single Operand, Double Operand and Jump instructions is achieved
via six bits:

_ _ _ _ _ _
|m|m|m|r|r|r|
|Mode |Reg |

where the modes are as follows: (Reg = Register, Def = Deferred)

Mode 0 Reg Rn Direct addressing – register contains the

operand
Mode 1 Reg Def (Rn) Content of Reg is the address of the operand
Mode 2 AutoIncr (Rn)+ Content of Reg is the address, then Reg
incremented
Mode 3 AutoIncrDef @(Rn)+ Content of Reg is addr of addr, then Reg
Incremented
Mode 4 AutoDecr -(Rn) Reg is decremented then content is used as
address
Mode 5 AutoDecrDef @-(Rn) Reg is decremented then content is used as addr of
addr
Mode 6 Index X(Rn) Content of Reg + Following word is address
Mode 7 IndexDef @X(Rn) Content of Reg + Following word is addr of
addr

Note that the right-most bit of the mode is an indirection bit.

Although not special cases, when dealing with R7 (the PC), some of these modes are
called different things:

_ _ _ _ _ _
|m|m|m|1|1|1|
|Mode | R7 |

Mode 2 Immediate Operand follows the instruction

 Mode 3 Absolute Address of Operand follows the instruction
Mode 6 Relative Instr address+4+Next word is Address
Mode 7 RelativeDef Instr address+4+Next word is Address of address

Mainstream instructions are broken into Single operand and Double operand instructions,
which in turn can be word or byte instructions.

Double Operand Instructions

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b i i i|s s s|s s s|d d d|d d d|
| Op | Source | Dest |

Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table
below, the mnemonics and names are given in the order b=0/b=1.

The double operand instructions are:

b 000 ssssss dddddd

Non-double-operand instructions.
b 001 ssssss dddddd -- MOV/MOVB Move Word/Byte
Moves a value from source to destination.
b 010 ssssss dddddd -- CMP/CMPB Compare Word/Byte
Compares values by subtracting the destination from the source, setting the condition
codes, and then discarding the result of the subtraction.
b 011 ssssss dddddd -- BIT/BITB Bit Test Word/Byte
Performs a bit-wise AND of the source and the destination, sets the condition codes, and
then discards the result of the AND.
b 100 ssssss dddddd -- BIC/BICB Bit Clear Word/Byte
For each bit set in the source, that bit is cleared in the destination. This is accomplished
by taking the ones-complement of the source and ANDing it with the destination. The
result of the AND is stored in the destination.
b 101 ssssss dddddd -- BIS/BISB Bit Set Word/Byte
For each bit set in the source, that bit is set in the destination. This is accomplished by
ORing the source and destination, and storing the result in the destination.
b 110 ssssss dddddd -- ADD/SUB Add/Subtract Word
Adds the source and destination, storing the results in the destination.
Subtracts the source from the destination, storing the results in the destination.
Note that this is a special case for b=1, in that it does not indicate that byte-wide operands
are used.
b 111 xxxxxx xxxxxx
Arithmetic functions not supported by all implementations of the PDP-11 architecture.

Single Operand Instructions

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|0 0 0|i i i i i i|d d d d d d|
| | |Instruction| Dest |

Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table
below, the mnemonics and names are given in the order b=0/b=1. Unless otherwise stated, the
operand is read for the data to operate on, and the result is then written over that data.
The single operand instructions are:

b 000 000 011 dddddd -- SWAB/BPL Swap Bytes/Branch Plus

Swap bytes exchanges the two bytes found in the destination, writing the result back to it.
The branch (b=1) is described in the section on branches, below.

Note that SWAB is actually a bit pattern from the range reserved for branches. This
particular pattern is otherwise unused, as it would be a modification of BR, Branch
Always, which has no obvious semantics.

b 000 101 000 dddddd -- CLR/CLRB Clear Word/Byte

Sets all the bits in destination to zero.
b 000 101 001 dddddd -- COM/COMB Complement Word/Byte
Calculates the ones-complement of the operand, and stores it. The ones-complement is
formed by inverting each bit (0->1, 1->0) independently.
b 000 010 010 dddddd -- INC/INCB Increment Word/Byte
Adds one to the destination.
b 000 101 011 dddddd -- DEC/DECB Decrement Word/Byte
Subtracts one from the destination.
b 000 101 100 dddddd -- NEG/NEGB Negate Word/Byte
Calculates the twos-complement of the operand, and stores it. The twos-complement is
formed by adding one to the ones-complement. The effect is the same as subtracting the
operand from zero.
b 000 101 101 dddddd -- ADC/ADCB Add Carry Word/Byte
Adds the current value of the carry flag to the destination. This is useful for implementing
arithmetic subroutines with more than word-sized operands.
b 000 101 110 dddddd -- SBC/SBCB Subtract Carry Word/Byte
Subtracts the current value of the carry flag from the destination. This is useful for
implementing arithmetic subroutines with more than word-sized operands.
b 000 101 111 dddddd -- TST/TSTB Test Word/Byte
Sets the N (negative) and Z (zero) condition codes based on the value of the operand.
b 000 110 000 dddddd -- ROR/RORB Rotate Right Word/Byte
Rotates the bits of the operand one position to the right. The right-most bit is placed in
the carry flag, and the carry flag is copied to the left-most bit (bit 15) of the operand.
b 000 110 001 dddddd -- ROL/ROLB Rotate Left Word/Byte
Rotates the bits of the operand one position to the left. The left-most bit is placed in the
carry flag, and the carry flag is copied to the right-most bit (bit 0) of the operand.
b 000 110 010 dddddd -- ASR/ASRB Arithmetic Shift Right Word/Byte
Shifts the bits of the operand one position to the right. The left-most bit is duplicated. The
effect is to perform a signed division by 2.
b 000 110 011 dddddd -- ASL/ASLB Arithmetic Shift Left Word/Byte
Shifts the bits of the operand one position to the left. The right-most bit is set to zero. The
effect is to perform a signed multiplication by 2.
b 000 110 100 dddddd -- MARK/MTPS Mark/Move To Processor Status
Mark is used as part of one of the subroutine call/ return sequences. The operand is the
number of parameters.

MTPS is only on LSI-11s, and is used to move a byte to the processor status word. This is
needed because the LSI-11 does not support accessing registers via memory addresses.

b 000 110 101 dddddd -- MFPI/MFPD Move From Prev. Instruction/Data

 Pushes a word onto the current R6 stack from the operand address in the previous address
space, as indicated in the PSW. On PDP-11s that do not support separate instruction and
data spaces, MFPD is treated the same as MFPI.
b 000 110 110 dddddd -- MTPI/MTPD Move To Previous Instruction/Data
Pops a word from the current stack as indicated in the PSW to the operand address in the
previous address space, as indicated in the PSW. On PDP-11s that do not support
separate instruction and data spaces, MTPD is treated the same as MTPI.
b 000 110 111 dddddd -- SXT/MFPS Sign Extend/Move From Processor Status
SXT sets the destination to zero if the N (negative) flag is clear, or to all ones if N is set.
This is useful for implementing arithmetic subroutines with more than word-sized
operands.

MFPS copies the processor status byte to the indicated register. This only exists on LSI-
11s, and is needed there because those systems don't support accessing registers via
memory addresses.

Branches
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d|
| Branch Code | Destination |

The destination of a branch is +127 to -128 words from the word following the branch
instruction itself. This seems slightly odd, until you realize the sequence of events: the branch
instruction is read from memory and the PC incremented. If the branch is to be taken, the offset
is then added to the current value of the PC. Since the PC has already been incremented, the
offset is thus relative to the following word. Note that all branch instructions are one word long.

The various branches test the values of specific condition codes, and if the tests succeed,
the branch is taken. The condition codes are N (negative), Z (zero), C (carry), and V (overflow).
In the table below, the branch tests are shown as boolean expressions. `x' stands for exclusive-
OR. `v' stands for inclusive-OR.

0 000 000 1dd dddddd

BR: Branch Always
0 000 001 0dd dddddd
BNE: Branch if Not Equal (Z==0)
0 000 001 1dd dddddd
BEQ: Branch if EQual (Z==1)
0 000 010 0dd dddddd
BGE: Branch if Greater or Equal (NxV == 0)
0 000 010 1dd dddddd
BLT: Branch if Less Than (NxV == 1)
0 000 011 0dd dddddd
BGT: Branch if Greater Than (Zv(NxV) == 0)
0 000 011 1dd dddddd
BLE: Branch if Less or Equal (Zv(NxV) == 1)
1 000 000 0dd dddddd
BPL: Branch if PLus (N == 0)
1 000 000 1dd dddddd
BMI: Branch if MInus (N == 1)
1 000 001 0dd dddddd
BHI: Branch if HIgher (C==0 and Z==0)
1 000 001 1dd dddddd
BLOS: Branch if Lower Or Same (CvZ == 1)
1 000 010 0dd dddddd
BVC: Branch if oVerflow Clear (V == 0)
1 000 010 1dd dddddd
BVS: Branch if oVerflow set (V == 1)
1 000 011 0dd dddddd
BCC: Branch if Carry Clear (C == 0)
also known as
BHIS: Branch if Higher Or Same
1 000 011 1dd dddddd
BCS: Branch if Carry Set (C == 1)
also known as
BLO: Branch if Lower

Condition Code Operations

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|1|0|1|s|N|Z|V|C|
| O p c o d e | | Mask |

General opcode 000240x. Set/Clear corresponding bits depending on sense of bit 04 (set=1,
clear=0). Codes 240 and 260 set/clear no bits and are, thus, used as NOP. Although specific
mnemonic are provided for each flag and all flags, any combination may actually be set or
cleared at a time.

General mnemonics are:

CLx Clear x, where x is N, Z, V, or C

SEx Set x, where x is N, Z, V, or C
CCC Clear all condition codes
SCC Set all condition codes

0 000 000 010 1s0 000

NOP/NOP: No Operation
0 000 000 010 1s0 001
SEC/CLC: Set/Clear Carry
0 000 000 010 1s0 010
SEV/CLV: Set/Clear Overflow
0 000 000 010 1s0 100
SEZ/CLZ: Set/Clear Zero
0 000 000 010 1s1 000
SEN/CLN: Set/Clear Negative
0 000 000 010 1s1 111
SCC/CCC: Set/Clear All Condition Codes
Other, Miscellaneous
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|1|0|0|L|L|L|d|d|d|d|d|d|
| Opcode |Link_|Destination|

0 000 100 sss dddddd -- JSR Jump to Subroutine

The actual sequence of steps taken is:
MOV <Link>,-(R6)
MOV PC,<Link>
JMP <destination>

Thus, it loads the calling address into the specified link register (after saving the original
contents). It then jumps to the destination. The fun part is (as usual with the PDP-11) that
the PC is a general register, and the description above is the result when the PC is used as
the source.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|1|0|0|0|0|L|L|L|
| Opcode |Link_|

0 000 000 010 000 sss -- RTS ReTurn from Subroutine

Undoes the effects of a JSR. For predictable results, it is suggested that the same register
should be used as was named in the corresponding JSR instruction.

The actual operations involved are:

MOV <Link>,PC
MOV (R6)+,<Link>

This is the reverse of JSR. Obviously, the finesse here too is that you can use the PC, to
get what people normally consider a CALL/RETURN function.

Why is it done like this then? Well, consider this example:

...
JSR R0,FOO
.WORD A
.WORD B
MOV R1,C
...

FOO: MOV @(R0)+,R1

ADD @(R0)+,R1
RTS R0

This type of parameter passing is used extensively in the PDP-8 and PDP-10), for
example. Also, the FORTRAN runtime system on the PDP-11 do it this way. (It is fairly
easy to write a compiler that generates such a calling sequence, and then have a library of
functions which expect this calling convention.)
 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d|
| Opcode |Destination|

0 000 000 001 ddd ddd -- JMP JuMP

Loads the destination address into the PC, thus effecting an unconditional jump. Note that
a trap will occur on some systems if an odd address is specified. On others, the
destination is silently rounded down to the next-lower even address (i.e., the right-most
bit is ignored).
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|0|0|0|0|0|i|i|i|
| | | | | | Op |

0 000 000 000 000 000 -- HALT Halts the machine

Ceases I/O, and gives control to the console. Operator intervention is required to continue
or restart the system.
0 000 000 000 000 001 -- WAIT WAIT for interrupt
0 000 000 000 000 010 -- RTI ReTurn from Interrupt
0 000 000 000 000 100 -- BPT BreakPoint Trap
0 000 000 000 000 101 -- RESET Initializes the system

The following opcode ranges are all unused:

00 00 07 .. 00 00 77
00 02 10 .. 00 02 27
00 70 00 .. 00 77 77
07 50 40 .. 07 67 77
10 64 00 .. 10 64 77
10 67 00 .. 10 77 77

Other arithmetic and floating point instructions were added to the basic set over the years, but
those listed above form the core PDP-11 instruction set.