EMV Smart Card Reader

EMV SMART CARD READER/WRITER
Contents
EMV Smart Card Reader/Writer
Chapter 7.14
INTRODUCTION ...................................................................................................... 7.14-1
GENERAL DESCRIPTION ....................................................................................... 7.14-1
FUNCTIONAL DESCRIPTION ................................................................................ 7.14-3
EMV SCRW MODULE ............................................................................................. 7.14-3

MECHANICAL OPERATION ............................................................................. 7.14-3
SOFTWARE OPERATION ................................................................................. 7.14-4
Modes of Operation........................................................................................... 7.14-4
Card Entry ......................................................................................................... 7.14-4
Normal Sequence .............................................................................................. 7.14-4
ELECTRICAL OPERATION................................................................................ 7.14-5
Input Signals...................................................................................................... 7.14-5
Output Signals ................................................................................................... 7.14-5
Contacts ............................................................................................................. 7.14-5
Power Requirements ......................................................................................... 7.14-6
EMV SCIF BOARD ................................................................................................... 7.14-7

EMV SCIF CORE ELECTRONICS...................................................................... 7.14-7
Processor and Support Circuitry ....................................................................... 7.14-8
Memory and Address Decode ........................................................................... 7.14-9
Level 0 Diagnostics......................................................................................... 7.14-10
INTERFACES ..................................................................................................... 7.14-10
Power Interface ............................................................................................... 7.14-11
PIA Interface ................................................................................................... 7.14-11
SCRW Interface .............................................................................................. 7.14-14
Smart Card Interface ....................................................................................... 7.14-16
Smart Card Signal Chaacteristics .................................................................... 7.14-24
Power Fail Interface ........................................................................................ 7.14-25
Test Connectors............................................................................................... 7.14-25
ERROR CODES AND DIAGNOSTICS.................................................................. 7.14-27

LEVEL 0 DIAGNOSTICS .................................................................................. 7.14-27
Switch Settings................................................................................................ 7.14-27
LEDs................................................................................................................ 7.14-27
7.14-i
Test Descriptions EMV-SCIF ......................................................................... 7.14-28

Test 01 - CPU and EPROM ............................................................................ 7.14-28
Test 02 - External Memory ............................................................................. 7.14-29
Test 03 - External Data Memory Address and data Lines .............................. 7.14-29
Test 04 - NVRAM Initialize Disabled ............................................................ 7.14-30
Test 05 - NVRAM Initialize Enabled ............................................................. 7.14-30
Test 06 - Smart Card Communication Test..................................................... 7.14-30
Test 07 - Card Clock - Stop Low .................................................................... 7.14-31
Test 08 - Card Clock = XTAL/ 2 MHz ........................................................... 7.14-31
Test 09 - Card Clock = XTAL/ 4 MHz ........................................................... 7.14-31
Test 0A - Card Clock = XTAL/ 8 MHz .......................................................... 7.14-31
Test 0B - Card Clock = FINT/ 2 MHz ............................................................ 7.14-32
Test 0C - Card Stop High ................................................................................ 7.14-32
Test 0D - Card Signal Toggle ......................................................................... 7.14-32
Test 0E - Exercise Stopper Pin........................................................................ 7.14-32
Test 0F - Exercise Contact Unit ...................................................................... 7.14-33
SMART CARD STAGE ................................................................................. 7.14-33
SMART CARD RESET.................................................................................. 7.14-33
SMART CARD RELEASE ............................................................................ 7.14-33
SCIF INITIALISE........................................................................................... 7.14-34
SCIF SOLENOID ........................................................................................... 7.14-34
SCIF IDENTIFY ............................................................................................. 7.14-34
RUN-TO-RUN 1 ............................................................................................. 7.14-34
RUN-TO-RUN 2 ............................................................................................. 7.14-35
RUN-TO-RUN 3 ............................................................................................. 7.14-35
M_STATUS .................................................................................................... 7.14-35
M_DATA ........................................................................................................ 7.14-36
LEVEL 3 DIAGNOSTICS (TALLIES) .............................................................. 7.14-37
STRAPPING............................................................................................................. 7.14-39
ADJUSTMENTS ...................................................................................................... 7.14-39
TEST EQUIPMENT................................................................................................. 7.14-39

DIAGNOSTIC TEST CARDS ............................................................................ 7.14-39
PREVENTIVE MAINTENANCE ........................................................................... 7.14-39
INTERCONNECTIONS .......................................................................................... 7.14-39

SOLENOIDS AND PHOTODETECTOR CONNECTIONS ............................. 7.14-40
MOTOR AND SHUTTER CONNECTOR ......................................................... 7.14-41
SDC MCRW TO SCIF PIA INTERFACE BOARD ........................................... 7.14-42
SCIF TO MCRW CONTROLLER PIA CONNECTOR .................................... 7.14-43
POWER CONNECTIONS .................................................................................. 7.14-44
SMART CARD SIGNALS AND POWER ........................................................ 7.14-44
SCHEMATIC AND ASSEMBLY DIAGRAMS ..................................................... 7.14-45
7.14-ii
Contents
Chapter 7.14
EMV Smart Card Reader/Writer
INTRODUCTION
This chapter describes the EMV Smart Card Reader/Writer (SCRW) modules
that are attached to MCRWs in NCR ATMs to provide the ability to read and
write to smart cards. The combined SCRW and MCRW is refered to as the
Magnetic Smart Card Reader (MSCR). There are two types:
1. The MSCR reads and writes to smart cards and ISO magnetic cards in
compliance with the ISO 7816 (parts 1, 2 and 3) and the AFNOR/CP8 I.C.
card standards. The associated electronic circuits for the EMV SCRW are
contained on the EMV Smart Card Interface (SCIF) board.
2. The EMV MSCR replaces the above module. It provides the same func-
tions and additionally is designed to be compatible with EMV, GIE CB
(France), and Mondex. The term EMV is derived from Europay, Master
Card, and Visa. Its associated electronics board is termed the EMV SCIF.
GENERAL DESCRIPTION
The EMV Smart Card Reader/Writer (SCRW) reads and writes to smart cards
and ISO magnetic cards in compliance with EMV 3.1.1 and ISO 7816 (parts 1,
2 and 3) and the AFNOR/CP8 I.C. card standards. The Smart Card must have
the contacts at the front of the card and may have a magnetic strip at the
reverse side. Smart Cards with contacts in either the IOS position or the
AFNOR (CP8) position are supported.
The EMV SCRW feature adds on to the Magnetic Card Reader/Writer
(MCRW) or Magnetic Card Reader (MCR) modules for the 56XX/personaSXX
range of NCR Self Service Financial Terminals. The additional electronic func-
tions necessary for reading and writing of smart cards are provided by the
EMV Smart Card Interface (EMV SCIF) board which is also attached to the
MCRW. The main functional areas of the EMV SCIF board are shown in the
following block diagram.
7.14-1
EMV PIA
MCRW I/F
SCIF
SDC
I/F
MCR/MCRW PIA SCRW MCRW

SDC I/F Board
When an EMV SCRW module and EMV SCIF are configured in the host
machine the EMV SCIF interfaces with the same PIA bus (from the SDC
MCRW Interface Board) as the MCRW. A smart card command sent by the
host is identified by the EMV SCIF, which then disables the PIA interface to
the MCRW and takes control of the MCRW. Once the smart card operation is
complete, control is passed back to the host/MCRW interface.
The EMV SCIF also provides an encrypting function, with the encryption
algorithm incorporated in the firmware and the encryption keys stored in non-
volatile memory.
The following figure shows the EMV SCRW feature attached to an MCRW
7.14-2
FUNCTIONAL DESCRIPTION
The functional description of the EMV SCRW Module and EMV SCIF Board is
provided in the following sub-sections:
z EMV SCRW Module:
z Mechanical Operation
z Software Operation
z Electrical Operation
z EMV SCIF Board:
z SDC Interface
z EMV SCRW Interface
zz MCRW Interface.
In addition to the above interfaces, there are circuits associated with han-
dling power failure and providing test connectors.
EMV SCRW MODULE

MECHANICAL OPERATION
The figure below shows the components of the EMV SCRW Module:
Contact
Solenoid
Solenoid
Stopper Sensors
Pin PCB
Solenoid
Stopper Card Entry

Pin Mouth
Card
Sensor
Contacts
The EMV SCRW attaches to the rear of the MCRW/MCR. The rear trans-
port shaft of the MCRW/MCR is modified to have a double belt pulley turned
by a pint through the shaft which creates a half-turn clutch. A rubber wheel
on the shaft bears down on a lower nylon wheel to drive a card, passing
between them, into the EMV SCRW. The card is pushed against a reference
surface on the right-hand side of the EMV SCRW by a flat metal spring
attached to the left-hand side.
7.14-3
The card is detected in the EMV SCRW by an optical sensor (PD7). A sole-
noid energizes to lower a pin into the path of the card and stop it in position
under a set of spring metal contacts. The action of the solenoid is detected by a
photodetector (PD5) looking at a flag on the solenoid arm.
With the card correctly in position, a second solenoid is energized to lower
the spring metal contacts on to the contact area of the card. Another sensor
(PD6) detects the movement of this solenoid.
An O-belt from the MCRW rear transport pulley drives a shaft at the rear
of the EMV SCRW. This shaft carries a rubber wheel which bears down on a
lower nylon wheel to drive cards into the card capture bin. In a normal trans-
action the card will not reach these drive wheels but remain in the grip of the
MCRW rear transport wheels which reverse direction to drive the card back to
the cardholder.
SOFTWARE OPERATION
Control of the EMV SCRW is provided by the EMV SCIF board which has its
own on-board firmware. This firmware communicates with the host SSFT via
the SDC MCRW Interface Board, to control the solenoid and card movement
when in the smart card mode.
Modes of Operation
At initialization the MCRW/SCRW device driver and the EMV SCIF board
adopt MCRW mode. The device driver interrogates the hardware to determine
if the EMV SCIF is present and functioning correctly. If all is O.K. the device
driver will control the EMV SCRW by sending EMV SCIF commands to the
SCIF board (see the section “Normal Sequence” for a list of SCIF commands).
All hardware signals, including MCRW signals, are routed through the
EMV SCIF board. When a EMV SCIF command is received by the board, it
switches to EMV SCRW mode, produces the associated signals to achieve that
command and then switches back into the MCRW mode. The EMV SCIF
switches into the SCRW mode for the duration of each EMV SCIF command.
Card Entry
Card entry is identical to MCRW/MCR card entry. Once the card width and
card sense requirements are met and under application control, the card is
accepted and staged in the transport by the motor in the MCRW/MCR. An
EMV SCIF command is then issued to stage the smart card in the EMV
SCRW so that it is ready to be read from or written to.
Normal Sequence
The normal sequence of events for smart card operation is as follows:
z The MCRW/MCR Accept command stages the card
z The EMV SCIF command Stage Smart Card moves the card into the EMV
SCRW
z The EMV SCIF command Power On Card applies to the card and produces
an Answer To Reset from the card
z The EMV SCIF command Smart Card Direct reads/writes to the card.
These commands are card specific
z The EMV SCIF command Power Off Card removes power from the card
z The EMV SCIF command Release Card moves the card back to the
MCRW/MCR stage position.
7.14-4
ELECTRICAL OPERATION
The electrical logic to control the EMV SCRW is wholly located on the EMV
SCIF board as described on the section “EMV SCIF Board”. Connectors on the
EMV SCRW carry the power supplies, the signals from the smart card, the
sensor status, and the solenoid control signals, to the EMV SCIF board. Refer
to the section “Interconnections” for pinouts of these connectors.
Input Signals
The input signals are as follows:
z STP - When this signal is activated, the card stage stopper pin mechanism
is lowered
z TUD - When this signal is activated, the Connector lowering mechanism is
lowered.
Output Signals
The following TTL compatible output signals are generated:
z PD5 - This signal becomes logically high when the card stopper pin is low-
ered
z PD6 - This signal becomes logically high when the smart card contacts are
lowered on to the card
z PD7 - This signal becomes logically high when the smart card is correctly
staged in the EMV SCRW.
Contacts
Two rows of eight contacts are lowered on to the card. Of the 16 contacts, eight
are in the ISO contact group position and eight are in the AFNOR/CP8 contact
group position. The contacts provide power, and read or write, to cards of both
the ISO and AFNOR/CP8 formats.
Smart Card Contacts for ISO

The positions of the contacts on an ISO standard card are shown in the figure
below, with the position of the magnetic strip (on the underside of the card),
shown by dotted lines.
Rear of SCRW Magnetic Stripe
1 5
2 6
3 7
4 8
7.14-5
Smart Card Contacts for AFNOR/CP8

The positions of the contacts on a AFNOR/CP8 standard card are shown in the
figure below, with the position of the magnetic strip (on the underside of the
card), shown by dotted lines.
Rear of SCRW Magnetic Stripe
8 4
7 3
6 2
5 1
Function of Contacts
The following table lists the functions of the card contacts.
Contact
Signal Function
No.
VCC 1 Card power supply voltage
RST 2 Reset signal
CLK 3 Clock signal
RFU 4 Reserved for future use
GND 5 Ground
VPP 6 Not used
I/O 7 Data input/output
RFU 8 Reserved for future use
Power Requirements
Power for the SCRW is supplied from the SCIF board for stopper pin lowering,
lowering of contacts, and sensor operation. The maximum power required for
these functions is shown below.
Voltage Current Regulation

+VDD 24 Vdc 800 mA (operating ±10%
+VDD 5 Vdc 50 mA (operating ±5%
250 mA p-p
7.14-6
EMV SCIF BOARD
EMV PIA
MCRW I/F
SCIF
SDC
I/F
MCR/MCRW PIA SCRW MCRW

SDC I/F Board
In the following text the functions of the EMV SCIF are described with
reference to four areas in the block diagram above.
z EMV SCIF core electronics
z MCR/MCRW SDC I/F Board
z SDC I/F
z MCRW I/F
z SCRW I/F
z SCRW/MCRW.
In addition the following interfaces are also provided:
z Power interface
z Power fail interface
z Test connectors.
The schematics for the EMV SCIF Board are included at the end of this
chapter. Refer to these schematic diagrams while reading the following circuit
description.
NOTE: Sheets 4 and 5 of the schematics show a possible future expansion to

the interface board. This circuit is not described.
EMV SCIF CORE ELECTRONICS

The core of the EMV SCIF is the controlling electronics which is designed
around an 8 bit embedded controller.
The controlling electronics is described in the following subsections:
z Processor and support circuitry
z Memory and address decode
z Level 0 diagnostics
z Smart card interface signals.
7.14-7
Processor and Support Circuitry

Refer to schematic sheet 3 when reading the following text.
The processor is an TDA8006 8bit embedded controller operating at a fre-
quency of 14.745 MHz which is provided by a TTL compatible clock oscillator
with a 2K pull up resistor. This clock is also used to drive the smart card
encryptor timing circuits.
Port 0 of the processor operates as a multiplexed address/data bus with
the address latched by the ALE signal. The serial port provides the communi-
cation interface with the smart card.
The power-up/power-down and reset circuits are provided by a dedicated
microprocessor supervisory circuit. (Maxim 691) device which supplies a con-
tinuous voltage to the RAM, thereby providing an area of non-volatile memory.
A 3.6 volt 1 ampere-hour lithium battery supplies the RAM in the event of a
power failure.
Two fast reacting Schottky diodes are incorporated in the series path from
the battery to the Maxim 691A device to prevent a possible charging current
flowing into the battery. This satisfies UL/CSA safety requirements. A1 micro-
farad capacitor is included in the Maxim output circuit to provide smoothing
when switching.
The Maxim 691 also provides a reset signal which is used with the power-
up cycle. This reset signal, which is active high, lasts for approximately 35 to
70 ms (typically 50 ms). A 2K pull-up resistor ensures a strong reset signal.
7.14-8
Memory and Address Decode

The memory available on the board consists of 64 KB of EPROM and 32
KB of battery backed RAM. Memory-mapped I/O is located from8000H
upwards. This is above the 32K battery backed RAM.
The overall memory map is shown in the following figure.
Code Area Data Area

0FFFFH 0FFFFH
Not Populated
9000H
8FFFH
I/O
EPROM
8000H
7FFFH
NVRAM
7000H
Not Used
2000H
1FFFH
SRAM
0000H 0000H
Owing to the high population density of the board, all decodes for address
locations are performed by a 44-pin PLCC EPLD device. This device has a
large number of output ports which allow both RD- and WR- qualification on
address selection. The RD- and WR- qualification originates from the proces-
sor. Two 0.47 microfarad capacitors decouple the noise from the voltage plane
as required by the EPLD internal architecture.
7.14-9
The positions of the various ports in the memory-mapped I/O portion of

the overall memory map are shown in the following table:
RD/WR port Address

RD- MCRW Port A 8000H
WR- MCRW Port A
RD- MCRW Port B 8001H
RD- SCRW Status Port 8002H
WR- SCRW Card Control Port
WR- Not used 8003H
WR- Not used 8004H
RD- Not used 8005H
WR- Not used
RD- Switch Pack Level 0 8006H
WR- LEDs Level 0
Level 0 Diagnostics
The Level 0 diagnostics are performed using an 8-way switch pack and
eight LEDs.
The 8-way switch pack U4 is used for setting and running the extended
level 0 testing. The appropriate switch setting is obtained by reading memory
mapped I/O at address 8006H. When the switch is open a logical low is read
and, when closed, a logical high.
The 8 LEDs display information about the level zero tests that are being
run and also the result of the tests. The LEDs are accessed by writing to mem-
ory location 8006H. Each LED can be written to individually. A logical low sig-
nal turns the LED on, and a logical high turns the LED off.
The switch pack and LED signals are brought out to a DUAL 10-way RDI
connector along with a reset signal. This allows the board to be tested using a
remote level 0 testing device.
INTERFACES
The SCIF provides the following interfaces:
z Power
z PIA
z Port A
z Port B
z SCRW interface
z Input port
z Output port
z Solenoid drivers
z Smart card interface
z Smart card programming voltage (VPP)
z Digital to analogue conversion
z Vpp current limiting
z Smart card clock generation
z Smart card data (ISOn and AFNOR/CP8)
z Smart card Vcc
7.14-10
z Power fail interface

z MVF and MCB sense circuit
z MCF and MCB control output
z Test connectors
z Test evaluation connector
zz Remote diagnostic interface.
Power Interface
Refer to the schematic sheet 2 when reading the following text.
Dual 4-way connector J11 provides three power lines (+24V, +12V, +5V)
and associated return Grounds. T ensure good noise immunity, these lines are
connected directly into the inner planes of the PCB.
PIA Interface
Refer to the schematic sheets 1 and 9 when reading the following text.
The EMV SCIF monitors the PIA interface. When a smart card instruction
is recognised the EMV SCIF latches the data to the MCRW and assumes con-
trol.
The SCIF executes the smart card instruction then passes control back to
the host.
The PIA interface can be divided into the sections, Port A interface and
Port B interface. These are shown in the following figure:
Buffer 1
74ALS652 EMV SCIF
MCRW EMV SCRW

Buffer 2
Data
74F623
Buffer 3
Status Information
Host 74ABT623
PIA I/F
Port A Interface
Port A is an 8-bit wide bi-directional port which interconnects the following
status information:
z EMV SCIF to host
z Host to EMV SCIF
z MCRW to host
z Host to MCRW.
NOTE: EMV SCIF to MCRW and MCRW to EMV SCIF never occur.
7.14-11
The format of the signals is divided into sections A select, B select and C
select as shown below. For more information on the signal functions refer to
Chapters 7.2, 7.3, or 7.7.
Bit A Select B Select C Select

0 DW0 DR0 PD1
1 DW1 DR1 PD2
2 DW2 DR2 PD3
3 DW3 DR3 Busy
4 DW4 DR4 SW2
5 DW5 DR5 SW1
6 DW6 DR6 PD7
7 Not Used DR7 PD5 - PD6
The schematics (sheet 1 and 9) for the interconnections of Port A, show

that a communication link is present between the host and the MCRW and
between the host and the EMV SCIF. There is no direct communication
between the EMV SCIF and the MCRW.
The data is read and written by the EMV SCIF through buffer 1 (a
74ALS652, U37) which is mapped at memory location 8000H.
Buffer 2 (a 74F623, U44) provides the interface between the host and the
MCRW/SCRW.
Buffer 3 (74F623, U36) enables bit 0 to 5 from the MCRW and PD5, PD6
and PD7 from the SCRW on to the host’s bus. When the SCIF is in the smart
card mode buffer 2 and 3 are set to a high impedance.
DTA_s
DTAR
Data Valid Data
EMV SCIF to Host Handshaking Sequence
Data is written to the host using a handshaking mechanism that exists

between the host and the MCRW and uses signals DATR and DTA. A similar
method is used to transfer the data between the host and the EMV SCIF but
using signals DTA_s and DATR_s. When a smart card command is identified,
the data is latched into buffer 3 by writing to location 8000H.
The host requests data by setting DATR low. The data is then put on the
host bus by setting DATR_s low, DTA_s is also set low to indicate that data is
present from the EMV SCIF. The host acknowledges receipt of the data by set-
ting DATR high. The Handshake sequence is completed by setting DTA_s
high.
7.14-12
DTA_s
DTAR
Data Valid Data
Host to EMV SCIF Handshaking Sequence
A similar method of hand-shaking is used to read data from the host. The
EMV SCIF sets DTA_s low to indicate to the host that data is required. The
host responds to outputing the data to the bus and setting DATR low. The
SCIF reads the data by reading memory location 8000H.
DTA_s is reset high by the SCIF after the data is read and accepted. The
host then resets the DATR signal high and DATR is checked to ensure that
the host to EMV SCIF communication link is functioning correctly.
Port B Interface
The Port B interface carries the commands from the host to both the MCRW
and the EMV SCIF. It is through this interface that the smart card instruction
is sent. When the latch clock signal, LC, goes from a high to low transition an
interrupt is generated and the EMV SCIF firmware checks for a smart card
command. A smart card command is generated when:
z The SELECT signal is low
z The SC MODE signal is low
z The LC signal is an active low pulse.
The lower five bits of Port B are multiplexed by bit 7 of this port and are
referenced as register A and register B. These signals are detailed below.
NOTE: A hardware reset is generated by toggling PB3, Register A.
Port B
Register A Register B
Bit
PB0 MCF TS0
PB1 MCB TS1
PB2 SHE RW0
PB3 Reset RW1
PB4 SC Mode DT
PB5 DATR
PB6 Select
PB7 LC
7.14-13
Port B is located in memory mapped I/O at address 8001H. The Port B

commands from the host to the MCRW are interfaced through buffer 5 (a
transparent latch 74LS373, U45). When the EMV SCIF detects a smart card
command the SCIF_En signal is set high latching the signal from Port B to
the MCRW.
SCRW Interface
Refer to schematic sheet 6 and 7.
The MCRW interface is mapped in memory I/O at location 8002H and con-
sists of an input and an output port. All signals associated with the status,
that is, the sensors and control for the solenoids, are connected through this
interface.
Input Port
The input port (a 74HCT244,) is accessed by reading data from memory
location 8002H.
The signals associated with each bit are listed below:
Bit Signal
0 PD7
1 PD5
2 PD6
3 Not used
4 Not used
5 Not used
6 Not used
7 Not used
A description of each bit follows:

z Bit 0 - PD7 indicates if a card is present in the SCRW. A logical high signal
on this line indicates that a card is present. On power up, when no card is
present, this signal is low
z Bit 1 - PD5 reflects the status of the SCRW stop pin which is used to posi-
tion the card for correct contact alignment. The signal is low if the pin is in
the lowered position
z Bit 2 - PD6 indicates the position of the smart card contacts. If the con-
tacts are down and in contact with the card PD6 is a logical low. If the con-
tacts are up and not in contact with the card PD6 is high
z Bit 3 - Not used
z Bit 4 - Not used
z Bit 5 - Not used
z Bit 6 - Not used
z Bit 7 - Not used.
7.14-14
Output Port
U24 (a 74F259 latch) generates the signals on the SCRW output port. This
allows each bit to be individually addressed. A coded byte is written to location
8002H in the memory mapped I/O area. The byte is then decoded by the
hardware and the appropriate output bit set. The coded bytes should be
written to the output port, and the expected output, are given in the table
below:
Data Bit
0 4 5 6 Byte (hex) O/P Signal
Bit
0 Y0 L L L 00-low 01-high Y0 MCF_s
1 Y1 L L H 10-low 11-high Y1 MCB_s
2 Y2 L H L 20-low 21-high Y2 STP
3 Y3 L H H 30-low 31-high Y3 TUD
4 Y4 H L L 40-low 41-high Y4 SCIF_En
5 Y5 H L H 50-low 51-high Y5 Not used
6 Y6 H H L 60-low 61-high Y6 Not used
7 Y7 H H H 70-low 71-high Y7 Not used
A description of each signal follows:

z MCF_s - This signal controls, in conjunction with the MCB_s signal, the
motor direction. When MCF_s is high and MCB_s is low the card moves
forward in the MCRW
z MCB_s - This signal controls, in conjunction with the MCF_s signal, the
motor direction. When MCB_s is high and MCF_s is low the card moves
backwards in the MCRW
z STP - This signal operates the card stop solenoid. The solenoid is activated
when STP is set high
z TUD - This signal operates the smart card contact solenoid. When TUD is
set high the solenoid activates lowering the contacts on to the smart card
z SCIF_En - This bit is set high to enable the SCIF and disable/latch the
PIA signals to the MCRW
z CLK_SEL (CLOCK_SELECT) - Not used.
NOTE: The outputs of this buffer are all set low by a system reset.
Solenoid Drivers
The card stop pin and card contact solenoids are controlled by Darlington
power transistors. The STP and TUD signals are pulled high to 5 volts
through 2K2 resistors. This ensures sufficient base drive to saturate the
transistors.
Current limiting is obtained by a 470R resistor in the series path of the
base. Noise decoupling from the transistor base is obtained by a 0.1 micro-
farad capacitor. This reduces any ringing effect that may result from high
speed switching. Any back emf is decoupled by connecting two Schottky diodes
in reverse mode across the solenoid coils.
7.14-15
Smart Card Interface

Refer to schematic sheet 3.
The smart card signals originate from the Philips TDA8006 custom micro-
processor. This custom device is designed with compatibility for emerging
standards such as EMV, GIE CB and Mondex. All these standards request
that Vpp is not connected to contact C6 as specified by ISO 7816. An enable
link is implemented on the EMV SCIF interface so that where systems require
Vpp it may be configured. The default is Vpp disconnected.
The TDA8006 supports all other signals from the smart card (Data I/O,
reset, Vcc, clock).
TDA8006 Internal Architecture)

The Philips TDA8006 custom microprocessor has three major blocks
associated with the setup and control of the smart card signals. The 80C52
core addresses these blocks through four address lines (P1.2 to P1.5), two
control lines (P1.6 and P1.7), and an 8-bit data bus (P4.0 to P4.7).
The figure below shows the basic structure:
80C52 Core
P4.0 to P1.6 & P1.2 to

P4.7 P1.7 P1.5
Control Lines
Address Bus
Data Bus
En- ADO Data En- ADO Data En- ADO Data

& to Bus & to Bus & to Bus
R/W- AD3 R/W- AD3 R/W- AD3
ISO 7816 UART ON/OFF Sequencer Clock Generator
Smart Card Interface Circuitry
Smart Card
Each block contains registers that require setting before the device
becomes operational. The mechanism to address, read and write to/from these
blocks listed in the table below:
Two control signals are used to transfer data to or from the data bus. The
enable signal (En-), when set to low, permits data to flow between the 80C52
core and the registers within each functional block. The second contgrol signal
(R/W-), controls the direction the data flows, if R/W- is set high then data is
read and if R/W- is low, then data is written.
7.14-16
NOTE: After resetting En- high, the controller must set P4 high to free up
the data bus. The address lines AD0 to AD3 are used to select the appro-
priate register.
The read and write procedures are summerized as follows:

z Read operation
z Set P4 to FFH
z Select the appropriate register with AD0, AD1, AD2, AD3
z Set R/W- high
z Set En- low, the data is available on the data bus
z Read the data
z Set En- high
zz Set P4 to FF hex, the bus is back to high Z
z Write operation
z Select the correct register with AD0, AD1, AD2, AD3
z Set R/W- low
z Write the data to the data bus
z Set En- low, the data is written into the register
z Set En- back high
zz Set P4 to FF hex, the bus is back to high Z.
These sequences are summerized as follows :
P4 XX FF DATA FF DATA FF
R/W
AD0...3 X AD AD
EN
READ DATA CYCLE WRITE DATA CYCLE
The addresses of the various control registers are listed in the table below.
Functional Block Register W/R- AD0 AD1 AD2 AD3

Clock Generator Clock Configuration Register (CCR) 0 0 0 0 0
Programmable Divider (PDR) 0 1 0 0 0
ISO 7816 UART Synchronous Out Register (SOR) 0 1 1 0 0
Synchronous In Register (SIR) 1 1 1 0 0
UART Transmit Register (UTR) 0 0 0 1 0
UART Receive Register (URR) 1 0 0 1 0
UART Status Register (USR) 1 1 0 1 0
UART Configuration Register (UCR) 0 1 0 1 0
Guard Time Register (GTR) 0 0 1 1 0
ON/OFF sequencer Peripheral Extension Register (PER) 0 1 1 1 0
7.14-17
The setup procedures and functions of each register is explained in the fol-
lowing sections.
Clock Generator Configuration

The clock to the microcontroller (OSC), the clock to the card (CLK), the clock
to the ISO 7816 UART and the clock to the external world (LCLKOUT) are
derived from the main clock signal (XTAL = 14.745 MHz), or the internal
oscillator (f INT). The frequencies at which each clock operates is determined by
the contents of two, write only, registers - namely the CCR and the PDR.
The following two tables show the possible setup configurations:
Clock Configuration Register (CCR)
D7 D6 D5 D4 D3 D2 D1 D0 UART CLK CLKOUT OSC

X X X X X X X 0 /31
X X X X X X X 1 /32
X X X X 0 0 0 X Stop low
x x x x 0 0 1 X XTAL/2
X X X X 0 1 0 X XTAL/4
X X X X 0 1 1 X XTAL/8
X‘ X X X 1 0 0 X Fint/2
X X X X 1 0 1 X Stop high
X X 0 0 X X X X XTAL/4
X X 0 1 X X X X XTAL
X X 1 0 X X X X XTAL/2
0 0 X X X X X X Fint/8
0 1 X X X X X X XTAL
1 0 X X X X X X XTAL/2
1 1 X X X X X X Fint/2
Programmable Divider Register (PDR)
D7 D6 D5 D4 D3 D2 D1 D0 Division factor
x7 x6 x5 x4 x3 x2 x1 x0 x7x6x5x4x3x2x1x0 hex
After power-on or reset, the microcontroller is clocked with fINT/8. On

completion of the power-on sequence, the application may decide to change the
operating clock frequency to f INT/2, or fXTAL/2 or fXTAL. All frequency changes are
aynchronous, ensuring no hang-up due to short spikes etc.
It is possible to select one of four different frequencies for the smart card
clock (CLK) output. The frequencies are fXTAL/2, fXTAL/4, fXTAL/8 or fINT/2 (1.2
MHz), the clock signal can also be stopped in either the high or low logical
states. All transitions are synchronous, ensuring correct pulse length during
start or change in frequency, in accordance with ISO 7816. After power-on or
reset, CLK is stopped at low level.
7.14-18
The clock that drives the ISO 7816 UART originates from the clock that
drives the smart card clock contact. To achieve the different baud rates on I/O
as defined by the F and D parameters (as specified in ISO 7816 part 3), a pres-
caler (divide by 31 or 32) and an autoreload 8 bit programmable counter is
implemented (internal to the TDA8006). The following table shows what val-
ues should be loaded to archive the appropriate F and D values.
D \F 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
0001 31;F4 31;F4 31;EE 31;E8 31;DC 31;D0 31;C4 32;F0 32;E8 32;E0 32;D0 32;CD
0010 31;FA 31;FA 31;F7 31;F4 31;EE 31;E8 31;E2 32;F8 32;F4 32;F0 32;E8 32;E0
0011 31;FD 31;FD - 31;FA 31;F7 31;F4 31;F1 32;FC 32;FA 32;F8 32;F4 32;F0
0100 - - - 31;FD - 31;FA - 32;FE 32;FD 32;FC 32;FA 32;F8
0101 - - - - - 31;FD - 32;FF - 32;FE 32;FD 32;FC
0110 - - - - - - - - - 32;FF - 32;FE
1000 31;FF 31;FF - 31;FE 31;FD 31;FC 31;FB - 32;FE - 32;FC -
1001 - - - - - - 31;FD - - - - -
NOTE: The prescalar value is first and the PDR value is second.
On/Off Sequencer Configuration

The on/off sequencer block main function is to control the activation/ de-
activation of the smart card interface. The register that addresses this
function is called the Peripheral Extension Register (PER). The PER is a write
only register. The bit allocation of the PER is as follows:
Bit Name Description

D0 CMDVCC Set high to start activation sequence
Set low to start de-activation sequence
D1 RSTIN Set card RST control to minimum
D2 FIP (Force Inverse Parity) Set low to process data parity as specified by ISO7816 part 3.
Set high to process data in an inverse format. (This forces par-
ity errors in transmission and NAKs in reception - to aid test-
ing)
D3 ATREN (Automatic ATR Set high to allow automatic control of ATR processing.
processing enable) Set low to disable automatic ATR processing.
D4 K0- Auxiliary 2mA push-pull output control (Inverted output)
The activation and de-activation sequences can only be initiated after the
ISO7816 UART has been reset and the card present bit is set. The activation
sequence is initiated by setting CMDVCC (PER, bit D0) high, conversely to
deactivate the smart card contacts this bit must be set low. To initiate a warm
reset, toggle RSTIN (PER, D1).
Activation/de-activation of the smart card contacts can be set to automatic
or manual mode by configuring bit D3 of the PER. When set for automatic
mode the UART starts counting the clock cycles during the ATR and the smart
card RST signal is controlled as specified by ISO7816 part 3. Data is received
before 2x45,000 smart card CLK cycles, if data is detected, this bit is reset and
7.14-19
the ATR is collected. If the UART detects no data within the specified time
frame then the card is declared mute, this bit (PER, D3) is reset by the hard-
ware.
The UART can be forced to operate with inverse parity checking. This is
used to generate parity errors in transmission of data and generate NAKs
during reception of data. This is only used as a debug tool.
ISO 7816 UART

The UART associated with the smart card signals is fully compliant with ISO
7816 part 3 supporting both T=0 and T=1 protocols (in conjunction with the
appropriate libraries). Synchronous cards are also supported by this device.
There are seven registers associated with this functional block, two regis-
ters (GTR and UCR) are used to configure the UART, the remaining registers
are used for data and status information. The registers are listed in the follow-
ing table, with subsequent sections describing their functions.
Symbol Expanded name Function

UTR UART Transmit Register Data control
URR UART Receive Register Data control
USR UART Status Register Status Information
SIR Synchronous In Register Data control
SOR Synchronous Out Register Data control
GTR Guard Time Register Control
UCR UART Configuration Register Control
UART Configuration Register (UCR)

The UART Configuration Register (UCR) is used to configure the UART. The
UCR is a write only register. The bit allocation and association functions are
as follows:
Bit Symbol Name Description

D0 RIUN Reset ISO UART Set low to reset the UART
Must be set high to allow UART use.
D1 SS Start Session Set high to allow auto detection of the con-
vention indicated by the initial character
during ATR.
D2 LCT Last Character to Transmit Set high to allow automatic toggling
between transmission and reception after
a successful transmission.
D3 TRN Transmit/Receive - N Set high to enable transmission mode.
Set low to enable reception mode.
An interrupt is generated when TRN is set.
D4 Not used Not used
D5 PS Protocol Selection Set high to enable protocol T=1.
Set low to enable protocol T=0.
D6 TFN 3V/5V Set high to enable 3V operation.
Set low to enable 5V operation.
D7 SAN Synchronous/Asynchronous -N Set high to allow direct monitoring of I/O.
Set low to allow I/O to feed into the UART.
7.14-20
In order to start a session with the card, the bit RIUN (UCR,D0), which
resets the ISO7816 UART when low, must be set high.
Reception: During reception, the UART recognises the convention (direct or

inverse) on the characters received while the Start Session (SS) bitis high. The
UART automatically converts any transmitted or received characters
accociated to this convention into characters written in direct convention.
NOTE: Thetart Session bit must be reset after correct reception of the first
character (TS) of the ATR and before complete reception of the next char-
acter.
Reception mode is selected when TRN is set low. An interrupt is generated

(if set to do so) that indicates when a character has been received. The inter-
rupt is cleared on the rising edge of the En- signal during a read cycle from the
UART Receiv Register (URR). ISO7816 part 3 defines the format and protocol
characteristics of the received data.
Transmission: Transimssion mode is selected by setting TRN high. If enabled,

an interrupt is generated on the rising edge of TRN, indicating that the
transmission buffer is empty and may be written to. The character is written
into the UTR on the falling edge of En- and during the write operation. Its
transmission starts on the rising edge of En-. ISO7816 part 3 defines the
format and protocol characteristics of the transimtted data.
Guard Time Register (GTR)

The Guard Time (GT) is a requirement of ISO7816 part 3, and is used to slow
down the transmission and reception of characters. the GT value is generally
passed back by the smart card when powered on initially (although the
application can also set GT using the protocol type select command).
The GTR ia a writ only register and is structured as follows:
D7 D6 D5 D4 D3 D2 D1 D0 Guard time T=0 Guard time T=1

x7 x6 x5 x4 x3 x2 x1 x0 x7x6x5x4x3x2x1x0 hex x7x6x5x4x3x2x1x0 hex
1 1 1 1 1 1 1 1 0 -1
UART Receive Register (URR)

The UART Receive Register (URR) is located at address 4 and is read only.
The data received from the card is transferred in direct convention (as
specified by ISO7816 part 3).
The received character is loaded into the URR 0.5 etu after receipt of the
parity bit. It is therefore essential that the previous character is read prior to
this time, otherwise the old character will be over written and lost. The parity
is automatically verified during character reception, the Parity Error (PE) flag
in the USR is set if an error is detected. At the same time the Receiv Buffer
Full (RBF) flag is also set in the USR.
7.14-21
UART Transmit Register (UTR)

The UART Transmit Register (UTR) is located at address 4 and is write only.
The data to be transmitted is written to register in direct convention (as
specified by ISO7816 part 3), the UART will then re-structure the data (as
specified by the TS format character).
The Transmit Buffer Empty (TBE) flag is set in the USR to indicate when
data can be loaded into the UTR. If this occurs beyond 12.5 etu + GT after the
previous start bit, then the transmission starts on the rising edge of En- dur-
ing the write operatiopn. If this occurs before 12.5 etu + GT, then the UART
will wait until 12.5 etu + GT after the previuus start bit before starting the
transmission.
UART Status Register (USR)

The UART Status Register (USR) is located at address 5 and is a read only
register. The register supplies information relating to the activity of the UART
and is used extensively to control the flow of traffic while receiving/
transmittion data.
7.14-22
NOTE: All bits with the exception of bit D5 will generate an internal inter-
rupt (INT-) when reset.
In case of Early Answer (EA) or Mute Card (MC) during automatic ATR
processing, the card is not automatically deactivated. An interrupt is gen-
erated if enabled, and it is up to the controller to deactivate or not.
Bit Symbol Name Description

D0 TBE TX Buffer Empty This bit is set when the UART has finished transmitting data,
or on the rising edge of TRN. It is reset on the rising edge of
En-, during a read status operation.
D1 RBF RX Buffer Full This bit is set when the UART has finished receiving a char-
acter from the card.
It is reset on the falling edge of En-, during the read charac-
ter operation.
D2 FSD First Start Detect This bit is set on the falling edge of the first start bit if SS = 1.
It is reset on the rising edge of En-, during a read status
operation.
D3 PE Parity Error This bit is set when a parity error is detected (by the UART)
when the UART is transmitting or receiving data.
operation.
D4 EA Early Answer This bit is set if a start bit is detected on I/O between 200
and 400 CLK pulses (when the UART is configured in Auto-
matic ATR poeration).
operation.
D5 OFF This bit is set if th ecard is present and reset if the card is not
present.
If CMDVCC is high, it may also be reset if a hardware prob-
lem causing an emergency deactivation sequence has
occurred.
D6 OFFI OFF Interrupt This bit is set when OFF (bit D5) changes.
operation.
D7 MC Mute Card This bit is set if a card has not answered after 90000 CLK
pulses when the ISO7816 UART is configured in Automatic
ATR processing.
operation.
Synchronous Cards
It is not a requirement of the EMV SCIF to provide an interface for
synchronous cards. However, the TDA8006 is capable of communicating with
synchronous cards and therefore, for completeness, this section briefly
describes the synchronous function.
If SAN (UCR, D7) is set then the software may deal with synchronous
card. I/O is copied on bit data0 of the data bus when SIR or SOR registers are
selected, without entering the UART. The synchronous cards clock can be con-
trolled by selecting STOP HIGH or STOP LOW on CLK.
When the Synchronous Input Register (SIR) is selected, I/O is copied on
data0 (P40). When the Synchronous Output Register (SOR) is selected, then
data0 (P40) is output onto the I/O line on the falling edge of En-.
7.14-23
Smart Card Signal Chaacteristics
Reset Signal
The drive capabilities of the Reset signal pin is as follows:
Symbol Parameter Conditions Min Typ Max Unit

VOL Low level output voltage IOL=200uA 0 - 0.3 V
VOH High level output voltage IOH=200uA Vcc-0.5 - Vcc V
tr Rise time C1=30pF - - 0.1 uS
tf Fall time C1=30pF - - 0.1 uS
Clock Signal
The drive capabilities of the Clock signal pin is as follows:

VOL Low level output voltage IOL=200uA 0 - 0.3 V
VOH High level output voltage IOH=200uA Vcc-0.5 - Vcc V
tr Rise time C1=30pF - - 8 nS
tf Fall time C1=30pF - - 8 nS
F Frequency 1.25 - 6 MHz
I/O Signal
The drive capabilities of the smart card I/O signal is as follows:

VOL Low level output voltage IOL=1mA 0 - 0.3 V
I/O configured as output
VOH High level output voltage IOH<=-50uA 0.8xVcc - Vcc+0.25 V
I/O configured as output
VIL Low level input voltage -0.3 - 0.8 V
I/O configured as input
VIH High level input voltage 1.5 - Vcc V
I/O configured as input
tr, tf Input transition times C1=30pF - - 1 uS
tr, tf Output transition times C1=30pF - - 0.1 uS
Rpu Internal pull-up resistor 8K 10K 12K Ohms
between I/O and Vcc
7.14-24
Vcc Signal
The drive capabilities of the smart card Vcc signal is as follows:

Vo(inactive) Output voltage no load 0 - 0.1 V
inactive 1mA injected 0 - 0.3 V
Vcc Output voltage Icc <65mA; 5V card 4.75 5 5.25 V
Icc <65mA; 3V card 2.8 3 3.2 V
Current pulses of 40nAs 4.6 - 5.4 V
with I<200mA, t<400nS,
f<20MHz; 5V card
Current pulses of 24nAs 2.75 - 3.25 V
with I<200mA, t<400nS,
f<20MHz; 3V card
Icc Output current 3V and 5V - - 65 mA
Overload detection - 80 - mA
Shutdown current - -90 - mA
Vcc shorted to ground - - 250 mA
SR Slew Rate Up or down (max cap 0.10 0.16 0.22 V/uS
300nF)
Vpp Signal
The default setting for the smart card Vpp signal is “no condition” as specified
by the EMV requirements document.
There is a link that lets the smart card Vcc signal to be routed to the Vpp
signal. Voltages greater than 5V on the Vpp line are not supported.
Power Fail Interface

Schematic sheets 11 and 12 show part of the SCIF circuit which is not used in
56XX SSFTs but is used by the power-fail module in 50XX ATMs. This is
described in Chapter 3.9 of the
Test Connectors
Refer to schematic sheets 8, 10 and 17.
Three test connectors are provided, a test evaluation connector, a remote
diagnostic interface connector, and a smart card signal connector.
Test Evaluation Connector

Dual 4-way connector J16 provides an interface for test evaluation processes.
It is used mainly during board manufacture.
The signals available at J16 are as follows:
z The three major clock signals 12 MHz, 14.31818 MHz and 19.6608 MHz
z The serial link signals, RXD and TXD
z The system reset signal, Test_Reset.
7.14-25
Remote Diagnostic Interface

The Remote Diagnostic Interface (RDI) is a dual 10-way connector, J9, which
provides the interface with the Level 0 diagnostic switch pack, U4, and LEDs.
These TTL-compatible signals are 8 bits wide. A reset line, RDI_RE_SET,
which is also TTL-compatible, is also provided and can be used to reset the
SCIF hardware.
Smart Card Signals Connector

Dual 3-way stake pin header J12 is provided to make it easier to test and
monitor the smart card signals rather than via the flexible signal connectors
J8 and J10. The signals on J12 pass via the flexible circuit connectors and,
therefore, breaks in the tracks on the SCIF pcb will also be detected.
This connector is only fitted to early EMV SCIF boards.
7.14-26
ERROR CODES AND DIAGNOSTICS

LEVEL 0 DIAGNOSTICS
Level 0 diagnostics tests for the SCIF/EMV SCIF execute whenever power is
applied or a hardware reset occurs. There are two modes of operation:
z Start-up. A sequence of tests which takes no longer than 10 seconds to run
z Extended Level 0 diagnostics. Individual tests can be selected to run.
All the diagnostics tests performed during the start-up diagnostics can
also be performed by using the extended diagnostics.
NOTE: There are no “Loop” or “Continue on Error” options available with

these diagnostics.
Switch Settings
Select the diagnostic mode using the eight switches (SW1 to SW8) located on
the diagnostic switchpack. These switches are numbered 1 (LSB), for the
right-most switch, to 8 (MSB), for the left-most switch.
Switch No. SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1
Start-Up 0 0 0 0 0 0 0 0
Selected 1 0 0 <--------------------TEST ID------------------>
0 = Switch open
1 = Switch closed
LEDs
The test results display on the eight LEDs, D1 to D8. These LEDs are
numbered 1 (LSB), for the right-most LED, to 8 (MSB), for the left-most LED.
The test number displays on LED 1 to 5.
If a test fails, the test number shows for one second and the test result
shows for two seconds.
If a bad switch setting is made, the LEDs do not flash but display the fol-
lowing error code:
z ODH - bad Switch Setting.
7.14-27
Test Descriptions EMV-SCIF

The tests available are identified by a unique number. The following table
shows the test ID, the test description and whether they are available in the
Start-up or Selected mode. the majority of tests available only in Selected
mode.
Test ID Test Description Start-Up Selected

01 CPU and EPROM Test X X
02 RAM data Test X X
03 RAM Address Test X X
04 NVRAM Initialize (Dual Voltage Disabled) X
05 NVRAM Initialize (Dual Voltage Enabled) X
06 Smart Card Test X X
07 Card Clock - Stop Low X
08 Card Clock = XTAL/2 MHz X
09 Card Clock = XTAL/4 MHz X
0A Card Clock = XTAL/8 MHz X
0B Card Clock = FINT/2 X
0C Card Clock - Stop High X
0D Card Signals Toggle X
0E Exercise Stopper Pin X
0F Exercise Contact Unit X
Test 01 - CPU and EPROM
Description
The following tests are performed:
z CPU registers. All register banks are tested
z CPU instructions. Arithmetic and manipulation instructions are tested
z Stack, Push and Pop sequence
z EPROM - Cyclic Redundancy Check (CRC) calculation
z Internal RAM. This is tested by writing alternate 55, AA and FF bytes in
RAM. These values are checked. If O.K., inverted checked again
z CPU special purpose timers and interrupt registers are tested.
Test Results
LEDs Status
00H Test passed
08H CPU fault
09H CPU internal RAM/stack fault
0AH CPU timer fault
0BH CPU interrupt register fault
0CH Serial control register fault
0DH EPROM CRC check fault
7.14-28
Test 02 - External Memory
Description
The following tests are performed:
z Volatile RAM. This is tested by writing alternate 55, AA and FF bytes in
RAM. These values are checked. If O.K., inverted and checked again
z Non-volatile memory data. Header checked. CRC check of contents. Only
performed when smart card encrypyion (SCE) is not used.
Test Results
LEDs Status
00H Test passed
08H Volatile RAM error
09H Non volatile memory error - possible battery failure
0DH Non volatile memory CRC fail - possible corruption of NVRAM
NOTE: If test results 09 or 0D are returned, corrective action must be taken

to replace the battery or SRAM. On replacement Test 04 or 05 must be
performed to ensure that the EMV-SCIF is installed. This test will write a
header block to NVRAM, calculate and store a CRC for the contents of
NVRAM.
Test 03 - External Data Memory Address and data Lines
Description
The volatile RAM is filled with zeroes, except for byte 00, which is filled with
FF hex. The contents of RAM is then verified. The RAM contents is then read
using an address of 1 left rotating zero that is 1, 2, 4, 8, 16.... .
If the data read from these addresses equals FF hex, the external connec-
tion of that address line is faulty. If the data read of one of the addresses is
neither 00 or FF hex, one or more data lines are faulty.
The non-volatile memory contains FF hex on byte 00 zero bytes on
addresses having only one bit set that is 1, 2, 4... . If the data read from these
addresses equals FF hex, external connection of that address line is faulty. If
the data read from one of the addresses is neither 00 nor FF hex, one or more
data lines are faulty.
The information stored in the non-volatile memory is placed so that it does
not interfere with the check bytes.
This test is not applicable when a smart card encryptor is used.
Test Results
LEDs Status
00H Test passed
08H Data error while verifying 00 hex write
09H Data error while verifying FF hex write
xAH Volatile RAM address bus error, address line x (0-F)
xBH Volatile RAM data bus error, data line x (0-7)
xCH Non-volatile memory address bus error, address line x (0-F)
xDH Non-volatile memory data bus error, data line x (0-7)
7.14-29
Test 04 - NVRAM Initialize Disabled
Description
The area of NVRAM from external data memory addresses 7000H to 8000H is
initialized. During this process the memory is over written with zeros, a
header block is written into NVRAM and a CRC is done over the contents of
NVRAM and the result written. This test is done to indicate a “start of life”
condition for the EMV-SCIF board.
Test Results
LEDs Status
00H Test passed
Test 05 - NVRAM Initialize Enabled
Description
The area of NVRAM from external data memory addresses 7000H to 8000H is
initialized. During this process the memory is over written with zeros, a
header block is written into NVRAM containing an additional byte indicating
the support of Dual Voltage Cards, and a CRC is done over the contents of
NVRAM and the result written. This test is done to indicate a “start of life”
condition for the EMV-SCIF board.
Test Results
LEDs Status
00H Test passed
NOTE: Either test 04 or 05 must be performed the first time the EMV-SCIF
is powered on. If either test has not been run, the header block and CRC
will not have been written into NVRAM. Test 02 will always fail. Similarly
if the battery or SRAM has been replaced, this test must be run the first
time the EMV-SCIF is powered on.
Test 06 - Smart Card Communication Test
Description
The interface to the IC card on the EMV-SCIF is controlled exclusively by the
Philips TDA8006 Device thus constricting direct access to the SC signals. The
level of testing performed by this test depends on whether it is called as part
of the Start-up test, or as a Selected Test. Start-up testing performs a limited
compared to the Selected Test.
Test Results
LEDs Status
00H Test passed
08H Initialisation of system failure (“Error at library procedure Init_System”)
09H I/O line not at zero
0AH Card Present (For Start-Up: Error at library procedure “Power-Up”)
7.14-30
Test 07 - Card Clock - Stop Low
Description
The EMV-SCIF sets the card clock low. The clock signal can be measured using
an oscilloscope.
At the start of this test the contacts are lowered but no lower position
checking is made.
NOTE: During the execution of this test, the diagnostic LEDs display the
test ID. No error response is returned.
Test 08 - Card Clock = XTAL/ 2 MHz
Description
The EMV-SCIF sends a clock signal of XTAL/ 2 MHz to the smart card clock
contact. The clock signal can be measured using an oscilloscope.
checking is made.
Test 09 - Card Clock = XTAL/ 4 MHz
Description
checking is made.
Test 0A - Card Clock = XTAL/ 8 MHz
Description
checking is made.
7.14-31
Test 0B - Card Clock = FINT/ 2 MHz
Description
The EMV-SCIF sends a clock signal of FINT/ 2 MHz to the smart card clock
checking is made.
Test 0C - Card Stop High
Description
The EMV-SCIF sets the card clock high. The clock signal can be measured
with an oscilloscope.
checking is made.
Test 0D - Card Signal Toggle
Description
The EMV-SCIF toggles the smart card Vcc, Resety and I/O line.
checking is made.
NOTE: During the execution of this test, the diagnostic LEDs flash the test
ID. No error response is returned.
Test 0E - Exercise Stopper Pin
Description
The EMV-SCIF performs the following sequence:
1. Activates the stopper pin solenoid.
2. Checks for lower pin position.
3. Waits one second.
4. Deactivates the stopper pin solenoid.
5. Checks for upper pin position.
7. Repeats steps 1 to 6.
7.14-32
Test Results
Test No. and test results shown on the LEDs are:
LEDs Status
09H Stopper pin failed to reach either the low or high position
Test 0F - Exercise Contact Unit
Description
The EMV-SCIF performs the following sequence:
1. Activates the contact unit solenoid.
2. Checks for lower contact unit position.
4. Deactivates the contact unit solenoid.
5. Checks for upper contact unit position.
7. Repeats steps 1 to 6.
Test Results
LEDs Status
09H Contact Unit failed to reach either the low or high position
LEVEL 1 DIAGNOSTICS
The level 1 diagnostic tests available for smart card are:
z SMART CARD STAGE
z SMART CARD RESET
z SMART CARD RELEASE
z SCIF INITIALISE
z SCIF SOLENOID
z SCIF IDENTIFY
z RUN-TO-RUN 1
z RUN-TO-RUN 2
z RUN-TO-RUN 3.
SMART CARD STAGE

The SMART CARD STAGE test moves the card from the MCRW transport
into the SCRW and brings the contacts down on to the card.
SMART CARD RESET

The SMART CARD RESET applies power to the card under the contacts. The
resultant data stream from the smart card is displayed.
SMART CARD RELEASE

The SMART CARD RELEASE test raises the card contacts and moves the
card out of the SCRW back into the MCRW transport.
7.14-33
SCIF INITIALISE
The SCIF INITIALISE test causes the SCIF board to switch into SCRW mode
and toggle the SCIF reset line. Power is removed from any card present and
the smart card contacts and stopper pin solenoids are de-energized. The SCIF
board switches to MCRW mode.
SCIF SOLENOID
The SCIF SOLENOID test activates the SCRW stopper pin and contact
solenoids.
NOTE: The card should not be in the SCRW when this test is selected.
SCIF IDENTIFY
The SCIF IDENTIFY test allows the operator to display or print the ROM
firmware number as T_DATA.
The firmware ID is returned as an 21 digit ASCII coded number similar to
the following:
<---------ROM Firmware ID---------> 14

00 00 00 30 30 39 30 31 36 32 31 34 30 3X 30 30 30 30 30 30 30
Where,
z The first 3 digits are 0
z The next nine digits contain the EPROM ID number. The example above
shows the EMV EPROM number 009016214. Notice that the number after
the 9 is one digit short of the actual part number that appears on the
EPROM label. The full number is 009-0016214.
z Digit 13 and digits 15 to 21 all have the value 0.
z Digit 14 (X) can take the following values:
z 0 = non-EMV SCIF
z 5 = 5 V only, is applied to the smart card during the Power Up
sequence
zz 3 = 3 V is applied to the smart card during the Power Up sequence
and, if no valid ATR is returned, then 5V is applied. The value 3 there-
fore means that Dual Voltage Support is enabled. Refer to Level 0
Diagnostics Test 05H, in Chapter 4.2.9).
RUN-TO-RUN 1
The RUN-TO-RUN 1 test automatically performs the following tests in
sequence:
z SHUTTER/SENSOR
z ENTER
z READ ISO TRACK 1 (If configured)
z READ ISO TRACK 2
z SMART CARD STAGE
z SMART CARD RESET
z EJECT
z CAPTURE.
7.14-34
NOTE: See the appropriate MCR/MCRW chapters in this manual for disrup-
tions of tests not specific to smart card.
RUN-TO-RUN 2
sequence:
z ENTER
z CAPTURE.
RUN-TO-RUN 3
sequence:
z ENTER
z READ ISO TRACK 2
z SMART CARD STAGE
z SMART CARD RESET
z EJECT.
M_STATUS
M_STATUS values, and their meaning for the SCRW, are shown below.
Original severity is also shown.
The M_STATUS codes for the associated MCRW are given in the appropri-
ate Chapter in this manual, refer to Chapter 7.2, 7.3 or 7.7 as required.
Original
M_STATUS Meaning
Severity
50 Card not in SCRW stage position. 2
51 Smart card stopper pin lowered, unable to capture. This is only in 4
response to card capture.
52 Invalid smart card command code error. 2
53 Invalid smart card command data error. 2
54 SCIF not configured/not responding. 2
55 SCIF response timeout exceeded. 2
57 Invalid smart card response length. 2
7.14-35
Additional M_STATUS codes may be returned by the SCIF as shown

below.
M_STATUS Meaning
00 Good
64 Invalid command code
65 Invalid command format
67 Invalid key ID
68 Invalid key type
69 Invalid host key type
70 Invalid key - does not exist
71 Invalid password - not decimal
72 Invalid password - no match
73 Key integrity error
74 Key parity error
75 Invalid data format
76 Stopper pin failure
77 Contact unit failure
78 Card movement failure
79 SC switch off failure
80 Smart card removed error
81 No smart card response
82 Smart card transmission error
83 Smart card switched off
84 Illegal card type/parameter
85 Power up time exceeded
86 ANSI X9.8 pin block error
M_DATA
Entries are returned in Byte 0 and 4 as follows:
Byte 0
70H = SCIF Command
Byte 4
Bit 1 - PD5/6 (1 = stopper pin/contacts down)
Bit 0 - PD7 (1 = blocked).
7.14-36
LEVEL 2 DIAGNOSTICS
None.
LEVEL 3 DIAGNOSTICS (TALLIES)

The EMC SCRW firmware updates a number of tallies. These tallies are
updated in diagnostic and normal modes.
The tallies are as follows:
z SMART CARD STOPPER PIN SOLENOID ACTUATION ATTEMPTS
(SPSOLOPS) - Incremented when the smart card stopper pin solenoid is
actuated during execution of the command to stage the smart card
z SMART CARD STOPPER PIN SOLENOID ACTUATION FAIL (SPSOL-
ERR) - Incremented when the smart card stopper pin solenoid is actuated
but the stopper pin is detected not to have moved, during execution of the
command to stage the smart card
z SMART CARD CONTACTS SOLENOID ACTUATION ATTEMPTS
(STSOLOPS) - Incremented when the smart card contacts solenoid is
actuated during execution of the command to stage the smart card
z SMART CARD CONTACTS SOLENOID ACTUATION FAIL (STSOL-
ERR) - Incremented when the smart card contacts solenoid is actuated but
the contacts is detected not to have moved, during execution of the com-
mand to stage the smart card
z NON SMART CARD DETECTED (NONSCDET) - Incremented when the
card present is detected not to be a smart card, during the execution of the
command to power on the smart card
z SMART CARD DETECTED (SCDETECT) - Incremented when the card
present is detected to be a smart card, during the execution of the com-
mand to power on the smart card
z ISO SMART CARD DETECTED (ISOSCDET) - Incremented when the
card present is detected to be an ISOtype smart card, during the execution
of the command to power on the smart card
z AFNOR/CP8 SMART CARD DETECTED (CP8SCDET) - Incremented
when the card present is detected to be a AFNOR/CP8 type smart card,
during the execution of the command to power on the smart card
z SMART CARD RESET ATTEMPT (SCRESETS) - Incremented when a
smart card reset is carried out during the execution of the command to
power on the smart card
z SMART CARD ANSWER TO RESET FAIL (SCRSTERR) - Incremented
when an error is found in the answer to reset during the execution of the
command to power on the smart card
z SMART CARD POWER ON TIMEOUT (SCPWRTIM) - Incremented when
the limit on the specified smart card power on time has been reached
z SCIF COMMS ATTEMPTS (SCIFCMAT) - Incremented when an attempt
is made by the device controller to send or receive a message to or from the
SCIF
z SCIF COMMS FAIL (SCIFCMFL) - Incremented when the device control-
ler fails in its attempt to send or receive a message to or from the SCIF
z SCIF RESPONSE TIMEOUT (SCIFRSPT) - Incremented when the SCIF
fails to respond within the timeout specified by the SCIF command mes-
sage
z SMART CARD COMMS ATTEMPTS (SCCOMAT) - Incremented when a
communication is attempted between the SCIF and the smart card
7.14-37
z SMART CARD COMMS RETRIES (SCCOMRTY) - Incremented when a

communication retry was successfully carried out during the execution of
a smart card related command
z SMART CARD RESPONSE TIMEOUT (SCRSPTIM) - Incremented when
the SCIF reports that the smart card has failed to respond within the
specified timeout
z SMART CARD INTERFACE REINITIALIZATION ATTEMPTS
(SCIF_RES) - Incremented when Reinitialization command issued.
Tally numbering and threshold values are shown in the following table.
Tally Mnemonic Number Frame of Reference Threshold

SPSOLOPS 28 REF10000
SPSOLERR 29 SPSOLOPS 10
CTSOLOPS 30 REF10000
CTSOLERR 31 CTSOLOPS 10
NONSCDET 32 SCRESETS N/A
SCDETECT 33 SCRESETS N/A
ISOSCDET 34 SCRESETS N/A
CP8SCDET 35 SCRESETS N/A
SCRESETS 36 REF1000
SCRSTERR 37 SCRESETS 1000
SCPWRTIM 38 SCRESETS N/A
SCIFCMAT 39 SCRESETS N/A
SCIFCMFL 40 SCRESETS N/A
SCIFRSPT 41 SCRESETS N/A
SCCOMATT 42 SCRESETS N/A
SCCOMRTY 43 SCRESETS N/A
SCRSPTIM 44 SCRESETS N/A
SCIF_RES 45 N/A
7.14-38
STRAPPING
None.
ADJUSTMENTS
None.
TEST EQUIPMENT
DIAGNOSTIC TEST CARDS
You need the following test cards to perform level 1 diagnostic testing on the
SCRW:
z AFNOR/CP8 test card - NCR part number 009-0009493
z ISO test card - NCR part number 009-0009494
z Cleaning card - NCR part number 998-0052929.
PREVENTIVE MAINTENANCE
The only preventive maintenance necessary for the SCRW is to clean the feed
roller. This should be done using the diagnostic “clean” facility and cleaning
card for the associated MCRW in this manual, that is Chapter 7.2, 7.3 and 7.7.
INTERCONNECTIONS
The interconnections between the SCRW, the MCRW and the SCIF are shown
in the following figures.
7.14-39
SOLENOIDS AND PHOTODETECTOR CONNECTIONS
7.14-40
MOTOR AND SHUTTER CONNECTOR
7.14-41
SDC MCRW TO SCIF PIA INTERFACE BOARD
7.14-42
SCIF TO MCRW CONTROLLER PIA CONNECTOR
7.14-43
POWER CONNECTIONS
SMART CARD SIGNALS AND POWER
7.14-44
SCHEMATIC AND ASSEMBLY DIAGRAMS

The following pages contain the assembly drawings and schematic diagrams
of the EMV SCIF board as follows:
z Page-46 Assembly 455-0650241
z Page-47 to -55 - Schematic Diagram for 455-0650243.
7.14-45
445-0650241
EMV SCIF board Assembly Drawing
7.14-46
EMV SCIF board Schematic Diagram (Sheet 1 of 9)
7.14-47
7.14-48
7.14-49
7.14-50
7.14-51
7.14-52
7.14-53
7.14-54
7.14-55
7.14-56

EMV Smart Card Reader

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EMV SMART CARD READER/WRITER

EMV Smart Card Reader/Writer

INTRODUCTION ...................................................................................................... 7.14-1

GENERAL DESCRIPTION ....................................................................................... 7.14-1

FUNCTIONAL DESCRIPTION ................................................................................ 7.14-3

EMV SCRW MODULE ............................................................................................. 7.14-3

EMV SCIF BOARD ................................................................................................... 7.14-7

ERROR CODES AND DIAGNOSTICS.................................................................. 7.14-27

Test Descriptions EMV-SCIF ......................................................................... 7.14-28

ADJUSTMENTS ...................................................................................................... 7.14-39

TEST EQUIPMENT................................................................................................. 7.14-39

PREVENTIVE MAINTENANCE ........................................................................... 7.14-39

INTERCONNECTIONS .......................................................................................... 7.14-39

SCHEMATIC AND ASSEMBLY DIAGRAMS ..................................................... 7.14-45

EMV Smart Card Reader/Writer

MCR/MCRW PIA SCRW MCRW

EMV SCRW MODULE

Stopper Card Entry

Smart Card Contacts for ISO

Rear of SCRW Magnetic Stripe

Smart Card Contacts for AFNOR/CP8

Voltage Current Regulation

EMV SCIF BOARD

MCR/MCRW PIA SCRW MCRW

NOTE: Sheets 4 and 5 of the schematics show a possible future expansion to

EMV SCIF CORE ELECTRONICS

Processor and Support Circuitry

Memory and Address Decode

Code Area Data Area

The positions of the various ports in the memory-mapped I/O portion of

RD/WR port Address

z Power fail interface

74ALS652 EMV SCIF

MCRW EMV SCRW

Bit A Select B Select C Select

The schematics (sheet 1 and 9) for the interconnections of Port A, show

Data Valid Data

EMV SCIF to Host Handshaking Sequence

Data is written to the host using a handshaking mechanism that exists

Data Valid Data

Host to EMV SCIF Handshaking Sequence

NOTE: A hardware reset is generated by toggling PB3, Register A.

Port B is located in memory mapped I/O at address 8001H. The Port B

A description of each bit follows:

A description of each signal follows:

Smart Card Interface

TDA8006 Internal Architecture)

P4.0 to P1.6 & P1.2 to

En- ADO Data En- ADO Data En- ADO Data

Smart Card Interface Circuitry

The read and write procedures are summerized as follows:

READ DATA CYCLE WRITE DATA CYCLE

Functional Block Register W/R- AD0 AD1 AD2 AD3

Clock Generator Configuration

Clock Configuration Register (CCR)

D7 D6 D5 D4 D3 D2 D1 D0 UART CLK CLKOUT OSC

Programmable Divider Register (PDR)

After power-on or reset, the microcontroller is clocked with fINT/8. On

On/Off Sequencer Configuration

Bit Name Description

ISO 7816 UART

Symbol Expanded name Function

UART Configuration Register (UCR)