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CC1000
Single Chip Very Low Power RF Transceiver
Applications
• Very low power UHF wireless data • Home automation
transmitters and receivers • Wireless alarm and security systems
• 315 / 433 / 868 and 915 MHz ISM/SRD • AMR – Automatic Meter Reading
band systems • Low power telemetry
• RKE – Two-way Remote Keyless Entry • Game Controllers and advanced toys
Product Description
Features
• True single chip UHF RF transceiver • RSSI output
• Very low current consumption • Single port antenna connection
• Frequency range 300 – 1000 MHz • FSK data rate up to 76.8 kBaud
• Integrated bit synchroniser • Complies with EN 300 220 and FCC
• High sensitivity (typical -110 dBm at 2.4 CFR47 part 15
kBaud) • Programmable frequency in 250 Hz
• Programmable output power –20 to steps makes crystal temperature drift
10 dBm compensation possible without TCXO
• Small size (TSSOP-28 or UltraCSP™ • Suitable for frequency hopping
package) protocols
• Low supply voltage (2.1 V to 3.6 V) • Development kit available
• Very few external components required • Easy-to-use software for generating the
• No external RF switch / IF filter CC1000 configuration data
required
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CC1000
Table of Contents
CC1000........................................................................................................................... 1
3. Electrical Specifications......................................................................................... 4
4. Pin Assignment....................................................................................................... 8
5. Circuit Description.................................................................................................. 9
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CC1000
L = 7125 / f ................................................................................................................. 38
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CC1000
Under no circumstances the absolute the limiting values may cause permanent
maximum ratings given above should be damage to the device.
violated. Stress exceeding one or more of
2. Operating Conditions
Supply voltage 2.1 3.0 3.6 V Note: The same supply voltage
should be used for digital (DVDD)
and analogue (AVDD) power.
3. Electrical Specifications
Tc = 25°C, VDD = 3.0 V if nothing else stated
Parameter Min. Typ. Max. Unit Condition / Note
Transmit Section
Transmit data rate 0.6 76.8 kBaud NRZ or Manchester encoding.
76.8 kBaud equals 76.8 kbit/s
using NRZ coding. See page 16.
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CC1000
Parameter Min. Typ. Max. Unit Condition / Note
IF Section
Intermediate frequency (IF) 150 kHz Internal IF filter
10.7 MHz External IF filter
RSSI linearity ±2 dB
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CC1000
Parameter Min. Typ. Max. Unit Condition / Note
Frequency Synthesiser
Section
Crystal Oscillator Frequency 3 16 MHz Crystal frequency can be 3-4, 6-8
or 9-16 MHz. Recommended
frequencies are 3.6864, 7.3728,
11.0592 and 14.7456. See page
35 for details.
Output signal phase noise -85 dBc/Hz At 100 kHz offset from carrier
PLL lock time (RX / TX turn time) 200 µs Up to 1 MHz frequency step
Digital Inputs/Outputs
Logic “0” input voltage 0 0.3*VDD V
Logic “1” output voltage 2.5 VDD V Output current 2.5 mA,
3.0 V supply voltage
Current Consumption
Power Down mode 0.2 1 µA Oscillator core off
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CC1000
Parameter Min. Typ. Max. Unit Condition / Note
Current Consumption,
transmit mode 433/868 MHz:
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CC1000
4. Pin Assignment
Pin no. UltraCSP Pin name Pin type Description
pin no.
1 G3 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF)
2 F2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF)
3 G2 RF_IN RF Input RF signal input from antenna
4 G1 RF_OUT RF output RF signal output to antenna
5 F1 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA)
6 E2 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA)
7 E1 AGND Ground (A) Ground connection (0 V) for analog modules (PA)
8 D1 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler)
9 C1 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler)
10 B1 L1 Analog input Connection no 1 for external VCO tank inductor
11 A1 L2 Analog input Connection no 2 for external VCO tank inductor
12 B2 CHP_OUT Analog output Charge pump current output
(LOCK) The pin can also be used as PLL Lock indicator. Output is high
when PLL is in lock.
13 C2 R_BIAS Analog output Connection for external precision bias resistor (82 kΩ, ± 1%)
14 F3 AGND Ground (A) Ground connection (0 V) for analog modules (backplane)
15 A2 AVDD Power (A) Power supply (3 V) for analog modules (general)
16 B3 AGND Ground (A) Ground connection (0 V) for analog modules (general)
17 A3 XOSC_Q2 Analog output Crystal, pin 2
18 A4 XOSC_Q1 Analog input Crystal, pin 1, or external clock input
19 B4 AGND Ground (A) Ground connection (0 V) for analog modules (guard)
20 C3 DGND Ground (D) Ground connection (0 V) for digital modules (substrate)
21 C4 DVDD Power (D) Power supply (3 V) for digital modules
22 D4 DGND Ground (D) Ground connection (0 V) for digital modules
23 E4 DIO Digital Data input/output. Data input in transmit mode. Data output in
input/output receive mode
24 F4 DCLK Digital output Data clock for data in both receive and transmit mode
25 G4 PCLK Digital input Programming clock for 3-wire bus
26 D3 PDATA Digital Programming data for 3-wire bus. Programming data input for
input/output write operation, programming data output for read operation
27 D2 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up.
28 E3 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional
external IF and demodulator. If not used, the pin should be left
open (not connected).
A=Analog, D=Digital
(Top View)
1 28
AVDD RSSI/IF
2 27
AGND PALE
3 26
RF_IN PDATA
4 25
RF_OUT PCLK
5 24
AVDD DCLK
6 23
AGND DIO
CC1000
7 22
AGND DGND
8 21
AGND DVDD
9 20
AVDD DGND
10 19
L1 AGND
11 18
L2 XOSC_Q1
12 17
CHP_OUT XOSC_Q2
13 16
R_BIAS AGND
14 15
AGND AVDD
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CC1000
5. Circuit Description
RSSI/IF
MIXER
RF_IN LNA IF STAGE DEMOD CONTROL DIO
DCLK
PDATA, PCLK, PALE
3
/N
RF_OUT PA
BIAS R_BIAS
~
XOSC_Q2
CHARGE
VCO LPF PD /R OSC
PUMP XOSC_Q1
L1 L2 CHP_OUT
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CC1000
6. Application Circuit
Very few external components are Component values for the matching
required for the operation of CC1000. A network and VCO inductor are easily
typical application circuit is shown in calculated using the SmartRF® Studio
Figure 2. Component values are shown in software.
Table 1.
6.3 Additional filtering
6.1 Input / output matching Additional external components (e.g. RF
C31/L32 is the input match for the LC or SAW-filter) may be used in order to
receiver. L32 is also a DC choke for improve the performance in specific
biasing. C41, L41 and C42 are used to applications. See also “Optional LC filter”
match the transmitter to 50 Ω. An internal p.36 for further information.
T/R switch circuit makes it possible to
connect the input and output together and 6.4 Power supply decoupling
match the CC1000 to 50 Ω in both RX and Power supply decoupling and filtering
TX mode. See “Input/output matching” must be used (not shown in the
p.31 for details. application circuit). The placement and
size of the decoupling capacitors and the
6.2 VCO inductor power supply filtering are very important to
The VCO is completely integrated except achieve the optimum performance.
for the inductor L101. Chipcon provides reference designs
(CC1000PP and CC1000uCSP_EM) that
should be followed very closely.
Figure 2. Typical CC1000 application circuit (power supply decoupling not shown)
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CC1000
Note that the component values for Chipcon provide reference layouts that
868/915 MHz can be the same. However, should be followed very closely in order to
it is important the layout is optimised for achieve the best performance. The
the selected VCO inductor in order to reference design can be downloaded from
centre the tuning range around the the Chipcon website.
operating frequency to account for
inductor tolerance. The VCO inductor
must be placed very close and
symmetrical with respect to the pins (L1
and L2).
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CC1000
7. Configuration Overview
8. Configuration Software
Chipcon provides users of CC1000 with a CC1000. In addition the program will
software program, SmartRF® Studio provide the user with the component
(Windows interface) that generates all values needed for the input/output
necessary CC1000 configuration data matching circuit and the VCO inductor.
based on the user’s selections of various
parameters. These hexadecimal numbers Figure 3 shows the user interface of the
will then be the necessary input to the CC1000 configuration software.
microcontroller for the configuration of
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CC1000
CC1000 is configured via a simple 3-wire The timing for the programming is also
interface (PDATA, PCLK and PALE). shown in Figure 4 with reference to Table
There are 28 8-bit configuration registers, 2. The clocking of the data on PDATA is
each addressed by a 7-bit address. A done on the negative edge of PCLK.
Read/Write bit initiates a read or write When the last bit, D0, of the 8 data-bits
operation. A full configuration of CC1000 has been loaded, the data word is loaded
requires sending 22 data frames of 16 bits in the internal configuration register.
each (7 address bits, R/W bit and 8 data
bits). The time needed for a full The configuration data is stored in internal
configuration depend on the PCLK RAM. The data is retained during power-
frequency. With a PCLK frequency of 10 down mode, but not when the power-
MHz the full configuration is done in less supply is turned off. The registers can be
than 46 µs. Setting the device in power programmed in any order.
down mode requires sending one frame
only and will in this case take less than 2 The configuration registers can also be
µs. All registers are also readable. read by the microcontroller via the same
configuration interface. The seven address
In each write-cycle 16 bits are sent on the bits are sent first, then the R/W bit set low
PDATA-line. The seven most significant to initiate the data read-back. CC1000 then
bits of each data frame (A6:0) are the returns the data from the addressed
address-bits. A6 is the MSB (Most register. PDATA is in this case used as an
Significant Bit) of the address and is sent output and must be tri-stated (or set high n
as the first bit. The next bit is the R/W bit the case of an open collector pin) by the
(high for write, low for read). During microcontroller during the data read-back
address and R/W bit transfer the PALE (D7:0). The read operation is illustrated in
(Program Address Latch Enable) must be Figure 5.
kept low. The 8 data-bits are then
transferred (D7:0). See Figure 4.
TSA THA
PCLK
PALE
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CC1000
PCLK
PALE
PALE setup TSA 10 - ns The minimum time PALE must be low before
time negative edge of PCLK.
PALE hold THA 10 - ns The minimum time PALE must be held low after
time the positive edge of PCLK.
PDATA setup TSD 10 - ns The minimum time data on PDATA must be ready
time before the negative edge of PCLK.
PDATA hold THD 10 - ns The minimum time data must be held at PDATA,
time after the negative edge of PCLK.
Rise time Trise 100 ns The maximum rise time for PCLK and PALE
Fall time Tfall 100 ns The maximum fall time for PCLK and PALE
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CC1000
PDATA
PCLK Micro-
CC1000 PALE controller
DIO
DCLK
(Optional)
CHP_OUT
(LOCK)
(Optional)
RSSI/IF ADC
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CC1000
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CC1000
Transmitter side:
Receiver side:
Transmitter side:
Receiver side:
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CC1000
Transmitter side:
Receiver side:
10110001101
TX
data
Time
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CC1000
Average
filter
A block diagram of the digital demodulator acquired value will be kept also after
is shown in Figure 11. The IF signal is Power Down or Transmit mode. After a
sampled and its instantaneous frequency modem reset
is detected. The result is decimated and (MODEM1.MODEM_RESET_N), or a
filtered. In the data slicer the data filter main reset (using any of the standard
output is compared to the average filter reset sources), the averaging filter is reset.
output to generate the data output.
In a polled receiver system the automatic
The averaging filter is used to find the locking can be used. This is illustrated in
average value of the incoming data. While Figure 12. If the receiver is operated
the averaging filter is running and continuously and searching for a
acquiring samples, it is important that the preamble, the averaging filter should be
number of high and low bits received is locked manually as soon as the preamble
equal (e.g. Manchester code or a is detected. This is shown in Figure 13. If
balanced preamble). the data is Manchester coded there is no
need to lock the averaging filter
Therefore all modes, also synchronous (MODEM1.LOCK_AVG_IN=’0’), as shown
NRZ mode, need a DC balanced in Figure 14.
preamble for the internal data slicer to
acquire correct comparison level from the The minimum length of the preamble
averaging filter. The suggested preamble depends on the acquisition mode selected
is a ‘010101…’ bit pattern. The same bit and the settling time. Table 4 gives the
pattern should also be used in Manchester minimum recommended number of chips
mode, giving a ‘011001100110…chip for the preamble in NRZ and UART
pattern. This is necessary for the bit modes. In this context ‘chips’ refer to the
synchronizer to synchronize correctly. data coding. Using Manchester coding
every bit consists of two ‘chips’. For
The averaging filter must be locked before Manchester mode the minimum
any NRZ data can be received. If the recommended number of chips is shown
averaging filter is locked in Table 5.
(MODEM1.LOCK_AVG_MODE=’1’), the
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CC1000
Settling Manual Lock Automatic Lock
NRZ mode UART mode NRZ mode UART mode
Table 4. Minimum preamble bits for locking the averaging filter, NRZ and UART mode
Settling Free-running
Manchester mode
MODEM1. MODEM1.LOCK_
SETTLING AVG_MODE=’1’
(1:0) MODEM1.LOCK_
AVG_IN=’0’
00 23
01 34
10 55
11 98
Table 5. Minimum number preamble chips for averaging filter, Manchester mode
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CC1000
RX PD RX
Averaging filter
free-running / not used
PD RX
PD RX
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CC1000
Table 6. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3,
frequency separation 64 kHz, normal current settings
Table 7. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3,
frequency separation 20 kHz, normal current settings
Table 8. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3,
frequency separation 64 kHz , low current settings
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CC1000
RX mode:
fRF fvco
fLO (low-side) fLO (high-side)
(Receive frequency)
fIF fIF
TX mode:
f0 fRF f1 fvco
(Lower FSK (Center frequency) (Upper FSK
frequency) frequency)
fsep
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CC1000
synthesis PLL is near the limit of generate register is checked when changing
the frequency requested, and the PLL frequencies and when changing between
should be recalibrated. RX and TX mode. If lock is not achieved, a
It is recommended that the calibration should be performed.
LOCK_CONTINOUS bit in the LOCK
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CC1000
16. VCO
Only one external inductor (L101) is Typical tuning range for the integrated
required for the VCO. The inductor will varactor is 20-25%.
determine the operating frequency range
of the circuit. It is important to place the Component values for various frequencies
inductor as close to the pins as possible in are given in Table 1. Component values
order to reduce stray inductance. It is for other frequencies can be found using
recommended to use a high Q, low the SmartRF® Studio software.
tolerance inductor for best performance.
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CC1000
Write CAL:
CAL_START=0
Write MAIN:
RXTX = 1; F_REG = 1 TX frequency register B is calibrated second
RX_PD = 1; TX_PD = 0; FS_PD = 0
CORE_PD = 0; BIAS_PD = 0; RESET_N=1
Write CAL:
CAL_START=0
End of calibration
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CC1000
Write CAL:
CAL_START=0
End of calibration
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CC1000
CC1000 offers great flexibility for power A typical power-on and initialising
management in order to meet strict power sequence for minimum power
consumption requirements in battery consumption is shown in Figure 18 and
operated applications. Power Down mode Figure 19.
is controlled through the MAIN register.
There are separate bits to control the RX PALE should be tri-stated or set to a high
part, the TX part, the frequency level during power down mode in order to
synthesiser and the crystal oscillator (see prevent a trickle current from flowing in the
page 39). This individual control can be internal pull-up resistor.
used to optimise for lowest possible
current consumption in a certain PA_POW should be set to 00h before
application. power down mode to ensure lowest
possible leakage current.
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CC1000
Power Off
Power turned on
Power Down
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CC1000
Power Down
RX TX
RX or TX?
RX mode
PA_POW = ‘Output power’
Wait 20 µs
Power Down
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CC1000
C31
RF_IN
TO ANTENNA RF_OUT
CC1000
C42
AVDD=3V
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CC1000
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CC1000
CC1000 has a built-in RSSI (Received The RSSI measures the power referred to
Signal Strength Indicator) giving an the RF_IN pin. The input power can be
analogue output signal at the RSSI/IF pin. calculated using the following equations:
The IF_RSSI bits in the FRONT_END
register enable the RSSI. When the RSSI P = -51.3 VRSSI– 49.2 [dBm] at 433 MHz
function is enabled, the output current of P = -50.0 VRSSI– 45.5 [dBm] at 868 MHz
this pin is inversely proportional to the
input signal level. The output should be The external network for RSSI operation is
terminated in a resistor to convert the shown in Figure 21. R281 = 27 kΩ, C281
current output into a voltage. A capacitor = 1nF.
is used in order to low-pass filter the
signal. A typical plot of RSSI voltage as function
of input power is shown in Figure 22.
The RSSI voltage range from 0 – 1.2 V
when using a 27 kΩ terminating resistor,
giving approximately 50 dB/V. This RSSI
voltage can be measured by an A/D
converter. Note that a higher voltage
means a lower input signal.
1.3
1.2
1.1 433Mhz
1
RSSI/IF 0.9
868Mhz
CC1000 TO ADC
Voltage
0.8
0.7
0.6
0.5
0.4
0.3
C281 R281 0.2
0.1
0
-105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50
dBm
Figure 21. RSSI circuit Figure 22. RSSI voltage vs. input power
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CC1000
23. IF output
CC1000 has a built-in 10.7 MHz IF output The external network provides 330 Ω
buffer. This buffer could be applied in source impedance for the 10.7 MHz
narrowband applications with ceramic filter.
requirements on mirror image filtering.
The system is then built with CC1000, a
10.7 MHz ceramic filter and an external
10.7 MHz demodulator. The external
network for IF output operation is shown in
Figure 23. R281 = 470 Ω, C281 = 3.3nF.
RSSI/IF
CC1000
To 10.7MHz filter
and demodulator
C281
R281
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CC1000
XTAL
C181 C171
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CC1000
L71
C71 C72
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CC1000
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CC1000
Non-resonant monopole antennas shorter where f is in MHz, giving the length in cm.
than λ/4 can also be used, but at the An antenna for 869 MHz should be 8.2
expense of range. In size and cost critical cm, and 16.4 cm for 434 MHz.
applications such an antenna may very
well be integrated into the PCB. The antenna should be connected as
close as possible to the IC. If the antenna
Helical antennas can be thought of as a is located away from the input pin the
combination of a monopole and a loop antenna should be matched to the feeding
antenna. They are a good compromise in transmission line (50 Ω).
size critical applications. But helical
antennas tend to be more difficult to For a more thorough primer on antennas,
optimise than the simple monopole. please refer to Application Note AN003
SRD Antennas available from Chipcon’s
Loop antennas are easy to integrate into web site.
the PCB, but are less effective due to
SWRS048A Page 38 of 55
CC1000
REGISTER OVERVIEW
ADDRESS Byte Name Description
00h MAIN MAIN Register
01h FREQ_2A Frequency Register 2A
02h FREQ_1A Frequency Register 1A
03h FREQ_0A Frequency Register 0A
04h FREQ_2B Frequency Register 2B
05h FREQ_1B Frequency Register 1B
06h FREQ_0B Frequency Register 0B
07h FSEP1 Frequency Separation Register 1
08h FSEP0 Frequency Separation Register 0
09h CURRENT Current Consumption Control Register
0Ah FRONT_END Front End Control Register
0Bh PA_POW PA Output Power Control Register
0Ch PLL PLL Control Register
0Dh LOCK LOCK Status Register and signal select to CHP_OUT (LOCK) pin
0Eh CAL VCO Calibration Control and Status Register
0Fh MODEM2 Modem Control Register 2
10h MODEM1 Modem Control Register 1
11h MODEM0 Modem Control Register 0
12h MATCH Match Capacitor Array Control Register for RX and TX impedance matching
13h FSCTRL Frequency Synthesiser Control Register
14h Reserved
15h Reserved
16h Reserved
17h Reserved
18h Reserved
19h Reserved
1Ah Reserved
1Bh Reserved
1Ch PRESCALER Prescaler and IF-strip test control register
40h TEST6 Test register for PLL LOOP
41h TEST5 Test register for PLL LOOP
42h TEST4 Test register for PLL LOOP (must be updated as specified)
43h TEST3 Test register for VCO
44h TEST2 Test register for Calibration
45h TEST1 Test register for Calibration
46h TEST0 Test register for Calibration
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CC1000
MAIN Register (00h)
REGISTER NAME Default Active Description
value
MAIN[7] RXTX - - RX/TX switch, 0 : RX , 1 : TX
MAIN[6] F_REG - - Selection of Frequency Register, 0 : Register A, 1 :
Register B
MAIN[5] RX_PD - H Power Down of LNA, Mixer, IF, Demodulator, RX part of
Signal Interface
MAIN[4] TX_PD - H Power Down of TX part of Signal Interface, PA
MAIN[3] FS_PD - H Power Down of Frequency Synthesiser
MAIN[2] CORE_PD - H Power Down of Crystal Oscillator Core
MAIN[1] BIAS_PD - H Power Down of BIAS (Global_Current_Generator)
and Crystal Oscillator Buffer
MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default
values to all other registers than MAIN. Bits in MAIN do
not have a default value, and will be written directly
through the configurations interface. Must be set high to
complete reset.
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CC1000
CURRENT Register (09h)
REGISTER NAME Default Active Description
value
CURRENT[7:4] VCO_CURRENT[3:0] 1100 - Control of current in VCO core for TX and RX
0000 : 150µA
0001 : 250µA
0010 : 350µA
0011 : 450µA
0100 : 950µA, use for RX, f= 400 – 500 MHz
0101 : 1050µA
0110 : 1150µA
0111 : 1250µA
1000 : 1450µA, use for RX, f<400 MHz and f>500
MHz; and TX, f= 400 – 500 MHz
1001 : 1550µA, use for TX, f<400 MHz
1010 : 1650µA
1011 : 1750µA
1100 : 2250µA
1101 : 2350µA
1110 : 2450µA
1111 : 2550µA, use for TX, f>500 MHz
CURRENT[3:2] LO_DRIVE[1:0] 10 Control of current in VCO buffer for LO drive
00 : 0.5mA, use for TX
01 : 1.0mA , use for RX, f<500 MHz*
10 : 1.5mA,
11 : 2.0mA, use for RX, f>500 MHz *
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CC1000
PA_POW Register (0Bh)
REGISTER NAME Default Active Description
value
PA_POW[7:4] PA_HIGHPOWER[3:0] 0000 - Control of output power in high power array.
Should be 0000 in PD mode . See Table 11
page 32 for details.
PA_POW[3:0] PA_LOWPOWER[3:0] 1111 - Control of output power in low power array
Should be 0000 in PD mode. See Table 11
page 32 for details.
1111 : Divide by 15
PLL[2] ALARM_DISABLE 0 h 0 : Alarm function enabled
1 : Alarm function disabled
PLL[1] ALARM_H - - Status bit for tuning voltage out of range
(too close to VDD)
PLL[0] ALARM_L - - Status bit for tuning voltage out of range
(too close to GND)
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CC1000
LOCK Register (0Dh)
REGISTE NAME Default Active Description
R value
LOCK[7:4] LOCK_SELECT[3:0] 0000 - Selection of signals to CHP_OUT (LOCK) pin
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CC1000
MODEM2 Register (0Fh)
REGISTER NAME Default Active Description
value
MODEM2[7] PEAKDETECT 1 H Peak Detector and Remover disabled or
enabled
0 : Peak detector and remover is
disabled
1 : Peak detector and remover is
enabled
MODEM2[6:0] PEAK_LEVEL_OFFSET[6:0] 0010110 - Threshold level for Peak Remover in
Demodulator. Correlated to frequency
deviation, see note.
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CC1000
MODEM0 Register (11h)
REGISTER NAME Default Active Description
value
MODEM0[7] - - - Not used
MODEM0[6:4] BAUDRATE[2:0] 010 - 000 : 0.6 kBaud
001 : 1.2 kBaud
010 : 2.4 kBaud
011 : 4.8 kBaud
100 : 9.6 kBaud
101 : 19.2, 38.4 and 76.8 kBaud
110 : Not used
111 : Not used
MODEM0[3:2] DATA_FORMAT[1:0] 01 - 00 : NRZ operation.
01 : Manchester operation
10 : Transparent Asyncronous UART operation
11 : Not used
MODEM0[1:0] XOSC_FREQ[1:0] 00 - Selection of XTAL frequency range
00 : 3MHz – 4MHz crystal, 3.6864MHz
recommended
Also used for 76.8 kBaud, 14.7456MHz
01 : 6MHz – 8MHz crystal, 7.3728MHz
recommended
Also used for 38.4 kBaud, 14.7456MHz
10 : 9MHz – 12MHz crystal, 11.0592 MHz
recommended
11 : 12MHz – 16MHz crystal, 14.7456MHz
recommended
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CC1000
PRESCALER Register (1Ch)
REGISTER NAME Default Active Description
value
PRESCALER[7:6] PRE_SWING[1:0] 00 - Prescaler swing. Fractions for
PRE_CURRENT[1:0] = 00
00 : 1 * Nominal Swing
01 : 2/3 * Nominal Swing
10 : 7/3 * Nominal Swing
11 : 5/3 * Nominal Swing
PRESCALER[5:4] PRE_CURRENT 00 - Prescaler current scaling
[1:0]
00 : 1 * Nominal Current
01 : 2/3 * Nominal Current
10 : 1/2 * Nominal Current
11 : 2/5 * Nominal Current
PRESCALER[3] IF_INPUT 0 - 0 : Nominal setting
1 : RSSI/IF pin is input to IF-strips
PRESCALER[2] IF_FRONT 0 - 0 : Nominal setting
1 : Output of IF_Front_amp is switched to
RSSI/IF pin
PRESCALER[1:0] - 00 - Not used
SWRS048A Page 46 of 55
CC1000
TEST3 Register (for test only, 43h)
REGISTER NAME Default Active Description
value
TEST3[7:5] - - - Not used
TEST3[4] BREAK_LOOP 0 - 1 : PLL loop open
0 : PLL loop closed
TEST3[3:0] CAL_DAC_OPEN 0100 - Calibration DAC override value, active when
BREAK_LOOP =1
SWRS048A Page 47 of 55
CC1000
SWRS048A Page 48 of 55
CC1000
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
E1 E2 E3 E4
F1 F2 F3 F4
500um
+/- 10um
G1 G2 G3 G4
535um
392um +/-20um
+/-20um
500um 417um
292um 250um +/- 10um +/-20um
+/-20um +/- 10um
SWRS048A Page 49 of 55
CC1000
Vertical cross section (UltraCSP™)
A Die
h1
A Die
h2
SWRS048A Page 50 of 55
CC1000
Tube Specification
Package Tube Width Tube Height Tube Units per Tube
Length
TSSOP 28 268 mil 80 mil 20” 50
SWRS048A Page 51 of 55
CC1000
Advance Information Planned or Under This data sheet contains the design specifications for
Development product development. Specifications may change in
any manner without notice.
Preliminary Engineering Samples This data sheet contains preliminary data, and
and First Production supplementary data will be published at a later date.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
No Identification Noted Full Production This data sheet contains the final specifications.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
SWRS048A Page 52 of 55
CC1000
SWRS048A Page 53 of 55
CC1000
Internet
TI Semiconductor Product Information Center Home Page: support.ti.com
TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase
Japan
Fax International +81-3-3344-5317
Domestic 0120-81-0036
Internet/Email International support.ti.com/sc/pic/japan.htm
Domestic www.tij.co.jp/pic
SWRS048A Page 54 of 55
CC1000
Asia
Phone International +886-2-23786800
Domestic Toll-Free Number
Australia 1-800-999-084
China 800-820-8682
Hong Kong 800-96-5941
India +91-80-51381665 (Toll)
Indonesia 001-803-8861-1006
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Malaysia 1-800-80-3973
New Zealand 0800-446-934
Philippines 1-800-765-7404
Singapore 800-886-1028
Taiwan 0800-006800
Thailand 001-800-886-0010
Fax +886-2-2378-6808
Email tiasia@ti.com or ti-china@ti.com
Internet support.ti.com/sc/pic/asia.htm
SWRS048A Page 55 of 55
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Feb-2009
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Feb-2009
Pack Materials-Page 2
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