INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
2394-9007
Vol. V, No. I, February 2018
Review on Dual Supply based Low Power 10T
SRAM Cell
Vineet Singh, Mukul Shrivastava
Abstract— The power consumption in commercial processors and
application specific integrated circuits increases with decreasing
technology nodes. Power saving techniques has become a first class design
point for current and future VLSI systems. These systems employ large
on-chip SRAM memories. Unfortunately, state of the art techniques like
power-gating can only be applied to logic as these would destroy the
contents of the memory if applied to a SRAM system. Fortunately,
previous works have noted large temporal and spatial locality for data
patterns in commercial processors as well as application specific ICs that
work on images, audio and video data. This thesis presents a novel
column based Energy Compression technique that saves SRAM power by
selectively turning off cells based on a data pattern. This technique is
applied to study the power savings in application specific integrated
circuit SRAM memories and can also be applied for commercial
processors. The thesis also evaluates the effects of processing images
before storage and data cluster patterns for optimizing power savings.
Keywords: SRAM, Dual Power Supply, Low Power.
I. INTRODUCTION
SRAM (Static Random Access Memories) is used in
processing image frame buffers [1, 2, 3]. Videos have multiple
frames that need to be stored. SRAM provide a low latency
solution for comparing master video frames with subsequent
frames. SRAM have low access time and can service a request
for data elements quicker than DRAM (Dynamic Random
Access Memories). They are fabricated on-chip, thus allowing
them to use the same technology process in their manufacture
as that of the core and other on-chip logic. SRAM is a volatile
memory element, but does not require refreshing like that of
DRAM. As there is high amount of temporal locality between
subsequent video frames, usually the differential between the
master frame and adjacent frames is stored on disk. The
master frame is stored in a SRAM system that predominantly
only reads this frame [1, 2].
SRAM memory system for image and video processing in
application specific integrated circuits (ASICs) consume upto
81% of the power as standby/leakage power [4]. The power
dissipation of the chip is dictated by the amount of power
consumed by unit area.
Manuscript received on February, 2018.
Vineet Singh, Research Scholar, Department of Electronics &
Communication Engineering, Lakshmi Narain College of Technology,
Bhopal, M.P., India.
Prof. Mukul Shrivastava, Asst. professor, Department of Electronics &
Communication Engineering, Lakshmi Narain College of Technology,
Bhopal, M.P., India.
Impact Factor: 4.012
Published under
Asian Research & Training Publication
ISO 9001:2015 Certified
ISSN No.
www.ijrtonline.org
The total power in the system is comprised of two
components, active power and idle power. Active power is
consumed when the processor chip is busy. This power is used
while processing data. Since the usage patterns of commercial
electronic appliances imply that a device need not be busy all
the time, there are gaps of idle periods. Transistors consume
idle power (leakage power) during all times. At sub-
nanometer nodes, the leakage power of transistors increases
and their threshold voltage (Vth) is found to reduce.
A lower Vth results in more leaky transistors as the
pressure differential of Drain-Source voltages induces a small
sub-threshold current even when the device is not active. This
results in increased idle power, thus increasing the overall
system power even when the processor or application specific
IC is not active. SRAM consumes significant area of the on-
chip real estate. For video processing, this number has
increased as the number of processing engines has increased.
Since each processing engine can operate on independent
portion of memory, an increase in number of processor engines
require an increase in SRAM size for better throughput [2].
The size of SRAM impact system performance and most
processing engines are allocated significant on chip area for
SRAM system. Leakage power is determined by the number of
SRAM cells. As the size of SRAM system in commercial
appliances increases leakage power for SRAM is found to
dominate the total power consumption. Commercial processors
and ASICs reduce operating power using techniques like
power gating and frequency scaling for cores or processing
engines and other on-chip logic circuits during idle modes [5].
Power gating drives the supply nodes (VDD/GND) into high
impedance by using power gating transistors. This results in
reduced power into the logic circuitry but also results in tri-
stating this logic circuitry. Memory elements store data and
validity of data cannot be compromised. Most large memory
elements like L3 (Level Three) caches have additional error
correcting circuits to ensure data fidelity. Since for memories,
one cannot afford to have a loss in data reliability as it results
in incorrect execution or crashing of applications that are run
by the cores or incorrect processing of video frames and
images by the processing engines. Thus we cannot use
techniques like power gating for SRAM system, as tri-stating
these elements result in data loss. Studies show that processors
and image, audio or video processing engines operate on data
that is biased towards a particular data value zero or one [6, 7,
8
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. I, February 2018
8]. This results in SRAM memories having larger number of
data cells that these biased values. Thus architecting memories
that have biased properties for storing biased values has been
suggested in some previous literature.
II. LITERATURE REVIEW
Amit Chhabra et al. [1], design of a low-energy power-ON
reset (POR) circuit is proposed to reduce the energy consumed
by the stable supply of the dual supply static random access
memory (SRAM), as the other supply is ramping up. The
proposed POR circuit, when embedded inside dual supply
SRAM, removes its ramp-up constraints related to voltage
sequencing and pin states. The circuit consumes negligible
energy during ramp-up, does not consume dynamic power
during operations, and includes hysteresis to improve noise
immunity against voltage fluctuations on the power supply.
The POR circuit, designed in the 40-nm CMOS technology
within 10.6-μm2 area, enabled 27 × reductions in the energy
consumed by the SRAM array supply during periphery power-
up in typical conditions.
A. Wang et al. [2], in ultra-low power application design
of energy efficient SRAM structures is very important. In
traditional, the SRAM array contains more number of rows
than the number of columns, but here at a particular lower
supply voltage, better energy efficiency can be achieved with
a wider SRAM structure where the number of rows is less
than the number of columns. Here we can get an energy
improvement of 38% for a 64Kb and 10% for 8kb SRAM
array with same power supply voltage. Minimum energy can
be consumed by using a power supply voltage whose value is
equal or lower than the threshold voltage value. But the lower
value of power supply voltage affects the stability of the
design, i.e. noise margin is reduced. It can be observed that
minimize energy consumption is achieved in non-square type
memory array structures, whereas minimum access time is
achieved in square type memory array structure. Both
dynamic and static energy of word lines and bit lines are
affected by power supply voltage, i.e. energy consumption
decreases with decreasing the supply voltage. The limitations
of the 6T SRAM cell are eliminated by 8T cell which uses
separate port for reading operation.
S. Fisher et al. [3], compared to conventional 6T SRAM
the proposed read static noise margin free 7T-SRAM has less
area which is 23% smaller than conventional SRAM [25]. To
reduce the power dissipation in the memory design, Dynamic
Voltage Scaling (DVS) technique is used. With the lower
supply voltage, the delays in SRAM increases at a higher rate
compared to the delays of CMOS logic circuits and during
read operation, lower supply voltage results loss of data stored
in the memory cell [25]. To find the effect caused by a
transistor mismatch in the memory cell, Monte Carlo
Simulations are performed with a standard deviation of (1/10)
of threshold voltage. The values of Read Static Noise Margin
and cell current are highly depending on the driving capability
of NMOS access Transistors. As driving capability of access
Impact Factor: 4.012
Published under
Asian Research & Training Publication
ISO 9001:2015 Certified
ISSN No. 2394-9007
www.ijrtonline.org
transistor increases then the value of read static noise margin
decreases whereas cell current increases.
T. Heijmen et al. [4], to reduce the leakage current
present in the access transistors, a 4T-SRAM is proposed that
uses negative word-line scheme which gives lot of
improvement in terms of power dissipation. As the memory
size increases, then the leakage currents also increases which
results more power dissipation even in standby mode. High
speed and low power memory design is very important and
this can be achieved by varying the threshold voltage values of
access transistors, which are controlled by the word lines. Low
threshold access transistors are used to speed up the read and
write operation of memory cell [26], whereas high threshold
access transistors are used to reduce the leakage current
present in the memory cell. Unlike conventional 6T SRAM,
the 4T SRAM does not contain any load and 4T SRAM
occupies 35% less area compared to conventional SRAM and
it consumes 29% less power dissipation compared to
conventional 6T SRAM Memory cell. It is observed that
leakage current in NMOS transistors is greater than the
leakage current in PMOS transistors for a particular reverse
voltage of same magnitude. Also we can notice that the p type
latch n type access 4T SRAM saves more power compared to
n type latch p type access 4T SRAM when negative word line
scheme used .
R. C. Baumann et al. [5], the contribution of leakage
current in power dissipation is increases with the voltage
scaling in case of SRAM based memories. By increasing the
reverse bias voltage at body we can increase threshold voltage
which results reduction in sub threshold current but speed of
memory is reduces because of the above reverse biasing.
Hence after reverse biasing at body, the subsequent delay rises
and less number of cells violates the original delay of the
SRAM memory block and these cells are replaced by spare
SRAM columns and rows. In the sub 90 nm technologies
because of the within-die variations, identical memory cells
also shows different delays in a memory cell array [27]. From
the Empirical formulae based studies it is known that 3.54%
of random variation in delay is observed because of within-die
variation in case of 90 nm field programmable gate arrays
(FPGAs). These variations can be modeled by using Gaussian
distribution whose results are matched to the results of
statistical based studies. Cache memory leakages can be
reduced by switch off the unused parts and put them in a
sleepy mode which is having lower energy and this can be
done by using two different power supply voltages. By using
dual threshold voltages and dual oxide thickness values we
can minimize the leakages present in the SRAM Based cache
memories.
III. PROBLEM FORMULATION
The main purpose of this thesis is to reduce power dissipation
during the Write operation in CMOS SRAM cell. Other factor
like- cell area, switching delay, power dissipation and how
many transistors are used in the implementation of SRAM are
also optimizing. Cell Area: Cell area is reduced by a proper
9
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. I, February 2018
selection of the value of width and length. Switching Delay:
Switching delay affect the speed of the CMOS gate is limited
by the time taken to charge and discharge the load
capacitance. Switching delay is reduced by a proper selection
of the value of rise time and fall time.
IV. PROPOSED METHODOLOGY
In this scheme, in proposed cell, M5 is write access transistor
and M6 is for read access. Having individual access transistors
in our cell, it is possible to increase size of write access
transistor to improve write-ability and choose minimum size
for read access transistor to enhance read stability, whereas in
6T there is a conflict while sizing the access transistors.
Fig. 1: Dual Supply Based Low Power 10T SRAM Cell
Fig. 2: Design Flow
Impact Factor: 4.012
Published under
Asian Research & Training Publication
ISO 9001:2015 Certified
ISSN No. 2394-9007
www.ijrtonline.org
In the proposed SRAM cell, the added pMOS and nMOS
transistors (M7, M8) become OFF during write operation and
transistors (M9, M10) are used to control dynamic power
supply which is controlled by WL/WLB. In proposed, before
read and write operation WL/WLB is used to control two kind
of supply VddL and VddH for right sided inverter. Supply
VddL connected to right side inverter during standby mode,
while VddH connected to right side inverter during read or
write. The flow chart of proposed design methodology shown
in figure 2. Here also, M3/M4 is used as pull up transistor and
M1/M2 is used as pull-down transistor.
V. CONCLUSION
Write access time, read access time and power dissipation are
the major issues in high speed SRAM cells. In this paper, a
novel low power 10T dual VDD CMOS based SRAM will
have been proposed, which dissipates less write dynamic
power during write operation due to stack transistor M9 and
M10, Which is dynamically controlled by WL/WLB. Low
static power and low dynamic power obtained by proposed
design using two supplies VDDH and VDDL. VDDL provide
the supply to inverter during standby mode, while VDDH
provide the supply to inverter during read/write mode. The
simulation shows that the proposed SRAM cell dissipates
lesser dynamic power during write; has better write access
time; dissipates lesser current leakage during the mode
transitions than the other existing SRAM cells. This cell
occupies similar area like WRE8Tbut shows better
performance in term of write access time and writes power.
REFERENCES
[1] Rakesh Biswas, Siddarth Reddy Malreddy and Swapna
Banerjee, “Area and Energy-Efficient Complementary Dual-
Modular Redundancy Dynamic Memory for Space
Applications”, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Volume:25, Issue: 2, Feb.2017.
[2] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba,
“Impact of scaling on neutron-induced soft error in SRAMs
from a 250 nm to a 22 nm design rule,” IEEE Trans. Electron
Devices, vol. 57, no. 7, pp. 1527–1538, Jul. 2010.
[3] L. W. Massengill, B. L. Bhuva, W. T. Holman, M. L. Alles, and
T. D. Loveless, “Technology scaling and soft error reliability,”
in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Apr. 2012, pp.
3C.1.1–3C.1.7.
[4] R. C. Baumann, “Soft errors in advanced computer systems,”
IEEE Des. Test Comput., vol. 22, no. 3, pp. 258–266, May/Jun.
2005.
[5] S. Lutkemeier, T. Jungeblut, H. K. O. Berge, S. Aunet, M.
Porrmann, and U. Ruckert, “A 65 nm 32 b sub-threshold
processor with 9T multi-Vt SRAM and adaptive supply voltage
control,” IEEE J. Solid- State Circuits, vol. 48, no. 1, pp. 8–19,
Jan. 2013.
[6] L. Atias, A. Teman, and A. Fish, “Single event upset mitigation
in low power SRAM design,” in Proc. IEEE Conv. Elect.
Electron. Eng. Israel (IEEEI), Dec. 2014, pp. 1–5.
[7] M. A. Bajura et al., “Models and algorithmic limits for an ECC-
based approach to hardening sub-100-nm SRAMs,” IEEE Trans.
Nucl. Sci., vol. 54, no. 4, pp. 935–945, Aug. 2007.
10
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. I, February 2018
[8] J. Maiz, S. Hareland, K. Zhang, and P. Armstrong,
“Characterization of multi-bit soft error events in advanced
SRAMs,” in IEDM Tech. Dig., 2003, pp. 21.4.1–21.4.4.
[9] J. Teifel, “Self-voting dual-modular-redundancy circuits for
singleevent- transient mitigation,” IEEE Trans. Nucl. Sci., vol.
55, no. 6, pp. 3435–3439, Dec. 2008.
[10] L. Sterpone and M. Violante, “Analysis of the robustness of the
TMR architecture in SRAM-based FPGAs,” IEEE Trans. Nucl.
Sci., vol. 52, no. 5, pp. 1545–1549, Oct. 2005.
[11] K. C. Mohr and L. T. Clark, “Delay and area efficient first-level
cache soft error detection and correction,” in Proc. Int. Conf.
Comput. Design (ICCD), Oct. 2006, pp. 88–92.
Impact Factor: 4.012
Published under
Asian Research & Training Publication
ISO 9001:2015 Certified
ISSN No. 2394-9007
www.ijrtonline.org
[12] T. Calin, M. Nicolaidis, and R. Velazco, “Upset hardened
memory design for submicron CMOS technology,” IEEE Trans.
Nucl. Sci., vol. 43, no. 6, pp. 2874–2878, Dec. 1996.
[13] S. M. Jahinuzzaman, D. J. Rennie, and M. Sachdev, “A soft
error tolerant 10T SRAM bit-cell with differential read
capability,” IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3768–
3773, Dec. 2009.
[14] O. Chertkow, A. Pescovsky, L. Atias, and A. Fish, “A novel low
power bitcell design featuring inherent SEU prevention and self-
correction capabilities,” J. Low Power Electron. Appl., vol. 5,
no. 2, pp. 130–150, 2015.
11