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Faculty of Electrical Engineering, UTeM, Melaka, Malaysia

UMPEDAC Research Centre, University of Malaya, Kuala Lumpur, Malaysia

UMPEDAC Research Centre, University of Malaya, Kuala Lumpur, Malaysia

azrita@utem.edu.my, nasrudin@um.edu.my, mohd azlan@um.edu.my _

Abstract- This research aimed to design a three-phase ac-dc short-circuit, and easy in-rush current. One of the disadvatages

buck converter to achieve low-THO unity-power-factor of buck rectifier is that there is no path for reverse inductor

sinusoidal input current and regulated dc voltage via modified current on the dc side, so modified PWM is required, for

pulse-width-modulation (PWM) technique. A 6-switch topology reverse-current flow path. The PWM switching scheme is

with bidirectional power flow capability is presented. The discussed in [5-7] for PWM flyback converter (3-switch 12-

modified PWM switching strategy is discussed and verified via

diode rectifier) and implemented via FPGA. This paper focuses

Matlab-Simulink and implemented in Digital Signal Processor

on three-phase PWM buck rectifier with bidirectional

(DSP) TMS320F28335. The topology and the switching technique

capability by improving the conventional six switches-six

performed well for sinusoidal input current, power factor,

diodes buck rectifier topology. The bidirectional topology uses

harmonic distortion level of the ac input currents, and regulated

one carrier signal, instead of two carrier signal as discussed in

dc voltage, and enabled return of power flow from the dc side

back to the ac. Simulation using Matlab-Simulink is presented to

[5, 6], to create the PWM gating signals for the switches. The

verify the effectiveness of the circuit configuration.

modified PWM switching strategy is discussed and verified via

Matlab-Simulink and implemented in DSP TMS320F28335.

The converter and the switching technique is designed to

Keywords- bidirectional; three-phase power converter; modified improve power quality, which is described as nearly sinusoidal

PWM;DSP input current, regulation of input power factor to unity, low

harmonic distortion of line current (THD below 5%), and

I. INTRODUCTION stabilization of DC-link voltage (or current).

A comprehensive review on three phase ac-dc converters

II. CIRCUIT CONFIGURATION & PRINCIPLE OF OPERATION

has been done on the configuration using IGSTs as a

replacement of the conventional diodes rectifiers. These

converters have been extensively developed to improve power A. Circuit Configuration

quality. The main feature of the improved power quality are Two common topologies for three-phase buck rectifier

described as nearly sinusoidal input current, regulation of input using PWM to improve ac mains power quality and output dc

power factor to unity, low harmonic distortion of line current bus [5- 12] as shown in Fig.I. Topology 1 is conventional 6-

(based on standards such as IEEE 5 19, IEC-1000 and IEC switch 6-diode and Topology 2 is modified 3-switch 12-diode,

6 1000-3-2 [ 1-2] ), adjustment and stabilization of DC-link which has less driver-devices and less complicated PWM

voltage (or current) and reduced capacitor (or inductor) size switching pattern. These topologies are classified as

due to the continues current. unidirectional. The topologies with capability of bidirectional

power flow have been studied in [ 12-13].

Rectifiers are nonlinear system, generating harmonic

current into the ac line power. High harmonic content in line

current causes low power factor in a load and problems such as

voltage distortion and electromagnetic interference (EM\) in

power distribution systems, affecting power-system users and

increasing volt-ampere ratings of power-system equipment

such as generators and transformers. The topologies can be S2

divided into two main categories: unidirectional and bi

directional. Three phase ac-dc converter configurations for

unidirectional that use various switching techniques for control

of power has been proposed in [3]. The most widely used is

pulse width modulation (PWM), which requires high switching

frequency, for wide bandwidth and small inductor-current

ripple. The bidirectional or regenerative rectifiers using PWM

(a) (b)

technique had been discussed in [4].

Some of the attractive features of buck rectifiers include the Figure 1. The topology's configuration (a) Topology 1 (b) Topology 2

requirement for various controllable output dc voltage, inherent

Monitoring (IPPP), University of Malaya under postgraduate research grant

PS I 13-2009C

2011 IEEE First Conference on Clean Energy and Technology CET

2S0 r-----,----,---....---,

: Phase A: : Phase B : : Phase C

200 , ,

y--------

, ,

, ,

;:

\ \/ '

\ : /\ !

A

\! : ' :

, ' ,

/ .,"

B

\ t

J \"-

·SO 1\ / j I: :

,

,

,

,

>:'\:

! \-" !

, ,

.100

·1S0

·200 '!

', . . . .• . • !"-- �

I II : ill

.2S00�----'1t ----':-t2---t3L-- ---'4t --....

t5---.J15

....L

Figure 2. The topology's configuration Time (s)

bidirection:tl converter Figure 4. Three-phase supply-voltage waveforms (divided into six equal

sections of the 3600 mains cycle).

r-=�IIA

ruI� �rl:'

I'J••"A,�RI 1 J.

VA

Phu.B,�RI crz 1 $ Cd� RL

VB

$ r� c: " T

'--_--'-_I--_..J 1 I

illustrating the rectifier/inverter principle of operation for

PWM switching [6]. The IGST switching is divided into six

Phase c: L( Rf

vc� equal sections of the 3600 mains cycle. Similar patterns repeat

in each section, giving rise to the idea of designing only one

PWM-pattem section. Positive cycle represents upper side of

Figure 3. A rectifier's overall system drawn in Matlab-Simulink. the switches (S 1, S2, and S3) while the lower side switches

(S3, S4, and S5) is represented by negative cycle. The

The circuit configuration in [ 13] is used in this paper (Fig. technique reduces the number of power-device switching and

2) with modification on switching technique to make it easier reduces switching losses [ 14]. At any given time, only two

in constructing gating signals in DSP. Fig. 3 shows the three converter legs are modulated independently, while another leg

phase bidirectional system, drawn in Simulink-Matlab. There is in the 'on' state. Voltage and current waveforms can be

are two supply voltage, ac supply for rectifying mode and dc expressed as follows:

supply for inverting mode.

Va = Vrn sinO)t (2)

For the input filter, capacitor Cf is delta-connected, which,

la = Irnsin(O)t +$) (3)

compared with star connection, gives good differential-mode

performance and reduced resonant frequency. Parameters for 21t

Vb = Vrn sin(rot - ) (4)

the ac-side and dc-side filters are: (ac-side) Lf = 1 mH, Rf = 3

0.5 n, and Cf= 1 !iF, and (dc-side) Ld= 2mH, Rd= 0.5 n, and _ 21t

Cd = 200 !iF. Parameters for the snubber's (Rs-Cs circuit) lb = 1m sin(O)t + $) (5)

IGST and diode are Rs-Cs= 10 n -0.001 !iF. 3

21t

The value of inductor, Ld for dc-side filter is obtained using Vc = Vrn sin(O)t +) (6)

equation: 3

21t

Ie = I rn sin(O)t+ +$) (7)

Ld :2:. ( RL(1- ..J3 * M) * Ts) : ML,ripple(rnax)

( 1) 3

2 IL

Where, Vrn is peak voltage, I rn is peak current, and $ is the

Where, RL = 20 n (load resistance), M = 0.9 (modulation

amplitude), Ts 1/fs 1/ 19.8 kHz (sampling time), and

= =

angle between phase voltage and current or displacement

factor. Each section has three modes of circuit operation.

ML,ripple(rnax)

::; 15% . Using ( 1), Equations for current flow and bridge voltage (V d for the

IL switch combinations in section 1are as follows:

Ld:2:. (20(1- ..J3 * 0.9) * 1 / 19.8K) + 0. 15 :2:.1.5mH Mode 1: la = IL*M*Ta, Ib= -la, Ic= 0, VL = Vab (8)

2 Mode 2: la= 0, Ib= -Ic, Ic = IL*M*Tb, VL = Vcb (9)

Therefore, the chosen value for Ld is 2mH. Mode 3: Ia= 0, Ib= 0, Ic =O,VL = 0 ( 10)

2011 IEEE First Conference on Clean Energy and Technology CET

3

VL = *M*Vrn *cos (¢) (II)

2"

0.8

Mode 3 allows freewheeling current to flow on the dc

� 0.6

(!)

0.

switches are off. Therefore the switch on the same leg must � 0.4

be tum 'on' to create freewheeling path for inductor current

at dc side as shown in Fig. 5. The dc voltage Vde is less than 0.2

the bridge voltage by the drop Rd across the resistor. The

voltage dc output voltage Vde can be obtained using (12). %�--------

��-------- -��--------

�

20 40 60

Degree

RL

Vde =�*M*Vrn *cos"'* (12)

2 'f' RL + Rd

where, Rd is the equivalent series resistor (ESR) of the �. Figure 6. Reference signal consists of 132 data (for 60°).

Table I shows the commutating process during each

topology's switching period T. Theoretically the dc voltage can A. Generating the Look-up Table (reference signal)

be controlled between 0 and 1.5 times of the phase voltage The 60° sinusoidal waveform (reference signal) look-up

peak Vm (in ideal condition where ¢ equals zero or unity power tables, as shown in Fig. 6, are used to generate modulated

factor) as stated in (12). PWM Ta. Modulated PWM Tb is obtained by manipulating the

look-up table of the reference signal. The PWM is based on

Ld

asymmetrical switching technique, generating 132 data of

reference signal stored in the look-up table. The modulation

It index can be controlled from 0 to 1 by multiplying the value

(freewheeling) with the reference's look-up table.

RL

The process of generating PWM for a 50Hz main frequency

using asymmetrical switching technique is shown in Fig. 7.

DATA is the reference look up table, i refers to the number of

look up table's data, Zero and PRO occur when carrier's signal

value is zero and maximum, respectively.

Figure 5. Freewheeling mode (Mode 3).

Section Switches

SI S2 S3 S4 S5 S6

I Ta Tr Tb TofT To n TofT

V Tr Tb Ta To n TofT TofT

Carry on the

Five repeating similar patterns are generated for each process

switches, comprising modulated PWM (Ta and Tb), "on" state

(Ton), "off' state (Toff) and "freewheeling" state (Tr) as shown

in Table 1. Sixty-six samples of carrier signal of 19.8 kHz are

generated in each section, resulted 396 samples of carrier

signal to produce a 50Hz main frequency. Figure 7. The process on generating PWM signals using assymmetrical

switching technique.

2011 IEEE First Conference on Clean Energy and Technology CET

Tek • Stop M Pos: 552,O)Js MEASURE

.. CH1 Specifications for the IGBTs and the diodes are:

Freq

20,OOkHz? lGBT: Ron 0,00 10, Lon 0, forward voltage IV, current

.....

r1 � n n r'1 = = =

= =

= = =

1

Part II describes the design of the input and the output

,JlTlllllllflmTI lHl

filters, Figs, 10- 13 show the input current in phases A, B, and

C, the FFT analysis graph for input current (phase A), the dc

voltage (VRL) with output current IL, the bridge voltage Vbridge

,.lUUUH U HJ II �.JI.IUJt

None of each topology and, with these specifications: input voltage

V in 200V (Vpeak for Phases A, B, and C), modulation index

=

None

demonstrate the proposed topology obtained near-unity power

CH1 2,OOV CH2 2,QOV M 100)Js CH3 f 1.44V factor (0,99) with a good THO value (less than 5%), regulated

CH3 2,QOV 5-May-11 13:10 1,22154kHz dc output voltage at steady-state (250V), and stable bridge

voltage (dc voltage before filtering), when operated in

Figure 8. PWM signals generated via DSP.

rectifying mode, The efficiency of the system is calculated

89.3%,

The references signals are compared with carrier signals,

respectively to generate PWM To. PWM Tb, and PWM Tr

patterns, Fig, 8 shows the PWM signals generated via OSP,

Zooming illustrate the PWM Tf (bottom) is "on" when both

PWM Ta (upper) and Tb (middle) are "off',

Fig, 9(a) and (b) show the PWM pattern of 50Hz main

frequency via OSP (captured by oscilloscope) for switches S I,

S4, S2, S5, and simulation MATLAB for switches S 1-S6,

Time

::F :

0

0 0 02 0 04

",

0 06 0.08 0.1

'l;

- 50

0 0 02 0 04

"

Time

0 06 0.08

• l 0.1

(b)

Figure 12. The dc voltage with output current IL

Figure 9. PWM pattern (modulation index=1.0) via (a) DSP (b) MATLAB

2011 IEEE First Conference on Clean Energy and Technology CET

Improvement in controller design is needed to improve the

transient response of dc current (rectifying mode). The

intelligent controller needs to be investigated to resolve the

conversion between rectifying and inverting modes.

Time

ACKNOWLEDGMENT

Figure 13. The bridge voltage VL before filtering UTeM and MOHE, for sponsoring Authorl,s study. This

project was funded by Institute of Research Management and

Monitoring (IPPP), University of Malaya under postgraduate

300,-

--�--�----, research grants (PS113-2009C).

REFERENCES

[I] IEEE Recommended Practices and Requirements for Harmonics Control

in Electric Power Systems, IEEE std. 519, 1992.

[2] Electromagnetic Compatibility (EMC)-Part 3: Limits-Section 2: Limits

for Harmonic Current Emissions (Equipment Input Current Emissions

(Equipment Input Current < 16A per Phase), IECI000-3-2 Doc., 1995.

[3] B. Singh, B. N. Singh, A. Chandra, K. AI-Haddad, A. Pandey and D. P.

• 3Wo!::2:---:

- ;-O

o .04::----;

o.�

06;- :----:;-O0.08 .I--

::;----;0':-

; --:0,-':

.1-:- .1 4:----:0,-':. 1-;-

2 ---;007 6 ---;007. - 0.2;'

.18,------; Kothari, "A review of three-phase improved power quality AC-DC

Time converters", IEEE Trans. Ind. Electron., vol. 51, no. 3, pp. 641-660, June

�. 2004.

Rectifying Inverting [4] Jose R. RodriguezJuan W. Dixon, Jose R. Espinoza, and Pablo Lezana,

"PWM Regenerative Rectifiers: State of the Art", IEEE Trans. Ind.

Electron., vol. 52, no. I, pp. 5-22, Feb. 2005.

Figure 14. The input current and voltage for phase A for rectifYing and [5] S. Mekhilef, A.M. Omar and N. A. Rahim" "Modeling of Three-phase

inverting modes Uniform Symmetrical Sampling Digital PWM for Power Converter",

IEEE Trans. Ind. Electron., vol. 54, no. I, pp. 427-432, Feb. 2007.

::f : :::: 1

[6] A.M. Omar, N. A. Rahim, and S. Mekhilef, "Three-phase syncronous

PWM for flyback converter with power-factor correction using FPGA

ASIC design", IEEE Trans. Ind. Electron., vol. 51, no. I, pp. 96-106,

: � : :!C' {' : : : 1

V" I Feb. 2004.

&�02'-�--- 0�.0� � 7

4--0. 0�

6 � 0�

.0�

8--�O .L I--�0�.1�

2---:-0.LI� � 6---:-0L.I8�---;

4 � 0�.1 0.2 ;' [7] A.M. Omar and N. A. Rahim, , "FPGA-based ASIC design of the three

phase synchronous PWM flyback converter", lEE Proc.- Electr. Power

Appl. , vol. 150, no. 3, pp. 263-268, May 2003.

[8] C. J. Cass, R. Burgos, F. Wang and D. Boroyevich, "Improved charge

control with adjustable input power factor and optimized switching

pattern for a 150kHz three-phase buck rectifier", Applied Power

&02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time

Electron. Conf. and Exposition, APEC 2008, 23rd Annual IEEE, pp.

1200-1206, 2008.

�III

Rectifying Inverting [9] B. W. Williams, M. M. Moud, D. Tooth, and S. J. Finney, "A three

phase AC-to-DC converter with controllable displacement factor", in

Proc. IEEE PESC'95, pp. 996-1000, 1995.

Figure 15. The dc voltage with output current IL

[IO] T. J. Omedi, R. Barlik, "Three-phase ac-dc unidirectional PWM rectifier

topologies-selected properties and critical evaluation", in Proc. IEEE

Figs. 14-15 show simulation results of input current and ISIE'96, 1996, pp. 784-789.

voltage at ac side for phase A and the dc voltage across RL with [II] Milanovic, M., and Slibar, P., "IDF Correction based PWM Algorithm

inductor current at dc side, for rectifying and inverting modes. for a Three-Phase AC-DC Buck Converter", IEEE Trans. Ind. Electron.

(In Press).

V.

DISCUSSION & FUTURE WORKS [I2] T. C. Green, M. H. Taha, N.A. Rahim, B.W. Williams, " Three-phase

step-down reversible AC-DC power converter", IEEE Trans. Ind.

The three phase bidirectional circuit topology which uses Electron., vol. 12, no. 2, pp. 319-324, Mar. 1997.

six switches is presented (fewer switches than a conventional [I3] L. S. Yang, T. J. Liang, and J. F. Chen, "Three Phase ACIDC Buck

anti parallel converter). Modified PWM switching is shown to Converter With Bidirectional Capability," Power Electronics Specialists

Conference 2006, pp.I-6, 2006.

improve power quality of ac-dc buck rectifier. It provides a

sinusoidal input current, near-unity power factor, low harmonic [I4] H. M. Rashid, "Power electronics: circuits, devices and applications",

United States of America: Pearson Prentice Hall, 2004. pp. 257.

distortion, regulated dc voltage, and a good percentage in

efficiency. The proposed bidirectional topology is verified to

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