ESc201 : Introducton to Electronics

Sequental Circuits

Dept. of Electrical Engineering

IIT Kanpur

1
Recap: Edge Triggered Latch or Flip-flop

D Q

clk

Clock

Positive edge triggered flipflop

Recap: Negative Edge Triggered Latch or Flip-flop

D Q

clk

Clock

D
Positive edge triggered D Flip-flop

S
2
5 Q

clk
6 Q
3
R

D 4
Characteristic table
Given a input and the present state of the flip-flop, what is the next state of
the flip-flop
Characteristic table
Given a input and the present state of the flip-flop, what is the next state of
the flip-flop

D Q Inputs (D) Q(t+1)

clk 0 0
1 1
Characteristic table
Given a input and the present state of the flip-flop, what is the next state of
the flip-flop

D Q Inputs (D) Q(t+1)

clk 0 0
1 1

Characteristic equation: Q(t  1) D

 JK Flip-flop

J Q

clk

Characteristic table:

Inputs J K Q(t+1)
0 0 Q(t)
No Invalid States 0 1 0
1 0 1
1 1 Q(t)
 JK Flip-flop

J Q

clk

Characteristic table:

Inputs J K Q(t+1)
0 0 Q(t)
No Invalid States 0 1 0
1 0 1
1 1 Q(t)

Characteristic equation: Q(t  1)  JQ (t )  K Q(t )

Toggle or T Flip-flop

T Q

clk
Toggle or T Flip-flop

T Q
Inputs (T) Q(t+1)
clk
0 Q(t)
1 Q(t)
Toggle or T Flip-flop

T Q
Inputs (T) Q(t+1)
clk
0 Q(t)
1 Q(t)

Characteristic equation: Q(t  1) T  Q(t )

Toggle or T Flip-flop

T Q
Inputs (T) Q(t+1)
clk
0 Q(t)
1 Q(t)

Characteristic equation: Q(t  1) T  Q(t )

T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
 SequentialCircuits
X Z The binary information stored in
CC the storage elements at any given
time defines the state of the
sequential circuit at that time
Storage
elements

Output is a function of input as well as the present state of the

storage elements.
Next state is also a function of the present state and the
external inputs.
 SynchronouslSequentialCircuits
Input Combinitonial Output
Circuit
Faip-fops
Clock

Employs signals that affect the storage elements only at

discrete instants of time.

Synchronization is achieved via the clock pulses.

Synchronous Clocked Sequental Circuits
Analysis

A
x A
D

B
A B z
D
x x

clk
Analysis
Next state Logic Output Logic
A
x A
D

B
A B z
D
x x

clk
memory
Analysis
Next state Logic Output Logic
A
x A
D

B
A B z
D
x x

clk
memory
Output z depends on the input x and on the state of the memory (A,B)
Analysis
Next state Logic Output Logic
A
x A
D

B
A B z
D
x x

clk
memory
Output z depends on the input x and on the state of the memory (A,B)
The memory has 2 FFs and each FF can be in state 0 or 1. Thus there
are four possible states: AB: 00,01,10,11.
Analysis
Next state Logic Output Logic
A
x A
D

B
A B z
D
x x

clk
memory
Output z depends on the input x and on the state of the memory (A,B)
The memory has 2 FFs and each FF can be in state 0 or 1. Thus there
are four possible states: AB: 00,01,10,11.

To describe the behavior of a sequential circuit, we need to show

1. How the system goes from one memory state to the next as the input
changes
2. How the output responds to input in each state
Analysis of Sequential Circuits
A
x
memory
A Output Logic
D

B
A B z
D
x x

Next state Logic

clk

DA  A.x  B.x ; DB  A.x ; z ( A  B ). x

Analysis of Sequential Circuits
A
x
memory
A Output Logic
D

B
A B z
D
x x

Next state Logic

clk

DA  A.x  B.x ; DB  A.x ; z ( A  B ). x

A(t  1)  A(t ).x  B (t ).x

B (t  1)  A(t ).x
z ( A  B ). x
Analysis of Sequential Circuits
A
x
memory
A Output Logic
D

B
A B z
D
x x

Next state Logic

clk

State Transition Table

DA  A.x  B.x ; DB  A.x ; z ( A  B ). x
Present State Input Next State Output
A B x A B z
0 0 0 0 0 0
0 0 1 0 1 0
A(t  1)  A(t ).x  B (t ).x
0 1 0 0 0 1
0 1 1 1 1 0
B (t  1)  A(t ).x
1 0 0 0 0 1
z ( A  B ). x 1 0 1 1 0 0
1 1 0 0 0 1
1 1 1
1 0 0
 State Transition Table

A
Present State Input Next State Output
memory Output Logic A B x A B z
x A
D
0 0 0 0 0 0
0 0 1 0 1 0
B
z
A
D
B 0 1 0 0 0 1
x x 0 1 1
1 1 0
Next state Logic clk 1 0 0 0 0 1
1 0 1
1 0 0
1 1 0 0 0 1
1 1 1
1 0 0
 State Transition Table

A
Present State Input Next State Output
memory Output Logic A B x A B z
x A
D
0 0 0 0 0 0
0 0 1 0 1 0
B
z
A
D
B 0 1 0 0 0 1
x x 0 1 1
1 1 0
Next state Logic clk 1 0 0 0 0 1
1 0 1
1 0 0
1 1 0 0 0 1
1 1 1
1 0 0

00 Memory state in which FF A& B have output values 00

 State Transition Table

A
Present State Input Next State Output
memory Output Logic A B x A B z
x A
D
0 0 0 0 0 0
0 0 1 0 1 0
B
z
A
D
B 0 1 0 0 0 1
x x 0 1 1
1 1 0
Next state Logic clk 1 0 0 0 0 1
1 0 1
1 0 0
1 1 0 0 0 1
1 1 1
1 0 0

00 Memory state in which FF A& B have output values 00

If x = 0 then z = 0, When the clock edge comes the

x=0/z system would stay in 00 state.
?
00 If x = 1 then z = 0. When the clock edge comes the
system would go to 01 state.
x=1/z
?
 State Transition Table

A
Present State Input Next State Output
memory Output Logic A B x A B z
x A
D
0 0 0 0 0 0
0 0 1 0 1 0
B
z
A
D
B 0 1 0 0 0 1
x x 0 1 1
1 1 0
Next state Logic clk 1 0 0 0 0 1
1 0 1
1 0 0
1 1 0 0 0 1
1 1 1
1 0 0

00 Memory state in which FF A& B have output values 00

If x = 0 then z = 0, When the clock edge comes the

x=0/z system would stay in 00 state.
?
00 If x = 1 then z = 0. When the clock edge comes the
system would go to 01 state.
x=1/z
0/0
?

00 01
1/0
Analysis of Sequential Circuits
A
x
memoryA Output Logic
D

B
A B z
D
x x

Next state Logic clk

Analysis of Sequential Circuits
A
memoryA
x
D
Output Logic A(t  1)  A(t ).x  B (t ).x
B B (t  1)  A(t ).x
A B z
x
D
x z ( A  B ). x
Next state Logic clk
Analysis of Sequential Circuits
A
memoryA
x
D
Output Logic A(t  1)  A(t ).x  B (t ).x
B B (t  1)  A(t ).x
A B z
x
D
x z ( A  B ). x
Next state Logic clk

State Transition Table

Present State Input Next State Output

A B x A B z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Analysis of Sequential Circuits
A
memoryA
x
D
Output Logic A(t  1)  A(t ).x  B (t ).x
B B (t  1)  A(t ).x
A B z
x
D
x z ( A  B ). x
Next state Logic clk

State Transition Table

1/0 Present State Input Next State Output

10 A B x A B z
0/0 0/1
0 0 0 0 0 0
1/0
0 0 1 0 1 0
00 01 11
1/0 1/0 0 1 0 0 0 1
0 1 1 1 1 0
0/1 1
1 0 0 0 0
0/1 1 0 1 0
1 0
1 1 0 0 0 1
State transition Graph 1 1 1 1 0 0
 LiblEximlInstructons
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 LiblEximlInstructons
B: Questions and Selection:

1) Your experiment will not necessarily be a 'carbon copy' repeat of the circuit and process carried out in the class. An element
of design could be present. You will have to calculate and choose suitable component values or logic interconnection to be used to
get the results asked for in the question.

2) Experiments will be allotted to each student by draw of lots.

3) You are allowed to ask for a change of experiment if you feel unhappy about the experiment you got. But this has to be
requested within 5mins of the exam starting, and will further cost you 25% marks straightaway: you will now be evaluated for only
75% of the marks. A change can be requested at most ONCE. The new experiment you get is also decided by draw of lots. You will
be allowed to try again only if the draw accidentally throws up exactly the same experiment again.

4) No additional time is given to students who opt for a change of question. They have to complete their experiment before the
closing time of their slot.
 LiblEximlInstructons
C: Experiment and Grading:

1) You can get the pin diagram of required IC during the lab exam - if you ask.. Please remember that it is up to you to ensure that you got
the right rated components for the exam from the staff. You cannot exonerate yourself by blaming the tutor/TAs/staff. Copies of class handouts
or other documentations will neither be provided nor allowed into the exam. ONLY PINOUT DIAGRAMS OF THE CHIPS USED - ON
REQUEST.
2) After choosing your question, you have to write out a brief summary of your experiment on the answer book provided, which includes
components to be used, their values and ratings, the circuit you will use, observations you will make and calculations to be made on the
observations. No long stories, just the bare clear, technical facts. This part of your work will carry 30% of the marks.
3) You need not go to your tutor/TA for approval of your write-up. Complete your write-up and proceed with your experiment. You need to
call the tutor/TA only in the end stage when your demo is ready. At that time, you will present your write-up as well.
4) You have to complete the experiment on your own: every time you seek help from the TAs for anything, or ask for clarifications, marks
will be deducted appropriately.
5) Complete your experiment and DEMONSTRATE its operation to the TAs/tutor to their satisfaction. Make the calculations, plots etc, if
any, in your answer book and submit it before the closing time of your slot. All this constitutes the conduct of the experiment and carries the
remaining 70% of the marks.
6) Your marks will be decided when you submit your experiments to the tutor/TAs for final inspection. If you have any dispute, bring it up
right there. The matter cannot be taken up for reconsideration once you leave the lab.
7) Irrespective of whether each student agrees fully pr partly with his/her marks or not, HE/SHE HAS TO COUNTERSIGN ON THE
MARKS AWARDED ON HIS/HER ANSWER BOOK BEFORE LEAVING THE ROOM. NO COMPLAINTS OF MARKS FUDGING
WILL BE ENTERTAINED LATER UNLESS THERE IS ANY STRIKING OUT OF THE MARKS. If you are still not satisfied with your
marks, please leave a written note on the front page of the answer book before leaving. This is essentially a regrade request and will be
considered later but we are not obliged to get back to you.
8) Communication during your exam with other students taking the exam will be considered a malpractice.