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Lecture 18
V. Kamakoti and
Shankar Balachandran
Overview of this Lecture
• Advanced Modeling Techniques
– Timing and Delays
– Switch Level Modeling
– User-Defined Primitives
Timing and Delays
• Functional Verification Vs Timing
Verification
• Increasingly important as circuits have
become smaller and faster.
• Check timing
– Perform a timing simulation
– Perform a Static timing verification
Static timing verification
• Designers first do a pure functional
verification and then verify timing
separately with a static timing verification
tool.
• We discuss static timing
verification/analysis later in the course
• Now we discuss timing simulation
Delay models
• Three types of delay models used in
Verilog
– Distributed delay model
– Lumped Delay model
– Pin-to-pin (path) Delay model
Distributed Delay Model
• Delays that are specified on a per element
basis
• Distributed delays
– modeled by assigning delay values - in gate
level modeling
– modeled by assigning delays in the
continuous assignment – in data flow
modeling
• Provides detailed delay modeling
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a
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c
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Thank You