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CAD for VLSI Design - I

Lecture 18

V. Kamakoti and
Shankar Balachandran
Overview of this Lecture
• Advanced Modeling Techniques
– Timing and Delays
– Switch Level Modeling
– User-Defined Primitives
Timing and Delays
• Functional Verification Vs Timing
Verification
• Increasingly important as circuits have
become smaller and faster.
• Check timing
– Perform a timing simulation
– Perform a Static timing verification
Static timing verification
• Designers first do a pure functional
verification and then verify timing
separately with a static timing verification
tool.
• We discuss static timing
verification/analysis later in the course
• Now we discuss timing simulation
Delay models
• Three types of delay models used in
Verilog
– Distributed delay model
– Lumped Delay model
– Pin-to-pin (path) Delay model
Distributed Delay Model
• Delays that are specified on a per element
basis
• Distributed delays
– modeled by assigning delay values - in gate
level modeling
– modeled by assigning delays in the
continuous assignment – in data flow
modeling
• Provides detailed delay modeling
e
a
#5
b
#4 out
c
#7
d f

module M (out,a,b,c,d); module M(out,a,b,c,d);


output out; output out;
input a,b,c,d; input a,b,c,d;
wire e,f; wire e,f;
and #5 a1(e,a,b); assign #5 e = a & b;
and #7 a2(f,c,d); assign #7 f = c & d;
and #4 a3(out,e,f); assign #4 out = e & f;
endmodule endmodule
Lumped delays
• Lumped delays are specified on a per
module basis.
• Single delay on the output gate of the
module – cumulative delays of all paths is
lumped at one location.
• They are easy to model compared with
distributed delays
e
a
b
#11 out
c
d f

module M (out,a,b,c,d); module M(out,a,b,c,d);


output out; output out;
input a,b,c,d; input a,b,c,d;
wire e,f; wire e,f;
and a1(e,a,b); assign e = a & b;
and a2(f,c,d); assign f = c & d;
and #11 a3(out,e,f); assign #11 out = e & f;
endmodule endmodule
Pin-to-Pin Delays
• Delays are assigned individually to paths
from each input to each output.
• Delays can be separately specified for
each input/output path.
e
a
#5
b
#4 out
c
#7
d f

path a-e-out, delay = 9


path b-e-out, delay = 9
path c-f-out, delay = 11
path d-f-out, delay = 11
Path Delays
• Pin-to-Pin delays are named as path delays
• The delay values got directly from Data Books
for standard elements.
• For larger Digital Circuits, a low level circuit
simulator like SPICE may be used.
• Designer needs to know the I/O pins of the
module rather than the internals of the module –
so easier to model, even though it is very
detailed.
Path Delays
• Distributed Delays and Lumped Delays –
already covered in detail in previous
lectures.
– Rise,fall, turnoff delays
– Min,max,typ delays
• We now study Path Delays
• specify blocks
module M (out,a,b,c,d);
e output out;
a
#5 input a,b,c,d;
b
#4 out wire e,f;
c specify
#7
d (a => out) = 9;
f
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
endspecify
and a1(e,a,b);
and a2(f,c,d);
and a3(out,e,f);
endmodule
Specify Blocks
• Specify blocks are outside initial and always
blocks.
• Inside specify blocks
– Parallel connections
– Full connections
– Conditional Connections
• Parallel: If a[3:0] and out[3:0] are 4-bit
vectors then, (a => out) = 9 stands for the
shorthand of
• (a[0] => out[0]) = 9;
• (a[1] => out[1]) = 9;
• (a[2] => out[2]) = 9;
• (a[3] => out[3]) = 9;
Specify Blocks
• If width does not match for ‘a’ and ‘out’,
then it is a illegal connection
• Full Connection: Here every bit in source
field connected to every bit of the
destination.
• A full connection is denoted by *>
module M (out,a,b,c,d);
e
a output out;
#5
b input a,b,c,d;
#4 out wire e,f;
c specify
#7
d f (a,b *> out) = 9;
(c,d *> out) = 11;
endspecify
and a1(e,a,b);
and a2(f,c,d);
and a3(out,e,f);
endmodule
specparam
• specify
• specparam d_to_q = 9;
• specparam clk_to_q = 11;
• (d => q) = d_to_q;
• (clk => q) = clk_to_q;
• endspecify
Conditional Path delays
• specify
• if (a) (a => out) = 9;
• if (~a) (a => out) = 10;
• if (b & c) (b => out) = 9;
• if ((c,d) == 2’b01) (c,d *> out) = 11;
• if ((c,d) != 2’b01) (c,d *> out) = 13;
• endspecify
Questions and Answers

Thank You

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