ADVANCED FLOORPLANNING WITH

MENTOR PLACE AND ROUTE FOR FAST

AND RELIABLE DESIGN CLOSURE

SUDHAK AR JILLA
ARVIND NARAYANAN
MENTOR GRAPHICS

W H I T E P A P E R

I C D I G I T A L D E S I G N

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Advanced Floorplanning with Mentor Place and Route

INTRODUCTION
As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and
opportunities that affect the rest of the design flow, from block implementation to chip assembly and top-
level closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad
placement, accurately estimate timing, power, and area, create top-level power networks, and to efficiently
partition the design. Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that
allows early timing estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-
Vdd flows, and offers wide flexibility between automatic and manual placements of all floorplan objects.

In this paper, we review floorplanning challenges and show how the Mentor place and route implementation
systems (Nitro-SoC and Olympus-SoC) comprehensively addresses all those challenges to produce the best
floorplan in the shortest time.

ABOUT HIERARCHICAL DESIGN METHODOLOGIES

Floorplanning is an essential element of hierarchical design flows, especially for large SoC designs. A typical SoC
could include hundreds of RAMs, soft and hard IP, analog blocks, and multiple power domains. A hierarchical
methodology extends the capacity of design-automation tools, improves tool runtimes, and mitigates overall
design risk by minimizing last minute design changes. A hierarchical design flow typically includes three main
stages:

■■ Floorplanning — block placement, pin assignment, design partitioning, time budgeting, power and clock
planning
■■ Block implementation — placement, clock tree synthesis (CTS), routing, optimization
■■ Chip assembly — block instantiation, top-level glue logic optimization, top-level CTS/routing, global wire
buffering, power and clock routing, etc.
The decisions made during floorplanning about the location of pins, pads, blocks, and partitions, as well as
the overall power plan, carry through and impact the rest of the implementation. Floorplanning allows
designers to perform “what-if” analysis of critical design metrics such as performance, timing, power, and area
when there is more flexibility in the layout. Estimations are shared, and floorplanning modifications are often
done iteratively between the package or board designers, the chip-level designer, and the block-level
engineers.

The outcome of the floorplanning stage is a completed arrangement of macros and IO pads, a power plan, and
partitioned blocks that can then be implemented in parallel. After the block implementations are complete,
everything is reassembled for top-level routing and optimization. This is where errors from poor floorplanning and
block implementation are revealed, which leads to unnecessary iterations, late-cycle unpredictability, and missed
market opportunities.

To minimize the impact of surprises in chip assembly, design teams need floorplanning, block implementation, and
chip assembly tools that accommodate small changes without disrupting the design flow. The ability to efficiently
incorporate small ECOs (engineering change orders) between the SoC-level and block level greatly reduce the risks
associated with hierarchical flows, and shorten the time to design closure. We will elaborate more on the ECO
process later in this paper.

FLOORPLANNING CHALLENGES
Each design project has different challenges and goals, but there are some issues that commonly arise for physical
design teams.

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Advanced Floorplanning with Mentor Place and Route

BAD IO PAD PLACEMENT

A common situation during floorplanning is the lack of well-defined IO constraints from the board or package
teams. With no guidance on IO placement, the order and location of IO pads can be suboptimal for package-
level requirements, and for chip level timing closure (Figure 1). The true impact of IO pad locations is usually
obscure until more detailed placement and routing is complete, at which point designers must iterate back
to floorplanning to fix the IO pad locations manually, then perform placement and routing again. These time-
consuming iterations can add unacceptable risk to design schedules.

TIME-CONSUMING AND SUBOPTIMAL MACRO PLACEMENT

Achieving optimal macro placement can be a significant
challenge, particularly for SoCs with hundreds of cores,
memories, and 3rd party IP. In years past, macro
placement was a purely manual task. Today, designers
must rely on floorplanning software for a quick,
automated initial placement before manual refinement.
Tools typically cluster macros based on wire length, but
there may be other metrics to consider, such as critical
path timing, power domains, congestion, and
minimization of narrow channels between blocks. These
are all factors that traditionally are addressed through
manual refinement of the seed floorplan. The challenge
lies in the difficulty of that task. On a practical level,
designers need better seed placement and a powerful Figure 1: Sub-optimal IO placements can lead to long paths
over macros. In the design shown, the IOs should be placed on
macro editing capability that can assist in spacing and
the bottom left side to have better access to the logic pins.
aligning groups of macros. The results of sub-optimal IO
Changing the IO placements can be tedious, particularly if the
placements is shown in Figure 1.
problem is not discovered until later in the design flow.

INADEQUATE REGION SHAPING, PARTITIONING, AND PIN ASSIGNMENT

In hierarchical flows, floorplans are partitioned into functional groups that constrain the physical placement of
standard cells and macros. The grouping criteria can be based on clock generation logic, hierarchical
implementation boundaries, or voltage domains (multi-Vdd).

Designers need a deep knowledge of the IC, but they also need the floorplanning tool to be flexible enough
to handle different use models and shapes (rectangular or rectilinear) for regions, while always respecting the
logical hierarchy of the input netlist. Challenges in floorplanning for multi-Vdd designs lie in defining the
voltage domains, creating multiple power grids, and in inserting the special cells such as switches, level
shifters, retention registers, and always-on buffers. Poorly shaped regions and broken logical hierarchy
contribute to delayed schedules and suboptimal timing, power, and area.

Once the regions are determined, the region/partition pins are assigned. The challenge is to create pin
placements that satisfy any number of design criteria, but most importantly the timing requirements between
blocks for all corner/mode scenarios. Typically, pin assignments are based on wire length only, as determined
by Steiner-based estimations. Poor pin assignments can wreak havoc on inter-partition timing paths, and lead
to costly ECOs between the block level and chip level late in the design cycle.

INACCURATE TIMING AND POWER ESTIMATIONS

Getting accurate estimations of timing, power, and area as quickly as possible is the goal of the floorplanning/
prototyping stage. The timing analysis does not need to be sign-off accurate, but it should include as many
corner cases as is feasible, and account for manufacturing variability. For example, if the timing signoff
includes a dozen mode/corner combinations, the floorplanning timing estimations are needed for all the
timing scenarios, and not just worst case and best case.

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Advanced Floorplanning with Mentor Place and Route

Power estimations at this stage need to correlate with more detailed analysis later in the flow. Inaccurate
power estimates can allow errors in the power plans to derail block and top-level closure. Multi-Vdd designs
also introduce additional power meshes, so the floorplanner must be capable of creating and connecting
multiple power domains

LACK OF TOOL CAPACITY, FLEXIBLE USE MODELS, AND ECOS

Design data sets are becoming ever larger, and EDA tool capacity hasn’t been able to keep up. Capacity and
runtimes are now interfering with design schedules for SoCs that can have hundreds of RAMs, 200 million
gates, multiple modes, multiple corners, and many power islands. For the larger designs, floorplanning is
often the only opportunity to view the entire design in a flat (vs. hierarchical) representation. This is essential
to obtaining good early estimations of design constraints by being able to run global routing, extraction, and
analysis.

While it is tempting to believe that the block implementations will advance independently of one another, the
reality is that implementation requires at least some iterations and feedback loops at the chip-level, and there
will probably be interactions among blocks as well. When the blocks can only be represented with
abstractions at the top-level, optimizations are limited to top-level logic. This limitation usually occurs
because a complete full-chip flat representation exceeds the data capacity of most tools.

Changes based on block-level work, such as modifications to block placement, incremental re-assignment of
block pin locations, power routing, or block timing and power budgets, are usually difficult to incorporate at
the chip- level. Without flexibility in use models and a robust engineering change order (ECO) capability,
designers can be stuck with time-consuming and non-convergent iterations between levels of physical and
logical hierarchy. This is particularly frustrating when faced with frequent file transfers between different
point tools in the design flow

THE MENTOR PLACE AND ROUTE FLOORPLANNING SOLUTION

To complete floorplanning faster and with better quality, the Mentor place and route floorplanner includes
the following tool capabilities:

■■ Flexible IO pad placement strategies

■■ Automatic macro placement
■■ Automatic region shaping, partitioning, and timing-driven pin assignment
■■ Native multi-corner multi-mode (MCMM) timing and signal integrity analysis
■■ Full UPF support and robust power planning for multi-Vdd designs
■■ Fast and reliable chip assembly support
■■ Highest tool capacity, compact memory footprint, and an intuitive, easy to use GUI

FLEXIBLE, HIGH-QUALITY IO PAD PLACEMENT

The Mentor place and route floorplanner has very flexible use models for IO pad placement. The tools can
implement a design with or without a pad ring or pin placement file from the package designer. In the
absence of external IO pad constraints, users can perform quick full-chip, timing-driven global placement and
global routing, to get the best logic clustering and timing estimations to meet design metrics, then assign the
IO pads based on that. This is a quick way to get very fast feedback regarding the rout ability and timing of
the design. A congestion map helps identify hot spots that can be fixed through further ‘what-if’ analysis
loops.

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Advanced Floorplanning with Mentor Place and Route

The Mentor place and route system also supports initial IO pad placement, followed by quick iterations
between prototype macro placement and IO pad refinement. Refinement can be done through automatic,
iterative re-placements, or through manually specifying constraints through the intuitive graphical user
interface.

Whether the IOs are placed before or after the standard cells and macros, designers must be able to easily add
and edit IO constraints to configure the side and order for the pads, and the layer and pitch for the pins.
Mentor place and route floorplanner provides the IO Constraint Editor, shown in Figure 2, which displays IOs
graphically and allows the user to assign sides, orders, layers, and pitches for the IO pins. It can also infer, or
derive, constraints based on an existing IO pad (and partition pin) placement, providing a useful starting place
for further constraint editing.

Figure 2: The IO Constraints Editor facilitates pin constraint editing with cross-probing, robust filtering, and flylines. IO ports can
be automatically aligned, and the Mentor place and route floorplanner can infer constraints based on current placements.

As the floorplan, or even the block implementation, progresses and more detailed information is available,
designers often find that the pin assignments need adjustment. Rather than re-assigning all pins, Mentor
place and route floorplanner supports incremental pin assignment. Designers can specify which pins to
re-assign, while keeping the rest of the pins fixed.

After placing the IO signal pins, the tool will place the IO filler cells and power/ground pads. The IO
placements can then be written out in industry-standard formats for use by board, package, or top-level SoC
planning purposes. This link between board, package, and SoC becomes more important at 45 nm and below
because of tighter design constraints and more pad-limited designs.

AUTOMATIC MACRO PLACEMENT AND MACRO REFINEMENT

The Mentor place and route system offers a completely automated macro placement (AMP) technology for
both block level and hierarchical designs that delivers the best QoR in the shortest time. It offers tools for
design space exploration to make the right trade-offs to meet various design metrics like timing, area, and
congestion. AMP includes powerful what-if macro analysis capabilities for fine-tuning macro placement
results. The AMP flow significantly reduces the design time and eliminates weeks of manual ECO iterations.
The output of automatic macro placement is shown in Figure 3.

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Advanced Floorplanning with Mentor Place and Route

Figure 3: Automatic macro placement output.

The AMP technology offers the following features:

■■ Data flow graph-driven macro placement and legalization

■■ Design space exploration with customizable recipes for parallel exploration
■■ Powerful macro analysis and refinement
■■ Completely automated flow with minimal manual intervention

AUTOMATIC REGION SHAPING, PARTITIONING, AND PIN ASSIGNMENT

Regions constrain the physical placement of standard cells to particular areas. This is typically used to address
timing and routability concerns, such as grouping clock generation logic, defining hierarchical
implementation boundaries, and defining voltage domain boundaries. The Mentor place and route
floorplanner supports many different use models for region creation. Regions can be defined as hard or soft
constraints for placement only, or for optimization and CTS. Regions can be automatically created based on
the design’s logical hierarchy, or manually shaped, facilitated by colorized logic groupings. Regions can also
be manually moved, resized, reshaped, or split into smaller regions. Egresses (bumps) and ingresses (notches)
are created by adding or deleting rectangles from the existing regions.

As regions are hardened into partitions, the fast timing-driven prototype placement and global routing
predicts where routes will cross the partition boundaries, and assigns partition pins based on that. The
placement and routing engines support multi-mode, multi-corner constraints, so pin assignments are
optimized based on timing and wire length that will satisfy all mode/corner scenarios, as shown in Figure 4.

Figure 4: Optimal pin assignment to minimize feedthroughs and port punching.

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Advanced Floorplanning with Mentor Place and Route

The Mentor place and route system performs congestion and timing-aware pinning and feedthrough insertion
based on the unified Global Route congestion prediction. The tool performs congestion abstraction to
represent core congestion and accurate timing estimation for prioritization of feedthroughs and minimizing
port punch-throughs. The proprietary pinning and feedthrough insertion algorithm ensures minimal
feedthrough count, buffer count and wire length.

MULTI-MODE, MULTI-CORNER TIMING ANALYSIS AND OPTIMIZATION

The Mentor place and route system concurrently analyzes and optimizes for all design metrics across any
number of mode/corner scenarios. Timing information for every circuit node is stored in a data structure
called the timing graph, which is the fundamental component of any place-and-route software architecture.
The core innovation in MCMM is an extremely concise vector-based timing graph structure that
simultaneously captures timing information for an unlimited number of mode/corner combinations. Rather
than merging timing files or performing sequential timing analysis for multiple scenarios, the Mentor place
and route system creates multiple timing graphs, and then stores them as a single representation. This
enables all the timing scenarios to be accurately represented without added memory or runtime costs.

MCMM timing analysis performed during floorplaning produces better IO pad and block pin assignments and
generates more accurate timing estimations for paths that span blocks.

COMPLETE SUPPORT FOR MULTI-VDD DESIGNS

The Mentor place and route floorplanner fully supports Unified Power Format (UPF) directives. Power islands
are created in the same manner as any partition, and the tool automatically inserts and connects special cells
such as switches, level shifters, always-on buffers, and retention registers. Mentor place and route system has
a multi-Vdd browser that supports cross-probing with the layout window to facilitate analysis and debugging
of the design, as shown in Figure 5.

Figure 5: With the Multi-Voltage Browser, the power domains and the cells assigned to each domain can be easily navigated.
Items selected in the browser are highlighted in the chip view for cross-probing operation.

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Advanced Floorplanning with Mentor Place and Route

Regardless of the number of voltage domains, the floorplanner can create and connect all power routing at
the block or top level. Rings, stripes, and vias are automatically generated based on user configuration and
connected to follow pins. Users can manually choose which vias to use or let the tool determine the correct
vias. Users can also specify which kind of power connections to make: stripe-to-stripe, stripe-to-macro, and
stripe-to-cell. Mentor place and route system has the ability to create multiple power networks for multi-Vdd
designs.

INTEGRATED SUPPORT FOR TOP-LEVEL OPTIMIZATION, CHIP ASSEMBLY, AND ECOS

For hierarchical designs, the Mentor place and route system can maintain convergence between top and block
levels during optimization at any stage of the design flow. If working with abstraction models for the
partitions, some optimizations will require ECO iterations. One way the tool improves the ECO flow is to allow
users to mix different levels of hierarchy at the top-level. Users can choose to view some blocks flat, others as
black-box models, and still others as traditional interface logic models ILMs. This conserves capacity, runtime,
and resources.

For even more top-level flexibility, Mentor place and

route system generates ILMs that contain the physical
placement and routing information that is relevant to
top-level optimizations. This allows the tool to access
block-level resources when optimizing inter-block routes.
For example, to fix an excessively long route between
two blocks, the tool can make adjustments to the block’s
pin placements, iteratively re-routing the wires and using
different layers if needed (Figure 6). This top-level wire
straightening is automated and iterative, and the changes
made to top-and block level logic are completely
convergent.
Figure 6: Layer promotion is a technique used by the Mentor
place and route system to reduce resistance in top-level
Another option available in the Mentor place and route
routing.
system is to stretch capacity and save on runtime is to
selectively “turn off” some levels of logical hierarchy with regard to timing. That allows the tool to access the
relevant physical information, but not spend computational resources on extraction and timing of those
modules. Mentor place and route system is unique in the level of flexibility offered in both flat and
hierarchical flows. It also offers capabilities like SyncOpt, which automatically updates all occurrences of a
block when a change is made to any of its instances.

Many IC flows also call for some amount of automatic or manual detail routing and wire editing of critical nets.
For manual editing, the wire editor provides a robust and intuitive environment, supporting automatic
preferred-layer routing, via creation, and non-adjacent layer wire creation. Mentor place and route system also
provides real-time, interactive DRC, giving instant feedback for all objects being manipulated (Figure 7).

Figure 7: Manual wire editing with interactive DRC

checking gives instant feedback on common
design rule violations as wires are drawn or moved.

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CAPACITY, RUNTIME, EFFICIENCY

The Mentor place and route system has the data capacity to load and process designs with hundreds of
millions of instances to provide faster floorplanning turn-around-time. The fully multithreaded timing engine
reduces analysis time, and the easy-to-use GUI greatly improves the efficiency of macro placement, IO pin
constraints editing, wire editing, and power domain analysis. All engines within Mentor place and route
system operate on a common database, so no time or memory are wasted in file transfers. Mentor place and
route supports all the standard inputs such as LEF, DEF, and Verilog, as well as UPF for power specifications.

CONCLUSION
Floorplanning is the foundation of a quality IC implementation. The decisions made regarding IO pad
placement, macro placement, partitioning, pin assignment, and power planning ripple through the place-and-
route flow. Designers need solutions that can handle extremely large data sets, design variability and
complexity, in addition to enabling fast, high-quality floorplanning.

The Mentor place and route system has a complete floorplanning solution with a flexible tool infrastructure
and large capacity. It generates high-quality floorplans and accurate early estimations of design constraints
based on MCMM timing. Flexible support for mixed-level hierarchy throughout the flow keeps ECOs to a
minimum and maintains physical and logical convergences between top and block levels. Mentor place and
route system is a complete, tapeout-proven, netlist-to- GDSII solution for very large, advanced-node SoCs.

For the latest product information, call us or visit: w w w.m e n t o r.c o m

©2009 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and
may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies.
In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks
mentioned in this document are the trademarks of their respective owners.

MGC 10-16 TECH8810-w

Advanced Floorplanning with Mentor Place and Route

For the latest product information, call us or visit: w w w.m e n t o r.c o m

©2009 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and
may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies.
In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks
mentioned in this document are the trademarks of their respective owners.

MGC 10-16 TECH8810-w