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7th Power Electronics, Drive Systems & Technologies Conference (PEDSTC 2016)
16-18 Feb. 2016, Iran University of Science and Technology, Tehran, Iran
Abstract— In this paper, a new topology for asymmetrical voltage sources have different values. However, the number of
cascaded multilevel inverter is proposed. The proposed topology switching devices still remains high in these topologies.
consists of series connection of several basic units. Reduction of In this paper, first a new topology for basic unit for multilevel
number of power switches, driver circuits, IGBTs and dc voltage inverter is proposed which utilizes lower number of power
sources are some advantages of the proposed topology in
comparison with the conventional cascaded multilevel inverters.
switches and dc voltage sources. Then, series connection of the
In order to generate all output voltage levels, a new algorithm to basic units is proposed as a generalized multilevel inverter. It is
determine the magnitudes of dc voltage sources is proposed. aimed to increase the number of output voltage levels and
Finally, to verify the performance of the proposed inverter, the reduce the number of power switches, driver circuits and total
simulation results by using PSCAD/EMTDC software on a 33- cost of the inverter. In order to generate all positive and
level single-phase inverter are used. negative levels at the output, a new algorithm to determine the
magnitudes of dc voltage sources are proposed. The proposed
Keywords—Asymmetric multilevel inverters; cascaded multilevel inverter is compared with several conventional cascaded
inverter; Basic unit multilevel inverters to investigate its advantages. Finally, the
accuracy performance of the proposed inverter is reconfirmed
I. INTRODUCTION by using simulation results on 33-level proposed inverter.
Multilevel inverters due to many advantages such as high II. PROPOSED BASIC UNIT
quality output waveform, reducing lower order harmonics,
lower switching losses and better electromagnetic interference
In this paper, a new basic unit for asymmetrical cascaded
are used in different applications [1-4]. The conventional
multilevel inverter is proposed. The proposed basic unit for
topologies are divided into three main groups: the neutral point
cascaded multilevel inverter is shown in Fig. 1. As shown in
clamped (NPC) multilevel inverter, flying capacitor (FC)
this figure, the proposed basic unit consists of m dc voltage
multilevel inverter and cascaded H-bridge (CHB) multilevel
inverter [5-9]. Among the multilevel inverter topologies, the sources that their magnitudes can be different values. Each
cascaded multilevel inverters have attracted more attention basic unit consists of m + 5 power switches. The power
mainly because of simple structure and easily of extending to switches used in the basic unit inverter are unidirectional and
higher voltage levels. Cascaded multilevel inverters synthesize bidirectional types. The power switches S 1 , S 3 , S 4 , S 6 , S 7 ,
a desired voltage output based on a series connection of power …, and S m + 5 are unidirectional and two switches S 2 and S 5
cells. In recent years, researchers have presented many various are bidirectional. There are different circuit configurations for
topologies of multilevel inverters for different purposes [10- bidirectional power switches. In this paper, the common
15]. Most of the presented topologies try to reduce the number emitter structure with one gate driver for a switch is used.
of components. One of these topologies is the modular Each unidirectional power switch consists of an IGBT with an
multilevel inverter [16]. This topology is simpler than the anti-parallel diode that is able to conduct current in both
cascaded four-switch H-bridge-based inverter and has several direction and block voltage in one polarity. While, the
advantages [17]. However, the topology does not consider bidirectional power switch includes of two IGBTs with Two
reduction in the number of components. The multilevel inverter anti-parallel diodes that conducts current in both direction and
presented in [18] is based on symmetric topology and uses blocks voltage in two positive and negative polarities. In the
series/parallel connection of the dc voltage sources. This condition, each bidirectional power switch needs one driver
topology uses lower number of switches in comparison with circuit. In the proposed basic unit, if the power switches of S 1 ,
the symmetric CHB. The topologies presented in [13] and [14]
S 4 or S 2 , S 5 or S 3 , S 6 turned on simultaneously, the
consider reduction in the components. These topologies are
basically based on asymmetric topologies; hence, the used dc output voltage will be zero and if the power switches of S 2 ,
186
2(m1 + m2 + " + mn ) + 2n, for m = 1, 2 In the proposed inverter, the number of generated output levels
N driver = ® (9) is completely depended on the magnitudes of dc voltage
¯m1 + m2 + " + mn + 5n, for m > 2
sources. At the following, a new algorithm to determine the
n
magnitudes of dc voltage sources is proposed.
N source = ¦ mi = m1 + m2 + " + mn (10)
i =1
For the first basic unit, the values of dc voltage sources are
considered as follows:
In order to generate the maximum number of output levels for a
fixed number of components, it is necessary to consider the V1 = Vdc (18)
equal number of dc voltage sources in each basic unit. In other
word: V i ,1 = 2 (i − 1)V 1,1 i = 2,3,! , m 1 (19)
m1 = m 2 = " = m n = m (11) For the second basic unit, the values of dc voltage sources are
determined as follows:
The different output voltage levels can be determined by
combination of switching states of basic units. If proper values V1,2 = Vdc + 2 (Vo ,max1 ) = (4 m1 − 1) Vdc (20)
for the dc voltage sources are selected, then the output voltage
n
of the inverter can be obtained between ¦ (V 1, j + V m, j ) and V i ,2 = 2 (i − 1) V 1,2 i = 2,3,! , m 2 (21)
j =1
n
−¦ (V 1, j + V m, j ) . The values of the dc voltage sources in the third basic unit are
j =1
assumed as following:
Considering (11), the equations (7) to (10) can be rewritten as
follows: V1,3 = Vdc + 2 (Vo,max1 + Vo ,max 2 ) = (4 m1 − 1)(4 m 2 − 1) Vdc (22)
n
V o ,max = ¦ (2 m j − 1) V 1, j (26)
j =1
S1,1 S 2,1 S3,1 S1,2 S2,2 S3,2 S1,n S2,n S3,n
N level = (4m1 − 1) × (4m 2 − 1) ×" × (4m n − 1)
n
V1,1 V2,1 S V1,2 V2,2 S V1,n V2,n S (27)
= ∏ (4m j − 1)
7,1 7,2 7,n
S 4,1 S5,1 S6,1 S4,2 S5,2 S6,2 S4,n S5,n S6,n Recently, some new topologies with reduced number of
switches have been presented for multilevel inverters. In this
First Unit Second Unit n th Unit section, the proposed cascaded multilevel inverter is compared
Fig. 3. The proposed cascaded multilevel inverter.
187
with several conventional cascaded multilevel inverters. This V1 +
Sb,1,1
comparison is done from different points of view such as the S1 v T1 T3
number of IGBTs, power switches and dc voltage sources. In Sa,1,1 Sc,1,1 o,1
V1
this comparison, the proposed cascaded multilevel inverter − i load
based on new proposed algorithm is indicated by P1 . The CHB
vo + −
multilevel inverter with binary algorithm is indicated by R1 . v load
( R1 for V 1 = 2 j −1V dc ( j = 1, 2," , n ) ) [5]. The presented Vn
+
Sb ,1,n
cascaded multilevel inverter in [19] is considered by R 2 . ( R 2 T4 T2
Sn v o,n
j −1 Sa,1,n S
for V j = ( m + 1) Vdc j = 1, 2, " , n ). In addition, for the Vn c ,1,n
−
presented inverter in [13], [20] and [21] three different (a) (b)
algorithms have been considered that are indicated by R 3 , R 4
and R 5 , respectively, as follows:
vo S1′
V1,1
R 3 for V j = (m j −1 ) Vdc ( j = 1, 2, " , n) V1,1
+ S2′ +
S1,1 − vo′ +
j −1
R4 for V1, j = 0.5V2, j = V3, j = 2 Vdc ( j = 1, 2, " , n) V2,1 S4,1 S5,1
vo,1
S1 S1 Uint 1
S 2,1
V n ,1 =V n ,2 =V dc × (5 × 2m − 2 − 1) n −1 , S m −1 S m −1 Uint 2
V2,2
S2,2
S4,2 S5,2
vo,2 vo
+ vL −
V3,2 iL
V n ,3 = 2V dc × (5 × 2m − 2 − 1)n −1 , ! , V1 S m Vn Sm
S3,2
−
T2 T4
Vn ,i = Vdc (2i − 4 × 5)(5 × 2m − 2 − 1)n −1 ( i = 4,! , m) ) V1,n
+
S1, n
V2, n S4, n S5, n
Uint n vo, n
Fig.4 shows all of the above-mentioned topologies. Fig. 5 (a) S2, n
V3, n
compares the number of IGBTs of the proposed topology with S3,n
− −
the above-mentioned cascaded multilevel inverters. As it is (c) (d)
obvious from this figure, the proposed cascaded inverter needs
lower number of IGBTs than other presented inverters in the
references except the presented inverter by R5 . It is pointed out
that the bidirectional and unidirectional power switches are ′
S 1,2 ′
S 1,3 ′
S 1,4 ′
S 1,5
io
used in the proposed cascaded inverter. As mentioned before, V 1,1 ′ T 1,1 T 1,2
S 1,2 S 1,3 S 1,4 S 1,5
the number of IGBTs is as same as the number of power +
v o1
diodes. As a result, the proposed inverter also needs minimum V 1,2 V 1,3 V 1,4 V 1,5 −
′
T 1,1 ′
T 1,2
number of power diodes than other conventional cascaded S 1,1
vo
inverters. The number of power switches in the proposed ′
S 2,2 ′
S 2,3 ′
S 2,4 ′
S 2,5
cascaded inverter is compared with above-mentioned inverters. V 2,1 S 2,2 S 2,3 S 2,4 S 2,5 T 21 T 22
This comparison is shown in Fig. 5(b). As it is obvious from +
vo2
this figure, the proposed multilevel inverter needs lower V 2,2 V 2,3 V 2,5
′
T 21 ′
−
T 22
number of power switches in comparison with other presented S 2,1
188
30
R2,R3
voltage of the inverter which is shown in Fig. 7 (c). As this
R4 R5 P1
25
R1
figure shows, the inverter can generate all of the expected
20
voltage levels. Fig. 7(d) shows the output current waveform.
N IGB T Regarding the waveforms of output current and voltage, there
15
is a phase displacement between them. This is resulted from the
10 inductive characteristic of the load.
5
vo
0 +
−
0 20 40 N level 60 80 100
(a)
S1,1 S2,1 S3,1
25 R3
R 4 R1 R4 V1,1 V2,1 S
P1 7,1 v o1
20 R5 S1,2 S2,2
vo2
15 V3,1 S8,1 V1,2
N switch S5,1 S6,1 S3,2
S4,1 S4,2
10
14 R4 R2,R3 R5
-25
0
R1 P1 -50
108
N source6 0.0000 0.0100 0.0200 0.0300 0.0400
64 (a)
20 Vo2 [V]
110
0
0 20 40 N level 60 80 100 55
(c) 0
Fig. 5. (a) variation of N IGBT versus N level ; (b) variation N switch of -55
versus N level ; (c) variation N source of versus N level . -110
189
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