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ADAPTIVE FILTER IMPLEMENTATION USING

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 TechnoFocus – 2012, DJSCOE

ADAPTIVE FILTER IMPLEMENTATION

USING FPGA
Dhruvil Shah1, Ruchik Vora1, Jay Khandhar1, Mr.Ninad Mehendale2
1. Undergraduate Student, EXTC Department, DJSCOE, Vile Parle (W), Mumbai.
2. Assistant Professor, EXTC Department, DJSCOE, Vile Parle (W), Mumbai.
Email:dhruvil_shah@hotmail.com, ruchikdv@gmail.com, jaykhandhar@gmail.com, ndm243@gmail.com

Abstract:-Filtering data in real-time requires dedicated
hardware to meet demanding time requirements. If
the statistics of the signal are not known, then
adaptive filtering algorithms can be implemented to
estimate the signal statistics iteratively. Modern Field
Programmable Gate Arrays (FPGAs) include the
resources needed to design efficient filtering
structures. Furthermore, some manufacturers now
include complete microprocessors within the FPGA
fabric. This mix of hardware and embedded software
on a single chip is ideal for fast filter structures with
arithmetic intensive adaptive algorithms. This paper
aims to combine efficient filter structures with
optimized code to create a solution for various
adaptive filtering problems. Several different adaptive
algorithms have been coded in VHDL. The designs
are evaluated in terms of design time, filter
throughput, hardware resources and power
consumption. Adaptive filters learn the statistics of
their operating environment and continually adjust
their parameters accordingly. In practice, signals of
interest often become contaminated by noise or other
signals occupying the same band of frequency. When
the signal of interest and the noise reside in separate
frequency bands, conventional linear filters are able
to extract the desired signal. However, when there is
spectral overlap between the signal and noise, or the
signal or interfering signal’s statistics change with
time, fixed coefficient filters are inappropriate. In
these situations, adaptive algorithms are needed in
order to continuously update the filter coefficients
Because of their ability to perform well in unknown
environments and track statistical time-variations,
adaptive filters have been employed in a wide range of
fields. This paper will focus on one particular
application, namely noise cancellation, as it is the
most likely to require in an embedded VLSI
implementation.
Keywords:-FPGA, Adaptive Algorithm, Filter, Noise.
I. INTRODUCTION
Digital Signal Processing, which spans a wide variety of
application areas including speech and image processing,
communications, neural networks and so on, is becoming
133
increasingly important in our daily life. Digital signal
processing applications impose considerable constraints on
area, power dissipation, speed and cost, and thus the
design tools should be carefully chosen. The most
commonly used tools are: Application Specific Integrated
Circuits (ASIC), Digital Signal Processors (DSP) and
Field Programmable Gate Array (FPGA). DSP is well-
suited to extremely complex math-intensive tasks, but
cannot process high sampling rate applications due to its
serial architecture. ASIC can meet all the constraints of
DSP, however, it lacks flexibility and requires long design
cycle. FPGA can make up the disadvantages of ASIC and
DSP. With the flexibility, time-to-market, risk-mitigation
and lower system costs, FPGA has become the first choice
for many digital circuit designers.
II. Adaptive Filter
In practice, signals of interest often become contaminated
by noise or other signals occupying the same band of
frequency. When the signal of interest and the noise
reside in separate frequency bands, conventional linear
filters are able to extract the desired signal. However,
when there is spectral overlap between the signal and
noise, or the signal or interfering signal’s statistics change
with time, fixed coefficient filters are inappropriate.
Figure 1:
A narrowband interference N(f) in a wideband signal S(f).
This situation can occur frequently when there are
various modulation technologies operating in the same
range of frequencies. In fact, in mobile radio systems, co-
channel interference is often the limiting factor rather
than thermal or other noise sources. If the statistics of the
noise are not known beforehand, or they change over

time, the coefficients of the filter cannot be specified in
advance. In these situations, adaptive algorithms are
needed in order to continuously update the filter
coefficients.
II. FPGA ARCHITECTURE
An FPGA is an alternative type of Programmable Logic
Device (PLD). FPGAs have a more flexible, gate-array-
like structure with a hierarchical interconnect
arrangement. The fundamental part of the FPGA is the
look-up table (LUT), which acts as a function generator,
or can be alternatively be configured as ROM or RAM.
They also include fast carry logic to adjacent cells
making them suitable for arithmetic functions and further
DSP applications. Majority of FPGAs are SRAM-based
and can therefore be programmed as easily as standard
SRAM. Thus, FPGAs are volatile and need to be
programmed each time power is applied. This is normally
accomplished with another part of the circuit that reloads
the configuration bit stream, such as a PROM. The
configuration bit stream stored in the SRAM controls the
connections made and also the data to be stored in the
LUTs. The LUTs are essentially small memories that can
compute arbitrary logic functions. The configurable logic
blocks (CLBs) are the basic blocks of an FPGA and are
generally placed in an island-style arrangement. Each
logic block in the array is connected to routing resources
controlled by an interconnect switch matrix.
With this layout, a very large range of connections can be
made between resources. A disadvantage to this flexible
routing structure is that unlike the CPLD, signal paths are
not fixed beforehand, which can lead to unpredictable
timing. However, FPGAs have an increased logic
complexity and flexibility.
Figure 2: Basic Architecture of an FPGA
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TechnoFocus – 2012, DJSCOE
III. ADAPTIVE FILTER
1. Overview
Adaptive filters learn the statistics of their operating
environment and continually adjust their parameters
accordingly. The goal of any filter is to extract useful
information from noisy data. Whereas a normal fixed
filter is designed in advance with knowledge of the
statistics of both the signal and the unwanted noise, the
adaptive filter continuously adjusts to a changing
environment through the use of recursive algorithms.
This is useful when the statistics of the signals are not
known beforehand or if they change with time.
Figure 3: Block diagram for the adaptive filter problem
The discrete adaptive filter shown in the figure above
accepts an input u(n) and produces an output y(n) by a
convolution with the filter’s weights w(k). Desired
references signal d(n) is compared to the output to obtain
an estimation error e(n). This error signal is used to
incrementally adjust the filter’s weights for the next time
instant. Several algorithms exist for the weight
adjustment, such as the Least-Mean-Square (LMS) and
the Recursive Least-Squares (RLS) algorithms. The
choice of algorithm depends upon the needed
convergence time and the computational complexity
available, as the statistics of the operating environment.
2. Applications
Because of their ability to perform well in unknown
environments and track statistical time-variations,
adaptive filters have been employed in a wide range of
fields. However, there are essentially four basic classes of
applications for adaptive filters. There are: identification,
inverse modeling, prediction, and interference
cancellation, with the main difference between them
being the manner in which the desired response is
extracted. These are shown in figure 4 a, b, c and d,
respectively. This paper will focus on one particular
application, namely noise cancellation, as it is the most
likely to be required in an embedded VLSI
implementation. Handheld radios and satellite systems
that are contained on a single silicon chip require real-
time processing.
 TechnoFocus – 2012, DJSCOE

IV. LMS ALGORITHM

The Least Mean Square (LMS) algorithm is similar to the
method of the steepest descent in that it adapts the
weights by iteratively approaching the MSE minimum.
Widrow and Hoff invented this technique in 1960 for use
in training neural networks. The key is that instead of
calculating the gradient at every step, the LMS algorithm
uses a rough approximation to the gradient.
The LMS algorithm is a widely used algorithm for
adaptive filtering. The algorithm is described by the
following equations:
e(n) = d(n) – y(n)
wi(n+1) = wi(n) + 2ue(n)x(n-i);
In these equations, the tap inputs x(n), x(n-1),……,x(n-
M+1) form the elements of the reference signal x(n),
where M-1 is the number of delay elements. d(n) denotes
the primary input signal, e(n) denotes the error signal and
constitutes the overall system output. wi(n) denotes the
tap weight at the nth iteration. In equation (3), the tap
weights update in accordance with the estimation error.
And the scaling factor u is the step-size parameter u
stability and convergence speed of the LMS algorithm.
The LMS algorithm is convergent in the mean square if
and only if u satisfies the condition:
0<u<2 / tap input power
Where tap input power is:
∑E [|u (n −k)|^2]
K=0
The flow chart of the LMS algorithm is as shown
below:

Figure 4: Four Basic Classes of Adaptive Filtering Applications

3. Adaptive Algorithms
There are numerous methods for performing weight
update of an adaptive filter. There is Wiener filter which
is the optimum linear filter in the terms
of mean squared errorand several algorithms that attemp
t to approximate it, such as the method of steepest
descent. There is also Least-Mean-Square algorithm
developed by Widrow and Hoff originally used for
artificial neural networks. Finally, there are other
techniques such as the Recursive-Least-Squares
Figure 5: Flowchart of the LMS Algorithm
algorithm and the Kalman filter. The choice of the
algorithm is highly dependent on the signals of interest V. HARDWARE IMPLEMENTATION
and the operating environment, as well as the In this work, the ANC described in the previous section is
convergence time required and computation power implemented in the Xilinx Spartan-3E Starter Kit board
available. that provides a convenient development board for
embedded processing applications. The board contains a
Xilinx XC3S500E Spartan-3E FPGA with up to 232
User-I/O pins 320-pin FPGA package and over 10,000
135

logic cells. The Spartan-3E Starter Kit also provides the
MicroBlaze 32-bit embedded RISC processor and the
Xilinx Embedded Development Kit (EDK) [10]. With
those features, the Xilinx Spartan-3E Starter Kit is well
suited for hardware implementation of our ANC system.
The hardware implementation process is described using
the flowchart.
Figure 6: Flowchart of the FPGA Implementation Process
1. Hardware Architecture
The whole embedded system consists of a MicroBlaze
core [10], two Fast Simplex Link (FSL) bus systems, an
On-Chip Peripheral Bus (OPB), a Local Memory Bus
(LMB), an OPB peripheral (RS232 Controller), the on-
chip block RAM and the user core. A block diagram of
the architecture is shown in Fig.4.
Figure 7: Hardware Architecture
2. LMS Core Implementation
The LMS core is the central part of our hardware
architecture. We programmed the LMS core with VHDL
under the platform of Xilinx ISE 9.1i, and simulate it
with ModelSim 6.1b. Then we test the validity of the
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TechnoFocus – 2012, DJSCOE
LMS core by using System Generator 9.1.
The LMS core is divided into five blocks：
1. The Control block arranges the timing of the whole
system. It produces four enable signals: en_x, en_d,
en_coee, en_err, which enable the Delay Block, the
Weight Update Block and the Error Counting Block
separately.
2. The Delay Block receives the reference signal x_in and
the primary input signal d_in under control of the enable
signal en_x and en_d. And it produces the M tap delay
signal x_out.
3. The Multiply Accumulator (MAC) Block multiply the
M_tap reference signal x_out with the M_tap weight w
separately, and add them together, then we get yn.
4. The Error Counting Block subtract yn from dn and get
the error signal e_out, which is also the output of the
whole system. And it produces signal xemu as a feedback
by multiplying e_out, x_out and the scaling factor u.
5. The Weight Update Block updates the weight vector
w(n) to w(n+1) that will be used in the next iteration.
Figure 8: Block Diagram of the LMS Core
VI. EXPERIMENTAL RESULTS
1. Convergence Performance
The convergence performance of LMS algorithm applied
in hardware architecture is analyzed with respect better
convergence performance. to an 8-tap LMS adaptive
filter with desired signal of constant 0.5, and input signal
of 0.25. Since the convergence speed of LMS algorithm
has closed relationship with step-size u, three cases of
performance are compared with different step-sizes. The
following 3 curves plotted in the figure below show the
traces of error between the desired signal and the output
signal. The step-sizes of the curves from left to right are:
1/2, 1/4 and 1/8. From the cases, we can see that with the
increase of step-size, convergence speed rises, which is in
accord with the theory of LMS algorithm. Convergence
performance can also be affected by bit-truncation effect.

Figure 9: Convergence Behaviour of the LMS Algorithm for Three Step
Sizes.
2. Tracking Ability
Tracking ability is also an important property of LMS
algorithm. We use a LMS filter (8-tap, u = 1/4) with an
input signal shown in Fig.10, which is a sinusoidal signal
at 1/32 of the sampling frequency corrupted by sinusoidal
noise at 1/3.2 of the sampling frequency. The SNR of the
input signal is 6 dB. Fig.11 shows the tracking ability of
the LMS filter, the desired signal is plotted in blue dashed
line, and the red real line represents the result signal. We
can see that, after about 200 iterations, the result signal is
converged to the desired one.
Figure 10: Input Signal
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TechnoFocus – 2012, DJSCOE
Figure 11: Tracking Ability of the LMS Filter
3. Software Implementation
In order to show the advantage in speed of hardware
implementation, we use a software implementation to
compare with it. In this architecture, we use the
MicroBlaze embedded processor to run the whole system
and the LMS algorithm is written in C code. The pseudo
C code of the software implementation is shown.
There are four major steps of the software
implementation:
1). delay the input signal;
2).Multiply-accumulate to get the intermediate signal y;
3). Error calculation;
4). weight update.
We make a comparison between software and hardware
implementation measured with clock cycles in one
iteration, the profiling results of the four steps are shown
in table I for three different values of N.
Figure 12: Pseudo C Code of the Pure Software Implementation
 TechnoFocus – 2012, DJSCOE

CONCLUSION NINAD MEHENDALE

Asst. Professor, Electronics and
Telecommunication Dept. in Dwarkadas J.
In this paper the hardware design is presented to Sanghvi College of Engineering, Mumbai. He
implement the ANC system. The performance of the completed his Diploma in Industrial Electronics
LMS algorithm implemented by hardware is from V.P.M’s Polytechnic, his Engineering in
comprehensively analyzed in terms of convergence Electronics from Somaiya College of
Engineering,Vidyavihar and his M.Tech in
performance, truncation effect and tracking ability. The Embedded Systems from NMIMS university
experimental results ensure the feasibility of the high- Area of Interest: Embedded Systems, Neural Network.
speed FPGA architecture of the LMS algorithm. Also, a
software implementation is presented. A comparison
between the two architectures shows that hardware
implementation accelerates the LMS filtering process,
and the speed up over pure software implementation
increases with the filter tap. The ANC system is chosen to
validate the performance of FPGA in digital signal
processing application; FPGA implementation will be
more effective for more complex digital signal processing
systems.

REFERENCES
[1] B. Widrow, J. R. Glover, J. M. McCool, J. Kuntz, C. S. Williams, R.
H. Hearn, J. R. Ziegler, E. Dong and R. C. Goodling, “Adaptive noise
cancelling: Principles and applications”, Proc. IEEE, vol. 63, Dec. 1975,
pp. 1692-1716.
[2] S. Haykin, Adaptive Filter Theory, Prentice-Hall, third edition,
2002.
[3] M. D. Meyer and D. P. Agrawal, “A high sampling rate delayed
LMS filter architecture,” IEEE Trans., Circuits Syst. II, Analog Digit.
Signal Process., vol. 40, Nov. 1993, pp. 727–729
[4] www.xilinx.com

BIO DATA OF AUTHOR(S)

DHRUVIL SHAH
Student, Third Year, Electronics and
Telecommunication Dept. of Dwarkadas J.
Sanghvi College of Engineering, Mumbai.
Area of interest: Embedded Systems, Digital
Signal Processing and Data Compression.

JAY KHANDHAR
Student, Third Year, Electronics and
Telecommunication Dept. of Dwarkadas J.
Sanghvi College of Engineering, Mumbai.
Area of interest: Embedded Systems and Data
Compression.

RUCHIK VORA
Student, Third Year, Electronics and
Telecommunication Dept. of Dwarkadas J.
Sanghvi College of Engineering, Mumbai.
Area of interest: Embedded systems and
Signal Processing.

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