Well proximity Effect;

once silicon features shrunk below 100nm into the world of nanotechnology, previously negligible physical phenomena now play a big role.
One of those annoying phenomena is the well proximity effect (WPE).

To explain how WPE affects integrated circuit designers, we have to first talk just a little bit on how PMOS transistors are created. The figure
above shows the standard textbook cross-section of a silicon wafer with an NMOS and PMOS transistor side-by-side. The silicon wafer, also
called the substrate, is a crystalline structure where each silicon atom shares four covalent bonds with neighbouring silicon atoms. However,
it is standard in the IC industry to lightly dope the silicon wafer substrate with boron. If you remember your high school chemistry, silicon
has four valence electrons and boron has only three. When boron is introduced into the silicon crystal structure, the four covalent bonds it
shares with neighbouring silicon atoms is short an electron. Hence, this type of material is called p-type silicon, where p stands for ‘positive’
(absence of electrons). The inverse to doping silicon with boron is doping with phosphorus, which has five valence electrons. When
phosphorus bonds with four neighbouring silicon atoms, an extra electron is left over, hence creating n-type silicon; n stands for ‘negative’
(excess of electrons).

NMOS transistors can be built right into the p-type silicon substrate. PMOS transistors, on the other hand, need to be built into n-type
silicon. By bombarding a small area at the top of the silicon wafer with phosphorus, a tub of n-type silicon can be created inside of the p-
substrate. As the diagram shows, this is typically called the n-tub (or n-well). With the creation of the n-well, PMOS transistors can now be
made.

During the fabrication process of ICs, one of the first steps is to create n-wells all throughout the wafer where PMOS transistors will live.
First, silicon-oxide (SiO2) is grown on top of the silicon wafer.

An opening is then made in the SiO2 where the location of the n-well is needed.
Phosphorus bombardment then takes place …

… and the n-well is created.

However, the doping concentration is not uniform throughout the n-well. While the phosphorus bombardment is ideally perpendicular to the
plane of the silicon surface, in reality, there is some angle to some of the particles. This means that phosphorus dopants get reflected from the
wall of the SiO2 barrier, creating a higher concentration of dopants at the edges.

When transistors were larger in the 130nm node, the minimum allowable distance from the PMOS to the edge of the well was large enough so
that transistors were always kept a safe distance away from the higher concentration of the well edge. However, in the 90nm node,
dimensions got so small that the allowable distance between the well edge and the PMOS transistor is now encroaching into the area of
higher dopant concentrations. This means two identically built PMOS transistors side-by-side will have different characteristics due to their
differing distances from the n-well edge. This creates problems for circuits that rely on good matching between close-by transistors, such as
current mirrors.
The first time I encountered this was when I designed a low-dropout (LDO) voltage regulator in 90nm. It was used as the voltage supply for
the rest of my circuitry. At that time, WPE was still a relatively new phenomenon and the transistor models did not take that into account. It
wasn’t until when we were very close to tape-out did our modeling team release WPE-enhanced models. However, we had to explicitly turn
on this new feature for every single transistor individually in our design if we wanted to see the effects of WPE in our simulations.
Unfortunately, for a variety of reasons, some important current mirror transistors inside the LDO did not have WPE turned on. When we got
the chip back, the output voltage of one LDO was consistently off by 10% while another one nearby of identical design but slightly different n-
well arrangement did not exhibit this behaviour. Another expensive lesson. Now that we’re in 28nm, things have not gotten easier.

Nanoscale side-effects, such as electromigration and WPE, typically only affect analog circuit designers. However, in my next installment
on A Matter of Scale, I’ll discuss how digital designers are now starting to feel the pain of scaling as well.

Overcome:

WPE is combated through brute force. Waste area and move sensitive devices away from the edge of the n-well. Else, make sure matching
transistors are the same distance from the same edge of the well.

High energy ion implants to form the well. Scattering from the edge of the photoresist mask, and
embedding in the silicon surface (near well edge). Transistors close to the well edge will
therefore have different properties. This is known as the well proximity effect (WPE). Important
for matching.
During N-well implantion process, atoms can scatter laterally from the edge of the photoresist mask and become embedded in the silicon
surface in the vicinity of the well edge. This will change channel dopping hence the threshold voltage.

the depletion region depends on channel doping.. so threshold voltage is more dominantly
depends on doping concentration..

But threshold voltage is a function of depletion region.

Could you please explain how depletion region is going to increase so that threshold voltage variation takes place.?

Because the doping level is the determinant of a mos's threshold voltage.. At the time of
fabrication MOS is having native threshold voltage... But we use doping to make that
voltage according to our specification and requirement

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The effect of the well-edge proximity to theMOSFET gates was
first reported in [4] and originates from the lateral scattering
of ion implantations at the photoresist edge when forming
MOSFET wells, which in turn causes a change in the MOSFET
threshold voltage. Fig. 1 schematically shows the reason for the
well-edge proximity effect on MOSFET devices from a crosssectional
viewpoint. The high-energy ions scattered at the well
photoresist edge introduce extra dopant atoms in the silicon
near the well edge. As the MOSFET gate approaches the well
edge, the dopant concentration of the MOSFET core area will
increase, therefore causing a comparative increase in threshold
voltage. The effect becomes of increasing importance as CMOS
devices continue to shrink further.
Origin of well-edge proximity effect. High-energy dopant ions scatter
at the well photoresist edge during well ion implantation, and the scattered ions
are implanted in the MOSFET channel before the gate is formed. SC denotes
the distance of the well photoresist edge to the MOSFET gate edge.

Origin of well-edge proximity effect. High-energy dopant ions scatter

at the well photoresist edge during well ion implantation, and the scattered ions
are implanted in the MOSFET channel before the gate is formed. SC denotes
the distance of the well photoresist edge to the MOSFET gate edge.