IFRSA’s International Journal Of Computing|Vol2|issue 4|Oct 2012 830

International journal of Computing

Journal homepage: www.ifrsa.org

A Comparative Study and Mathematical Analysis of Total

Harmonic Distortion in Multilevel Inverter Topologies in
Induction Motor and A Proposed Level for Optimum
Operation
1 Kazi Rizwanul Huq, 2 Kazi Samira ShamsiHuq, 3Imrul Ahsan 1
Eastern University Dhaka,
2
International University of Business, Agriculture & Technology Dhaka ,
3
Eastern Refinery,Chittagong.
ABSTRACT
This paper presents detail mathematical analysis and simulation of Total Harmonic distortion with the
variation of the level of inverter. MATLAB SIMULINK model is implanted for obtaining results. Though
increased level of operation results in smoother operation and less harmonic distortion but there is a limit
on increasing the number indefinitely. It has been found that the there is an optimum level for smoother
operation. This paper proposes an optimum level of multilevel inverter for best operation. Keywords: Total
Harmonic Distortion, Multilevel Inverter, Selective Harmonic Elimination
1. INTRODUCTION
It has been found that as the level of inverter increases in an inverter fed induction motor drive, the
amount of total harmonic distortion decreases significantly. But with the increase of the level the
complexity in circuit fabrication and the variation in the different parts of dc bus voltage and the losses
associated become significant. Also the number of achievable levels is limited by voltage unbalance
problems. So this paper is analyzing the relation of the total harmonic distortion with the level of inverter
and proposing the optimum level for smooth operation and low level of Total Harmonic Distortion. 1.1
Advantages of Multilevel? Present day drive types are the induction motor drives with voltage source
inverters. Also the voltage waveforms of traditional two level inverter fed Induction motor shows that the
voltage across the motor contains not only the required “fundamental” sinusoidal components, but also
pulses of voltage i.e. “ripple” voltage. Moreover the voltage waveforms produced by the inverter has sharp
edges. The rate of change of voltage with respect to time i.e. dv/dt is very
high at these edges, of the order of 500–5000 V/μs. Although high voltage ratings of the power
semiconductor devices are available, it is inadvisable to retain the 2-level configuration for higher voltage
motors. This is because high voltage pulses will be applied to the motor causing dv/dt stresses. Today,
medium voltage induction motors rated at the MW level are generally controlled using three level
inverters. The 3-Level inverter, on the other hand, allows the motor voltage to go up in steps. This
reduces the dv/dt stress for the same DC bus voltage V
dc
 . Inverters of higher number of levels such as 5 and 7 levels can also be
constructed. However, the circuit assembly becomes very complex and issues such as keeping all the
sections of the dc bus voltage equal have to be addressed. The general structure of the multilevel
converter is to synthesize a sinusoidal voltage from several levels of voltages. As the number of levels
increases, the synthesized output waveform adds more steps, producing a staircase wave which
approaches the sinusoidal wave with minimum harmonic distortion. [1]
2. SOURCES OF HARMONICS
Multilevel inverter divide main dc supply voltages into several small sources or levels which are used to
synthesize an ac voltage into staircase or stepped, approximation of the desired sinusoidal waveform. A
waveform generated with five dc-sources each with a one-volt magnitude approximates the desired
sinusoid, as shown in figure 1-1. The five dc sources (five level or five steps) produced a peak-to-peak
voltage of 10 Volts using 11 discrete levels. Thus multilevel inverter can yield operating characteristics
such as high voltages, high power levels and high efficiency without the use of transformers [2]. The
multilevel inverter combines individual dc sources at specified times to yield a sinusoidal resemblance.
The
Kazi R Huq, Kazi S S Huq, I Ahsan | A Comparative Study and Mathematical Analysis of Total Harmonic
 Distortion in Multilevel Inverter Topologies in Induction Motor and A Proposed Level for Optimum
Operation more the sinusoid deviates from ideal wave shape the more is the harmonic distortion. By
using more steps to synthesize the sinusoidal waveform, the waveform approaches desired sinusoid and
the total harmonic distortion approaches zero.
The number of output voltage levels in a cascaded multi-level inverter is 2S+1, where S is the number of
dc sources. An example phase voltage waveform for an eleven-level cascaded multi-level inverter with
five SDCSs (S=5) and five full bridges is shown in Fig. 2. The output voltage is given by V
an
=v1+v2+v3+v4+v5. With a large of levels and an appropriate switching
algorithm, the multi-level inverter results in an output voltage that is almost sinusoidal. [2]
3. MATHEMATICAL ANALYSIS OF TOTAL
HARMONIC DISTORTION:
3.1. Harmonic Elimination in Multi-Level Inverter The output voltage V (t) of the multi-level inverter can be
expressed in Fourier series as
IFRSA’s International Journal Of Computing|Vol2|issue 4|Oct 2012 831
........... (1)
Due to quarter wave symmetry of the output voltage the even harmonics are absent (
= 0) and only odd harmonics are present. The amplitude of the nth
harmonic a
n
is expressed only with the first quadrant switching angle α
1
.
а
n
, α2, α
3.........
α
m
=
................. (2)
0≤α
1
<α
2
< ... < α
5
≤ π/2............. (3)
For any odd harmonics can be expressed up to kth term, where m is the number of variable
corresponding to switching angle α
1

of the first quadrant. For a given fundamental peak voltage V1, it is required
to determine the S switching angles such that the selection of one angle is used to determine V1 and
remaining (S-1) angles are used to eliminate the same number of harmonics (generally lower order
harmonics), and also all switching angles should be in the range 0 ≤ α
1
through α
m
<α
2
< ... < α
5
≤ π/2. In three-phase power system, tripled harmonics are canceled out
automatically in line-to-line voltages as a result only
non-tripled odd harmonics are present in line-to-line voltages. [3], [4]. For an 11-level cascade inverter,
there are five bridges per phase i.e. S = 5 or five degrees of freedom are available; one degree of
freedom is used to control the magnitude of the fundamental output voltage and the remaining four
degrees of freedom are generally used to eliminate 5th, 7th, 11th and 13th order harmonic components
as they dominate the total harmonic distortion [5]. The modulation index, m is defined as the ratio of the
fundamental output voltage to the maximum obtainable voltage (maximum voltage is obtained when all
switching angles are zero). From (2), the relation between m and switching angles is given as: cos (α
1
) + cos (α
2
) +......+ cos (α
5
) = 5m ............ (4) Similarly from (2), expressions for 5th , 7th, 11th and 13th harmonic components
(scaled values) are given as: cos cos (5α (7α
1
1
) ) +cos +cos (5α (7α
2
2
) ) +......+cos +......+cos (5α (7α
5
5
))==hh
5
7 cos (11α
1
) +cos (11α
2
) +...+cos (11α
5
)=h
11 cos (13α
1
) +cos (13α
2
) +...+cos (13α
5
)=h
13 ............ (5)
Figure-2: output wave and the switching angles Equations (4) and (5) in combined form are known as
SHE (Selective Harmonic Elimination) equations in terms of five unknowns α
1
,α
2
,α
3
,α
4
and α
5
; provided that h
5
,h
7
,h
11
,h
13
 are identically zero. For the given value of m (from 0 to1), it is required to get complete
and all possible solutions for the switching angle (0 to π/2) when the solutions exist, with minimum
computational burden and complexity. Following objective function is formulated to solve SHE equations
using optimization technique: Φ(α
1
,α
2
,α
3
,α
4
,α
5
)=
Now, (4) is to be minimized subject to equality constraints given by (2) and 0 ≤ α1 < α2 < ... < α5 ≤
Kazi R Huq, Kazi S S Huq, I Ahsan | A Comparative Study and Mathematical Analysis of Total
Harmonic Distortion in Multilevel Inverter Topologies in Induction Motor and A Proposed Level
for Optimum Operation π/2. Feasible solutions exist only where objective function (4) is
identically zero. 3.2. Relation between Total Harmonics Distortion (THD) and level of inverter:
Total Harmonic Distortion is a measure of harmonic distortion. Mathematically,
THD =
As the nth harmonic component goes low, THD also goes low. For multilevel inverter the harmonic if S =
number of levels than the one level is used to contribute to the magnitude of the fundamental voltage and
the other (S-1) levels are used for harmonic elimination. So as the number of levels(S) increases the
order of nth harmonic decreases and consequently THD also decreases. To put it in other terms, the
output waveform approximates pure sinusoidal waveform more accurately.
4. COMPARATIVE ANALYSIS AND
SIMULATION RESULTS:
LEVEL
MODULATION INDEX
IFRSA’s International Journal Of Computing|Vol2|issue 4|Oct 2012 832
(%) THD 3 0.9 10.98 5 0.9 7.02 7 0.9 3.20
Figure 1: Level-3 Output Wave and THD
Figure 2: Level-5 Output Wave and THD
Figure 3: Level-7 Output Wave and THD
5. OPTIMUM LEVEL OF OPERATION
As we see the level of inverter plays a vital rule in the reduction of THD in the output voltage waveform.
But the use of multilevel inverter has following drawbacks- 1. Costs increase 2. Inverter reliability
decrease 3. Circuit complexity increase 4. Affects many sizing factors and control techniques. Therefore
the selection of optimum level of multilevel inverter is crucial. Trade-offs in specifying the number of levels
that the power conditioner will need and the advantages and complexity of having multiple voltage levels
available
Kazi R Huq, Kazi S S Huq, I Ahsan | A Comparative Study and Mathematical Analysis of Total
Harmonic Distortion in Multilevel Inverter Topologies in Induction Motor and A Proposed Level
for Optimum Operation are the primary differences that set a multilevel filter apart from a single
level filter. As a starting point, known is the nominal RMS voltage rating, V
nom,
IFRSA’s International Journal Of Computing|Vol2|issue 4|Oct 2012 833 In this paper a comparative study
of different level Multilevel inverter is studied and finally an optimum level of operation is proposed. The
simulation of various level of inverter is carried out in MATLAB Simulink. It is to be noted that among
various multilevel inverter topology the Cascaded H-Bridge (CHB) is most efficient, uses fewer
components as compared other multilevel topology and is a low loss topology and hence widely used
nowadays. The use of multilevel inverter greatly reduces the filter cost and complexity and ensures
smooth operation and high power quality.
REFERENCES
[1] Prathiba T, Renuga P, 2012: ‘A comparative study of Total Harmonic Distortion in Multi-level inverter
topologies’ Journal of Information Engineering and Applications, ISSN 22245782 (print) ISSN 22250506
(online) vol. 2, No.3. [2] Aghdam M, S. Fathi H and Gharehpetian G, ‘Harmonic Optimization Techniques
in Multi- Level Voltage-Source Harmonic Optimization Techniques in Multi-Level Voltage-Source’, JPE
8-2-8. [3] Peng F. Z, McKeever J. W, and Adams D. J, 1997: ‘Cascade Multilevel Inverters for Utility
Applications’, IECON Proceedings (Industrial Electronics Conference), vol. 2, pp.437-442. [4] Tolbert L.
M, Peng F. Z, and Abetler T. G, ‘Multilevel converters for large electric drives’, IEEE Transactions on
Industry Applications, vol. 35, no. 1, pp. 36-44. [5] Jagdish Kumar, Biswarup Das, and Pramod Agarwal,
May 2009: ‘Harmonic Reduction Technique for a Cascade Multilevel Inverter’, International Journal of
Recent Trends in Engineering, Vol 1, No. 3.
.
of the electrical system to which the multilevel inverter will be connected. The dc link voltage
must be at least as high as the amplitude of the nominal line-neutral voltage at the point of connection, or
The √2 parallel ⋅V
nom
.
inverter must be able to inject currents by imposing a voltage across the parallel inductors, L
PI
, that is the difference between the load voltage, V
L
and parallel inverter output voltage V
PI
. The most difficult time to impose a voltage across the inductors is when
the load voltage waveform is at its maximum or minimum. Simulation results have shown that the
amplitude of the desired load voltage V
nom
should not be more than 70 percent of the overall dc link voltage
for the parallel inverter to have sufficient margin to inject appropriate compensation currents. Without this
margin, complete compensation of reactive currents may not be possible. This margin can be
incorporated into a design factor for the inverter. Because the dc link voltage and the voltage at the
connection point can both vary, the design factor used in the rating selection process incorporates these
elements as well as the small voltage drops that occur in the inverters during active device conduction.
The product of the number of the active devices in series (m-1) and the voltage rating of the devices V
dev must then be such that The V
device minimum rating.
(m-1) number ≥ √V
nom of levels . D
design and factor
the voltage rating of the active devices (IGBTs, GTOs, power
MOSFETs, etc.) are inversely related to each other. More levels in the inverter will lower the required
voltage device rating of individual devices; or looking at it another way, a higher voltage rating of the
devices will enable a fewer minimum number of levels to be used.
6. CONCLUSIONS