University of Waterloo

Department of Electrical and Computer Engineering

SE 141
Digital Circuits and Systems
Winter 2004

Midterm Examination Solutions

Instructor(s): W. D. Bishop
Date: Wednesday, February 25, 2004, 7:00 p.m.
Duration: 90 minutes
Type: R—“Closed Book.”

Instructions:

1. No aids permitted. No calculators of any type permitted.

2. There are 5 questions, most with multiple parts.
3. The exam period lasts 90 minutes and there are 100 marks. Some marks are easier
to earn than others. Read the paper carefully and use your time wisely.
4. Print your name in the space provided below and at the top of each page.
5. Write your answers directly on the question sheets. You may use either pen or
pencil to answer questions. Answers that are too light to read or smudged will be
assigned a grade of zero.
6. If you take the examination apart to work on the sheets separately, please call a
proctor over 5 minutes before the end of the exam to staple the pages.
7. You may use the backs of pages for rough work. If you must put solutions on the
backs of pages, be sure they are neat, and clearly indicate where to find them.
8. After reading and understanding the instructions, sign your name in the space
provided below.

Name ID Number Signature

For Examiner Use Only

Question Mark Maximum Mark
1 20
2 20
3 20
4 20
5 20
Total 100

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SE 141, Winter 2004 Midterm Exam Solutions

Question 1. Number Systems [20 marks total]

Part A) Number System Conversions [8 marks]

Fill in the table below by converting (84)10 to the number system representations listed
in the table. Show your calculations in the space below the table.

Number System Value

Base-10: Decimal (84)10

Base-2: Binary (0101 0100)2

Base-6 (220)6

Base-8: Octal (124)8

Base-16: Hexadecimal (54)16

Part B) Fractional Conversions [4 marks]

In the space below, convert the real number (24.375)10 to its equivalent unsigned binary
representation. Show your work.

(24.375)10 = (1 1000.011)2

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SE 141, Winter 2004 Midterm Exam Solutions

Part C) 2’s Complement Number Representations [4 marks]

What is the largest positive decimal number that can be represented by an 8 bit, signed
2’s complement binary number?

(0111 1111)2 = (127)10

What is the largest negative decimal number that can be represented by an 8 bit, signed
2’s complement binary number?

(1000 0000)2 = (−128)10

Part D) Number System Analysis [4 marks]

Given the following equation:

(24)X + (17)X = (40)X

Determine the Base-X that permits the equation to be true. Show your work.

Given the X is the base, the equation can be rewritten as follows:

2 × X1 + 4 × X0 + 1 × X1 + 7 × X0 = 4 × X1 + 0 × X0
2X + 4 + X + 7 = 4X
X = 11

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SE 141, Winter 2004 Midterm Exam Solutions

Question 2. Boolean Algebra [20 marks total]

Part A) Theorems of Boolean Algebra [8 marks]

Complete the theorems of Boolean algebra provided in the table below using two-valued
Boolean algebra. You need not show your work.

Theorem Algebraic Expression

1(a) Closure x+x= x

1(b) Closure x·x= x

2(a) Identity x+1= 1

2(b) Identity x·0= 0

Part B) Canonical Form [5 marks]

Shown below is a truth table for a Boolean function F .

A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Given the truth table, express the Boolean function F in canonical form using a sum of
products. You may use either literal terms or minterms in your expression.

Literal Terms:
F = A0 B 0 C + AB 0 C 0 + AB 0 C + ABC 0 + ABC
Minterms:

F = m1 + m4 + m5 + m6 + m7

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SE 141, Winter 2004 Midterm Exam Solutions

Part C) Canonical Form Conversion [3 marks]

Shown below is a convenient notation for a Boolean function F as a sum of products.

P
F (A, B, C) = (1, 4, 5, 6, 7)

Express the Boolean function F as a product of sums in a convenient notation.

Q
F (A, B, C) = (0, 2, 3)

Part D) DeMorgan’s Theorem [4 marks]

Apply DeMorgan’s Theorem to the following Boolean function G to convert it to an

expression of G0 as a product of sums. Do not simplify the Boolean function for G0 .

G = AB 0 C 0 + A0 BC 0 + A0 B 0 C + ABC

G0 = (A0 + B + C)(A + B 0 + C)(A + B + C 0 )(A0 + B 0 + C 0 )

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SE 141, Winter 2004 Midterm Exam Solutions

Question 3. Gate-Level Minimization [20 marks total]

Part A) Circuit Diagrams [12 marks]

The circuit diagram shown below produces a single output signal, H.

A
B
C'
H
A
B'
C

Derive an expression for the output signal H. Do not attempt to simplify the expression.

H = (ABC 0 )(A + B 0 + C)

Redraw the circuit diagram using only NAND gates. You may assume that you can use
any of combination of the literals (A, B, C, A0 , B 0 , and C 0 ) as inputs to your modified
circuit. However, the output must still be H.

HINT: An unsimplified solution can be achieved using 5 NAND gates.

A
B
C'
H
A'
B
C'

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SE 141, Winter 2004 Midterm Exam Solutions

Part B) Karnaugh Maps [8 marks]

The following truth table describes a Boolean function I.

A B C D I
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Use a Karnaugh Map to perform gate-level minimization on the Boolean function I.

Remember to label the axes of the Karnaugh Map. State the minimized Boolean function
I in standard form below the Karnaugh Map.

CD
00 01 11 10
AB

00 0 1 0 0

01 1 1 1 1

11 1 1 1 1

10 1 0 0 0

I = B + AC 0 D0 + A0 C 0 D

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SE 141, Winter 2004 Midterm Exam Solutions

Question 4. Combinational Logic [20 marks total]

Part A) Full Adder [8 marks]

Fill in the truth table below for a full adder circuit. si represents the sum and ci represents
the carry.

xi yi zi si ci

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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SE 141, Winter 2004 Midterm Exam Solutions

Part B) Full Adder Implementation [8 marks]

Using a 3 × 8 decoder and any other necessary gates you feel are necessary, construct a
full adder.

0
xi 2
2
1
si
2
1 3
yi 2 4
5
0
6
zi 2 7 ci
3x8
Decoder

Part C) Time Multiplexing Wires [4 marks]

Describe in a few sentences two different ways to time multiplex (i.e., share over time)
the use of a wire.

Multiplexers and tristate bus drivers can be used to time multiplex the use of a wire.
Multiplexers connect 1 of n input signals to a wire. Tristate bus drivers perform a similar
function in a distributed fashion. Each tristate bus driver determines if its input signal is
enabled.

Describe in a few sentences one situation when you might wish to time multiplex the use
of a wire?

The time multiplexing of a wire allows multiple output devices (drivers) to connect to an
input of another device. This helps to reduce the number of wires and input pins in a
system. This approach is most often used when there are several devices that need to
drive a single device via a bus. For example, PCI cards time multiplex data and address
signals that attach to a PCI bus controller.

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SE 141, Winter 2004 Midterm Exam Solutions

Question 5. Synchronous Sequential Logic [20 marks to-

tal]

Part A) Definitions [8 marks]

Define the term trigger and clearly explain why triggers are an important concept for
synchronous sequential logic.

A trigger is an event that causes something to happen. In the context of synchronous

sequential logic, a trigger causes a storage element to store data. Triggers may be either
the presence of a level or the detection of an edge in a signal. Triggers and storage
elements permit the development of sequential logic that saves state based on a clock.
Without triggers, sequential logic would not be possible.

Define the terms latch and flip-flop. In your definition, clearly explain how the terms are
different and give a few examples of each type of device.

A latch is a level-triggered 1-bit storage element. A latch continously updates its output
when a specific level is asserted. Examples of latches include the SR latch and the D
latch.

A flip-flop is an edge-triggered 1-bit storage element. A flip-flop captures an input signal

when a signal transition occurs on a control input (e.g., clock signal). Examples of
flip-flops include the JK flip-flop, D flip-flop, and T flip-flop.

Part B) SR Latch [4 marks]

The SR latch can be used as the basic building block for all latches and flip-flops. In the
space below, draw a positive-logic SR latch.

R
Q

Q'
S

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SE 141, Winter 2004 Midterm Exam Solutions

Part C) Characteristic Tables [8 marks]

Fill in the characteristic tables below for the JK flip-flop, the D flip-flop, and the T
flip-flop.

J K Q(t + 1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q0 (t)

D Q(t + 1)

0 0

1 1

T Q(t + 1)

0 Q(t)

1 Q0 (t)

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SE 141, Winter 2004 Midterm Exam Solutions

[100 marks grand total]

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