Physics of the ferroelectric nonvolatile memory field effect transistor

S. L. Miller and P. J. McWhorter

Citation: Journal of Applied Physics 72, 5999 (1992); doi: 10.1063/1.351910

View online: http://dx.doi.org/10.1063/1.351910
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Published by the American Institute of Physics

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Physics of the ferroelectric nonvolatile memory field effect transistor
S. L. Miller and P. J. McWhorter
Sandia National Laboratories, Albuquerque, New Mexico 87185
(Received 29 June 1992; accepted for publication 9 September 1992)
The operation of the ferroelectric nonvolatile memory field effect transistor is theoretically
examined extensively for the first time. The ferroelectric transistor device properties are derived
by combining the silicon charge-sheet model of metal-oxide-semiconductor field-effect transistor
device operation with Maxwell’s first equation which describes the properties of the ferroelectric
film. The model we present describes ferroelectric transistor 1-V and C-V behavior when
time-dependent voltages are applied which result in hysteresis due to ferroelectric switching. The
theoretical results provide unique insight into the effects of geometrical and material parameters
on the electrical properties of the transistor. These parameters include the ferroelectric
spontaneous and remanent polarization, the coercive field, and dielectric layer thicknesses. We
have found that the conventional concept of threshold voltage is no longer useful, and that
increasing the spontaneous polarization has only a minor impact on memory operation due to
reverse dipole switching of the ferroelectric layer. The application of the model to optimize
design and fabrication parameters is illustrated with a virtual prototyping example. The model
is also used to develop a practical testing methodology for this unique device.

I. INTRODUCTION material parameters can significantly accelerate technology

The hysteresis in the polarization of ferroelectric ma-
terials makes possible their use as electrically switchable
nonvolatile data storage elements.lb5 The more commonly
implemented ferroelectric data storage element is a capac-
itor consisting of a thin ferroelectric film sandwiched be-
tween two conductive electrodes.677 The direction of the
ferroelectric polarization vector is set by a voltage pulse to
the capacitor. The stored bit is read by applying another
voltage pulse and determining whether or not the polariza-
tion switched direction. This method of nonvolatile mem-
ory implementation suffers from the fact that data are de-
stroyed during the reading process. Consequently the bit
must be reprogrammed after each read, resulting in the
accumulation of large numbers of read/write cycles. Dur-
ing the read process data storage is volatile, i.e., data could
be lost if power is lost during the read. The ferroelectric
memory field-effect transistor ( FEMFET) 8-’’ data storage
element offers a significant advantage over the ferroelectric
capacitor approach: reading the data does not require the
memory to be reprogrammed.
The ferroelectric memory field effect transistor consists
of a field-effect transistor (FET) whose gate dielectric is
comprised of a ferroelectric material, or a stack of dielec-
trics with one ferroelectric layer.s-” The application of a
voltage pulse to the gate sets the direction of the polariza-
tion, and hence the value of the drain current of the tran-
sistor. The electrically programmable drain current can be
used to define two logic states, much like other semicon-
ductor nonvolatile memories,12 such as the silicon-nitride-
oxide-semiconductor (SNOS) nonvolatile memory transis-
tor.13
A comprehensive, quantitative model of ferroelectric
transistor operation has not been previously developed,
and is now needed for several reasons. Understanding the
dependence of the electrical properties on fabrication and
development. The successful design of nonvolatile memo-
ries implementing the ferroelectric transistor requires a
thorough understanding of how electrical performance is
related to design parameters. To characterize this relatively
unfamiliar device, new electrical characterization tech-
niques must be developed which measure the fundamental
device properties. In order to rapidly optimize design and
fabrication parameters, and develop relevant characteriza-
tion techniques, we need to quantitatively model the elec-
trical performance as a function of these parameters. This
is a capability that has not been previously developed.
To address this modeling need, we have derived and
solved the equations governing the operation of the ferro-
electric field effect transistor. The derivation of the model
is presented in Sec. II. Numerical analysis techniques used
to solve the resulting equations in a practical and efficient
manner are described in Sec. III. Theoretical results are
presented and discussed in Sec. IV for a range of relevant
device parameters. We focus on the basic (often nonintu-
itive) device properties of this novel structure. In Sec. V,
an example of technology optimization through the appli-
cation of virtual prototyping is given. A testing methodol-
ogy, based on the model, is also presented and discussed.
Finally, the paper is summarized in Sec. VI.
II. THEORY
A. Approach
To develop the ferroelectric transistor model, we com-
bine the switching physics of ferroelectric capacitors with
the silicon physics of metal-oxide-semiconductor (MOS)
FETs. Brews developed a successful model of MOSFET
transistor device operation14”* based on the charge-
sheet16”” approximation. This approach assumes that the
inversion layer of the silicon can be approximated by a
conducting plane of zero thickness. In Brews’ model, there

5999 J. Appl. Phys.72(12),15 December1992 0021-8979/92/245999-12$04.00 @ 1992 American institute of Physics 5999

Ferroelectric
Id(t)
v,
drain / ~ s
N,
@ms I
Vb
FIG. 1. Cross-sectional schematic of the FEMFET device being modeled.
The gate dielectric stack consists of a switching ferroelectric sandwiched
between two nonswitching dielectric layers.
are two contributions to the current: drift (governed by the
lateral electric field, which is determined by the drain-
source bias) and diffusion (governed by the carrier con-
centration, which is a function of the quasi-Fermi poten-
tial). Miller et al. is*19 have developed a model that
accurately describes ferroelectric switching in capacitor
structures by solving Maxwell’s first equation in the dielec-
tric stack. We combine these two approaches to derive the
equations governing the operation of the ferroelectric tran-
sistor.
The transistor drain current is physically determined
by the quasi-Fermi potential at the surface of the silicon
along the length of the channel. The quasi-Fermi potential
is related to the electrostatic potential at the silicon surface,
which in turn is related to the applied gate voltage; it is a
function of the properties of the dielectric layers on top of
the silicon, and of the silicon itself. Our approach now is to
first derive the equations governing the polarization, field,
and silicon surface potential as a function of gate voltage
for a ferroelectric capacitor on silicon. Using these results,
we then solve the basic transistor equations to obtain an
expression for the drain current.
B. Definitions
Before proceeding with the derivation of the relevant
equations, we define the physical structure being modeled,
along with the associated terminology.
The structure being modeled is shown in Fig. 1. (The
definition of the physical parameters are given in the Ap-
pendix.) A stack of three dielectrics exists between the
silicon and conductive gate. The central dielectric consists
of a switching ferroelectric dielectric layer, while the outer
two layers are nonswitching dielectrics. The thickness and
linear dielectric constants for each layer are independent.
For this derivation we assume that there is no space charge
in the dielectric layers; free charge exists only on the gate
and in the silicon. This capacitor structure, with the addi-
tion of the source and drain regions, comprise the FEM-
FET. We derive the equations for an n-channel device (p-
type substrate, n-type source and drain). The results can be
6000 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
20 -
72
5 IO-
g o-
s
B -10 -
B -20 -
ELECTRIC FIELD (kV/cm)
FIG. 2. The dipole switching contribution to the ferroelectric polariza-
tion is a function of the history of the electric field. The polarization must
lie on or within the saturated hysteresis loop.
directly applied to a p-channel device by making the stan-
dard sign transformations.
The ferroelectric dielectric layer is assumed to have a
dipole polarization that is a function of the history of the
electric field internal to the ferroelectric. The basic hyster-
etic nature of the ferroelectric polarization is illustrated in
Fig. 2, where the switched polarization (the linear contri-
bution to the polarization is omitted in this figure) is plot-
ted as a function of the ferroelectric field. Minor hysteresis
loops, along with the saturated loop, are shown. We note
that the polarization must lie on or within the saturated
polarization hysteresis loop.
C. Capacitor equations
The silicon physics of a MOS device (capacitor or
transistor) is independent of the dielectric structure that
exists above the surface of the silicon. The structure above
the silicon simply determines the relationship between the
applied gate-to-substrate voltage Vgb and the silicon sur-
face potential 4, For most MOS devices, once this rela-
tionship is determined, the device characteristics can be
expressed directly in terms of V86’The same is true for a
ferroelectric capacitor or transistor, except that the rela-
tionship between Y86 and (p, depends on the electrical his-
tory of the device. In this section, we derive the equations
relating the silicon surface potential to the gate-to-
substrate voltage as a function of the properties of the
dielectric layers on top of the silicon.
The electrostatic equations for the capacitor structure
illustrated in Fig. 1 are derived starting with Maxwell’s
equation
V-D =p, (1)
where p is the free charge density and D, the displacement
vector, is given by D =e,,E+ P,,. (Vector quantities are
signified by bold symbols, and are taken to be positive in
the direction pointing downward from the top electrode, as
shown in Fig. 1.) The total polarization is the sum of the
S. L. Miller and P. J. McWhorter 6000
linear contribution and the contribution resulting from
switching dipoles. Thus
D=E,,E+E,,xE+P~=E~E+P~,
where E= 1 +x is the linear dielectric constant for a given
dielectric layer, and Pd, the contribution to the polarization
due to switching dipoles, is nonzero only in the ferroelec-
tric layer. Since Pd is a function of the electric field in the
ferroelectric layer (as well as the field history), it is written
as PJ E2). Using Eqs. ( 1) and (2) in conjunction with the
definition E= -VI$, where 4 is the electrostatic potential,
and recalling that the dielectric layers contain no trapped
charge, we arrive at
4
-pd(Ed
~04,
where
the lateral electric field resulting from the source-drain
bias. The other contribution is diffusion of carriers due to
the carrier concentration gradient. The relative contribu-
(2)
tions of the two mechanisms to the total current may vary
along the length of the channel. However, the total current
itself (steady state) clearly must be independent of posi-
tion, otherwise charge would build up in the channel. The
carrier density automatically adjusts to result in the same
total current. This variation of carrier density with channel
position is physically explained in terms of an adjustment
of the Fermi level. Specifically, the conventional Fermi
level is replaced by a quasi-Fermi level that varies along the
length of the channel, resulting in a total current that is
(3)
constant.
Taking into account the mechanisms of drift and dif-
fusion, the current can be expressed in terms of the quasi-
Fermi potential asl’

(4)

and the field is given by where the derivative is along the length of the channel, and
x is the distance from the source.
E2= - [as+pd(E2) 1 The goal now is to find an expression for the inversion
652 * charge density IV1 and the derivative of the quasi-Fermi
The silicon charge a, is given as a function of the silicon potential dd,/dx.
surface potential c$, by”
2. Inversion charge N,
a,(A) = -SGN(&) fi(e&lfiL~J [ (e-B4s+P#s- 1) The determination of the inversion charge layer is fa-
+ (nJNJ2(P+34s- 1) Y2, (6) cilitated by making a simple observation. The inversion
charge layer is typically a very thin sheet of charge located
where the bulk Debye length LB is given by at the silicon surface. Thus, the inversion layer is approx-
LJy= ( Eo$@qNJ 1’2. (7) imated by a sheet of charge. This approximation eliminates
the need to obtain complex solutions to the electrostatic
Equations (3), (5), and (6) together completely describe equations in the silicon.
the capacitor operation of the device illustrated in Fig. 1, The total silicon charge density is just the sum of the
when the function Pd(E2) is known. These equations are charge in the inversion layer -qN, and the charge in the
valid for accumulation, depletion, and inversion. The solu- depletion layer -qN,w, i.e.,
tion to this set of equations will be addressed later.
a,= -qNr-qN,w, (9)
D. Transistor equations: General formulation where the depletion width w is given by
Having derived the equations relating the silicon sur- w = JzLB( pep,, 1’2. (10)
face potential to the applied voltage, we now proceed to
derive the transistor equations. This derivation follows Eliminating w from Eqs. (9) and (lo), one obtains the
closely that given by Brewst4*t5 for the nonferroelectric desired result
MOSFET. Since the polarization is related to the silicon c stack es
surface potential and charge [see Eq. (3)], Brews’ equa- q&=7 -4~w2-~ (11)
tions are rewritten to properly take into account the effects ( stack

of the hysteretic ferroelectric polarization. The equations where

are derived below for n-channel transistors; application to
0= & 6J’%&~stack). (12)
p-channel devices can be made with the standard sign
changes.
3. Quasi-Fermi potential &,,
1. Basic current equation
A suitable expression for the quasi-Fermi potential is
When the surface potential is sufficiently large to form needed to evaluate Eq. (8) for the current. The equation
an inversion region at the surface of the silicon, an electri- relating the silicon charge and surface potential can be
cal channel connecting the source and drain is formed. The expressed in terms of the quasi-Fermi potential by”
current that flows through this channel consists of two
contributions, each caused by fundamentally different as= -OF [ p$+ (~)‘@L l)&%+bp] 1’2. (13)
mechanisms. One contribution is drift of the carriers due to

6001 J. Appt. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6001
Equation ( 13) is strictly valid only for the range of surface
potentials resulting in depletion and strong inversion. The
complete expression that is also valid for accumulation is
not necessary for the analysis of transistor operation, since
negligible current flows in accumulation. Equation ( 13) is
inverted to obtain the quasi-Fermi potential
( -fld~c,tack)2-fl#s
The 1 in the denominator can typically be dropped since
exp(&,)>l when not in accumulation.
It can be inferred from Eq. ( 14) that there is a value of
@$, that cannot be exceeded. As the surface potential &$,
increases, the numerator in the log term approaches zero,
and hence /3+F,, diverges to positive infinity. The value of 4,
at which $Fn diverges is called &, and is given by
-&(&at>~&ack= (Pdsat)1’2*
In I$. ( 15) we indicate the explicit dependence of the
charge a, on the surface potential. For fixed gate and
source voltages, increasing the drain voltage will increase
the silicon surface potential at the drain. This potential
asymptotically approaches &; this is the condition that
results in pinch-off of the channel. The term pinch-off is
used because at this point the inversion layer vanishes [see
Eqs. (11) and (15)], and the channel is “pinched-off.” The
value of the drain voltage V,,, that results in saturation of
the surface potential at the drain (pinch-off) is defined by
V,, = I$,,~ - I&,, where & is the surface potential at the
source end of the channel.
Finally, a useful expression for d/3 $F,,/dx is obtained.
This is done by taking the derivative of Eq. ( 14). The
result is
l- [2&d(~~stack)2]
&Fn=( 1+ (-&d~cstack)
This expression may be simplified considerably by making
the following observations. The first two terms of Eq. ( 17)
are simply PqN/Cstack Thus the third term of Eq. (17)
contributes significantly to the current only when N1 is
small, i.e., near pinch-off. Consequently, we replace the
third term of Eq. (17) by its value near pinch-off. Using
Eq. ( 15) to do this, IQ. ( 17) becomes
* (14)
Idx=
(18)
The current is obtained by integrating the above ex-
pression along the length of the channel, from the source to
the drain. We designate the effective channel length by L,
and the silicon surface potential at the source and drain by
(15)
+d) and 4sL, respectively. Since the current is constant
along the channel, the left-hand side of Eq. ( 18) becomes
IL. All terms on the right-hand side of Eq. (18) can be
integrated directly except those that contain a,. We recall
that o, is a function of @, and is given by [see Eq. (3)]
-‘;““)
stack
=&y-&b,+P,(E2)
2 . (19)
If the drain-to-source bias V,, is kept sufficiently low (typ-
ically < -0.5 V), the FE polarization will not vary signif-
icantly along the length of the channel, and Pd( E2) can be
treated as a constant for the purpose of integration. Inte-
grating Eq. ( 18) using Eq. ( 19), we obtain
I= -$‘+ [ (1+&++z f%E,))(@$s~-&)
(~~~s@~s)
2
+‘#%

The terms on the right-hand side of Eq. (8) have now

been defined [see Eqs. ( 11) and ( 16)]. These quantities
+a[. wsLY2- pAilY21 *
1 (20)

The values of the surface potentials 4,L and 4a are

cannot be evaluated directly to obtain the current. How- determined using the boundary conditions15
ever, if Eq. (8) is integrated from the source to the drain,
the current can be determined. +F&ource) =‘#‘F+ vbs (21)
and
4. Determining the current #Fn(drain)=&+ VbYt- vds. (22)
Now that the inversion charge N1 and the derivative of
The potentials #a and & are then given [combining Eq.
the quasi-Fermi potential d&$&dx have been determined,
( 14) with Eqs. (21) and (22)] by solving the transcenden-
we proceed to evaluate Eq. (8) to obtain the current. Sub-
tal equations
stituting Eqs. ( 11) and ( 16) into Eq. (8)) we obtain
- w@stack -@s l/2
I=
p2 c,,, - ‘(“‘)

+
a(1 - [2~q/(~~,,,,k)21
[ ( -&duCstack)
(%J-~~~~~s)~
+ (8h)1’21
-fvK+ (23)

(17) and

6002 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6002
 Wz TABLE I. FEMFET deviceparameters.
Pv.b+Gpd(EZ)
Parameter Value Unit

p* 1.0 &/cm2
(24) p/p, 0.8
EC 100 kV/cm
The ferroelectric dipole polarization in Eqs. (20), (23), 4 300 A
and (24) is evaluated at the source end of the channel. EI 3.9
Brews’ original raUlt iS recovered by Setting Pd=O. 4 1000 A
4 10
In order to solve Eqs. (20), (23 ), and (24) for the 10 .A
4
drain current, explicit definitions of the dipole polarization 63
Pd(E2) must be given. We discuss this in the following NC 3;ik cmm3
section, after first making a few comments regarding the P 0.08 m’/(V s)
treatment of interfacial charge. W 8 w
L 4 Pm
We note that the derivation presented here is in a form -1.15 V
4,
that allows the quantitative treatment of interface states at vd 0.1 V
the silicon surface, the occupancy of which is a function of V* 0 V
the difference between the surface potential and quasi- vb 0 V
Fermi potential. The inclusion of interfacial charge results
in slight modifications to Eqs. (3) and (5); these changes
are then carried through the remainder of the analysis.
Care must be taken when integrating the equation analo- The equations have thus been given that govern the
gous to Fq. ( 17) since both the surface potential and quasi- ferroelectric transistor drain current as a function of the
Fermi potential are functions of position along the channel applied voltage history, geometry, and material properties.
length. The detailed treatment of interface states is omitted In the following section we discuss some issues associated
with the numerical evaluation of the above equations.
in the present paper.

III. NUMERICAL ANALYSIS TECHNIQUE

E. Dipole polarization
The value of the dipole polarization depends on the
previous history of the ferroelectric electric field. Thus the
polarization is determined by integrating dP,(E,)/dE,
from some specified initial condition. Since the form of
dPd(E)/dE (we drop the subscript 2 for notational conve-
nience) has been extensively discussed previously for arbi-
trary field histories, 18V19
the results are simply stated here.
The saturated polarization hysteresis loop is defined by
P&(E)=P&.anh[ (E-E,)/2S],
where
Since the polarization (and hence the surface potential
and current) depend on the history of the electric field in
the ferroelectric, the drain current is calculated as a func-
tion of the applied gate voltage by integrating the polariza-
tion from known initial conditions. The procedure to ac-
complish this is outlined below.
A. initial condition computations
( 1) Define the constants required for the computa-
tions. These include P,, P, E. T, N,, p, W, L, d,, d2, d3, el,
(25) E2, E3, v, vb, and v,.

S=Ec[ ln( :Tig)]-‘, (26)

and the + superscript signifies the positive-going branch of

the loop. The negative-going branch of the loop is given by
P;,(E) = -P&( -E). (27)
The derivative of the polarization, whether or not the
polarization lies on or within the saturated hysteresis loop,
is given by

(28)

where
0
I’=l-tanh[ (E)1’2], (29) time
and c= + 1 when dE/dt > 0 and ,$= - 1 when dE/dt < 0. FIG. 3. The time-dependent voltage Vg applied to the transistor.

6003 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhotter 6003
 (2) Define the initial conditions, i.e., the initial gate
voltage Ve and initial polarization Pa Using these values,
the silicon surface potential +S and silicon charge density a,
are calculated by simultaneously solving Eqs. (3) and (6).
The initial value of the ferroelectric field is then calculated
using Eq. (5). The derivative dP,(E)/dE is also evaluated
[using Eq. (28)]. Note that the initial choice of Ve and Pd
must satisfy the physical requirement that the polarization
lie on or within the saturated hysteresis loop.
(3) Finally, the initial current is computed. If 4, < +p
then the channel is off and the drain current is effectively
zero. If #$> 4p then the current is computed as follows.
Calculate fl+d) and p+SL using Eqs. (23) and (24). Then
substitute these values into Eq. (20) to give the drain cur-
rent. The value of Pd used to evaluate Eqs. (23), (24)) and
(20) is that used in step 2 above.
B. Numerical integration
To perform the integration from the initial conditions
to a new set of conditions, a technique to simultaneously
Using Eq. (3 1) in conjunction with Eq. (28), compute the
mth value of the dipole polarization. Next, calculate Y86
from Eq. (3). Using the above results, solve Eqs. (23) and
(24) for the silicon surface potential at the source and
drain end of the channel. Finally, evaluate Eq. (20) to
obtain the mth value of the drain current.
Though the numerical implementation of the equa-
tions to obtain the drain current as a function of an arbi-
trary time-dependent gate voltage may appear somewhat
complex, it is actually quite straightforward.
IV. MODEL RESULTS
The behavior of a FEMFET device is now investigated
using the equations derived above. The parameters used to
perform the analyses are given in Table I, unless otherwise
specified. The initial conditions are ?‘a= Vfb and Pd=O.
The applied voltage history is shown in Fig. 3. To maintain
clarity in the following figures, only the quantities associ-
ated with the portion of the voltage history indicated by
the heavy line in Fig. 3 are shown.
For reference, we first show the “standard” polariza-
tion hysteresis loop, i.e., the contribution to the ferroelec-
tric polarization due to the switching dipoles as a function
of the ferroelectric field. This is plotted in Fig. 4 for several
values of P, while maintaining a constant ratio P/P, The
arrows indicate the direction of the hysteresis path in this
and the following figures. Though the amplitude of the
applied signal is the same for all three cases, the maximum
ferroelectric field decreases with increasing P,. In fact, for
P,= 1.0 &/cm2, the hysteresis loop is unsaturated. The
6004 J. Appl. Phys., Vol. 72, No. 12, 15 D&ember 1992
solve Eqs. (3), (5), (6), and (28) must be developed. The
approach we pursue is to compute the mth value of the
relevant quantities, and numerically integrate. In order to
avoid confusion, we drop the subscript 2 on the ferroelec-
tric electric field. We now introduce a new subscript, m,
which signifies that the given quantity is evaluated at the
mth integration increment.
First, select an mth value for 4, Calculate the mth
value of a,( 4,) from Eq. (6). Write the dipole polarization
as
PcAEm)
=P~&,+I) + (-%--Em-,) -& [P&3 11~~~~
,
(30)
where the vertical bar signifies that the derivative is eval-
uated at the field E,,+ i. Using Eq. (5) to eliminate E,, E~J.
(30) becomes
(31)
maximum and minimum field for each curve are different
in magnitude due to the non-zero flatband voltage.
The ferroelectric polarization Pd is shown as a function
of the applied gate voltage Vg in Fig. 5 for several values of
PF Note that at Vg=O, the polarization is less than the
remanent polarization P, This nonintuitive result occurs
because the ferroelectric field reverses direction when the
gate voltage is reduced from a saturating value back to 0 V.
This field-reversal results in the additional polarization re-
duction observed in Fig. 5. It also results in the fact that
the polarization at zero gate bias is relatively insensitive to
the spontaneous polarization when it is increased beyond
-0.5 ,uC/cm2. The nature of the electrostatic boundary
conditions that must be satisfied at the dielectric layer in-
terfaces is the physical origin of this behavior. For com-
pleteness, we show the dependence of the ferroelectric field
on the applied gate voltage in Fig. 6. Note that the direc-
tion of the path taken around the hysteresis loop is opposite
to that of the polarization shown in Figs. 4 and 5. We also
point out that the changing depletion layer capacitance of
the silicon is the origin of the “kink” that disrupts the
symmetry in Figs. 5 and 6.
The electric field in the non-switching layers (or the
silicon) can become quite large if the ratio of the dielectric
constant of the ferroelectric layer to that of the nonswitch-
ing dielectric layers (or the silicon) is not close to unity.
We illustrate this by plotting the field in the bottom non-
switching layer as a function of the gate voltage in Fig. 7.
The rate at which the field increases with voltage scales
with P, during switching, and is independent of P, after
S. L. Miller and P. J. McWhorter 6004
 0.8
0.4

0.2

z
g 0
V
N
w -0.2

-0.8l’ ’ s ” “I ”
-500 -250 0 250 500 -12 -8 -4 0 4 8 12

E, (kV/cm) vg(V)
FIG. 4. The ferroelectric polarization P,+as a function of the ferroelectric FIG. 6. The direction of the hysteresis of the ferroelectric field vs the gate
field is hysteretic due to the applied signal shown in Fig. 3. voltage is oppositethat of the polarization, resulting in field reversal when
the gate bias is reduced to 0.

switching is complete. This rapid increase in the field dur-

ing switching is a direct consequence of the boundary con-
ditions associated with this stacked dielectric structure.
The polarization of the FE layer reduces the electric field
internal to the FE film, and hence increases the field in the
dielectric layers external to the FE film. Spontaneous po-
larization values that are not very small can result in fields
exterior to the ferroelectric that can easily become compa-
rable to the breakdown field for such films, and can cer-
tainly result in parasitic effects such as charge injection or
transport through the films.
Since the transistor drain current is a function of the
silicon surface potential, the I-V characteristic of the tran-
sistor depends on the relationship between the gate voltage
and surface potential. The silicon surface potential (with
no drain bias) is shown in Fig. 8 as a function of gate
voltage for several values of Pr (Note that increasing P, by
a factor of four has only a minor impact on the gate voltage
at which the transition from accumulation to inversion
occurs.) The occurrence of ferroelectric switching not only
results in hysteresis of the d,( Vg) curve, but also results in
a change in shape relative to that of a non-switching de-
vice. In particular, when the gate voltage passes through
the range where switching occurs (see Fig. 5), the slope
dt&/dV, increases due to the changing polarization. These
results significantly impact our intuition regarding such
concepts as threshold voltage.

0.8
3

0.4 2

E 1
Ni
0 O Y
2
is O
ci?
-0.4 w” -1

-2

-0.8
, * 1 * * * * ” a ’ 1 ’ ” I”” a ‘3
-12 -8 -4 0 4 8 12 -3

vg09 -12 -8 -4

vgW)
0 4 8 12

FIG. 5. The hysteresis of the polarization Pd as a function of gate voltage

k’s demonstrates the reverse switching due to field reversal in the ferro- FIG. 7. The field in the non-switching dielectric layers is amplified by the
electric. The “kink” in the curves disrupting the symmetry is due to the switching polarization of the ferroelectric layer. Depending on the geom-
changing capacitance of the silicon. etry, it can easily reach values comparable to the breakdown field.

6005 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6005

0.8
-12 -8 -4 0 4 8 12
vg W)
FIG. 8. The silicon surface potential as a function of the gate voltage is
hysteretic, resulting in distorted transistor Z-V characteristics exhibiting
hysteresis.
For an “ideal” MOS transistor, the threshold voltage
can be defined as the gate voltage that results in the silicon
surface potential at the source being equal to 2+P The
subthreshold region corresponds to gate biases resulting in
+F < +S< 2#F The #,( Vg) hysteresis curves in Fig. 8 are
those for saturating (in the sense that the polarization sat-
urates) or nearly saturating gate biases. Minor hysteresis
loops can take any path within the corresponding saturated
loop. Consequently, the notion of threshold voltage is com-
pletely ambiguous; the gate voltage that corresponds to
$,=21$~ depends on the voltage history. Moreover, all as-
pects of the transistor I-V curve (e.g., subthreshold swing
and k’) depend on the voltage history due to the fact that
the ferroelectric polarization depends on the internal field
history.
Transistor I-V curves for several values of P, are
shown in Fig. 9; Fig. 9(b) is identical to 9(a) except for
the scale on which the current is plotted. The amplitude of
the gate bias is sufficient to saturate the polarization (see
Fig. 4). The “subthreshold slopes” of the switching tran-
sistors are greater than that for the nonswitching transistor
( PS=O); this occurs because of the greater sensitivity of the
surface potential to the gate voltage during the switching
process. In addition, the maximum transistor current is
greater due to the larger fields resulting from the switched
dipoles (see the discussion associated with Fig. 7).
Figure 9(b) highlights some additional striking prop-
erties of FEMFET hysteresis. The apparent slope of the
“on” I-V curves has two components; the larger slope re-
sults when dipole switching is still occurring, while the
smaller slope results when switching is complete. Note that
for voltages large enough for switching to be complete, the
slope is the same as that of a nonswitching transistor, and
the actual current is proportional to the spontaneous po-
larization P,. In addition, the “apparent” threshold voltage
shift associated with the hysteresis is relatively independent
6006 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
0.25
120 ,
80 -
‘fl Ps = 0.0 yC/cm’
-2 0 2 4 6 a 10 12
vg (V)
FIG. 9. Transistor Z-V curves exhibit hysteresis due to ferroelectric
switching. The same data are plotted in both (a) and (b); the only
difference is current scale. The apparent “threshold” voltage shift is gov-
erned by EO while P, governs the current offset at large voltages.
of P,. The boundary conditions are such that the onset of
strong inversion corresponds to a relatively small value of
ferroelectric polarization. This polarization is relatively in-
dependent of P, (as is clearly seen in Fig. 5) as long as P,
is larger than some very small critical value (which de-
pends on the geometry of the device). The “apparent”
threshold voltage shift, rather than being dependent on the
spontaneous polarization, is directly proportional to the co-
ercive field E,
The dependence of the flatband (or equivalently,
“threshold voltage”) shift on E, is clearly illustrated by the
C-V curves in Fig. 10. Recall that the C-V curves only
sample the range in surface potential corresponding to the
formation of the depletion layer, i.e., - 0 < 4, < - 24,+ This
corresponds to a very limited range of the FE polarization
Pd, as can be inferred from Figs. 8 and 5. As noted earlier,
the gate biases corresponding to this range of polarization
are relatively independent of the spontaneous polarization
P, To summarize, the apparent flatband shift of the C-V
hysteresis curves is proportional to the coercive field. The
shape of the C-V hysteresis curves is governed by the de-
pendence of the FE polarization on gate voltage for a range
S. L. Miller and P. J. McWhorter 6006
 Ps = 1 .o j.lc/cm*
0.9
2
0 0.8
3
0.7
0.6
vgw
FIG. 10. Capacitor C-Y curves exhibit hysteresis; the flatband voltage
shift is proportional to E, The shape of the C-Y curves results from the
ferroelectric polarization sweeping through only a small range in polar-
ization.
in polarization where this dependence is a very weak func-
tion of the spontaneous polarization.
V. DISCUSSION
The above analyses reveal a number of unique and
nonintuitive aspects of the behavior of FEMFET devices
that are not observed with either fixed-threshold FET de-
vices or other types of conventional silicon-based nonvol-
atile memories. It is not possible to measure a “conven-
tional” C&-threshold transistor I-V curve. The act of
performing the measurement changes the ferroelectric po-
larization, and the resulting curve depends on the previous
electrical history. The concept of a well-defined threshold
voltage does not exist; the gate voltage resulting in #s=2r$F
depends on the voltage path taken due to the changing
ferroelectric polarization. In addition, the “subthreshold”
portion of the I-Y curve is always steeper than that of a
similar nonswitching FET. Specifically, as the gate voltage
is increased (decreased), the transistor turns on (off)
faster due to the ferroelectric switching; this is why the 1-V
hysteresis occurs in the counter-clockwise direction (see
Fig. 9).
These types of behavior present some interesting prob-
lems regarding FEMFET technology development and de-
vice characterization. Since much of our standard intuition
and characterization approaches are not applicable to
FEMFET devices, we show how the model developed
above can facilitate the design and electrical characteriza-
tion of these devices.
A. Virtual prototyping application
Virtual prototyping is the application of predictive
models to answer questions that would normally be ad-
dressed by designing, fabricating, and testing devices (i.e.,
physical prototyping ). Virtual prototyping can signifi-
6007 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
,ZOlarizatiin Swi,ChlnQ field
decreases with thickness
0 0.5 1 1.5
d2 W-d
FIG. 11. Following a positive voltage pulse, the transistor drain current
is significant only for a finite range of ferroelectric film thicknesses. This
virtual prototyping approach can be used to rapidly optimize a number of
design and fabrication parameters.
cantly reduce both the time and expense of performing
technology optimization, as well as reduce the number of
design iterations.
We illustrate a virtual prototyping application using
the above FEMFET model. A fabrication parameter that
impacts the electrical performance of a FEMFET memory
device is the thickness of the ferroelectric layer. In our
virtual prototyping example, we determine the optimum
ferroelectric layer thickness to maximize the transistor
drain current after a programming voltage pulse to the
gate. The physical parameters associated with the device of
interest are those listed in Table I. For the sake of illustra-
tion, we assume that the polarization Pd is zero immedi-
ately before the programming voltage pulse. A positive 10
V pulse is then applied to the gate, after which the gate-
to-substrate voltage is maintained at 0 V. Immediately af-
ter the pulse, the polarization will be different from zero,
resulting in a change in the transistor drain current. The
desired information is the value of the drain current (im-
mediately after the pulse) as a function of the ferroelectric
layer thickness.
The conventional way to determine this information is
to develop the appropriate fabrication processes, fabricate
devices with different ferroelectric thicknesses, and then
perform electrical measurements. Instead, we perform vir-
tual prototyping to determine the same information within
minutes.
The results of the virtual prototyping analysis are
shown in Fig. 11, where the drain current at zero gate bias
is plotted as a function of the ferroelectric film thickness.
Note that the transistor is on after the pulse for only a
limited range of thicknesses. For large thicknesses, the field
resulting from the applied voltage is not sufficient to switch
the polarization, and the transistor remains off (as it was
with zero polarization). For slightly thinner films, the field
is sufficient to switch the polarization. However, when the
S. L. Miller and P. J. McWhorter 6007
gate voltage is reduced to zero after the pulse, reverse
switching of the dipoles occurs due to the field reversal in
the ferroelectric film (see Fig. 5 and the associated discus-
sion). Consequently, the transistor current after the pulse
is reduced to a value that is less than it was during the
pulse. For very thin films, the current again drops to zero.
This is because the impact of the ferroelectric polarization
on the silicon surface potential is roughly proportional to
the film thickness [see Eq. (3)]. We note that after negative
gate pulses, the transistor is turned off.
Though we have considered a single application of vir-
tual prototyping here, it is clear that the FEMFET device
model may be used to rapidly optimize a number of design
and fabrication parameters associated with the FEMFET
technology, e.g., film thicknesses, device areas, operating
voltage, bit line capacitance, and FE film properties such as
E. P,, P, and E.
8. Testing methodology
There are several physical properties of the ferroelec-
tric film that are relevant to the successful design, fabrica-
tion, and delivery of FEMFET devices. These include the
polarization versus field hysteresis loop (impacts design
parameters and material selection), the relaxation of the
polarization with time (determines data retention), and
the change in these properties with repeated reprogram-
ming (endurance). The polarization vs field hysteresis loop
of FE capacitors is typically obtained using a Sawyer-
Tower circuit;” unfortunately, the standard analysis typi-
cally performed is not valid due to the highly nonlinear
relationship between the applied voltage and ferroelectric
electric field. Data retention in conventional silicon-based
nonvolatile memories is typically characterized by measur-
ing the change in threshold voltage with time; this cannot
be done for FEMFET devices since changing the gate volt-
age changes the “threshold voltage.” Characterization of
endurance simply involves measuring the above properties,
for example, as a function of accumulated reprogramming
cycles. Clearly, a new approach must be taken to electri-
cally characterize FEMFET devices.
The development of a testing methodology must be
performed with extreme care due to the unique properties
of the FEMFET device. It requires a quantitative under-
standing of the relationship between measured quantities
(such as currents and voltages) and basic device parame-
ters in order to electrically characterize the relevant phys-
ical properties. We discuss below how the FEMFET device
model is used to develop a relevant testing methodology.
The first step is to determine the basic ferroelectric
hysteresis loop parameters P,, P, and EC We recall from
Fig. 9(b) that these parameters are directly related to the
saturated I-V hysteresis loop. The model parameters are
determined by adjusting them so that the model 1-V curve
matches the experimental I-V data; EC is adjusted to match
the apparent “threshold voltage” shift, P, is adjusted to
give the correct parallel offset for the saturated portion of
the 1-V curve, the dielectric constant e2 is adjusted to give
the correct saturated slope, and P, is adjusted to give the
correct curvature during switching. To do this, the other
6008 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
0.2 0.3
Pd (pC/cm2)
FIG. 12. The computed current vs polarization curve can be used to infer
the ferroelcctric polarization from drain current measurements at zero
gate bias. The polarization is thus not disturbed during the measurement
process.
device parameters such as channel doping, channel length
and width, film thicknesses, and dielectric constants must
be known or determined using other standard techniques.
Data retention is governed by the rate at which the
polarization relaxes with time after the programming
pulse. To determine the polarization as a function of time
after a positive gate pulse, the drain current at zero gate
bias is measured as a function of time. Note that this mea-
surement process does not disturb the polarization pro-
vided the drain bias is kept low. To determine the time
dependence of the polarization, the drain current as a func-
tion of the polarization (and at zero gate bias), is com-
puted using the previously determined physical parame-
ters. Figure 12 illustrates the results of such a computation
for the parameters listed in Table I. Using Fig. 12, a given
current value is mapped directly to the ferroelectric film
polarization. We note that this technique permits polariza-
tion measurements for a limited range of values due to the
fact that the transistor must have a measurable drain cur-
rent at zero gate bias. To measure the decay of polarization
having a different range, one may perform the same mea-
surements on an identical n-channel transistor having a
threshold-adjust implant, or test a p-channel transistor fol-
lowing a negative gate pulse.
Using the above approach, the basic ferroelectric pa-
rameters may be determined after various numbers of ac-
cumulated reprogramming cycles. In this way, the endur-
ance of the ferroelectric film is characterized.
The testing methodology described above may be di-
rectly extended using the FEMFET device model to de-
velop additional characterization techniques.
VI. SUMMARY
The device properties of a ferroelectric memory field
effect transistor (FEMFET) have been theoretically inves-
S. L. Miller and P. J. McWhorter 6008
tigated. This was done by solving Maxwell’s first equation
for the stacked dielectric structure in conjunction with the
charge-sheet approximation to the silicon inversion layer.
The resulting equations allow the determination of the
transistor drain current, ferroelectric polarization, and di-
electric layer fields as functions of arbitrary time-
dependent gate voltages. It was found that the polarization
at zero gate bias (which is relevant to device applications)
is relatively insensitive to the spontaneous polarization due
to reverse switching, a result that can significantly impact
the development of the FEMFET technology. This reverse
switching is caused by field reversal in the ferroelectric
layer; boundary conditions derived from Maxwell’s first
equation for a ferroelectric film on silicon require this to
occur. It was quantitatively demonstrated that the fields in
nonswitching films comprising the dielectric stack can eas-
ily become comparable to the breakdown field for such
films, another result that impacts FEMFET technology
development. Depending on the properties of the film, par-
asitic effects such as charge injection could easily result.
The FEMFET I-V curves were extensively investi-
gated. The I-V hysteresis occurs in a counter-clockwise
direction (this is opposite to that of other silicon-based
nonvolatile memories such as floating gate or SNOS) due
to polarization switching. The well-defined features nor-
mally associated with fixed-threshold FET I-V curves are
dependent on the gate voltage history, and are thus ambig-
uous. For example, the concept of a well-defined threshold
voltage is no longer relevant since the gate voltage at which
+,=24F is history dependent. Also, the “subthreshold
slope” is steeper than that of an equivalent fixed-threshold
device due to dipole switching. The coercive field governs
the apparent threshold voltage shift of saturated I-V
curves. The spontaneous polarization plays only a minor
role in determining the apparent threshold voltage shift
(provided it is larger than some critical value), contrary to
normal intuition and contrary to the way such data is com-
monly interpreted. In the triode region of operation (often
referred to as the linear region), the I-V curve demon-
Silicon
Surface
tc
E
Fn
FIG. 13. A band diagram illustrating the definitions of the relevant po-
tentials in the silicon.
6009 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
strates two characteristic slopes. At high voltages when
switching is complete, the slope is governed by the same
parameters as a normal nonswitching FET (but the cur-
rent itself is higher by an amount proportional to the spon-
taneous polarization). At lower voltages the slope is larger,
and is impacted by the shape of the ferroelectric P-E hys-
teresis curve. Having two different slopes renders the nor-
mal concept of k’ somewhat ambiguous. Hence, we have
quantitatively shown that most aspects of FEMFET device
operation differ significantly from those of standard MOS-
FET operation.
Because of these differences, the FEMFET device
model was applied to develop a viable testing methodology
that allows the experimental determination of relevant
physical properties of the ferroelectric film. Use of the
model was essential because quantitative relationships be-
tween measured quantities and physical device properties
are required.
The application of the FEMFET device model to per-
form technology optimization was illustrated with an ex-
ample of virtual prototyping. The drain current as a func-
tion of the ferroelectric film thickness was computed for a
specific programming pulse. It was found that the transis-
tor is in a high current state after the pulse for only a
narrow range of thicknesses, allowing the optimum choice
of ferroelectric layer thickness without costly fabrication
iterations.
ACKNOWLEDGMENTS
We thank D. Lampe at Westinghouse Electric Corpo-
ration for stimulating discussions. We are also grateful to
B. Filter and T. Meisenheimer for critically reviewing this
manuscript.
This work performed at Sandia National Laboratories
supported by the U.S. Department of Energy under Con-
tract No. DE-AC04-76DPOO789.
APPENDIX
The physical parameter and symbol definitions are
given below, along with their associated MKS units.
di, d,, d3, = dielectric layer thicknesses (m) .
el, Q, e3, =linear dielectric constant (unitless).
l ,=linear dielectric constant of the silicon (unitless).
eo=permittivity of free space -8.85X 10-l’ (F/m).
P,=remanent polarization [C/m’], i.e., the ferroelec-
tric dipole polarization occurring at zero electric field on a
saturated hysteresis loop.
P,=spontaneous polarization [C/m*], i.e., the maxi-
mum ferroelectric dipole polarization occurring on a satu-
rated hysteresis loop.
&=coercive field (V/m), i.e., the electric field at
which the ferroelectric dipole polarization is zero on a sat-
urated hysteresis loop.
V,=applied transistor or capacitor gate voltage (V).
V,= applied transistor drain voltage (V).
V,=applied transistor source voltage (V).
Vb= applied transistor or capacitor substrate voltage
09.
S. L. Miller and P. J. McWhorter 6009
 v,,= v,- v,
V,,= - ( V,- V,). The sign of V,, is chosen so that V,,
is a positive number when the source/substrate diode is
reversed biased.
vgs= vg- v,
Vgb= Va- V, = I&+ V,, In order to account for con-
tributions to the flatband voltage not explicitly addressed
in the following derivation, such as the gate-to-substrate
work function difference 4, or fixed trapped dielectric
charge, VBbshould be replaced in the equations that follow
with Vgb- Vu, where Vu, is the additional contribution to
the flatband voltage. For example, Vn, = 4,, when no other
charges are present, and Vgb+ Vgb- Vfb= Vgb-~ms
W=electrical channel width (m).
L = electrical channel length (m).
,u=channel mobility [m2/(V s)].
ni=intrinsic carrier concentration ( mm3).
N, = substrate doping concentration (assumed to be
uniform) [mm3].
n =free carrier concentration ( me3).
q=charge unit - 1.6~ lo-i9 (C).
T= absolute temperature (K) .
k=Boltzmann’s constant - 1.38~ 1O-123(J/K).
8=q/(kT) (V-l).
Figure 13 contains a band diagram illustrating the fol-
lowing definitions:
Ei= intrinsic level (J) .
EF= Fermi level (J) .
EFn=electron quasi-Fermi level (J). In a capacitor,
this is typically equal to the Fermi level.
N,= inversion layer charge density ( mW2).
a,= charge density in the silicon ( C/m2).
4 = [Ei( CO) - Ei]/q = band bending (function of posi-
tion) (V).
4S= [Ei( co ) - Ei]/q = band bending (at the silicon sur-
face) (V).
6010 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992
4~=[Ei(~0)-E&q=P-‘log(N,/n~)=Fermi poten-
tial (V).
#F,, = [Ei( 00 ) - EFn]/q = quasi-Fermi potential (V).
n=n,exp[(E,,-Ei)/k~=n,exp[P(~-~Fn)]=carrier
concentration ( mm3).
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