Notes: - A free block is only processed if it is specifically assigned to a sampling time via the allocated U95x

parameter; see sheet [702]!

- Parameterization of the sampling sequence is also described on sheet [702].
- The approximate calculating time per block is indicated in {µs} for each type of block.

1 2 3 4 5 6 7 8
Free blocks fp_vc_700_e.vsd Function diagram
- 700 -
Cover sheet 30.06.06 MASTERDRIVES VC
 Sampling time Sampling sequence
2 ... 20 2 ... 20
U950 ... U953 U960 ... U963 Setting and monitoring the sampling
times and sampling sequence
Function Parameter for Parameter for
Function block setting the sampling time setting the sampling sequence
number Parameter No. (factory setting) Parameter No. (factory setting) Example of the sampling time and sampling
001 U950.01 (20) U960.01 (20) sequence of a function block:
Processing of input terminals and 002 U950.02 (20) U960.02 (20)
receive data from serial interfaces ... ... ... ... ... This function block has the function block number 314
019 U950.19 (20) U960.19 (20)
It is deactivated in the factory setting (U953.14 = 20).
020 U950.20 (20) U960.20 (20)
Processing of output terminals and
... ... ... ... ...
transmit data to serial interfaces
029 U950.29 (20) U960.29 (20)
031 U950.31 (20) U960.31 (20) U953.14 = __ (20)
Uxxx (0)
032 U950.32 (20) U960.32 (20) K Kxxxx
... ... ... ... ...
099 U950.99 (20) U960.99 (20)
Free function blocks
101 U951.01 (20) U961.01 (20)
102 U951.02 (20) U961.02 (20)
... ... ...
330 U953.30 (20) U963.30 (20) Via U953.14 = 4 the function block can be allocated to the sampling time
331 U953.31 (20) U963.31 (20) T4 (= 4 x T0 = 4.8 ms).
Angle synchronism and positioning ... ... ... ... ...
350 U953.50 (20) U963.50 (20)
351 U953.51 (20) U963.51 (20) The function block is processed in the factory setting at the 3140th
Internal sequence control and
... ... ... ... ...
setpoint calculation
370 U953.70 (20) U963.70 (20)
position. By setting U963.14 to a value not equal to 3140,
the block can be allocated to a different position in the
371 U953.71 (20) U963.71 (20)
Reserve ... ... ... ... ...
sampling sequence.
399 U953.99 (20) U963.99 (20)

Parameter for setting the sampling time Parameter for setting the sampling sequence:
Value range: 2 ... 20 Value range: 0 ... 9999
Monitoring of calculating time
Factory setting: 20 (block is not calculated) Factory setting: Function block number x 10
B0090
Parameter value Sampling time 1) Sampling time at i.e. in the factory setting the blocks
T0 = P357 P357 = 1.2 ms are processed in the sequence "Calculating time" alarm A001
of the block numbers
Exception: Function block number B0091
2 T2 = 1 x T0 1.2 ms
3 T3 = 2 x T0 2.4 ms 10, 14, 15, 20 - 25, 371 Time monitoring "Calculating time" fault F042
4 T4 = 4 x T0 4.8 ms
5 T5 = 8 x T0 9.6 ms
6 T6 = 16 x T0 19.2 ms Computer workload
7 T7 = 32 x T0 38.4 ms r829
8 T8 = 64 x T0 76.8 ms
9 T9 = 128 x T0 153.6 ms
10 T10 = 256 x T0 307.2 ms
11 ... 19 Reserved for future applications 1) WE: 1.2 ms
20 Block is not calculated

1 2 3 4 5 6 7 8
Free blocks fp_vc_702_e.vsd Function diagram
- 702 -
Setting and monitoring the sampling times and sampling sequence 21.08.00 MASTERDRIVES VC
9 fixed setpoints (1-word) {2 µs} 8 fixed setpoints (2-word) {2 µs} 8 fixed control bits {2 µs} 3 connector displays {1 µs} U952.76 = __ (10)

U001.F (0.00) U950.31 = __ (10) U011.F (0.000) U950.40 = __ (10) U021.F (0) U950.48 = __ (10) U033 (0)
n034
-200.00...200.00 % -200.000.. 0...1 U952.75 = __ (10) K
-200.0...200.0 %
..200.000 %
U031 (0)
K0401 KK0411 B0401 n032 U952.77 = __ (10)
K
-200.0...200.0 %
U002.F (0.00) U950.32 = __ (10) U012.F (0.000) U950.41 = __ (10) U022.F (0) U950.49 = __ (10) U035 (0)
n036
-200.00...200.00 % -200.000.. 0...1 K
-200.0...200.0 %
..200.000 %
K0402 KK0412 B0402
4 double connector displays {3 µs}
U003.F (0.00) U950.33 = __ (10) U013.F (0.000) U950.42 = __ (10) U023.F (0) U950.50 = __ (10)
U952.78 = __ (10) U952.80 = __ (10)
-200.00...200.00 % -200.000.. 0...1
..200.000 % U037 (0) n038 U041 (0) n042
K0403 KK0413 B0403 KK -200.000.. KK -2 147 483 647..
..200.000 % ..2 147 483 647
U004.F (0.00) U950.34 = __ (10) U014.F (0.000) U950.43 = __ (10) U024.F (0) U950.51 = __ (10) U952.79 = __ (10) U952.81 = __ (10)
-200.00...200.00 % -200.000.. 0...1
..200.000 % U039 (0) n040 U043 (0) n044
K0404 KK0414 B0404 KK -200.000.. KK -2 147 483 647..
..200.000 % ..2 147 483 647
U005.F (0.00) U950.35 = __ (10) U025.F (0) U950.52 = __ (10)
-200.00...200.00 % U015.F (0) U950.44 = __ (10) 0...1 4 binector displays {1 µs}
-2 147 483 647.. U952.82 = __ (10) U952.84 = __ (10)
<2>
K0405 ..2 147 483 647 B0405
KK0415 U045 (0) U049 (0)
U006.F (0.00) U950.36 = __ (10) U026.F (0) U950.53 = __ (10) n046 n050
B B
-200.00...200.00 % 0...1 0...1 0...1
U016.F (0) U950.45 = __ (10)
-2 147 483 647.. U952.83 = __ (10) U952.85 = __ (10)
<2>
K0406 ..2 147 483 647 B0406
U047 (0) U051 (0)
KK0416 n048 n052
U007.F (0.00) U950.37 = __ (10) U027.F (0) U950.54 = __ (10) B B
0...1 0...1
-200.00...200.00 % U017.F (0) U950.46 = __ (10) 0...1
-2 147 483 647..
K0407 ..2 147 483 647
<2>
B0407 1 connector display with smoothing {5 µs}
KK0417 τ ≈ 300 ms U952.86 = __ (10)
U008.F (0.00) U950.38 = __ (10) U028.F (0) U950.55 = __ (10)
-200.00...200.00 % U018.F (0) U950.47 = __ (10) 0...1 U053 (0) n054
-2 147 483 647.. K -200.00..
<2>
K0408 ..2 147 483 647 B0408 ..200.00 %
KK0418

U009.F (0) U950.39 = __ (10) 1 double connector display with smoothing {8 µs}
<2> corresponds to -200 ... 200 %
0...65535 <1> U952.87 = __ (10)
τ ≈ 300 ms

K0409 U055 (0) n056

KK -200.000..
<1> corresponds to -200 ... 200 % ..200.000 %

1 2 3 4 5 6 7 8
Free blocks fp_vc_705_e.vsd Function diagram
- 705 -
Fixed setpoints, fixed control bits, connector/binector displays 15.04.99 MASTERDRIVES VC
 4 fault message trigger signals {2 µs} 4 alarm message trigger signals {2 µs} 3 connector/double connector converters {9 µs}
U952.59 = __ (20) U952.63 = __ (20)
U061 (0) U065 (0)
B 1 = "Fault F148" B 1 = "Alarm A061"

U952.60 = __ (20) U952.64 = __ (20) U950.56 = __ (20)

U062 (0) U066 (0) U070 (0)
B 1 = "Fault F149" B 1 = "Alarm A062" K .01 Hi Word KK0420
K .02 Lo Word
K .03 Hi Word KK0421
K .04 Lo Word
U952.61 = __ (20) U952.65 = __ (20) .05 Hi Word
U063 (0) U067 (0) K KK0422
B 1 = "Fault F150" B 1 = "Alarm A063" K .06 Lo Word

U952.62 = __ (20) U952.66 = __ (20)

U064 (0) U068 (0)
B 1 = "Fault F151" B 1 = "Alarm A064"

Voltage monitoring of electronics power supply 3 double connector/connector converters {11 µs}

[470.3]
[760.4]
[760.7]
[775.1]
[775.3] U952.88 = __ (20)
U071 (0)
100 ms POWER ON [775.7] .01 Hi Word
KK K0423
POWER ON [834] Lo Word K0424
B0400
KK .02 Hi Word K0425
10 ms
Lo Word K0426
POWER OFF POWER OFF
KK .03 Hi Word K0427
Lo Word K0428

1 2 3 4 5 6 7 8
Free blocks fp_vc_710_e.vsd Function diagram
- 710 -
Fault/alarm trigger signals, connector <==> double connector converter 15.04.99 MASTERDRIVES VC
 3 connector/binector converters {11 µs}
U072.01 (0) Bit field 1
K Connector/binector converter 1 n073
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B0410
U950.57 = __ (20)
B0411
B0412
7-segment display B0413
of the bit field to n073 B0414
15 14 13 12 11 10 9 8 B0415
B0416
B0417
7 6 5 4 3 2 1 0 B0418
B0419
B0420
B0421
B0422
B0423
B0424
B0425

U072.02 (0) Bit field 2 U072.03 (0) Bit field 3

K Connector/binector converter 2 n074 K Connector/binector converter 3 n075
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B0430 B0450
U950.58 = __ (20) U950.59 = __ (20)
B0431 B0451
B0432 B0452
7-segment display B0433 7-segment display B0453
of the bit field to n074 B0434 of the bit field to n075 B0454
15 14 13 12 11 10 9 8 B0435 15 14 13 12 11 10 9 8 B0455
B0436 B0456
B0437 B0457
7 6 5 4 3 2 1 0 B0438 7 6 5 4 3 2 1 0 B0458
B0439 B0459
B0440 B0460
B0441 B0461
B0442 B0462
B0443 B0463
B0444 B0464
B0445 B0465

1 2 3 4 5 6 7 8
Free blocks fp_vc_715_e.vsd Function diagram
- 715 -
Connector/binector converters 02.11.98 MASTERDRIVES VC
 4 binector/connector converters {12 µs}
U076 (0) U952.89 = __ (20) U078 (0) U952.90 = __ (20)
.01 .01
B B
.02 .02
B B
.03 .03
B B
.04 .04
B B
.05 .05
B B
.06 .06
B B
.07 7-segment display .07 7-segment display
B B
.08 of the bit field to n077 .08 of the bit field to n079
B B
.09 .09
B 15 14 13 12 11 10 9 8 B 15 14 13 12 11 10 9 8
.10 .10
B B
.11 .11
B B
.12 .12
B B
.13 7 6 5 4 3 2 1 0 .13 7 6 5 4 3 2 1 0
B B
.14 .14
B B
.15 .15
B n077 B n079
.16 0...FFFFh .16 0...FFFFh
B B

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field 4 K0431 Bit field 5 K0432
Binector/connector converter 1 Binector/connector converter 2

U080 (0) U952.91 = __ (20) U057 (0) U952.56 = __ (20)

.01 .01
B B
.02 .02
B B
.03 .03
B B
.04 .04
B B
.05 .05
B B
.06 .06
B B
.07 7-segment display .07 7-segment display
B B
.08 of the bit field to n081 .08 of the bit field to n058
B B
.09 .09
B 15 14 13 12 11 10 9 8 B 15 14 13 12 11 10 9 8
.10 .10
B B
.11 .11
B B
.12 .12
B B
.13 7 6 5 4 3 2 1 0 .13 7 6 5 4 3 2 1 0
B B
.14 .14
B B
.15 .15
B n081 B n058
.16 0...FFFFh .16 0...FFFFh
B B

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field 6 K0433 Bit field 7 K0490
Binector/connector converter 3 Binector/connector converter 4

1 2 3 4 5 6 7 8
Free blocks fp_vc_720_e.vsd Function diagram
- 720 -
Binector connector converters 12.10.01 MASTERDRIVES VC
 4 adders with 2 inputs (1-word) {3 µs} 3 sign inverters (1-word) {2 µs} 1 modulo 2^16 adder/subtracter {2 µs}
U950.83 = __ (20) U951.42 = __ (20) U950.84 = __ (20) U096 (0) U951.72 = __ (20)
U082 (0) U084 (0) U098 (0) x y K .01
.01 + 200% .01 + 200%
K
K .02 K0442
K
K .02 K0444 K -1 K0458 K .02
.03
K0456
+ -200% + -200% K <1>
y = -x <1> Arithmetic two's complement without evaluation
U951.01 = __ (20) U952.20 = __ (20) of carry and borrow:
U951.17 = __ (20) No limitation in the case of overflows and
U083 (0) U085 (0) underflows outside of the number range of 16 bit
K .01 + 200%
K .01 + 200%
U099 (0) (Example: 65535+40000=39999 at modulo 2^16 addition).
K0443 K0445 x y
K .02
+ -200%
K .02
+ -200%
K -1 K0459

y = -x 1 modulo 2^32 adder/subtracter {2 µs}

4 adders with 2 inputs (2-word) {6 µs}
U952.36 = __ (20) U097 (0) U951.91 = __ (20)
U951.15 = __ (20) U952.05 = __ (20) U100 (0) KK .01
x y
U090 (0)
KK .01 + 200%
U092 (0)
KK .01 + 200% K -1 K0460 KK .02
.03
KK0457
.02 KK0450 .02 KK0452 KK
KK KK y = -x
+ -200% + -200% <1> Arithmetic two's complement without evaluation
of carry and borrow:
U951.29 = __ (20) U952.21 = __ (20) No limitation in the case of overflows and
underflows outside of the number range of 32 bit
U091 (0)
.01 + 200%
U093 (0)
.01 + 200% 2 sign inverters (2-word) {4 µs} (Example: (232-1)+40000=39999 at modulo 2^32 addition).
KK KK
.02 KK0451 .02 KK0453
KK KK
+ -200% + -200% U951.03 = __ (20) 1 switchable sign inverter
U101 (0) x y
3 subtracters (1-word) {3 µs} KK -1 KK0461 (1-word) {2 µs}
U951.02 = __ (20) U952.06 = __ (20) y = -x U103 (0) U951.30 = __ (20)
U087 (0) U089 (0) B
K .01 + 200%
K .01 + 200% U952.22 = __ (20)
.02 K0447 .02 K0449 U104 (0)
K K U102 (0) x y 0
– – K
-200% -200% KK -1 KK0462 x y K0463
U951.58 = __ (20)
y = -x
-1 1
U088 (0)
K .01 + 200% y = -x
.02 K0448
K
– -200% 1 adder with 4 inputs (1-word) {7 µs}
U951.57 = __ (20) 1 switchable sign inverter
2 subtracters (2-word) {6 µs} U086 (0)
K .01
200%
(2-word) {4 µs}
K .02
U951.16 = __ (20) U952.35 = __ (20) .03 + K0446
U094 (0) U095 (0) K U105 (0) U951.90 = __ (20)
.04 -200%
KK .01 + 200%
KK .01 + 200% K B
.02 KK0454 .02 KK0455
KK KK U106 (0)
– -200% – -200% 0
KK
x y KK0465
-1 1
y = -x

1 2 3 4 5 6 7 8
Free blocks fp_vc_725_e.vsd Function diagram
- 725 -
Adders, subtracters, sign inverters 21.08.00 MASTERDRIVES VC
 3 multipliers (1-word) {12 µs} 2 dividers (1-word) {15 µs} 3 high-resolution multipliers/dividers (1-word) {18 µs}

U951.04 = __ (20) U951.05 = __ (20) U951.06 = __ (20) Scaling

U107 (0) U111 (0) x4 y2
.01 x1 .01 x1 y2 = 100% KK0482
K y K y U114 (0)
.02 x2 K0467 K0471 .01 x1
K K .02 x2 K x4
.02 x2 y
x1⋅ x2 When divided by 0 (x2=0): ⋅
x1100%
K (32bit) K0481
.03 <1> (32bit)
100 % x1 > 0 : y = +199,99 % x2 K x1 ⋅ x 2
x1 = 0 : y = 0,00 % y= x4
When divided by 0 (x3=0): x3 (16bit) x3
x1 < 0 : y = -199,99 % x4 > 0 : y = +199,99 %
x4 = 0 : y = 0,00 % Value range of x4 corresponds to -400 % ...+400 %;
U951.59 = __ (20) x4 < 0 : y = -199,99 % it is restricted at KK0482 to the range -200 %...+200 %
U108 (0)
.01 x1 U952.23 = __ (20)
K y U112 (0)
.02 x2 K0468 .01 x1
K K y U951.32 = __ (20) Scaling
x1⋅ x2 .02 x2 K0472 x4 y2
K y2 = 100% KK0484
100 % U115 (0)
When divided by 0 (x2=0): ⋅
x1100% .01 x1
x1 > 0 : y = +199,99 % x2
K x4
.02 x2 y
x1 = 0 : y = 0,00 % K (32bit) K0483
x1 < 0 : y = -199,99 % .03 <1> (32bit)
U952.37 = __ (20) K x1 ⋅ x 2
U109 (0) When divided by 0 (x3=0): y = xx43
.01 x1 x3 (16bit)
K y x4 > 0 : y = +199,99 %
.02 x2 K0469 x4 = 0 : y = 0,00 % Value range of x4 corresponds to -400 % ...+400 %;
K
x4 < 0 : y = -199,99 % it is restricted at KK0484 to the range -200 %...+200 %
x1⋅ x2
100 %

U951.73 = __ (20) Scaling

x4 y2
y2 = 100% KK0486
1 multiplier (2-word) {33 µs} 1 divider (2-word) {70 µs} U116 (0)
.01 x1
K x4
.02 x2 y
K (32bit) K0485
.03 <1> (32bit)
K x1 ⋅ x 2
y= x4
When divided by 0 (x3=0): x3 (16bit) x3
U951.31 = __ (20) U951.43 = __ (20) x4 > 0 : y = +199,99 %
U110 (0) U113 (0) x4 = 0 : y = 0,00 % Value range of x4 corresponds to -400 % ...+400 %;
.01 x1 .01 x1 x4 < 0 : y = -199,99 % it is restricted at KK0486 to the range -200 %...+200 %
K y KK y
.02 x2 KK0470 .02 x2 KK0473
K KK
x1⋅ x2 When divided by 0 (x2=0): ⋅
x1100%
100 % x1 > 0 : y = +199,99 % x2
x1 = 0 : y = 0,00 %
x1 < 0 : y = -199,99 %

1 2 3 4 5 6 7 8
Free blocks fp_vc_730_e.vsd Function diagram
- 730 -
Multipiliers, dividers 02.11.98 MASTERDRIVES VC
 1 high-resolution multiplier/divider New Blocks (from V3.2 and higher)
(2-word) {25 µs}
4 shift multipliers/dividers (2-word)

Number of shift steps Number of shift steps

U405 (0) U951.12 = __ (20) -31 ... +31 -31 ... +31
(32bit) x
KK (48bit) U442.01 (0) U442.03 (0)
y
U406 (1) (16bit) KK0602
.01 a (32bit) n n
K
.02 b n = 0...-31 U953.36 = __ (20) n = 0...-31 U953.38 = __ (20)
K y=(x*a)/b
Sign 31 10 Sign 31 10
0 0
31
U443.01 (0) n = 0...+31 2 -1 U443.03 (0) n = 0...+31 231-1
x y x y
KK KK0618 KK KK0620

y = x * 2n -231-1 y = x * 2n -231-1
2 P-amplifiers/multipliers (2-word)

P amplification
-1000.00 ... 1000.00
U440.01 (1.00)
U953.39 = __ (10)

U441.01 (0) 231-1 Number of shift steps Number of shift steps

KK KK0616 -31 ... +31 -31 ... +31
U442.02 (0) U442.04 (0)
231-1
n n
n = 0...-31 U953.37 = __ (20) n = 0...-31 U952.03 = __ (20)

Sign 31 10 Sign 31 10
0 0
P amplification
-1000.00 ... 1000.00 U443.02 (0) n = 0...+31 231-1 U443.04 (0) n = 0...+31 231-1
x y x y
U440.02 (1.00) KK KK0619 KK KK0621
U951.54 = __ (10)
y = x * 2n -231-1 y = x * 2n -231-1
U441.02 (0) 231-1
KK KK0617
231-1

1 2 3 4 5 6 7 8
Free blocks fp_vc_732_e.vsd Function diagram
- 732 -
Multipliers/dividers, P-amplifiers, shift multipliers 02.11.98 MASTERDRIVES VC
 New Blocks (from V3.2 and higher)
2 Delay elements for analog signals (2-word) {10 µs}
Deceleration cycles Deceleration cycles
0 ... 32 sampling times 0 ... 32 sampling times
U401 (0) U403 (0)
U950.63 = __ (20) U950.64 = __ (20)
T T
U400 (0) T T U402 (0) T T
KK KK0600 KK KK0601

1 differentiator (2-word) {16 µs} 2 settable smoothing elements, high-resoltuion (2-word) {16 µs}
Nominal acceleration time
(during this acc. time dx/dt would be 100 %) Smoothing time Smoothing time
0.01 ... 300.00 s 0 ... 10000 ms 0 ... 10000 ms
U421 (0.01) U415 (0) U418 (0)
U952.32 = __ (20) U952.31 = __ (20) U952.43 = __ (20)

U420 (0) x d U414 (0) x y U417 (0) x y

dx/dt
KK dt KK0607 KK KK0605 KK KK0606

D Portion U416 (0) U419 (0)

Set setting Set setting
B B
command y=x command y=x

2 integrators (2-word) {30...50 µs}

U409 (611) U951.53 = __ (20) U412 (612) U951.85 = __ (20)
K Integral time constant K Integral time constant
Integral time constant Integral time constant
0.000 ... 60.000 s (1000dec = 1 sec) 0.000 ... 60.000 s (1000dec = 1 sec)
K0611 Ti K0612 Ti
U433 (0.000) U434 (0.000)

U408 U411
.01 (0) .01 (0)
KK Input Output KK0603 KK Input Output KK0604

Ti Ti

.02 (0) .02 (0)

KK Upper limit Output to KK Upper limit Output to
.03 (0) B0577 .03 (0) B0579
KK Lower limit upper limit KK Lower limit upper limit
.04 (0) .04 (0)
KK Setting value KK Setting value

Output to Output to
U410 (0) B0578 U413 (0) B0580
lower limit lower limit
B Setting command B Setting command

1 2 3 4 5 6 7 8
Free blocks fp_vc_734_e.vsd Function diagram
- 734 -
Delay elements, differentiator, integrator, smoothing elements 02.11.98 MASTERDRIVES VC
 3 absolute-value generators with smoothing (1-word) {7 µs} 2 limiters (1-word) {5 µs}

U118 (0) Smoothing time const. U129.F

U950.75 = __ (20) 0...3 0...10000 ms (100.00)
U119 (0) U951.74 = __ (20)
B+ y x>B+ B0470
K0503 U130 B+
3 .01 (503)
U117 (0)
-1 K
x K .02 (0) x y K0501
2 x
K -1 K0491
K .03 (502)
1
0 K0502 B-
B- x<B- B0471
-1
U121 (0) Smoothing time const. U131.F
U952.47 = __ (20) 0...3 0...10000 ms (100.00)
U122 (0) U952.38 = __ (20)
B+ y x>B+ B0472
K0506 U132 B+
3 .01 (506)
U120 (0)
-1 K
x K .02 (0) x y K0504
2 x
K -1 K0492
K .03 (505)
1
0 K0505 B-
B- x<B- B0473
-1
U124 (0) Smoothing time const.
U952.67 = __ (20) 0...3 0...10000 ms
U125 (0)

3
U123 (0)
-1
2
K -1 K0493
1
0 1 limiter (2-word) {11 µs}

U133.F
1 absolute-value generators with smoothing (2-word) {10 µs} (100.00)
U952.48 = __ (20)
B+ y x>B+ B0474
U127 (0) Smoothing time const. KK0509 U134 B+
U952.07 = __ (20) 0...3 0...10000 ms .01 (509)
KK
U128 (0) .02 (0)
x KK x x y KK0507
KK .03 (508)
3
U126 (0)
-1 KK0508 B-
B- x<B- B0475
KK -1 2
KK0494 -1
1
0

1 2 3 4 5 6 7 8
Free blocks fp_vc_735_e.vsd Function diagram
- 735 -
Absolute-value generators with smoothing, limiters 02.11.98 MASTERDRIVES VC
 1 limit-value monitor with smoothing (2-word) {24 µs}
Hysteresis
Smoothing time const. 0.00 ... 199.99 %
0...10000 ms U148 (0) U952.68 = __ (20)
U147 (0) KK0516
2 limit-value monitors with smoothing (1-word) {15 µs}
U148 U148
U146
.01 |A|<B U149 (0)
KK A 0 A
KK .02
Hysteresis B B
Smoothing time const. 0.00 ... 199.99 % (515)
0...10000 ms U148 0
U138 (0.00) U951.18 = __ (20)
U137 (0) K0512 A<B
U145 (0.00) KK0515 1 B0478
0 A
U138 U138 -200.00 ... 200.00 % 2
B
U136
.01 |A|<B U139 (0) U148
K A 0 A
K .02 B A=B
B B 0
(511)
U138 0 B U148 A
A<B
U135 (0.00) K0511 1 B0476
0 A
-200.00 ... 200.00 % B 2
U138

B A=B
0
B U138 A 1 limit-value monitor without smoothing (2-word) {18 µs}
Hysteresis
0.00 ... 199.99 %
U152 (0.00) U951.75 = __ (20)
Hysteresis
Smoothing time const. 0.00 ... 199.99 %
0...10000 ms U143 (0.00) U952.49 = __ (20)
K0514 U152 U152
U142 (0)
U151
.01 |A|<B U153 (0)
U143 U143 KK A 0 A
KK .02
U141 B B
.01 |A|<B U144 (0) (517)
K A 0 A U152 0
K .02
B B A<B
(513) U150 (0.00) KK0517 1 B0479
U143 0 0 A
A<B -200.00 ... 200.00 % B 2
U140 (0.00) K0513 1 B0477
0 A U152

-200.00 ... 200.00 % B 2 B

0 A=B
U143
B A
B A=B
U152
0
B U143 A

1 2 3 4 5 6 7 8
Free blocks fp_vc_740_e.vsd Function diagram
- 740 -
Limit-value monitors with and without smoothing 21.08.00 MASTERDRIVES VC
 2 cam-contactor groups each with 2 cams (2-word) {9 µs}

U950.60 = __ (20) ON position 1 OFF position 1 U950.61 = __ (20) ON position 1 OFF position 1
-2 147 483 647.. -2 147 483 647.. Hysteresis -2 147 483 647.. -2 147 483 647.. Hysteresis
..2 147 483 647 ..2 147 483 647 0..2 147 483 647 ..2 147 483 647 ..2 147 483 647 0..2 147 483 647
U154 (0) U160 (0)
U156.F (0) U157.F (0) U155.1 (0) U162.F (0) U163.F (0) U161.1 (0)
KK KK

Y1 Y1

Y1 Y1
B0480 B0482
U155 U155 X U161 U161 X

Y2 Y2
<1> <1>

Y2 Y2
B0481 B0483
U155 U155 X U161 U161 X

<1> <1>
In the case of a round shaft, In the case of a round shaft,
U158.F (0) U159.F (0) U164.F (0) U165.F (0)
a cam overscoring the zero point a cam overscoring the zero point
ON position 2 OFF position 2 ON position 2 OFF position 2
can be realized by ORing can be realized by ORing
-2 147 483 647.. -2 147 483 647.. -2 147 483 647.. -2 147 483 647..
the two cam outputs. the two cam outputs.
..2 147 483 647 ..2 147 483 647 ..2 147 483 647 ..2 147 483 647

U155.2 (0) U161.2 (0)

Axis cycle Axis cycle
0..2 147 483 647 0..2 147 483 647

<1> If the input variable is a rotary axis and a cam passes the axis
cycle jump of the rotary axis, the axis cycle of the rotary axis
has to be entered in parameter U155.2.
To ensure that cam 1 doesn't overlap itself, the hysteresis
must only be half the value of the distance to go between size
of the cam and the axis cycle. If this requirement is not met,
the output binector remains inactive.
<1> If the input variable is a rotary axis and a cam passes the axis
cycle jump of the rotary axis, the axis cycle of the rotary axis
has to be entered in parameter U161.2.
To ensure that cam 1 doesn*t overlap itself, the hysteresis
must only be half the value of the distance to go between size
of the cam and the axis cycle. If this requirement is not met,
the output binector remains inactive.

1 2 3 4 5 6 7 8
Free blocks fp_vc_745_e.vsd Function diagram
- 745 -
Cam-contactor groups 21.07.04 MASTERDRIVES VC
 1 extended cam-contactor group with 2 cams
U950.80 = __ (20)

U437 Hysteresis
U436 .01
Cam3 FSetp1 KK (0) 0..2 147 483 647
.02(0) .02 ON position 1
On position 1 KK0566 KK (566) U436.01 (0)
.03(0) .03 OFF position 1
Off position 1 KK0567 KK (567)
Cam3 FSetp2
Y1

Value range of
On/Off positions:
-2 147 483 647.. Y1
B0484
2 147 483 647 Hyst Hyst X

Y2
<1>

Y2
B0485
Hyst Hyst X

U436 Cam3 FSetp3 U437

.04(0) .04
On position 2 KK0568 KK (568)
.05(0) .05 ON position 2
Off position 2 KK0569 KK (569)
OFF position 2
Cam3 FSetp4

U436.6 (0)
<1> If the input variable is a rotary axis and a cam passes the axis Axis cycle
cycle jump of the rotary axis, the axis cycle of the rotary axis 0..2 147 483 647
has to be entered in parameter U436.6.
To ensure that the cam doesn't overlap itself, the hysteresis
must only be half the value of the distance to go between size
of the cam and the axis cycle. If this requirement is not met,
the output binector remains inactive.

1 2 3 4 5 6 7 8
Free blocks fp_vc_745a_e.vsd Function diagram
- 745a -
Cam-contactor groups 21.07.04 MASTERDRIVES VC
 5 Analog signal switches (1-word) {2 µs} 1 Analog signal multiplexer with 8 channels (2-word) {6 µs}
U166 (0) U950.85 = __ (20) U172 (0) U951.60 = __ (20) U186 U951.78 = __ (20)
.01 (0)
B B B
.02 (0)
B
U167 (0) U173 (0) .03 (0)
.01 0 .01 0 B
K K .04 (1) Signal selector
.02 K0521 .02 K0524 B 0001
K K switch does not
1 1 Memory
ENABLE switch until
ENABLE = 1

U168 (0) U951.19 = __ (20) U174 (0) U951.76 = __ (20) 22 21 20

B B U187 (0) Signal select
.01
KK 0
U169 (0) U175 (0) .02
.01 0 .01 0 KK 1
K K .03
K0522 K0525 KK 2
.02 .02 .04
K K KK 3
1 1 .05 KK0539
KK 4
.06
KK 5
U170 (0) U951.21 = __ (20) .07
KK 6
B .08
KK 7 MUX
U171 (0)
.01 0
K
.02 K0523
K
1

5 Analog signal switches (2-word) {4 µs} 1 Analog signal demultiplexer with 8 channels (2-word) {8 µs}
U176 (0) U950.86 = __ (20) U182 (0) U951.77 = __ (20) U188 U950.62 = __ (20)
.01 (0)
B B B
.02 (0)
B
U177 (0) U183 (0) .03 (0)
.01 0 .01 0 B
KK KK .04 (1) Signal selector
.02 KK0526 .02 KK0529 B 0001
KK KK .05 (0) switch does not
1 1 B Memory
ENABLE switch until
ENABLE = 1

U178 (0) U950.87 = __ (20) U184 (0) U952.08 = __ (20) 22 21 20

B B Signal select
MODE
U189 (0) 0 KK0531
U179 (0) U185 (0)
.01 0 .01 0 KK
KK KK 1 KK0532
.02 KK0527 .02 KK0530 MODE = 0:
KK KK 2 KK0533
1 1 The 7 non-through-connec-
ted output connectors 3 KK0534
are each permanently
U180 (0) U951.20 = __ (20) assigned to the value '0'.
4 KK0535
B MODE = 1: 5 KK0536
The 7 non-through-connected
output connectors remain 6 KK0537
U181 (0) 'frozen' at the old value.
.01 0 DEMUX 7 KK0538
KK
.02 KK0528
KK
1

1 2 3 4 5 6 7 8
Free blocks fp_vc_750_e.vsd Function diagram
- 750 -
Analog signal switches/multiplexers/demultiplexers 02.11.98 MASTERDRIVES VC
 3 characteristic blocks with 10 support values (1-word) {15 µs}

Y values Y values Y values

U192.01 to .10 (0) U195.01 to .10 (0) U198.01 to .10 (0)
U951.07 = __ (20) U951.33 = __ (20) U952.09 = __ (20)
y 10 y 10 y 10
y10 y10 y10
9 9 9
8 8 8
U190 (0) -200% 7 U193 (0) -200% 7 U196 (0) -200% 7
x y x y x y
K x1 x K0541 K x1 x K0542 K x1 x K0543
The distance 5 x10 The distance 5 x10 The distance 5 x10
between 2 adjacent
6 between 2 adjacent
6 between 2 adjacent
6
X or Y values must 23 4 +200% X or Y values must 23 4 +200% X or Y values must 23 4 +200%
not be more than y1 not be more than y1 not be more than y1
199.99 %. 1 199.99 %. 1 199.99 %. 1

U191.01 to .10 (0) U194.01 to .10 (0) U197.01 to .10 (0)

X values X values X values

1 dead zone (1-word) {2 µs}

Dead zone z
U200 (0,00)
U950.88 = __ (20)

U199 (0) -z y
x
K K0544
z x

1 2 3 4 5 6 7 8
Free blocks fp_vc_755_e.vsd Function diagram
- 755 -
Characteristic blocks, dead zone 02.11.98 MASTERDRIVES VC
 1 Maximum selection (2-word) {8 µs} 2 tracking / storage elements (2-word) {6 µs}

U950.76 = __ (20) U952.69 = __ (20)

1 ⇒ y=x 1 ⇒ y=x
U203 (0) ⇒ freeze y U206 (0) ⇒ freeze y
B .01 B .01
Power On Mode Power On Mode
U201 (0) U952.24 = __ (20) .02 .02
B U205 (0) B U208 (0)
KK .01 x1 .03 .03
y B <1> B <1>
KK .02 x2 MAX KK0545 TRACK TRACK
KK .03 x3 U204 (0) U207 (0)
y = Maximum of x1, x2, x3 KK x y KK0551 KK x y KK0552
(e.g. -40 % greater than -50 %)

<1> <1>
U205 = 0: STORE U208 = 0: STORE
No 'non-volatile' No 'non-volatile'
Priority: Priority:
storage storage
U205 = 1:
1. RESET U208 = 1:
1. RESET
'Non-volatile' RESET (y=0) 2. TRACK 'Non-volatile' RESET (y=0) 2. TRACK
storage 3. STORE storage 3. STORE

1 Minimum selection (2-word) {8 µs} 2 analog signal storages (2-word) {4 µs}

U950.77 = __ (20) U952.50 = __ (20)

U210 (0) U212 (0)
SET SET
B B
(y=x) (y=x)
U202 (0) U952.25 = __ (20)
KK .01 x1 U209 (0) U211 (0)
.02 x2 y KK x y KK0553 KK x y KK0554
KK MIN KK0546
KK .03 x3
y = Minimum of x1, x2, x3 RESET RESET
(e.g. -50 % less than -40 %) POWER ON POWER ON
(y=0) (y=0)

1 2 3 4 5 6 7 8
Free blocks fp_vc_760_e.vsd Function diagram
- 760 -
Minimum/maximum selection, tracking/storage elements 02.11.98 MASTERDRIVES VC
 18 AND elements with 3 inputs each {3 µs} 12 OR elements with 3 inputs each {3 µs}
U950.78 = __ (20) U951.44 = __ (20) U952.26 = __ (20) U950.90 = __ (20) U951.93 = __ (20)
U221 (1) U227 (1) U233 (1) U239 (0) U245 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0601 B
.02
.03 & B0607 B
.02
.03 & B0613 B
.02
.03 ≥1 B0619 B
.02
.03 ≥1 B0625
B B B B B

U950.79 = __ (20) U951.61 = __ (20) U952.39 = __ (20) U950.91 = __ (20) U952.10 = __ (20)
U222 (1) U228 (1) U234 (1) U240 (0) U246 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0602 B
.02
.03 & B0608 B
.02
.03 & B0614 B
.02
.03 ≥1 B0620 B
.02
.03 ≥1 B0626
B B B B B

U950.89 = __ (20) U951.62 = __ (20) U952.51 = __ (20) U951.23 = __ (20) U952.11 = __ (20)
U223 (1) U229 (1) U235 (1) U241 (0) U247 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0603 B
.02
.03 & B0609 B
.02
.03 & B0615 B
.02
.03 ≥1 B0621 B
.02
.03 ≥1 B0627
B B B B B

U951.09 = __ (20) U951.79 = __ (20) U952.52 = __ (20) U951.45 = __ (20) U952.40 = __ (20)
U224 (1) U230 (1) U236 (1) U242 (0) U248 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0604 B
.02
.03 & B0610 B
.02
.03 & B0616 B
.02
.03 ≥1 B0622 B
.02
.03 ≥1 B0628
B B B B B

U951.22 = __ (20) U951.80 = __ (20) U952.54 = __ (20) U951.63 = __ (20) U952.70 = __ (20)
U225 (1) U231 (1) U237 (1) U243 (0) U249 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0605 B
.02
.03 & B0611 B
.02
.03 & B0617 B
.02
.03 ≥1 B0623 B
.02
.03 ≥1 B0629
B B B B B

U951.35 = __ (20) U951.92 = __ (20) U952.92 = __ (20) U951.81 = __ (20) U952.93 = __ (20)
U226 (1) U232 (1) U238 (1) U244 (0) U250 (0)
.01 .01 .01 .01 .01
B B B B B
B
.02
.03 & B0606 B
.02
.03 & B0612 B
.02
.03 & B0618 B
.02
.03 ≥1 B0624 B
.02
.03 ≥1 B0630
B B B B B

1 2 3 4 5 6 7 8
Free blocks fp_vc_765_e.vsd Function diagram
- 765 -
AND/OR elements 02.11.98 MASTERDRIVES VC
 10 inverters {2 µs} 8 NAND elements with 3 inputs each {2 µs} 3 EXCLUSIVE OR elements {2 µs}

U951.08 = __ (20) U951.64 = __ (20) U950.92 = __ (20) U952.12 = __ (20) U950.93 = __ (20)
U251 (0) U256 (0) U261 (0) U265 (0) U276 (0)
.01 .01 .01
B 1 B0641 B 1 B0646 B
.02
B
.02
B
=1 B0666
B
.03 & B0681 B
.03 & B0685 B .02
B B

U951.10 = __ (20) U951.94 = __ (20) U951.24 = __ (20) U952.27 = __ (20) U950.96 = __ (20)
U252 (0) U257 (0) U262 (0) U266 (0) U277 (0)
.01 .01 .01
B 1 B0642 B 1 B0647 B
.02
B
.02
B
=1 B0667
B
.03 & B0682 B
.03 & B0686 B .02
B B

U951.11 = __ (20) U952.41 = __ (20) U951.47 = __ (20) U952.42 = __ (20) U952.28 = __ (20)
U253 (0) U258 (0) U263 (0) U267 (0) U278 (0)
.01 .01 .01
B 1 B0643 B 1 B0648 B
.02
B
.02
B
=1 B0668
B
.03 & B0683 B
.03 & B0687 B .02
B B

U951.37 = __ (20) U952.53 = __ (20) U951.95 = __ (20) U952.94 = __ (20)

U254 (0) U259 (0) U264 (0) U268 (0)
.01 .01
B 1 B0644 B 1 B0649 B
.02
B
.02
B
.03 & B0684 B
.03 & B0688
B B

U951.46 = __ (20) U952.55 = __ (20)

U255 (0) U260 (0)
B 1 B0645 B 1 B0650

5 digital signal switches {2 µs}

U950.94 = __ (20) U950.97 = __ (20) U951.48 = __ (20) U951.65 = __ (20) U951.96 = __ (20)
U271 (0) U272 (0) U273 (0) U274 (0) U275 (0)
.01 .01 .01 .01 .01
B B B B B
.02 0 .02 0 .02 0 .02 0 .02 0
B B B B B
.03 B0661 .03 B0662 .03 B0663 .03 B0664 .03 B0665
B B B B B
1 1 1 1 1

1 2 3 4 5 6 7 8
Free blocks fp_vc_770_e.vsd Function diagram
- 770 -
Inverters, NAND elements, EXCLUSIVE OR elements, digital signal switches 02.11.98 MASTERDRIVES VC
 2 D flipflops {5 µs} 12 RS flipflops {3 µs}

U951.25 = __ (20) U951.34 = __ (20) Priority: 1. RESET, 2. SET U951.82 = __ (20) Priority: 1. RESET, 2. SET U952.14 = __ (20) Priority: 1. RESET, 2. SET

U281 (0) U285 (0) U289 (0)

.01 SET .01 SET .01 SET
U279 (0) SET (Q=1) B Q B0501 B Q B0509 B Q B0517
.01 .02 (Q=1) .02 (Q=1) .02 (Q=1)
B B B B
B .02 D Q B0525
B .03 RESET RESET RESET
.04 ≥1 (Q=0) Q
B0502 ≥1 (Q=0) Q
B0510 ≥1 (Q=0) Q
B0518
B POWER ON POWER ON POWER ON
STORE
Priority:
1. RESET Q B0526 U951.36 = __ (20) Priority: 1. RESET, 2. SET U951.97 = __ (20) Priority: 1. RESET, 2. SET U952.29 = __ (20) Priority: 1. RESET, 2. SET
2. SET
3. STORE RESET (Q=0) U282 (0) U286 (0) U290 (0)
.01 SET .01 SET .01 SET
B Q B0503 B Q B0511 B Q B0519
.02 (Q=1) .02 (Q=1) .02 (Q=1)
B B B
≥1
POWER ON RESET RESET RESET
≥1 (Q=0) Q
B0504 ≥1 (Q=0) Q
B0512 ≥1 (Q=0) Q
B0520
POWER ON POWER ON POWER ON

U951.49 = __ (20) Priority: 1. RESET, 2. SET U951.98 = __ (20) Priority: 1. RESET, 2. SET U952.30 = __ (20) Priority: 1. RESET, 2. SET

U283 (0) U287 (0) U291 (0)

.01 SET .01 SET .01 SET
B Q B0505 B Q B0513 B Q B0521
U952.15 = __ (20) .02 (Q=1) .02 (Q=1) .02 (Q=1)
B B B

RESET RESET RESET

U280 (0) SET (Q=1) ≥1 (Q=0)
Q B0506 ≥1 (Q=0)
Q B0514 ≥1 (Q=0)
Q B0522
B .01 POWER ON POWER ON POWER ON
B .02 D Q B0527
B .03
B .04 U951.66 = __ (20) Priority: 1. RESET, 2. SET U952.13 = __ (20) Priority: 1. RESET, 2. SET U952.71 = __ (20) Priority: 1. RESET, 2. SET
STORE U284 (0) U288 (0) U292 (0)
Priority: .01 SET .01 SET .01 SET
1. RESET Q B0528 B Q B0507 B Q B0515 B Q B0523
.02 (Q=1) .02 (Q=1) .02 (Q=1)
2. SET B B B
3. STORE RESET (Q=0)
RESET RESET RESET
≥1 (Q=0) Q
B0508 ≥1 (Q=0) Q
B0516 ≥1 (Q=0) Q
B0524
POWER ON POWER ON POWER ON
≥1
POWER ON

1 2 3 4 5 6 7 8
Free blocks fp_vc_775_e.vsd Function diagram
- 775 -
D and RS flipflops 02.11.98 MASTERDRIVES VC
 4 timers 0...60.000 s {11 µs} 2 timers 0...600.00 s {11 µs} 1 timer 0...60.000 s with adaption {21 µs}
U294.F (0.000) Mode U306.F (0.00) Mode
0.000...60.000 s U295 (0) 0.00...600.00 s U307 (0)
U950.95 = __ (20) U951.83 = __ (20)
T T
ON delay ON delay
T 0 0 T 0 0

OFF delay OFF delay

0 T 1 0 T 1
U293 (0) U305 (0)
B B0530 B B0538
ON/OFF delay ON/OFF delay
2 2 U313.F (0,000)
T T T T 0,000...60,000 s

1 B0531 1 B0539 T
Pulse generator Pulse generator
3 3 U312 (0) 1 U951.50 = __ (20)
T T K

⋅
x1T1
Mode
100 % P314 (0)
U297.F (0.000) Mode U309.F (0.00) Mode
T
0.000...60.000 s U298 (0) 0.00...600.00 s U310 (0)
U951.67 = __ (20) U952.16 = __ (20)
T T ON delay
ON delay ON delay T 0 0
T 0 0 T 0 0

OFF delay
OFF delay OFF delay 0 T 1
0 T 1 0 T 1 U311 (0)
U296 (0) U308 (0)
B B0542
B B0532 B B0540 ON/OFF delay
ON/OFF delay ON/OFF delay
2 2 T T 2
T T T T
1 B0543
Pulse generator 1 B0533 Pulse generator 1 B0541 Pulse generator
T 3 T 3 T 3

<1> Example: T1 = 40.000 s, x1 = 150 %

U300.F (0.000) Mode U303.F (0.000) Mode -> effective time T = 60 s
0.000...60.000 s U301 (0) 0.000...60.000 s U304 (0) T is limited to the value range 0...60.000 s.
U951.84 = __ (20) U951.99 = __ (20)
T T
ON delay ON delay
T 0 0 T 0 0

OFF delay OFF delay

0 T 1 0 T 1
U299 (0) U302 (0)
B B0534 B B0536
ON/OFF delay ON/OFF delay
T T 2 T T 2

Pulse generator 1 B0535 Pulse generator 1 B0537

T 3 T 3

1 2 3 4 5 6 7 8
Free blocks fp_vc_780_e.vsd Function diagram
- 780 -
Timers 02.11.98 MASTERDRIVES VC
 New Blocks (from V3.2 and higher)
1 Pulse generator (flash encoder) {5 µs / 15 µs if Tp is changed} 6 sampling time changers for control signals {1 µs}

U950.66 = __ (20) U950.69 = __ (20)

U404.01 (0) U404.04 (0)
B 1 B0570 B 1 B0573
U407 (613) U950.65 = __ (20)
K
Period Tp
0 ... 60000 ms K0613
U435 (0) U950.67 = __ (20) U950.70 = __ (20)
Sampling ratio 1:1 Tp
Max. output frequency B0576
U404.02 (0) U404.05 (0)
1/(2 x sampling time) B 1 B0571 B 1 B0574

Note: The implemented period Tp is always an integral U950.68 = __ (20) U950.71 = __ (20)
multiple of (2 x sampling time). U404.03 (0) U404.06 (0)
Example: Tab = 3.2 ms B 1 B0572 B 1 B0575
Tp = 10 ms
Implemented period = 6.4 ms
The block does not have any logic function.
It only transfers a digital signal consistently from
a faster sampling time to a slower one.
The block ensures that the signal has the same
value in the slow sampling time for all
"consumers" (signal sinks).

1 2 3 4 5 6 7 8
Free blocks fp_vc_782_e.vsd Function diagram
- 782 -
Pulse generator, sampling time changers 02.11.98 MASTERDRIVES VC
 Sampling interval slower time slot Sampling interval slower time slot Sampling interval slower time slot
2 ... 10 2 ... 10 2 ... 10
Sampling interval U060 (2) Sampling interval U270 (2) Sampling interval U349 (2)
faster time slot faster time slot faster time slot
U951.68 = ___(20) U951.69 = ___(20) U951.70 = ___(20)

Tx Ty Tx Ty Tx Ty

Q. SH1 KK Q. SH2 KK Q. SH3 KK

U019 S&H U029 S&H U346 S&H
KK .01 KK0640 KK .01 KK0652 KK .01 KK0664
KK .02 KK0641 KK .02 KK0653 KK .02 KK0665
KK .03 KK0642 KK .03 KK0654 KK .03 KK0666
KK .04 KK0643 KK .04 KK0655 KK .04 KK0667

Q. SH1 K Q. SH2 K Q. SH3 K

U020 U030 U347
K .01 K0644 K .01 K0656 K .01 K0668
K .02 K0645 K .02 K0657 K .02 K0669
K .03 K0646 K .03 K0658 K .03 K0670
K .04 K0647 K .04 K0659 K .04 K0671
K .05 K0648 K .05 K0660 K .05 K0672
K .06 K0649 K .06 K0661 K .06 K0673
K .07 K .07 K0662 K .07 K0674
K .08 K .08 K0663 K .08 K0675

Q. SH1 B Q. SH2 B Q. SH3 B

U059 U269 U348
B .01 B0631 B .01 B0651 B .01 B0669
B .02 B0632 B .02 B0652 B .02 B0670
B .03 B0633 B .03 B0653 B .03 B0671
B .04 B0634 B .04 B0654 B .04 B0672
B .05 B0635 B .05 B0655 B .05 B0673
B .06 B0636 B .06 B0656 B .06 B0674
B .07 B0637 B .07 B0657 B .07 B0675
B .08 B0638 B .08 B0658 B .08 B0676

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Free blocks fp_vc_783_e.vsd Function diagram
- 783 -
Sample & Hold 12.05.03 MASTERDRIVES VC
 Tension setpoint
U717.3 U951.86 = ___(20)
Diameter in %
Winding pressure Tension setpoint
KK0556
K0550 Tension torque Additional torque setpoint
U717.4
+

Diameter in LU Acceleration torque

U717.5=557 Machine acceleration

Winding characteristic
Acceleration precontrol factor
KK0559
J.total in %
U953.49 = ___(20) KK0558

P232=555
Moment of inertia calculation
KP adaption
FP327 U718.3=556 FD360
Machine speed FD318 P262
FP328
V Speed setpoint
Local + + +
setpoints P438=588 – –
P440=555
Diameter in % Diameter factor
Dancer control KK0556 KK0555
Technology controller
FD791 FD792 U953.47 = ___(20)
+ Winding speed
– U178.2=91
M
Machine speed v n Diameter in LU
D
U718.1 K0557

Diameter calculator

Dancer position

FD81 / FD83
P640=550 D U
A P
Setting
dancer power

1 2 3 4 5 6 7 8
Free blocks fp_vc_784a_e.vsd Function diagram
- 784a -
Overview of axial winder with dancer control 30.06.06 MASTERDRIVES VC
 SymmetryD FilterRawD D.minNormD
0 ... 1000ms 0 ... 60000ms 1 ... 65535 U953.47 = ___(20)
U716.2 (0) U716.1 (100) U714.1 (100)
0 D.FactorD
SrcAxialWinderKK
U718 KK0555
v web D KK (0) .1 Plausibility check -1 1 Multiplicator for
PlausPosD
Web speed setpoint channel
B0553 SrcAxialWinderB
Tol FactorD U719.3 (0)
n web D KK (091) .2
1 ... 65535 PlausNegD .3
Winding shaft speed B
U714.9 (5) B0554 D.maxLimD
WindBottomD
MatThickD 1 ... 65535
0.000 ... 65.534 U714.4 (1000)
U712 (0.000) ∆D/∆T D.actD[LU]
n NormD MaxLimitD n706
y
0 ... 65535 rpm Diameter B0557 D.actDLU
v n U707 (0) memory x K0557
D
n minD B0558 Diameter in LU
0.000 ... 200.000% MinLimitD
n < n.min
U715.2 (1.000)
D.actD%
v minD D.minLimD KK0556
0.000 ... 200.000%
U715.1 (1.000)
v < v.min ≥1 hold
1 ... 65535
U714.3 (100)
Diameter in %

SrcAxialWinderB D.maxNormD
U719 (0) .1 1 ... 65535
D.holdD B U714.2 (1000)

D.setD B .2 set Diameter calculator

SrcAxialWinderK {112 µs} without plausibility check
U717 {146 µs} with plausibility check
D.SetValD LU K (0) .6 Setting value

D.minNormJ JCoreJ
Moment of inertia {71 µs} 1 ... 65535 0.000 ... 200.000% U953.49 = ___(20) Winding pressure {35 µs} U951.86 = ___(20)
U714.7 (100) U715.3 (0.000) D.minTP CharacteristicTP D.maxTP
SrcAxialWinderK 1 ... 65535 0 ... 1 1 ... 65535
MatWidthJ MatWidthJ U717 U714.5 (100) U711 (1) U714.6 (1000)
0.00 ... 200.00% K0540 K (540) .1
U713.1 (100.00) MatConstJ
.2 J.TotalJ
K0560 K (560) J.Total KK0558 SrcAxialWinderK <2>
SrcAxialWinderKK 0 Acc.FactorJ U717
U718 TensionSetp TP % K (0) .3
.3 <1> KK0559 .4 Tension
ThicknessJ D.actJ KK (556) -1 WindPressTP % K (0)
1
D.actTP LU K (557) .5 setpoint TP
0.00 ... 200.00%
K0550
U713.2 (100.00) D.maxNormJ JFixedJ
ScalingJ
1 ... 65535 0.000 ... 200.000% SrcAxialWinderB
0.00 ... 200.00% <2>
U714.8 (1000) U715.4 (0.000)
U713.3 (0.00) U719 (0) Characteristic = 0
WindBottomJ B .4
Characteristic = 1
  D.minNormJ  
4
<1> J.totalJ = D.actJ4 −  ∗ 100%   ∗ MatWidthJ ∗ ThicknessJ * ScalingJ + J.CoreJ + J.FixedJ
  D.maxNormJ  


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Free blocks fp_vc_784b_e.vsd Function diagram
- 784b -
Axial winder 08.09.04 MASTERDRIVES VC
 U951.38 = ___(20)
Software counter 16 bit (maximum counting frequency: 1/sampling time) {8 µs}
<3>

Counter output
U317 0...65535
.01 (0) Count up n318
B
Priority: & UP
OUT K0565
1. Enable counter
2. Set counter .02 (0) Count down
3. Stop counter B
4. Count up/down .03 (0) Stop counter & DOWN
B 1
.04 (0) Set counter (Binary code)
B
.05 (1) Enable counter
B 1

Counter minimum value U316 Set counter to

.01 (561) Minimum value minimum
0 ... 65535 K0561 K Overflow B0490
U315.1 (0) value

Counter maximum value

.02 (562) Maximum value
0 ... 65535 K0562 K Underflow B0491
U315.2 (65535)
Counter setting value Set counter to
.03 (563) Setting value <2>
0 ... 65535 K0563 K setting value
U315.3 (0)
Counter starting value
.04 (564) Starting value <2> Set counter to
0 ... 65535 K0564 K
U315.4 (0) starting value

Example: Minimum value = 2, Maximum value = 7

POWER ON <1>
[X4.4] 7 7 7 7
6 6 6 6
Counter output 5 5 5 5
4 4 4 4 4
3 3 3 3 3
2 2 2 2
<1>After POWER ON the counter is set to the starting value. Count up

<2>Starting value and setting value are limited to the range (minimum value... maximum value). Count down
2 2
<3>Example: The counter is operating in the 3.2 ms time slot -> max. counting frequency 310 Hz. Overflow
Attention: The sampling time and sampling sequence of the upstream signal processing has to be taking into account! 7 7
Underflow

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Free blocks fp_vc_785_e.vsd Function diagram
- 785 -
Software counter 02.11.98 MASTERDRIVES VC
 Acceleration time Unit for accel. time Deceleration time Unit for decel. time Initial rounding Final rounding
U951.51 = ___(20)
0.0...999.9 0=s, 1=min, 2=h 0.0...999.9 0=s, 1=min, 2=h 0.00...10.00 s 0.00...10.00 s
U330.F (10.0) U331.F (0) U332.F (10.0) U333.F (0) U334.F (0.00) U335.F (0.00) {70 µs}
Adaption of acceleration/deceleration time
U329 (1) <4> 0s 0s Without rounding and adaption
K 0.2 %
0 1 0 1 {130 µs}
With rounding and adaption
Bypass ramp-function generator (y:=x) 0s 0s
U328 (0) 0 1 0 1 Quick stop time
<1> <6>
B 0.0...999.9 s
U337.F (10.0)
0.0...+200.0 %
Quick stop comfort RGen U342 (100.0)
U343 (573)
U338 (0) 0 1 B+
<6> K0573 K
Ramp-function generator input B
U320 (0) 0...3599640.0 s Output limitation
KK
n339.01 n339.02 U344 (574)
0 n326 B-
0
-1 K0574 K
[790.8] (RGen output)
KK0571 KK0570 Tup Tdn AR ER
1
y Tup Tdn
0% 1 B+
U321 (0) (Freeze y)
100 % Comfort ramp-function generator n340
x
B y
Stop RGen KK0571
U322 (0) Bring RGen to a standstill RGen output
B <5>
t B-
U323 (0) <3>
Ramp-function generator setting value
KK Track RGen
Rated acceleration time (with this acceleration time
U324 (0) Set RGen (y = setting value) 0.01 ... 300.00 s dy/dt = 100 %)
B -100 % U336 (0.01)
y AR ER AR ER AR ER AR ER n341

dy/dt
U327 (0) Operating mode for rounding KK0572
0: Final rounding does not act upon sudden reduction t
of the input value during acceleration y=0
Tup_eff <2> B0550 Ramp-function generator output = 0
1: Rounding always acts (except when output limitation y=x
has responded). If there is a sudden reduction of the B0551 Acceleration finished
Rounding Mode Tdn_eff <2> y=0
input value, overshooting can occur.
<1>
1 = Enable ramp-function generator R Q B0552
U345 U325 (1) <6>
.01 0 = Set ramp-function generator to zero 0 = RGen initial runs
Selection of function data set B (92) B
for comfort ramp-function generator B (93) .02
POWER ON 1 S
<1> At U328 = 552 the RGen only acts once in each case after enabling (^ edge) [710.5] Priority: <6> Priority of control commands:
<2> Effective accel.time: Tup_eff = Tup * adaption factor + (AR/2 + ER/2)/adaption factor 1. S (SET) 1. Set RGen to zero
Effective decel.time: Tdn_eff = Tdn * adaption factor + (AR/2 + ER/2)/adaption factor 2. R (RESET) 2. Quick stop comfort RGen
(If adaption is used, the jerk remains the same) 3. Set ramp-function generator
<3> Ramp-function generator is tracked when a limitation responds (y:=RGen output) 4. Bypass RGen (y:=x)
<4> Rounding and adaption do not act with the 'min' or 'h' unit for accel./decel. time 5. Bring RGen to a standstill
<5> Rounding also acts during a zero passage 6. Stop ramp-function generator

1 2 3 4 5 6 7 8
Free blocks fp_vc_790_e.vsd Function diagram
- 790 -
Comfort ramp-function generator 12.10.01 MASTERDRIVES VC
 U951.87 = __ (20)

Simple ramp-function generator {12 µs}

Acceleration time Deceleration time
0.00...100.00 0.00...100.00
U383.01 (10.00) U383.02 (10.00)

U380 (0)
K x y K0577

Set simple ramp-function generator

U381 (0)
B
Setting value of simple RGen
U382 (0)
K

If you wish to use the simple ramp-function generator as a setpoint ramp function generator
for the technology controller, the following signal connection can be recommended:
- Output of simple ramp-function generator ==> Setpoint input of technology controller (U352 = 577) [792.1]
- Technology controller disabled ==> Set simple ramp-function generator (U381 = 556) [792.3]
- Actual-value technology controller ==> Setting value of simple ramp-function generator (U382 = value of U335) [792.1]

1 2 3 4 5 6 7 8
Free blocks fp_vc_791_e.vsd Function diagram
- 791 -
Simple ramp-function generator 02.11.98 MASTERDRIVES VC
 Smoothing time constant U952.01 = ___(20)
0.00 ... 60.00 s
U353 (0.00)
<4> Basic gain Effective gain Integral time {50 µs}
0.00 ... 125.00 (-250.00...+250.00) 0.00 ... 100.00
TeCntr Setp U364.F (3.00) n365 U366.F (3.00) Precontrol signal
U352 (0) x y Gain adaption
<1> U386 (0)
K n354 U363 (1) K
Droop K
U362 (0)
Controller type K P-Component
0 ... 1
KP Tn K0583
U351 (1) 0 1
0 = normal PID controller I-Component <3>
1 = PI controller with D-component <2> Technology controller K0584
in actual-value channel Smoothing time constant Controller output
0.00 ... 60.00 s Output technology controller
K0585
U358 (0.00) n372
y
n356 n357 n359 B+
TeCntr ActV –
U355 (0) + + +
x x y
K IN OUT K0588
– + + +
D-Component B-
d D-Component
B0555
K0580 dt K0582 K0581

Set I-component
<1> <5> U360 (556) Message "Technology
controller to output limitation"
Derivation time B0556 B
0.00 ... 60.00 s
U367.F (0.00) SetV I-Comp
U361 (0)
If output limitation responds, track the
K
I-component in such a manner that |x| ≥ |y|

Technology controller disabled

Enable technology controller <3>
1 Enable limitation
U350 (0)
At "0" signal: OUT = 0 ramp-function generator
B

<1>Tv = 0 ==> D-component disabled

Tn = 0 ==> I-component disabled (acts as Tn = ∞) Normally the output limitation is set via U369
<2>Open signal path = 0 % and acts instantaneously and symmetrically
<3>Priority of the control signals for setting the controller output K0585: (same limit values for positive and
1. "Enable technology controller" = 0 negative variables)
2. "Set I-component" = 1 U370
0.0 ... 200.0 % .01 (586) If parameterized correspondingly, the 2
(However: Setting the I-component also acts on K0585 when K0586 K limitation ramp-function generators enable
U369 (100.0 %) .02 (587)
controller is disabled) K0587 K smooth approach or the output limits after
<4>Use the simple ramp-function generator on sheet 791, the technology controller has been enabled.
if you wish to avoid an abrupt switch-in -1
of the "TeCntr setpoint".
<5>With U360 = 556, the "Setting value I-component" is adopted Accel/Decel time
when "Enable technology controller" is activated. 0.00 ... 100.00 s
U371 (0.00)

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Free blocks fp_vc_792_e.vsd Function diagram
- 792 -
Technology controller 02.11.98 MASTERDRIVES VC
 U952.02 = ___(20)
(Time portion of the rising edge)
Wobble amplitude Wobble frequency Phase displacement P skip negative P skip positive Duty factor
0.00 ... 20.00 % 0.1 ... 120.0 1/min 0 ... 360 °el 0.00 ... 100.00 % 0.00 ... 100.00 % 0 ... 100 %
U393.F (0.00) U394.F (60.0) U395.F (360) U396.F (0.00) U397.F (0.00) U398.F (50) Wobble generator {83 µs}
<1>

Wobble - synchronizing input

Synchronizing signal from master

U391 (0)
B
Wobble enable
U395 U395 Wobbling always commences with a
positive zero passage and always
ends with the next zero passage
U392 (0)
Wobble - delta generator B
U398
OUT
U393
U396
n399

Setpoint, unwobbled 0% 0 Wobble signal

U390 (0) K0590
OUT
K IN
1

+ Setpoint, wobbled
K0591
U397 +
-U393
U394

Wobble - synchronizing output

Synchronizing signal to slave

B0560

<1>at U395 = 360:

0.5 x Tw Synchronizing signal from master is not taken
notice of (freewheeling wobbling).

1 2 3 4 5 6 7 8
Free blocks fp_vc_795_e.vsd Function diagram
- 795 -
Wobble generator 03.07.00 MASTERDRIVES VC
 U953.70 = ___(20)
Only the values 20 and 02 are permitted.
To avoid overlaps, the usual trace must
be switched off with U953.72 = 20.

PRBS shift div.

To be set by means of the 0..10
DriveMonitor mask U476.1/2 (0)
Diagnostics/trace: Trace
settings. Start noise and
trace with the
Start button !
Mean value Averaging of cycles by addition
first period
Src.Trace input – +
U480.01 (0) + +
KK >> Channel 1 (System output)
A032 Export trace file in ASCII
format to DriveMonitor. Data
Src.Trace input
U480.02 (0) +
Alarm
Overflow
Trace memory DriveMonitor
analysis is the user's respon-
+ sibility.
KK >> Channel 2 (System input / PRBS)
–
+
Mean value
first period

TraceStatusStart
0..2 Start measuring, number of channels
U488.1/2 (0) Noise output
-1 K0630
Trace double word
0..1 Trace words or double words
U481.1 (0)
PRBS cycles CntD
n479
Number of cycles

U477 (1.00 %) U478 (20)

0.00 ... 100.00 % 0 ... 200
PRBS ampl PRBS cycles

PILOT VERSION 3.4

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Free blocks fp_vc_796_e.vsd Function diagram
- 796 -
PRBS (Pseudo Random Binary Sequence) - Signal with Trace 21.07.04 MASTERDRIVES VC
 Trace: cyclical output channel 1 to 8

Record Trace U952.72 = __ (20) U952.96 = __ (20)

Trigger Thresh Trigger BitNr. Trigger Cond Pre Trigger TriggerStatusStart TraceTriggerOut TraceTriggerOut
-231 ... (231-1) 0 ... 16 0 ... 6 0 ... 100 % 0 ... 2 B0561 B0565
U484.01...08 (0) U485.01...08 (16) U486.01...08 (0) U487.01...08 (0) U488.01...08 (0)
Trace memory Trace memory
Src Trigger In Channel 1 TraceValOut Channel 5 TraceValOut
U483 KK0592 KK0596
.01
KK
.02
KK
.03
KK
.04
KK
.05
KK U952.73 = __ (20) U952.97 = __ (20)
.06
KK
.07
KK
.08
KK TraceTriggerOut TraceTriggerOut
B0562 B0566
Src B Trigger In
U489 Trace memory Trace memory
.01 Channel 2 TraceValOut Channel 6 TraceValOut
B
.02 KK0593 KK0597
B
.03
B
.04 Channel 1 to 8
B
B
.05 Trace memory
.06
B
.07 U952.74 = __ (20) U952.98 = __ (20)
B
.08
B

Src Trace In TraceTriggerOut TraceTriggerOut

U480 B0563 B0567
.01
KK Trace memory Trace memory
.02
KK
.03
Channel 3 TraceValOut Channel 7 TraceValOut
KK KK0594 KK0598
.04
KK
.05
KK
.06
KK
.07
KK
.08
KK U952.95 = __ (20) U952.99 = __ (20)

U953.72 = 2
Only parameter value = 2 or 20 TraceDoubleWord TraceSamplingTime TraceTriggerOut TraceTriggerOut
is permissible 0 ... 1 1 ... 200 B0564 B0568
U481.01...08 (0) U482.01...08 (1) Trace memory Trace memory
The trace memory has a total size of 8192 words. Channel 4 TraceValOut Channel 8 TraceValOut
Memory depth per channel = 8192 words / number of activated channels. KK0595 KK0599
Binector trigger input U489 from V3.3
Trace function detachable (U953.72) from V3.4

1 2 3 4 5 6 7 8
Free blocks fp_vc_797_e.vsd Function diagram
- 797 -
Trace: Record Trace / cyclical output 21.07.04 MASTERDRIVES VC
 5 Connector-to-parameter/ parameter-to-connector converters n959.76 = 6

Only parameters of the CU (Pxxx, rxxx, Uxxx, nxxx) can be Block is not calculated in T6!
converted. Parameters of the technology boards Time of processing of block is not defined!
T100, T300, T400 (Hxxx, Lxxx) are not processed.
Parameter Connector
<5> SrcConnToParParNo Index 1 ConnToParValue
<5> ConnToPar ParNo U438.1..5 (479) Parameter value KK0474
Parameter
0 ... 2999 K0479 K
number
Index = Read Write
U445.1...5 (0) <1> Enable Enable Write Value EEPROM Index 2 KK0475
Select parameter SrcConnToParIndex
ConnToPar Index U439.1...5 (480) Index 3 KK0476
0 ... 255 K0480 K
U446.1...5 (0) <1> 1 Index 4 KK0477

SrcParToConnRead Index 5 KK0478

Direction of conversion: 0 = Connector-to-parameter conversion
Select direction of U449.1...5 (0)
1 = Parameter-to-connector conversion
conversion B

SrcConnToPParTrig
U447.1...5 (0) Carry out conversion <3>
Carry out conversion
B

SrcConnToParVal ConnToParChkb
U444.1...5 (0) Value to be entered in the selected parameter <2> Connector B0544 Index 1
Relevant in the case of KK
connector-to-parameter
SrcConnToParEEPROM B0545 Index 2
conversion
U448.1...5 (0) Type of memory: 0/1 = Storage im RAM / EEPROM <4>
B B0546 Index 3

<1> Internally, the parameter numbers or the indices of all five index places (1 to 5) are passed B0547 Index 4
on via the connector. Only the value of the first index is displayed via the connector. Important:
<2> Word parameter should be written via connectors, Parameters must be specified in Index 5
and double-word parameters via double connectors. B0548
decimal form (incl. decimal
<3> Consult the parameter list in the Compendium to find out the operating states places) and are signalled back in 1 = Parameter transfer OK
in which a parameter change can be made. decimal form as well (PKW 0 = Parameter transfer not OK
Value entered in parameter <2>: <4> In the case of dynamic signals, the RAM must be used for storage normalization).
(a parameter can only be written 100 000 times in the EPROM)
Double connector <5> U and n parameters are addressed with Uxxx = 2xxx and nxxx=2xxx .
KKxxxx K K
1 Example of connector-to-parameter conversion: 2 Another example of connector-to-parameter conversion: 3 Example of parameter-to-connector conversion:
HW LW The value of connector K0409 should be fed to The parameter "Source n/f (act)" is to be set to Parameter P103 is to be connected to connector
Double-word parameter: parameter U279.02. Alteration in the RAM ==> 94 (corresponds to SBP setpoint channel 1) ==> KK0477 ==>
- U445.1=2279 (parameter number) - U445.1 = 222 - U444.4 = 477
Word parameter HW - U446.1=2 (index) - U446.1 = 1 - U445.4=103 (parameter number)
- U449.1=0 (connector-parameter conversion) - U449.1 = 0 - U446.4=0 (non-indexed parameter)
Connector - U447.1=1 (permanent transfer) - U447.1 = 1 - U449.4=1 (parameter-connector conversion)
Kxxxx K 0 - U444.1=409 (source connector) - U444.1=409 (source connector) - U447.4=1 (permanent output)
- U448.1=0 (write into the RAM) - U448.1=0 (write into the RAM)
Double-word parameter: HW 0 For this purpose, set U009 = 148 (= 94 Hex, as source connector) !
Please note that the values of "source" parameters are always hexadecimal values. Thus in U009 the
Word parameter: HW converted decimal value has to be provided.

1 2 3 4 5 6 7 8
Free blocks fp_vc_798_e.vsd Function diagram
- 798 -
Connector-to-parameter converter 12.05.03 MASTERDRIVES VC