Field Effect Transistors MOSFET Symbols

• MOSFET = METAL-OXIDE-SEMICONDUCTOR FET

N-channel N-channel P-channel P-channel
Enh. Mode Depl. Mode Enh. Mode Depl. Mode
• Four types: • N- or P-channel ENHANCEMENT MODE
• N- or P-channel DEPLETION MODE D D

• Physical Structure (N-channel, Enhancement Mode) Standard

B B
Symbol G G
Gate (G)
Source (S) Drain (D) S
S
D D
n+ Channel region n+ Simplified
= Oxide
= Metal
Symbol G G
p-type substrate

S S
Body (B)

• STANDARD SYMBOLS:
• Operation (simplified picture)
• Arrow on B indicates polarity of p-n junction formed between
• +ve voltage applied to GATE creates an electric field in the substrate and channel
underlying p-type region; this tends to force holes down into the
substrate, and attract electrons towards the surface • Position of G terminal distinguishes S from D
• Line representing channel is:
• For small VGS, the underlying region remains p-type, and no current
• Broken for Enh. Mode (channel normally OFF)
can flow between SOURCE and DRAIN
• Full for Depl. Mode (channel normally ON)
• For larger VGS, region near surface becomes inverted (i.e. changes
• SIMPLIFIED SYMBOLS (S & B connected):
from p-type to n-type), and an n-type CHANNEL is created. This
provides a current path between S and D
• Arrow on S:
• Appreciable channel conduction occurs only when VGS exceeds • Indicates normal direction of current flow in S
THRESHOLD VOLTAGE Vt (cf. arrow on BJT emitter)
• Distinguishes S from D
• Depletion mode device is similar, but has a built-in channel, so • Line representing channel is:
conduction can occur even when VGS = 0
• Thin for Enh. Mode
• Thick for Depl. Mode
NB: GATE is ELECTRICALLY ISOLATED by oxide layer, so
IG = 0; MOSFET is a voltage-controlled device !
• P-channel symbols obtained by reversing arrows

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 1 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 2
 MOSFET Operation - 1 MOSFET Operation - 2
TRIODE or LINEAR REGION SATURATION or ACTIVE REGION
(VGS > Vt , VDS < VGS - Vt) (VGS > Vt , VDS  VGS - Vt)

• If VDS continues to increase, the effective gate voltage at the drain end
• For small VDS, channel behaves as a linear resistance, with conductance eventually drops to Vt, and the channel “PINCHES OFF”:
proportional to (VGS - Vt):
VGS > Vt VVDS GS
DS==VVGS- Vt
ID
S
VGS > Vt IDsat
VDS small
ID n+ n+
S ID
p Pinch-off point
n+ n+ VDS
VDSsat
p n-Channel VGS - Vt
VDS
• This occurs when VGD = Vt or, equivalently:

VDS = VGS - Vt “pinch-off voltage” (3.3)

However: • Further increases in VDS beyond this point have little effect on ID:
• Linear behaviour breaks down as VDS increases, because the volt-
VGS > Vt VVDS
DS>>VVGS - Vt
DSsat
drop along the channel reduces the effective gate voltage towards the ID
drain end. This effect, which can be pictured as a tapering of the S
IDsat
channel, leads to an increase in the channel resistance
n+ n+
Analysis shows: (see Devices Lectures) p Pinch-off point
VDS
ID = K[ 2(VGS - Vt)VDS - VDS2 ] (3.2)
• Drain current in saturation region is obtained by substituting
VDS = (VGS - Vt) into Equn 3.2. This gives:
• K = CONDUCTIVITY PARAMETER
ID = K (VGS - Vt )2 = IDsat (3.4)
= (Cox e/2).(W/L)
NB: The term SATURATION has two quite different meanings
depending on whether we are discussing MOSFETs or BJTs. In fact
the saturation region of a MOSFET is equivalent to the active
region of a BJT. Sorry about this!

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 3 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 4
 MOSFET Operating Curves - 1 MOSFET Operating Curves - 2

• INPUT-OUTPUT ID vs VGS in saturation

• OUTPUT ID vs VDS
• N-Channel, Enh. Mode:
ID (mA)
20 SAT
TRIODE VGS = Vt + 8
ID (mA) VDS  VGS - Vt
K = 0.25 mA/V2 ID
20
15 VA = 100 V
D
K = 0.5 mA/V2 ID
15 Vt = 2 V G
D VGS = Vt + 6 VDS
10
G S
10 VDS
VGS
VGS = Vt + 4
S 5
5 VGS VGS = Vt + 2
VGS  Vt
0 VDS (V)
VGS (V) 0 5 10 15 20 25 30
-4 -2 0 2 4 6 8 10

• N-channel, Depl. Mode: • Boundary line between triode and saturation regions has the equation
ID = KVDS2 (i.e. Equn 3.4 with VDS = VGS - Vt)

ID (mA) VDS  VGS - Vt

20 • Finite slope of curves in saturation region arises from CHANNEL
ID LENGTH MODULATION
K = 0.5 mA/V2
15 Vt = - 2 V D
• Equn 3.4 becomes:
G
10 VDS
ID = K(VGS - Vt)2.(1 + VDS /VA) (3.5)
S
5 VGS
where VA is analogous to the Early voltage of a BJT
IDSS
VGS (V) • As for BJT, extra term can be ignored in bias analysis, but is
-4 -2 0 2 4 6 important in small-signal analysis

• IDSS = Drain current with VGS = 0

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 5 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 6
 MOSFET Small-Signal Model

• INPUT SIDE

Gate is capacitively coupled to D and S and capacitances are small

(measured in pF), so gate appears open-circuit even at moderate AC
frequencies

• OUTPUT SIDE

• From Equn 3.5, we can write the Drain signal current in saturation
as:

id = gmvgs + vds/ro

where:

gm = ID/VGS  2K(VGS - Vt) (3.6)

and:
ro = VDS/ID  VA /ID (3.7)

 SSEM:
G gmvgs D
vgs ro

NB VGS and ID in Equns 3.6 and 3.7 are quiescent values, so small-signal
parameters depend on bias conditions

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 7 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 8
 Common-Source Amplifier Common-Source Amplifier
Quiescent Analysis Small-Signal Analysis

VDD id
gmvgs
RD vgs ro
RG1
O/P RG RD
I/P vin vout

vs RS

RG2
RS

• Small-signal equations:

id = gm(vin - vs) + (vout - vs) /ro

• IG = 0, so: VG = VDD RG2/(RG1 + RG2)
vs = idRS
• Assuming MOSFET is Active:
vout = - idRD
ID = K(VGS - Vt)2 = K(VG - VS - Vt)2

and IS = ID, so:  VOLTAGE GAIN:

- gmRD
AV = _______________________
V S = ID R S 1 + gmRS + (RS + RD)/ro
(3.8)
 Need to solve a quadratic to obtain VS or ID NB: AV - gm (RD//ro) when RS bypassed
(2 roots obtained, only one of which is physically sensible)
• INPUT RESISTANCE: (obvious)
• VD obtained from:
Ri = RG (3.9)
VD = VDD - ID RD
Ri can be VERY large (limited by gate leakage current)

NB: Always go back and check that the active mode assumption was valid
i.e. that the calculated values of VG, VS and VD satisfy VDS  VGS - Vt • OUTPUT RESISTANCE: (not obvious!)

Ro = RD//[ro + (1 + gmro)RS] (3.10)

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 9 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 10
 C-S Amplifier Active Loads
Biasing with D-G Feedback
• Replace RD (or RC in a BJT amplifier) by a transistor configured to act
as a constant current source
VDD
e.g. N-channel Depletion Load
RD

RG O/P

 IDSS ro = VA /IDSS
I/P

Circuit Model when VDS  |Vt |

• IG = 0, so VG= VD !!
ID
 • VGD < Vt and (Enh. mode) MOSFET must be saturated
SAT
TRIODE
• VD obtained by solving

ID = K(VD - Vt)2 = (VDD - VD) /RD

• SSEC:
RG

0 VDS
gmvgs 0 |Vt |
vgs ro
vin RD vout • Advantages over passive, linear RD:

• Enhanced small-signal gain

• For integrated amplifier, active device occupies smaller area of

AV = - (gm - 1/RG).(RD//ro//RG) silicon

 - gm (RD//ro) if RG large

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 11 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 12
 Discrete NMOS Amplifier - 1 Discrete NMOS Amplifier - 2
Full I/P-O/P Relationship
VDD
• Using load-line method:
Q2
ID
O/P

I/P Q1 Load Line

C
B

gm1 vin A
0 VDS1
vin ro1 ro2 vout VDD - |Vt2| VDD
0

SSEC assuming both Q’s in saturation

VOUT
A
AV = - gm1(ro1//ro2) VDD

I II III IV
Points to note: VDD - |Vt2| Q1 OFF SAT SAT TRI
B
Q2 TRI TRI SAT SAT
• No bias network is shown - we are assuming the I/P voltage contains
both signal and bias components

• Quiescent drain current is set by IDSS of Q2 C

• If ro2  ro1 = VA/ID, gain is enhanced by factor of  VA/VDD compared

to passive RD case I II III IV

0 VIN
0 Vt1

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 13 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 14
 Integrated NMOS Amplifier Integrated CMOS Amplifier
• Body terminals of both N-channel FETs are (necessarily) grounded:
• Active load is now provided by a P-channel (Enh. mode) FET:
VDD
VDD
Q2
VSG2

Q2
O/P
Q1 O/P
Q1
I/P
I/P

• VBS of upper FET varies with the output voltage, and this modifies the
channel resistance (body acts like a second gate). This is the BODY • No body effect, because both devices have fixed VBS
EFFECT
 back to Av = - gm1(ro1//ro2)
• SSEC becomes:
• VSG2 establishes required drain bias current
gm1 vin gmb2vout
vin ro1 ro2 vout In practice, Q2/voltage source combination would be replaced by a
CURRENT MIRROR (next lecture!)

AV = - gm1(ro1//ro2//gmb2-1)

 - gm1/gmb2 if ro1, ro2 >> 1/gmb2

 - (gm1/gm2).(1/)

where  = gmb2/gm2 typically 0.1 to 0.3

 Body effect REDUCES GAIN significantly

EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 15 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 16
ANALOGUE ELECTRONICS
PROBLEMS 3

1. (a) When VGS > Vt and VDS is small, the channel of a MOSFET behaves as a voltage-
controlled resistor. Starting with the appropriate MOSFET equation, show that the
channel resistance in this regime is given by:

RDS = [2K(VGS - Vt)]-1

Hence sketch the relationship between vOUT and vIN at constant VG for the circuit below.
Your graph should cover the range 0 < vIN < 100 mV and show separate curves for VG =
2, 3, 4 and 5 V.

(b) On a separate graph, and for the same four VG values, show roughly how vOUT varies
with vIN over the range 0 < vIN < 10 V. (hint: in this case you need to consider what
happens to the input-output relationship when the MOSFET goes into saturation)

1 k
vIN vOUT

K = 1 mA/V2
Vt = 2 V
VG

2. For each of the configurations below, determine the operating mode of the MOSFET or,
if the mode is indeterminate, state all the possibilities.

> Vt

(a) (b) (c) (d)

EE1&ISE1 Analogue Electronics 2008/2009 - Problems 3 ASH 1

3. A given depletion NMOS FET has an IDSS value of 2 mA and a threshold voltage of -1 V.
Determine the minimum values of VDS for the device to operate in the saturation region
(a) when VGS = +1 V and (b) when VGS = +5 V. Also calculate the corresponding values
of the saturation drain current.

4. The drain current of a particular N-channel enhancement MOSFET is found to be 4 mA

when VGS = VDS = 9 V, and 1 mA when VGS = VDS = 5 V. What are the values of K and
Vt for this device?

5. (a) For the common-source amplifier in Figure Q5, choose values of RS and RD to give a
drain bias current of 1 mA and a quiescent output voltage of 5 V.

(b) Draw a small-signal equivalent circuit for the amplifier, assuming CS is effectively
short-circuit at signal frequencies, and determine the small-signal macromodel parameters
Ri, Ro and Av.

+10 V

RD
1.5 M
O/P
I/P
K = 0.25 mA/V2
Vt = 1 V, VA = 100 V

1 M
RS CS

Figure Q5

6. Draw a small-signal equivalent circuit for the amplifier in Question 5 assuming CS = 0,

and prove that the small-signal voltage gain in this case is given by:

- gmRD
AV = _______________________
1 + gmRS + (RS + RD)/ro

where gm and ro are the usual small-signal MOSFET parameters.

EE1&ISE1 Analogue Electronics 2008/2009 - Problems 3 ASH 2

7. (a) Calculate the drain bias current and the quiescent output voltage for the common-
source amplifier below.

(b) Draw a small-signal equivalent circuit for the amplifier, and determine the small-
signal voltage gain.
+10 V

3 k

1 M O/P

K = 0.5 mA/V2
I/P Vt = 2 V, VA = 120 V

8. (a) Show that the quiescent output voltage of the amplifier in Figure Q8 overleaf is given
by:
VOUT = Vt1 + |Vt2|(K2/K1)

where the subscripts 1 and 2 denote the lower and upper FETs respectively. You should
assume that both devices are in saturation.

(b) Draw a small-signal equivalent circuit, neglecting RG, and show that if the small-
signal output resistances of the two FETs are equal (i.e. VA1 = VA2 = VA) then the voltage
gain may be written as:

Av = - (VA /|Vt2|). (K1/K2)

Hence determine VOUT and Av for the case K1 = 0.5 mA/V2, Vt1 = 2 V, K2 = 1 mA/V2, Vt2
= -1 V, VA = 100 V.

Hint: you may find the relation gm = 2 (KID) useful.

9. (tricky) Figure Q9 shows an NMOS amplifier with an enhancement load. Draw a small-
signal equivalent circuit for this amplifier, and show that the voltage gain is given by:

Av = - gm1 (ro1//ro2//gm2-1)

Show also that if ro1 and ro2 are large compared to gm2-1, Av may be expressed as:

Av  -  (K1/K2)

EE1&ISE1 Analogue Electronics 2008/2009 - Problems 3 ASH 3

 VDD VDD

Q2 Q2

RG O/P O/P

I/P Q1 I/P Q1

Figure Q8 Figure Q9

Answers
2 (a) sub-threshold i.e. off; (b) triode/saturation; (c) saturation; (d) triode
3 (a) VDS = 2 V, ID = 8 mA; (b) VDS = 6 V, ID = 72 mA
4 K = 0.0625 mA/V2, Vt = 1 V
5 (a) RS = 1 k, RD = 5 k; (b) Ri = 0.6 M, Ro = 4.76 k, Av = -4.76
7 (a) ID = 2 mA, VOUT = 4 V; (b) Av = -5.70
8 VOUT = (2 + 2) = 3.41 V, Av = -100/2 = -71

EE1&ISE1 Analogue Electronics 2008/2009 - Problems 3 ASH 4