Nanowire Transistors by J P Colinge PDF

Preface
After the era of bulk planar CMOS, trigate field-effect transistors (FinFETs), and fully
depleted silicon-on-insulator (SOI), the semiconductor industry is now moving into the
era of nanowire transistors. This book gives a comprehensive overview of the unique
properties of nanowire transistors. It covers the basic physics of one-dimensional
semiconductors, the electrical properties of nanowire devices, their fabrication, and
their application in nanoelectronic circuits.
The book is divided into seven chapters:
Chapter 1: Introduction serves as an introduction to the other chapters. The reader is
reminded of the exponential increase in complexity of integrated circuit electronics over
the last 50 years, better known as “Moore’s law.” Key to this increase has been the
reduction in transistor size, which has occurred in a smooth, evolutionary fashion up to
the first decade of the twenty-first century. Despite the introduction of technology
boosters such as metal silicides, high-κ dielectric gate insulators, copper metallization,
and strained channels, evolutionary scaling reached a brick wall called “short-channel
effects” in the years 2010–2015. Short-channel effects are a fundamental device physics
showstopper and prevent proper operation of classical bulk MOSFETs at gate lengths
below 20 nm. The only solution to this problem is the adoption of new transistor
architectures such as fully depleted silicon-on-insulator (FDSOI) devices [1,2] or
trigate/FinFET devices [3]. Ballistic transport of channel carriers, which replaces clas-
sical drift-diffusion transport, is also introduced in this chapter.
Chapter 2: Multigate and nanowire transistors first explains the origin of the short-
channel effects that preclude the use of bulk MOS transistors for gate lengths smaller
than 20 nm. Based on Maxwell’s electrostatics equations, this chapter shows how the use
of multigate and gate-all-around nanowire transistor architectures will allow one to push
the limits of integration to gate lengths down to 5 nm and possibly beyond, provided the
diameters of the nanowires are decreased accordingly. In semiconductor nanowire with
diameters below approximately 10 nm (this value is temperature dependent and varies
from one semiconductor material to another), the coherence length of electrons and
holes can become comparable to or larger than the wire cross-sectional dimensions, and
1
J.P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd edition, Kluwer Academic Publishers/
Springer (2004).
2
O. Kononchuk and B.-Y. Nguyen (eds.), Silicon-on-Insulator (SOI) Technology Manufacture and
Applications, Woodhead Publishing (2014).
3
J.P. Colinge (ed.), FinFETs and Other Multi-Gate Transistors, Springer (2007).
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xii Preface
one-dimensional (1D) quantum confinement effects become observable. The formation

of 1D energy subbands in narrow nanowire transistors gives rise to several effects such
as an increase of energy band gap, oscillations of drain current when gate voltage is
increased, and oscillations of gate capacitance with gate voltage (quantum capacitance
effect). Some collateral effects can be predicted, such as a semimetal-to-semiconductor
transition in thin semimetal nanowires, and a MOSFET to single-electron transistor
transition in nanowire transistors with non-uniform channel properties.
Chapter 3: Synthesis and fabrication of semiconductor nanowires lists the dif-
ferent top-down and bottom-up techniques used to grow or etch and pattern nanowires.
Vertical nanowires can be grown by the VLS (vapor–liquid–solid) technique or confined
epitaxy, or formed using lithography and etching. Horizontal nanowires can also
be grown using the VLS technique, by patterning an SOI layer, or by patterning
heteroepitaxial layers, such as Si/SiGe/Si. Examples of nanowire transistor fabrication
processes are given. Chapter 3 also describes methods for smoothing and thinning
down silicon nanowires. The properties of heterojunction nanowires (core-shell
nanowires and axial heterojunctions) are described. Finally, strain effects in nanowires
are explored, including carrier mobility enhancement, Young’s modulus, and fracture
strength.
Chapter 4: Quantum mechanics in one dimension provides a résumé of the
physical description of one-dimensional systems in quantum mechanics. A brief sum-
mary of the principles of quantum mechanics is given. Particular emphasis is given to
topics that are related to describing nanowire transistors including momentum eigen-
states, energy dispersion, scattering states in one dimension, probability current density,
and transmission at potential energy barriers. A description of materials and nanowires
using the concept of electronic band structures is provided and calculation of simple
band structures is provided using simple examples such as a linear chain of atoms.
The relation of electronic band structures to the density of states and how the density of
states can be used to characterize three-dimensional (3D) bulk, two-dimensional (2D)
electron and hole gases, and (1D) nanowire material systems is presented.
Chapter 5: Nanowire electronic structure examines in greater detail the impact of
fabricating nanometer scale devices with one or more critical dimension comparable
to or smaller than the Fermi wavelength of the confined charge carriers. The crystal
structure of semiconductors commonly used in electronics such as silicon, germanium,
and gallium arsenide are introduced. Mention is made of two-dimensional materials
such as graphene and the transition metal dichalcogenides, and carbon nanotubes are
briefly discussed in relation to applications in electronics. Emphasis is placed on the
experimental measurement and theoretical calculation of electronic structure. Quantum
mechanical effects become apparent below 10 nm critical dimensions and below 6 nm
confinement and surface effects begin to dominate silicon nanowire properties. A greater
understanding of the dependence of orientation, surface chemistry, disorder, doping
effects, and other factors arising for nanopatterned materials is needed to optimize the
use of nanowires in transistor configurations. This chapter highlights how these factors
can influence electronic structure and demonstrates their impact with examples for
silicon nanowires with diameters below 10 nm.
Preface xiii
Chapter 6: Charge transport in quasi-1D nanostructures investigates how charge

carriers flow through nanowires. The operation of voltage sources as charge carrier
reservoirs interacting with nanowires is introduced, and the relationship of voltage to
current flow on the nanometer length scale leads to conductance quantization and the
Landauer conductance formula. Charge carrier mobility is introduced and the length
scales associated with scattering mechanisms leading to macroscopic mobilities are
outlined. For charge transport on length scales shorter than the scattering lengths,
ballistic and quasi-ballistic charge transport emerges. The chapter ends with a brief
introduction to the Green’s function approach to charge transport in nanowires as it
possesses the capability to describe charge transport from quantum ballistic to classical
drift and diffusion regimes.
Chapter 7: Nanowire transistor circuits describes the potential and performances
of nanowire transistors in logic, analog, and RF circuit applications. This includes an
in-depth analysis of SRAM and flash memory cells. New types of circuit architectures
are enabled by the use of nanowire devices, such as crossbar circuits and “nanoscale
application specific integrated circuits” (NASICs). The large surface area-to-volume
ratio of nanowires makes them ideal for sensing minute amounts of chemicals and
biochemicals. Nanowire transistors have proven to be efficient sensing devices, capable
of detecting chemicals in concentrations as low as a few tens of attomoles.
Contents
Preface page xi
1 Introduction 1
1.1 Moore’s law 2
1.2 The MOS transistor 4
1.3 Classical scaling laws 8
1.4 Short-channel effects 8
1.5 Technology boosters 9
1.5.1 New materials 10
1.5.2 Strain 11
1.5.3 Electrostatic control of the channel 11
1.6 Ballistic transport in nanotransistors 12
1.6.1 Top-of-the-barrier model 12
1.6.2 Ballistic scaling laws 14
1.7 Summary 15
References 16
2 Multigate and nanowire transistors 18

2.1 Introduction 18
2.2 The multigate architecture 19
2.3 Reduction of short-channel effects using multigate architectures 20
2.3.1 Single-gate MOSFET 22
2.3.2 Double-gate MOSFET 23
2.3.3 Triple- and quadruple-gate MOSFETs 24
2.3.4 Cylindrical gate-all-around MOSFET 25
2.4 Quantum confinement effects in nanoscale multigate transistors 29
2.4.1 Energy subbands 29
2.4.2 Increase of band gap energy 36
2.4.3 Quantum capacitance 37
2.4.4 Valley occupancy and transport effective mass 38
2.4.5 Semimetal–semiconductor nanowire transitions 40
2.4.6 Topological insulator nanowire transistor 43
2.4.7 Nanowire-SET transition 43
2.5 Other multigate field-effect devices 44
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viii Contents
2.5.1 Junctionless transistor 44

2.5.2 Tunnel field-effect transistor 45
2.6 Summary 46
Further reading 47
References 47
3 Synthesis and fabrication of semiconductor nanowires 54

3.1 Top-down fabrication techniques 54
3.1.1 Horizontal nanowires 54
3.1.2 Vertical nanowires 57
3.2 Bottom-up fabrication techniques 58
3.2.1 Vapor–liquid–solid growth technique 59
3.2.2 Growth without catalytic particles 63
3.2.3 Heterojunctions and core-shell nanowires 64
3.3 Silicon nanowire thinning 66
3.3.1 Hydrogen annealing 66
3.3.2 Oxidation 67
3.3.3 Mechanical properties of silicon nanowires 69
3.4 Carrier mobility in strained nanowires 72
3.5 Summary 73
References 74
4 Quantum mechanics in one dimension 81

4.1 Overview 81
4.2 Survey of quantum mechanics in 1D 81
4.2.1 Schrödinger wave equation in one spatial dimension 82
4.2.2 Electron current in quantum mechanics 83
4.2.3 Quantum mechanics in momentum space 84
4.3 Momentum eigenstates 85
4.4 Electron incident on a potential energy barrier 88
4.5 Electronic band structure 92
4.5.1 Brillouin zone 93
4.5.2 Bloch wave functions 94
4.6 LCAO and tight binding approximation 95
4.6.1 Linear combination of atomic orbitals (LCAO) 95
4.6.2 Tight binding approximation 97
4.7 Density of states and energy subbands 100
4.7.1 Density of states in three spatial dimensions 100
4.7.2 Density of states in two spatial dimensions 102
4.7.3 Density of states in one spatial dimension 104
4.7.4 Comparison of 3D, 2D, and 1D density of states 104
4.8 Conclusions 105
Further reading 106
References 106
Contents ix
5 Nanowire electronic structure 107

5.1 Overview 107
5.2 Semiconductor crystal structures: group IV and III-V materials 107
5.2.1 Group IV bonding and the diamond crystal structure 107
5.2.2 III-V compounds and the zincblende structure 110
5.2.3 Two-dimensional materials 113
5.3 Insulators, semiconductors, semimetals, and metals 117
5.4 Experimental determination of electronic structure 119
5.4.1 Temperature variation of electrical conductivity 119
5.4.2 Absorption spectroscopy 121
5.4.3 Scanning tunneling spectroscopy 123
5.4.4 Angle resolved photo-emission spectroscopy 127
5.5 Theoretical determination of electronic structure 129
5.5.1 Quantum many-body Coulomb problems 130
5.5.2 Self-consistent field theory 134
5.5.3 Optimized single determinant theories 146
5.5.4 GW approximation 147
5.6 Bulk semiconductor band structures 149
5.7 Applications to semiconductor nanowires 152
5.7.1 Nanowire crystal structures 152
5.7.2 Quantum confinement and band folding 154
5.7.3 Semiconductor nanowire band structures 157
5.8 Summary 160
Further reading 162
References 162
6 Charge transport in quasi-1D nanostructures 167

6.1 Overview 167
6.2 Voltage sources 167
6.2.1 Semi-classical description 167
6.2.2 Electrode Fermi–Dirac distributions 171
6.3 Conductance quantization 174
6.3.1 Subbands in a hard wall potential nanowire 174
6.3.2 Conductance in a channel without scattering 176
6.3.3 Time reversal symmetry and transmission 179
6.3.4 Detailed balance at thermodynamic equilibrium 182
6.3.5 Conductance with scattering 182
6.3.6 Landauer conductance formula: scattering at non-zero
temperature 186
6.4 Charge mobility 188
6.5 Scattering mechanisms 191
6.5.1 Ionized impurity scattering 191
6.5.2 Resonant backscattering 193
6.5.3 Remote Coulomb scattering 194
x Contents
6.5.4 Alloy scattering 194

6.5.5 Surface scattering 195
6.5.6 Surface roughness 195
6.5.7 Electron–phonon scattering 196
6.5.8 Carrier–carrier scattering 198
6.6 Scattering lengths 200
6.6.1 Scattering lengths and conductance regimes 200
6.6.2 Multiple scattering in a single channel 201
6.7 Quasi-ballistic transport in nanowire transistors 206
6.8 Green’s function treatment of quantum transport 210
6.8.1 Green’s function for Poisson’s equation 210
6.8.2 Green’s function for the Schrödinger equation 211
6.8.3 Application of Green’s function to transport in nanowires 213
6.9 Summary 217
Further reading 217
References 217
7 Nanowire transistor circuits 221

7.1 CMOS circuits 221
7.1.1 CMOS logic 221
7.1.2 SRAM cells 224
7.1.3 Non-volatile memory devices 227
7.2 Analog and RF transistors 231
7.3 Crossbar nanowire circuits 234
7.4 Input/output protection devices 237
7.5 Chemical and biochemical sensors 238
7.6 Summary 242
References 242
Index 249
1 Introduction
The history of electronics spans over more than a century. A key milestone in the history
of electronics was the invention of the telephone in 1876 and patents for the device were
filed independently by Elisha Gray and Alexander Graham Bell on 14 February that
same year. Bell filed first, and thus the patent was granted to him. This timely, or
untimely for Gray, coincidence has become a textbook example for teaching the
importance of intellectual property law in engineering schools across the globe.
Years later, the first radio broadcast took place in 1910 and is credited to the De Forest
Radio Laboratory, New York. Lee De Forest, inventor of the electron vacuum tube,
arranged the world’s first radio broadcast featuring legendary tenor Enrico Caruso along
with other stars of the New York Metropolitan Opera to several receiving locations
within the city. Experimental television broadcasts can be traced back to 1928, but
practical TV sets and regular broadcasts date back to shortly after the Second World War.
During this initial phase of development, electronics was based on vacuum tubes and
electromechanical devices. The first transistor was invented at Bell Labs by William
Shockley, John Bardeen, and Walter Brattain in 1947 and they used a structure named a
point-contact transistor. Two gold contacts acted as emitter and collector contacts on a
piece of germanium. William Shockley made and patented the first bipolar junction
transistor in the following year, 1948. It is worth noting that the point-contact transistor
was independently invented by German physicists Herbert Mataré and Heinrich Welker
of the Compagnie des Freins et Signaux, a Westinghouse subsidiary located in Paris [1].
The first patent for a metal-oxide-semiconductor field-effect transistor (MOSFET)
was filed by Julius Edgar Lilienfeld in Canada and in the USA during 1925 and 1928,
respectively [2,3]. The semiconductor material used in the patent was copper sulfide and
the gate insulator was alumina. However, a working device was never successfully
fabricated or published at that time. The first functional MOSFET was made by Dawon
Kang and John Atalla in 1959 and patented later in 1963 [4]. The successful field-effect
operation was enabled by the use of silicon and silicon dioxide for the metal-oxide-
semiconductor (MOS) stack. Unlike other insulator–semiconductor structures of the
time, the Si–SiO2 interface could be formed without a large density of electrically active
defects that would otherwise prevent the penetration of the electric field from the gate
into the semiconductor. Even when defects were present, means of deactivating them
by chemical and other means, known as passivation, were found.
Because of practical fabrication reasons, p-channel (pMOS) technology was devel-
oped first and relied on aluminum as the metal for the gate electrode. Later on, the advent
2 Introduction
of ion implantation and the use of polysilicon (heavily doped polycrystalline silicon) as
gate material made self-aligned n-channel (nMOS) transistors feasible [5]. In a 1963
paper presented at the IEEE International Solid-State Circuits Conference, C. T. Sah and
Frank Wanlass showed that p-channel and n-channel MOS transistors could be inte-
grated onto a single integrated circuit or “chip” forming a circuit configuration with
complementary symmetry [6]. This technology had the great advantage of drawing
close to zero power in standby mode. It was initially called COS-MOS (complementary
symmetry metal-oxide-semiconductor) and has since been universally adopted by the
semiconductor industry under the name complementary metal-oxide-semiconductor
(CMOS).
Another great advantage of MOS transistors is that they, unlike bipolar transistors,
have a planar, basically two-dimensional structure. MOS transistors occupy only a small
portion of the volume of a silicon wafer on which they are manufactured. The devices are
located at the top surface of the wafer and extend into the wafer to a depth of only a
fraction of a micrometer. As a consequence, the MOSFET is scalable, and scaled it has
been for the last 50 years, giving rise to the microelectronics revolution at the end of the
twentieth century and through to the beginning of the twenty-first.
1.1 Moore’s law
The MOSFET is the workhorse of the electronics industry. It is the building block of
every microprocessor, every memory chip, and every telecommunications circuit. A
modern microprocessor contains several billion MOSFETs and a 256 gigabyte micro
secure digital (SD) memory card weighing less than a gram contains a staggering
1,000,000,000,000 or 1012 transistors, assuming 2 bits stored per transistor. This number
is larger than the number of stars in our galaxy, as there is an estimated 200–400 billion
stars in the Milky Way. Although it can be used for other purposes, the MOSFET is
mainly used as a switch in logic circuits and a charge-storage device in memory chips.
Each day the semiconductor industry produces more MOSFETs than the number of
grains of rice that have been harvested by mankind since the dawn of time. That number,
astronomical as it is, is dwarfed by the rate at which transistors are increasingly packed
on a chip. The exponential growth of chip complexity and number of transistors per chip
is known as Moore’s law.
In 1965, Gordon Moore published what was to become a classic paper in which he
predicted that the density of transistors on a chip would double every 18 months [7]. This
prediction was based on data spanning only a few technology generations produced
during the period from 1959 to 1965, during which the number of transistors per chip
increased from a single transistor to less than a hundred transistors. Extrapolating from
the available data, Gordon Moore predicted that there would be 64,000 transistors per
chip in 1975, ten years after the publication of the article. Even though completely an
empirical observation, Moore’s law has proven to be remarkably accurate, not only until
1975 but continues at present and covers a period of over 50 years. Whether plotted in
terms of transistors per chip or transistors per square millimeter (Figs. 1.1 and 1.2), the
Figure 1.1 Evolution of the number of transistors per chip with time. Central processing units (CPU) or
microprocessors and graphics processing units (GPU) or graphics processors from different
vendors are shown. The top of the chart shows the date of introduction of some landmark products:
HP-35 pocket calculator, Apple II and Macintosh computers, iPod, iPhone, and the introduction of
second-, third-, and fourth-generation mobile phone networks (2G, 3G, 4G).
100,000,000
AMD CPU Atom
10,000,000 IBM CPU
Intel CPU
1,000,000 K6
Transistors / mm2
Motorola CPU
XBOX
AMD CPU One
100,000
SOC
NVIDIA CPU
10,000
6800
1,000 Pentium
68000
100
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015
Year
Figure 1.2 Evolution of the number of transistors per square millimeter with time. Microprocessors (CPU)
and graphics processors (GPU) from different vendors are shown. Some landmark
microprocessors are outlined for reference: Motorola’s 6800 and 68000, Intel’s Pentium and
Atom, and AMD’s K6 and XBOX One SOC (system on chip).
4 Introduction
10,000
X
0.7
/1
8m
Gate length (nanometers)
on
1,000 ths
AMD CPU
IBM CPU
Intel CPU
100
Motorola CPU
AMD CPU
NVIDIA CPU
10
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015
Year
Figure 1.3 Evolution of the gate length with time. Gate length is the smallest printed feature in a MOS
transistor, at least for traditional planar MOSFETs.
increases in the number of transistors and their density are spectacular. It is now part of
popular legend that Bill Gates once joked that “If the car industry had kept up with
technology like the computer industry has, we would all be driving 25-dollar cars that
can run 1,000 miles to the gallon.” He might have added that such a car would go around
the world in a few seconds while carrying a million passengers.
It is quite obvious that reducing the size of transistors increases their density on a chip,
which, for a constant chip size, increases the functionality of the circuits. There are other
incentives for making the transistors smaller. Doubling the density of transistors on a
chip implies reducing the linear dimensions, such as their length and width, by a scaling
pffiffiffi
factor equal to 2. The gate length of MOS transistors has been steadily decreasing
over the years, as shown in Fig. 1.3 where the data are plotted for the same circuits as for
Figs. 1.1 and 1.2. One can clearly see that the linear dimensions of the patterns of a chip,
such as the gate length, have been steadily decreasing by a factor of approximately
pffiffiffi
1= 2 ffi 0:7 every 18 months. Decreasing linear dimensions by 0.7 results in the surface
area of the transistors halving every 18 months, in agreement with Moore’s prediction.
1.2 The MOS transistor
The textbook example of a MOSFET is shown in Fig. 1.4. The device consists of a
p-type semiconductor substrate in which two n-type regions have been formed. These
n-type regions are called the “source” and the “drain.” Typically the semiconductor
VG
Inversion
channel
Vs VD
Gate electrode Tdielectric
Gate dielectric
N+ Source W
XJ L N+ Drain
Xdepl
P-type Substrate
Vsub
Figure 1.4 Schematic view of a classical bulk MOSFET.
material is silicon, although other semiconductors such as germanium (Ge), silicon

germanium alloys (SiGe), indium arsenide (InAs), and indium gallium arsenide
(InGaAs) can also be used. A thin layer of insulating material called the “gate dielectric”
covers the region between the source and drain. For many years silicon dioxide (SiO2)
was the standard dielectric, but in recent years, silicon oxynitride (SiON) and stacks
composed of insulators with high dielectric constant known as “high-κ dielectrics” have
become common. An example of high-κ dielectric material is HfO2 which has a
dielectric constant approximately five times higher than SiO2. The gate dielectric is
formed by deposition and subsequently topped by a metal electrode called the “gate.”
Under typical bias conditions, the source and the p-type substrate are grounded
(VS = Vsub = 0 V), and a positive voltage, VD, is applied to the drain. Under these
conditions, the drain pn junction is reverse biased and no current flows between the drain
and the substrate. Since the bias across the source pn junction is zero, there is no current
flowing from the substrate to the source either. As a result, there is no current flow
between the source and the drain, and the transistor is turned OFF, playing the role of an
open switch. If a positive voltage is applied to the gate, holes in the p-type substrate
underneath the gate are pushed away from the surface and a region void of holes, called
the “depletion region” forms beneath the gate. The depth of the depletion region, Xdepl,
increases with gate voltage up to a maximum value which depends on the p-type doping
concentration. It is worth noting that the gate-induced depletion region merges with the
source and drain junction depletion regions on the source side and drain side of the gate.
If the gate voltage is further increased, further increments of gate-induced charge are not
picked up by increasing the depletion depth, but rather by attracting electrons underneath
the gate dielectric. Electrons literally “spill out” from the n-type source to form an
electron-rich layer underneath the gate insulator called an “inversion channel.” The term
6 Introduction
Drain Current, ID (logarithmic scale)

On current
Drain Current, ID (linear scale)

1 mA 1.0 mA
100 mA Off current
0.8 mA
10 mA
1 mA
0.6 mA
100 nA 1/slope = SS
10 nA One decade 0.4 mA
1 nA of current Threshold
voltage 0.2 mA
100 pA DVG = 80 mV
10 pA
0.0 mA
0.0 0.2 0.4 0.6 0.8 1.0
Gate voltage, VG (Volts)
Figure 1.5 Drain current as a function of gate voltage in an MOS transistor at low drain bias. The two curves
represent identical data, plotted using either a linear scale (right-hand y axis) or a logarithmic scale
(left-hand y axis).
“inversion” is used because the top surface of the semiconductor, originally p-type
(rich in holes), is now void of holes and rich in electrons, which technically makes it
locally n-type. The silicon surface has thus been “inverted” from p-type to n-type. The
inversion channel forms a continuous electron bridge between the source and drain and
current can now flow between these two terminals. The transistor is considered to be in
the ON state and behaves as a closed switch.
A perfect switch features zero current flow when it is open, zero resistance when it is
closed, and is capable of switching sharply between the OFF state and the ON state. The
MOSFET is unfortunately an imperfect switch; the OFF current is not zero and the
ON-state resistance is finite. Furthermore, switching does not suddenly occur at a precise
value of the gate voltage, but it takes place gradually, over a range of gate voltage values.
Figure 1.5 illustrates how the drain current flowing through a MOSFET evolves as a
function of gate voltage with a fixed positive drain voltage of 50 mV. In this example, the
ON current is 1 mA and the OFF current is 50 pA. Looking at the current plotted on a
linear scale, it appears there is no current below a given gate voltage, called the
“threshold voltage” which is approximately equal to 0.5 V in the example shown in
Fig. 1.5. If the drain voltage is low (typically 50 mV), the drain current basically
increases linearly with the applied gate bias above threshold. The classical textbook
expression for this current, called the “linear” or “non-saturation” current, is [8]

W 1
IDðlinÞ ¼ μCox ðVG VTH ÞVD VD ; ð1:1Þ
L 2
where µ, Cox, L, W, VG, VTH, and VD are the carrier mobility in the channel (m2 V−1 s−1),
the gate capacitance (F m−2), the gate length (m), the gate width (m), the gate voltage
(V), the threshold voltage (V), and the drain voltage (V), respectively. The source and
the substrate are assumed to be grounded.
For larger values of the drain voltage (when VD > VG − VTH), the channel is pinched
off near the drain due to the increase of the depletion region with increasing drain voltage
and the drain current saturates (i.e. it no longer increases with increasing drain voltage
VD). In that case, the “saturation” drain current is given by
1 W
IDsat ¼ μCox ðVG VTH Þ2 : ð1:2Þ
2 L
Plotting the drain current on a logarithmic scale reveals that the drain current varies
exponentially with gate voltage below threshold, and that the OFF current is not equal to
zero. The rate of increase of current below threshold is characterized by a parameter
called the “subthreshold slope,” also called subthreshold swing (SS), defined by the
relationship SS ¼ dVG =dðlogðID ÞÞ where the logarithm is chosen to be base 10. The
subthreshold slope is expressed in units of millivolts per decade. A typical value for
the subthreshold slope of a bulk MOSFET is 80 mV/dec, which means that an 80 mV
increase of the gate voltage brings about a tenfold increase of drain current. Thus, in
order to “switch” the current from its OFF value (50 pA) to the ON state (ID = 100 µA at
threshold), a gate voltage swing of 80 mV log½100 μA=50 pA ¼ 0:5 V is required.
It can be shown that the subthreshold slope is equal to:
kB T T
SS ¼ n lnð10Þ ¼ n 59:6 mV=dec; ð1:3Þ
jqj 300 K
where kB is Boltzmann’s constant, T is the temperature, q is the charge of an

electron (taken in absolute value, since the charge of an electron is negative by
convention), ln(10) is the natural logarithm of 10, and n is the “body factor.” The
body factor represents the efficiency, or rather the inefficiency with which the gate
voltage electrostatically controls the channel region. The body factor is proportional
to the change in gate voltage with a change in channel potential (ΦCH ) and is
expressed mathematically through the relationship n ¼ dVG =dΦCH . In the best possible
case, if the electrostatic coupling between the gate and the channel region is 100%
effective, n ¼ 1 and the subthreshold slope is equal to ½kB T=jqj lnð10Þ ¼
59:6 mV=dec at room temperature (T = 300 K = 26.85°C). In practice, the gate control
of the channel region is not perfect due to the electrostatic coupling between the
substrate through the depletion layer. As a result, n typically has a value between 1.2
and 1.5 in bulk MOSFETs, which results in subthreshold slope values ranging from 70 to
90 mV/dec. It is impossible, as can be shown from thermodynamics arguments, to
reduce the subthreshold slope below 59.6 mV/dec at room temperature in classical
MOSFETs; the best one can hope for is to approach that limit as closely as possible.
The 59.6 mV/dec barrier can be breached using impact ionization effects [9,10],
quantum tunneling effects [11,12,13], and with special ferroelectric gate materials
[14], but none of these techniques have yet been proven to be reliable or reproducible
enough for industrial applications. The lack of scalability for the subthreshold slope is a
fundamental limit for the MOSFET and is sometimes referred to as the “Boltzmann
tyranny” [15,16].
8 Introduction
Table 1.1 Constant-electric field scaling rules for planar MOS transistors [17].
Parameter Equation Unit Scaling factor
Physical dimensions: L, W, Xj, Xdepl m γ1

1
Integration density m−2 γ2
WL
εSiO2
Equivalent oxide thickness (EOT) tox ¼ tdielectric m γ1
εdielectric
εSiO2
Dielectric capacitance Cox ¼ F/m2 γ
tox
Gate capacitance CG ¼ WLCox F γ1
Voltages VDS, VGS, VTH Electric field E = V/L = constant V/m γ1
1W
Drain current IDsat ¼ μCox ðVGS VTH Þ2 A γ1
2L
VDS IDsat
Power density W/m2 γ0 = 1
WL
Power consumption per transistor P ¼ VDS IDsat W γ2
CG VDS
Intrinsic gate delay τ¼ S γ1
IDsat
Power × delay product Pτ J γ3
1.3 Classical scaling laws
In 1974, Robert Dennard and co-workers published a seminal paper in which they demon-
strated the benefits of scaling [17]. Based on the assumption of maintaining a constant
electric field inside the transistor, Dennard et al. demonstrated that scaling the device by a
factor γ increases the switching speed by a factor γ, reduces the transistor power
dissipation by a factor γ2, and improves the power-delay product by a factor γ3 : It is
worthwhile noting that this scaling law implies reducing the supply voltage by a factor γ,
as well as reducing the threshold voltage by the same factor γ. The latter has not been
achieved in subsequent technologies because of the impossibility of scaling the sub-
threshold slope to achieve values lower than 59.6 mV/decade because of fundamental
thermodynamic reasons. Dennard’s scaling law was more or less followed by the
semiconductor industry for a duration of approximately 30 years, familiarly called the
“happy scaling” period. These years are now over, and the improvement of performance
due to scaling, at least in terms of microprocessor clock frequency, has reached satura-
tion. This is caused by so-called “short-channel effects” that arise when the distance
separating source from drain becomes very small. Short-channel effects increase as
devices are scaled down in length, as will be described in the following. The classical
scalling laws are shown in Table 1.1.
1.4 Short-channel effects
Short-channel effects result from the sharing of the electrical charges in the channel region
between the gate on one hand, and the source and drain on the other hand. The source and
(a) (b)
1 mA
(Amperes, logarithmic scale)

(Amperes, logarithmic scale)
VDS = 1 V
100 µA Short
VDS = 0.05 V 10µA channel
Drain Current, lD
Drain Current, lD
1µA
100 nA Long
channel
10 nA
1 nA
100 pA
10 pA
1pA
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
Gate voltage, VG (Volts) Gate voltage, VG (Volts)
Figure 1.6 (a) The drain-induced barrier lowering (DIBL) effect decreases the threshold voltage when the
drain voltage VDS is increased, which typically occurs when the device needs to be turned OFF.
(b) The subthreshold slope increases when channel length is decreased, which slows down the
variation of current with gate voltage below threshold. Both effects increase the OFF current.
drain junctions create depletion regions that penetrate the channel region from both sides of
the gate, thus shortening the effective channel length. These depletion regions carry with
them electric fields that penetrate some distance into the channel region and “steal” some
of the channel control from the gate. When the drain voltage is increased, this penetration is
amplified. As a result, the potential in the channel region and the resulting concentration of
electrons are no longer controlled solely by the gate electrode, but are also influenced by the
distance between source and drain and by the voltage applied to the drain. The observable
effects resulting from this loss of charge control by the gate are known as “drain-induced
barrier lowering” (DIBL), which causes the threshold voltage to decrease as the drain
voltage is increased, and a degradation (i.e. an increase) of the subthreshold slope results;
see Fig. 1.6. The effects are additive and increase the leakage current of the transistors,
which constitutes a serious impediment to further scaling of MOSFETs. The loss of
switching speed caused by the DIBL effect is given by Δf =f ¼ 2DIBL=ðVDD VTH Þ,
where f is the maximum operating frequency, VDD is the supply voltage, and VTH is the
threshold voltage of the transistor. For example, in a circuit operating with a supply
voltage of 0.9 V with transistors having a threshold voltage of 0.4 V, an increase of DIBL
by 50 mV will slow down operating frequency by as much as 20% [18].
1.5 Technology boosters
Scaling down the size of transistors is not just a matter of being able to pattern smaller
structures by improvement of lithography techniques. It also involves a constant striving to
improve the performance of both the “intrinsic” transistors (i.e. the channel) and the
“extrinsic” elements such as gate, source, and drain resistance. Reducing the dielectric
constant of inter-layer dielectrics, and using low-resistivity metals such as copper, has also
contributed to continuous improvement of the performance of integrated circuits. Aside
from the reduction of device dimensions using ever more sophisticated lithography techni-
ques, the performance of transistors has been enhanced by three main “technology boos-
ters”: the use of new materials, the use of strain, and the change of transistor architecture.
10 Introduction
1.5.1 New materials

During the 1980s, only a handful of elements were used in silicon chip manufacturing:
boron, phosphorus, arsenic, and antimony were used to dope silicon, oxygen, and
nitrogen for growing or depositing insulators, and aluminum for making interconnec-
tions. A few elements, such as hydrogen, argon, chlorine, and fluorine, are, and continue
to be, used during processing in the form of etching plasmas or oxidation-enhancing
agents. Gold was usually used at the end of the process to form an ohmic contact to the
back of the silicon wafer. Potassium was used in the form of KOH solutions, which can
etch silicon in an anisotropic manner.
Later during the 1990s, a few more elements were added to the list, such as titanium,
tungsten, cobalt, and nickel, which were used to form low-resistivity metal silicides.
Tungsten was introduced to form vertical interconnects known as “plugs,” and bromine
started to be used in a plasma form to etch silicon.
The 2000s saw an explosion in the number of elements used in silicon processing: the
rare earth metals, hafnium and lanthanum lanthanide are being used to form oxides with
high dielectric constants (high-κ dielectrics), carbon and germanium are used to change
the lattice parameter and induce mechanical stresses in silicon, fluorides of noble gases
are used in excimer laser lithography, and a variety of metals are used to synthesize
compounds that have desirable work functions or Schottky characteristics. Mercury,
cadmium, and tellurium are used in HgCdTe infrared sensors.
The 2010s saw the beginning of the use of sulfur and selenium as surface passivation
elements, as well as the use of tin, alloyed to Ge, for making high-mobility, low-band-
gap devices. Virtually all elements of the periodic table are now being put to use in
nanoelectronics manufacture, with the notable exception of alkaline metals, which
create mobile charges in MOS oxides and, of course, radioactive elements; see Fig. 1.7.
Figure 1.7 Elements used in semiconductor (silicon) industry. Radioactive elements are not used for obvious
reasons.
The use of new elements to obtain desirable properties is a technology booster that has
made it possible to extend the life of CMOS and reduce dimensions beyond barriers that
were previously considered insurmountable. For instance, the reduction of gate oxide
thickness below 1.5 nm leads to a gate tunnel current that quickly becomes prohibitively
high. Replacing silicon dioxide by high-κ dielectrics such as hafnium oxide (HfO2),
which has a dielectric constant of 22 (vs. 3.9 for SiO2), allows an increase in the
thickness of the gate dielectric by a factor 22/3.9 = 5.5 without reducing the gate
capacitance, which is directly proportional to the current drive of a MOSFET. The use
of new gate dielectrics gave rise to the notion of “equivalent oxide thickness” (EOT),
which is defined by the relationship EOT ¼ td εox =εd , where td is the thickness of the
dielectric layer, and εox and εd are the permittivity of silicon dioxide and the replacement
dielectric material, respectively. For example, a 4-nm thick layer of HfO2 is electrically
equivalent to a 0.7-nm thick layer of SiO2.
1.5.2 Strain
To improve the properties of transistors, another technology booster is commonly used:
strain. Compressive strain increases hole mobility in silicon, while tensile strain
increases electron mobility. Mobility can also be modified by using Si/Ge or Si/Ge/C
alloys. The strain ε ¼ ΔL=L0 (note: strain is represented by the symbol ε by convention
and should not be confused with the permittivity. Normally, this convention does not
cause confusion due to the different contexts in which they are applied) is the variation of
length ΔL relative to the relaxed (unstrained) length of a sample L0 due to an applied
tensile or compressive force (unitless). Stress, σ, is the pressure applied to the material
typically measured in Pascals (the symbol σ is also used to denote conductivity but there
is little actual confusion due to the different contexts in which it is applied). Strain
and stress are related to one another through Young’s modulus as discussed in
Section 3.3. Strain can be introduced in the channel of a transistor by various processing
techniques, all aimed at introducing stress to the semiconductor in such a way that a
desired strain level is reached. Compressive stress can be induced in the channel region
of a silicon transistor by introducing germanium in the source and drain. The resulting
“swelling” of the silicon in the source and drain compresses the channel region situated
between them. Tensile stress can readily be obtained by depositing a silicon nitride
contact-etch stop layer (CSEL) on top of the device. Mobility (and thus speed) improve-
ment in excess of 50% can be obtained using stress techniques.
1.5.3 Electrostatic control of the channel

The third technology booster deals with the physical geometry of the transistor. It aims at
maximizing the electrostatic control of the channel by the gate, which in turn minimizes
short-channel effects. For all practical purposes, it seems impossible to scale the
dimensions of classical bulk MOSFETs below 15–20 nm. This has forced the industry
to switch to new transistor architectures, such as fully depleted SOI (FDSOI) [19,20] and
multigate MOSFETs, which are the topic of Chapter 2.
12 Introduction
1.6 Ballistic transport in nanotransistors
The mobility μ used in Eqs. (1.1) and (1.2) is based on integrating both the effects of the
acceleration of an electron by an electric field and the slowing down of the same electron
by isotropic scattering events. The resulting mobility is given by μ ¼ qτ=m where m* is
the effective mass of the electron in the transport direction and τ is the “relaxation time”
or the average time between scattering events [21]. In very short-channel devices, the
probability that carriers in the channel undergo scattering events is reduced or, in other
words, an electron can travel from source to drain in a time smaller than or comparable
to τ. If no scattering event occurs the transport of the carrier is said to be “ballistic,” and
the concept of mobility, which is based on multiple scattering events, becomes irrele-
vant. This point will be addressed again in Chapter 6.
1.6.1 Top-of-the-barrier model

A convenient and easy-to-use model for current flow in a transistor based on ballistic
transport has been developed [22,23,24]. The current is described as the difference
between injected and backscattered fluxes of carriers. Carriers in the source are assumed
to have an intrinsic “Brownian” thermal velocity given by
rffiffiffiffiffiffiffiffiffiffiffi
2kB T
vtherm ¼ ; ð1:4Þ
πm
where T is the temperature in degrees Kelvin, kB is Boltzmann’s constant and m* is the

carrier’s effective mass. The thermal velocity vtherm is approximately equal to 1.2×
107 cm/s in silicon. When a gate bias is applied, the potential barrier in the channel is
lowered such that carriers from the source have sufficient thermal energy that they can
reach the top of the barrier in the channel close to the source and flow over it. In such a
case, the current is given by
ID ¼ WCox ðVG VTH Þvinj ; ð1:5Þ
where W is the transistor width, Cox is the gate oxide capacitance, VTH is the threshold
voltage, and vinj is the average velocity of the carriers injected into the channel. The
maximum value of vinj is approximately the equilibrium uni-directional thermal velocity,
because the charge carriers with positive (forward) momentum at the beginning of the
channel are injected from a reservoir where the carriers are at thermal equilibrium or at
least assumed to be in equilibrium in the source. Backscattering from the channel
determines how close to this upper limit the device operates. Under high drain bias,
the average velocity at the beginning of the channel can be related to a channel back-
scattering coefficient, Rc, which may be written as

1 Rc
vinj ¼ vtherm : ð1:6Þ
1 þ Rc
1.6 Ballistic transport in nanotransistors 13
Backscattering to
source is possible
Ba
Source
ck
kB T/q
sc
at s u
er nl
i
rin ike
g ly
to
l
so
u
rc
e
Drain
Figure 1.8 Carrier backscattering in a MOSFET under high drain bias. If a carrier travels beyond the top
of the barrier or virtual source by a distance l, it is unlikely to be backscattered to the source and
will exit the channel to the drain region.
Rc is a “reflection” or backscattering coefficient that represents the degree of ballisticity.

If Rc = 0 the current is purely ballistic, and if Rc = 1 all carriers are reflected back to the
source, such that none of them are transmitted to the drain. Combining the two latter
expressions results in

1 Rc
ID ¼ WCox ðVG VTH Þvtherm : ð1:7Þ
1 þ Rc
Note that pure ballistic current (Rc = 0) is independent of channel length. Dependence on
the gate length for a non-purely ballistic device is reflected by the “degree of ballisti-
city,” ð1 Rc Þ=ð1 þ Rc Þ term. Rc can be calculated from the mean free path for back-
scattering λ and a critical distance l passed when the electron in the channel cannot be
scattered back due to the lack of thermal energy kBT/q required to overcome the potential
barrier as depicted in Fig. 1.8. The expression for the backscattering coefficient in a
field-free semiconductor slab of length L is given by
L
Rc ¼ ; ð1:8Þ
Lþλ
which is shown in detail in Section 6.6. Since the carriers can only be backscattered
within the distance l from the top of the barrier or virtual source, the backscattering
coefficient Rc in this scenario becomes
l
Rc ¼ : ð1:9Þ
lþλ
From Fig. 1.8, it can be seen that l ¼ kB T=jqjE, where E ffi VDS/LG is the electric field
in the direction of transport on the drain side of the virtual source. In general, the mean
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
free path for backscattering can be expressed as λ ¼ τ 2πkB T=m .
14 Introduction
0.7
Electrons
0.6
Degree of ballisticity
0.5
(1-Rc) / (1+Rc)
0.4
0.3
0.2 Holes
0.1
0
10 100 1000
Gate length, LG (nm)
Figure 1.9 Degree of ballisticity,ð1 Rc Þ=ð1 þ Rc Þ; measured on n- and p-channel silicon gate-all-around
(GAA) nanowire transistors as a function of gate length. Nanowire diameter is 10 nm. After [28].
This simple “top-of-the-barrier” ballistic model is a very good physical model of the
behavior of nanoscale MOSFETs, except when attempting to explain the output
conductance, which is given by the variation of drain current with applied drain
voltage in saturation. More complete models that account for non-zero output con-
ductance, DIBL, finite source and drain resistance, and so on can be found in the
literature [25,26,27].
The degree of ballisticity can be measured using current–voltage measurements
performed at different temperatures [28]. Figure 1.9 shows ð1 Rc Þ=ð1 þ Rc Þ mea-
sured on silicon gate-all-around (GAA) nanowire transistors as a function of gate length.
As can be expected, the degree of ballisticity is very low in long-channel devices. It
increases as gate length is decreased and tends to unity as the gate length tends to zero. In
this graph, devices with LG > 100 nm operate in the drift-diffusion regime. They operate
in a quasi-ballistic regime for LG < 100 nm.
1.6.2 Ballistic scaling laws

One can derive scaling laws for nanoscale ballistic transistors in a similar way to the scaling
laws for classical MOSFETs, as shown in Table 1.1. Such a derivation can be found in [29]
for transistors whose channel is a two-dimensional electron gas (2DEG). The key features
are the inclusion of a “dark space” between the channel and the semiconductor/insulator
interface, tinv, the introduction of the “quantum capacitance” CDoS, and the non-scalability of
the subthreshold slope and the injection velocity. The intrinsic gate delay τ appears to scale
with the scaling factor γ, but only if the transistor’s input capacitance scales as γ. In
realistic devices, the input capacitance is the sum of the gate capacitance and “fringing”
capacitances between gate and source, and gate and drain. The latter tend to become
1.7 Summary 15
Table 1.2 Scaling rules for 2D nanoscale ballistic transistors. (*) In practice, fringing gate-source and gate-drain
capacitances are often larger than CG, such that the scaling factor is actually situated between γ0 and γ1 [29].
m∥ and m⊥ are the effective masses parallel and perpendicular to the transport direction, respectively.
Parameter Equation Unit Scaling factor
Physical dimensions: L, W, Xj, Xdepl m γ1

Channel wave function mean depth,
Tinv (dark space)
Voltages VDS, VGS, VTH Difficult to scale because subthreshold V γ0
slope cannot be decreased below
60 mV/decade
1
Integration density m−2 γ2
WL
εSiO2
Equivalent oxide thickness (EOT) tox ¼ tdielectric m γ1
εdielectric
εSiO2
Dielectric capacitance Cox ¼ F/m2 γ
tox
Gate capacitance CG ¼ WLCox F γ1
εsemicond WL
Capacitance of channel at depth Tinv Cdepth ¼ F γ1
T
qinv
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2
q g ðm2∥ m2⊥ ÞWL
DoS capacitance CDoS ¼ F γ1
(for g populated valleys) 2πℏ2
1
1 1 1
Gate-to-channel capacitance CGch ¼ þ þ F γ1
CG Cdepth CDoS
CGch
Electron density at the ns ¼ ðVG VTH Þ m−3 γ1
jqj
top of the barrier
!1
4 2jqjCGch ½VG VTH 2
Injection velocity vinj ¼ m s−1 γ0
3π m∥ CDoS
Drain current IDsat ¼ qns vinj ffi WCox ðVG VTH Þvinj A γ0
CG VDS
Intrinsic gate delay (neglecting τ¼ s γ1
IDsat
fringing capacitances)*
dominant in nanoscale devices, such that the gate delay does not improve significantly
with scaling. However, if the parasitic capacitances can be scaled similarly to the
transistor scaling, improvement can be seen as the intrinsic device speed continues to
increase with scaling. The current drive of the transistors decreases when gate length is
scaled below 15 nm [30]. Nanoscale “ballistic scaling rules” are listed in Table 1.2.
1.7 Summary
In this chapter, a brief history of electronics with an emphasis on Moore’s law is given
and a discussion on the technology boosters that have enabled the continued
16 Introduction
miniaturization of transistors is outlined. A summary of some of the challenges to the

operation of planar MOSFETs was introduced and motivated the requirement for
alternative transistor architectures below 20 nm. However, on these length scales new
physical mechanisms become important, such as ballistic transport, and a simple model
to describe charge transport in the quasi-ballistic regime was described. “Happy scaling”
of classical MOSFETs was introduced and compared to a similar set of rules that may
be applied to guide transistor design choices for transistors as they become scaled to
length scales at which ballistic effects begin to dominate electron and hole currents.
References
[1] http://en.wikipedia.org/wiki/Transistor
[2] J.E. Lilienfeld, “Method and apparatus for controlling electric current,” US patent
1745175, first filed in Canada on 22 October 1925.
[3] J.E. Lilienfeld, “Device for controlling electric current,” US patent 1900018, filed
on 28 March 1928.
[4] Dawon Kahng, “Electric field controlled semiconductor device,” US Patent
3,102,230, filed on 27 August 1963.
[5] R.W. Bower, R.G. Dill, “Insulated gate field effect transistors fabricated using the
gate as source-drain mask,” International Electron Device Meeting (IEDM)
Technical Digest, pp. 102–104 (1966).
[6] F. Wanlass, C. Sah, “Nanowatt logic using field-effect metal-oxide semiconductor
triodes,” IEEE International Solid-State Circuits Conference, Digest of Technical
Papers, p. 6 (1963).
[7] G.E. Moore, “Cramming more components onto integrated circuits,” Electronics
38, pp. 114–117 (1965), also reprinted in Proceedings of the IEEE 86(1), pp. 82–85
(1998).
[8] C.A. Colinge, J.P. Colinge, Physics of Semiconductor Devices, Kluwer Academic
Publishers (now: Springer), p. 196 (2002).
[9] G.A. Armstrong, J.R. Davis, A. Doyle, “Characterization of bipolar snapback and
breakdown voltage in thin-film SOI transistors by two-dimensional simulation,”
IEEE Transactions on Electron Devices 38, pp. 328–336 (1991).
[10] K.E. Moselund et al., “Punch-through impact ionization MOSFET (PIMOS): from
device principle to applications,” Solid-State Electronics 52, pp. 1336–1344 (2008).
[11] Q. Zhang, W. Zhao, A. Seabaugh, “Low-subthreshold-swing tunnel transistors,”
IEEE Electron Device Letters 27, pp. 297–300 (2006).
[12] H. Lu, A. Seabaugh, “Tunnel field-effect transistors: state-of-the-art,” IEEE
Journal of the Electron Device Society 2(4), pp. 44–49 (2014).
[13] A. Afzalian, J.P. Colinge, D. Flandre, “Physics of gate modulated resonant tunnel-
ing (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current,”
Solid-State Electronics 59, pp. 50–61 (2011).
[14] S. Salahuddin, S. Datta, “Use of negative capacitance to provide voltage amplifi-
cation for low power nanoscale devices,” Nano Letters 8, pp. 405–410 (2008).
[15] V.V. Zhirnov, R.K. Cavin, “Nanoelectronics: negative capacitance to the rescue?,”
Nature Nanotechnology 3(2), pp. 77–78 (2008).
References 17
[16] S. Salahuddin, S. Datta,“Can the subthreshold swing in a classical FET be lowered

below 60 mV/decade?,” Technical Digest of the International Electron Devices
Meeting (IEDM), pp. 693–696 (2008).
[17] R.H. Dennard et al., “Design of ion-implanted MOSFETs with very small physical
dimensions,” IEEE Journal of Solid-State Circuits 9(5), pp. 256–268 (1974).
[18] T. Skotnicki, F. Boeuf, “How can high-mobility channel materials boost or degrade
performance in advanced CMOS,” Proceedings VLSI Symposium, pp. 153–154
(2010).
[19] J.P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd edition,
Kluwer Academic Publishers (2004).
[20] O. Kononchuk, B.-Y. Nguyen (eds.), Silicon-On-Insulator (SOI) Technology:
Manufacture and Applications, Elsevier (2014).
Publishers (now: Springer), pp. 51–55 (2002).
[22] A. Rahman et al., “Theory of ballistic nanotransistors,” IEEE Transactions on
Electron Devices 50(9), pp. 1853–1864 (2003).
[23] K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor,” Journal of
Applied Physics 76(8), pp. 4879–4890 (1994).
[24] M.S. Lundstrom, Z. Ren, “Essential physics of carrier transport in nanoscale
MOSFETs,” IEEE Transactions on Electron Devices 49(1), pp. 133–141 (2002).
[25] A. Khakifirooz, O.M. Nayfeh, D. Antoniadis, “A simple semiempirical short-
channel MOSFET current–voltage model continuous across all regions of opera-
tion and employing only physical parameters,” IEEE Transactions on Electron
Devices 56(8), pp. 1674–1680 (2009).
[26] A. Majumdar, D.A. Antoniadis, “Analysis of carrier transport in short-channel
MOSFETs,” IEEE Transactions on Electron Devices 61(2), pp. 351–358 (2014).
[27] M.S. Lundstrom, D.A. Antoniadis, “Compact models and the physics of nanoscale
FETs,” IEEE Transactions on Electron Devices 61(2), pp. 225–233 (2014).
[28] R. Wang et al., “Experimental investigations on carrier transport in Si nanowire
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[29] M.J.W. Rodwell et al., “III-V MOSFETs: scaling laws, scaling limits, fabrication
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band atomistic modeling,” Applied Physics Letters 105, pp. 083508.1–4 (2014).
2 Multigate and nanowire transistors
As presented in Chapter 1, the use of a multigate architecture is a technology booster that

allows improved electrostatic control of a channel region by the gate electrode, and
therefore mitigates short-channel effects. Currently existing multigate architectures for
the MOSFET are described, and then compared in terms of short-channel effect control.
It is concluded that the gate-all-around structure associated with a nanowire-shaped
semiconductor offers the best possible electrostatic control of a channel. Different
effects arising from carrier confinement effects in semiconductor nanowires are con-
sidered. The chapter concludes with a discussion of novel phenomena arising from
quantum confinement, such as the semimetal–semiconductor transition, band folding
of the electronic structure in nanowires, and novel devices that can be devised on the
nanometer length scale.
2.1 Introduction
In the classical planar MOSFET, the gate dielectric and gate electrode sit above the
channel region. Electrostatic control of the channel by the gate is achieved through the
capacitive coupling between the gate and the channel. To maintain transistor scaling
laws, a reduction in the depths of the source and drain regions by the same factor as the
gate length reduction is required. This reduces short-channel effects at the cost of
rendering less effective the control of the channel region through source and drain
voltages. High-κ dielectrics are used as gate oxide materials to increase current drive
without having to pay a stiff penalty in gate oxide leakage, which is in turn largely
responsible for standby power consumption. Decreasing the equivalent gate oxide
thickness (EOT) through the replacement of the silicon dioxide insulating layer by
metallic oxides with higher dielectric constant improves the capacitive coupling
between the gate and the channel, and thus also reduces short-channel effects.
The electrostatics of a planar, long-channel MOSFET can be reduced in a first
approximation to a one-dimensional problem. Early textbooks on semiconductor device
physics introduced the “gradual channel approximation,” which can be solved by
Poisson’s equation – the equation that governs the relationship between electric fields
and electrical charges – in one dimension, vertically from the gate through the channel
and down through the silicon substrate. Short-channel effects whereby electric fields
from the source and the drain encroach laterally (horizontally) in the channel region
2.2 The multigate architecture 19
introduce a second dimension to the problem. In planar MOSFETs on bulk silicon, short-
channel effects become insurmountable once the gate length becomes smaller than
approximately 15 to 20 nm. Below that length scale, there is a requirement to improve
the electrostatic control of the channel region by thinning down the silicon substrate on
which the channel is formed. This is why the industry was recently forced to switch from
the familiar bulk MOSFET structure, to more advanced device architectures such as
fully depleted silicon-on-insulator (FDSOI) and multigate MOSFETs [1,2].
2.2 The multigate architecture
Improvement of the electrostatic control of the channel by the gate can be achieved by
modifying the shape of the MOSFET. Multigate MOSFETs take advantage of the third
dimension to counteract short-channel effects. The term “multigate” is perhaps not the
most appropriate one, as these devices have a single gate electrode. It simply means that
this electrode is wrapped around several sides of the channel region. For the sake of
clarity, the MOSFETs of Fig. 2.1(a) and Fig. 2.1(b) will be referred to here as “single-
gate” transistors, whilst the other devices of Fig. 2.1 will be described as double-gate,
and triple-gate or gate-all-around MOSFETs. The gate-all-around device is covered on
all sides by the gate electrode, while the pi-gate (П-gate) and the omega-gate (Ω-gate)
structures derive their names from the shape of the gate electrode [3,4].
The first publication describing a double-gate SOI MOSFET dates back to 1984. The
device received the acronym XMOS because of the resemblance of the structure with
the Greek letter Ξ (Xi) in which a thin silicon channel is sandwiched between two
gates [5]. This pioneering paper predicted an improvement of short-channel character-
istics brought by the double-gate architecture over the classical single-gate approach.
The first fabricated double-gate SOI MOSFET was the fully DEpleted Lean-channel
TrAnsistor (DELTA, 1989) with a silicon film stood vertically on its side [6]. Later
implementations of vertical-channel, high aspect ratio double-gate SOI MOSFETs
include the trigate FET or FinFET (Fig. 2.1(d) and (e)) [7,8]. To improve control of
the channel from three sides, the thickness (height) of the channel region must be
decreased, which produces nanowire-like devices such as the quantum-wire SOI
MOSFET [9] and the triple-gate MOSFET (Fig. 2.1(c)) [10]. Improved channel control
can be achieved using a field-induced, pseudo-fourth gate such as in the Π-gate
MOSFET [11] and the Ω-gate device (Fig. 2.1(f) and (g)) [12]. The first “gate-all-
around” (GAA) device, published in 1990, was in reality a double-gate transistor
although the gate electrode did wrap around all sides of the channel region [13].
Nowadays the term “GAA” is preferentially used to describe a nanowire-like
MOSFET where the gate is wrapped around the channel region (Fig. 2.1(h) and (i)).
Using such gate architectures, it is even possible to fabricate MOSFET devices without
introducing pn junctions for the source and drain [14]. Such “junctionless” multigate
transistors have a great potential for greatly simplifying the MOSFET fabrication
process at the nanometer length scale [15,16]. It is also possible to insert electron trap
layers or nanocrystals in the gate dielectric to create nanowire flash memory transistors
(a) (b) (c)
(f)
(d) (e)
(i)
(g) (h)
Figure 2.1 Different types of MOSFETs sorted by gate configuration. (a) Single-gate planar bulk MOSFET.
(b) Single-gate SOI MOSFET with mesa isolation. (c) Triple-gate (trigate) SOI nanowire
MOSFET with square cross-section. (d) Bulk trigate MOSFET with high aspect ratio (bulk
FinFET). (e) SOI trigate MOSFET with high aspect ratio (SOI FinFET). (f) Pi-gate (Π-gate) SOI
nanowire MOSFET. (g) Omega-gate (Ω-gate) SOI nanowire MOSFET. (h) Horizontal gate-all-
around (GAA, quadruple-gate, quad-gate) nanowire transistor with square section. (i) Vertical
gate-all-around (GAA) nanowire MOSFET with circular cross-section [20,21,22,23,24,25].
[17,18]. One of the shortest MOSFETs published to date has a gate length of 3.8 nm. It
employs a trigate structure and achieves a subthreshold slope of 92 mV/dec, and a drain-
induced barrier lowering (DIBL) of 148 mV/V [19].
2.3 Reduction of short-channel effects using multigate architectures
Subthreshold slope degradation and drain-induced barrier lowering (DIBL) are caused
by the encroachment of electric field lines from the source and drain into the channel
region, thereby competing for the available depletion charge, and reducing the threshold
voltage. The distribution of electrical potential in the channel region of a MOSFET can
be derived directly from Maxwell’s equation ∇ ~D ~ ¼ ρ where D ~ ¼ ε~E is the electrical
2.3 Reduction of short-channel effects 21
Top ga
te
x
y ate
Left g
Drain
z EX
EY
Source EZ
ate
Right g
Bottom g
ate
Figure 2.2 Coordinate system and electric field components in a multiple-gate device. The electric field
from the gates and from the drain “compete” for the control of the channel.
displacement field, ε is the permittivity of the material, ~ E is the electric field, and ρ is the
local charge density: dEx =dx þ dEy =dy þ dEz =dz ¼ ρ=ε = a constant value at a fixed
point.
The latter relation is called Poisson’s equation. It can be used to show how the gates
and the source/drain compete for control of the charge in a MOSFET’s channel. The
control by the gate electrode is exerted in the y and z directions and competes with the
variation of electric field in the x direction due to the source and drain voltages. Since
the sum of all the terms of Poisson’s equation is a constant, any increase of the control by
the top and bottom gates through dEz =dz or by the left- and right-hand side gates will
decrease the penetration of the source/drain electric fields in the channel region, dEx =dx.
Figure 2.2 shows the competition between the different electric fields for an elemental
charge in the channel region.
Based on Poisson’s equation and along with a few simplifying assumptions, it is
possible to calculate a parameter called the “natural length,” denoted λ. The analysis
leads to the conclusion that the natural length represents the extension of the electric field
lines from the source and drain into the channel region. A device will effectively be free of
short-channel effects if the gate is at least six times longer than λ. For instance, in the case
of a double-gate MOSFET, one can show that the subthreshold swing, SS, increases as the
gate length is decreased according to the following relationship, valid for LG > 2λ [26]:
kB T
SS ¼ lnð10Þ = ½1 2expðLG =2λÞ: ð2:1Þ
jqj
The potential distribution in the channel of a fully depleted, inversion-mode n-channel

MOSFET can be obtained by solving Poisson’s equation using the depletion
approximation
d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ qNa

þ þ ¼ : ð2:2Þ
dx2 dy2 dz2 ε Si
It is useful to understand the meaning of this equation. It can be rewritten in the form
dEx ðx; y; zÞ dEy ðx; y; zÞ dEz ðx; y; zÞ

þ þ ¼ C: ð2:3Þ
dx dy dz
This relationship means that about any point (x,y,z) in the channel, the sum of the
variations of the electric field components in the x, y, and z directions equals a
constant. Thus, as one of the components increases the other ones (or, to be more
exact, their sum) must decrease. In Fig. 2.2, the x component of the electric field
Ex represents the encroachment of the drain electric field on the channel region, and
therefore short-channel effects. The influence of Ex on a small element of the channel
region located at coordinates (x,y,z) can be reduced by either increasing the channel
length, L, or by increasing the control exerted on the channel by the top/bottom gates
through dEz ðx; y; zÞ=dz, or the lateral gates through dEy ðx; y; zÞ=dy. This can be achieved
by reducing the silicon fin thickness tSi and/or the fin width WSi and/or by decreasing the
gate oxide thickness. In addition, an increase of dEy ðx; y; zÞ=dy þ dEz ðx; y; zÞ=dz results
and, hence, a better control of the channel by the gates and fewer short-channel effects
can also be obtained by increasing the number of gates: dEz ðx; y; zÞ=dz can be increased
by having two gates (top and bottom gates) instead of a single gate, and dEy ðx; y; zÞ=dy
can be increased by the presence of two lateral gates.
2.3.1 Single-gate MOSFET

In the case of an infinitely wide single-gate SOI MOSFET, the electrostatic potential is
uniform along the y direction and dΦ=dy ¼ 0, Poisson’s equation simplifies to
d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ qNa

þ ¼ : ð2:4Þ
dx2 dz2 ε Si
Assuming the gate is above the channel as in Fig. 2.1(b) and using the depletion
approximation automatically yields a parabolic potential distribution in the silicon film
in the z (vertical) direction. The potential can be expressed as
Φðx; zÞ ¼ c0 ðxÞ þ c1 ðxÞz þ c2 ðxÞz2 : ð2:5Þ
In the case of a single-gate SOI device the boundary conditions to Eq. (2.4) are:
1. Φðx; 0Þ ¼ Φf ðxÞ ¼ c0 ðxÞ where Φf ðxÞ is the front surface potential;
2. dΦðx; zÞ=dzjz ¼ 0 ¼ εSi ðΦf ðxÞ ΦG Þ=εSi tox ¼ c1 ðxÞ where ΦG ¼ VG VFBF is the
front gate voltage VG minus the front gate flat-band voltage VFBF;
3. if we assume that the buried oxide (BOX) is very thick the potential difference across
any finite distance in the BOX is negligible in the y direction such that dΦðx; zÞ=dz ffi 0
in the BOX region. Therefore, we have: dΦðx; zÞ=dzjz ¼ tSi ¼ c1 ðxÞ þ 2tSi c2 ðxÞ ffi 0
and thus c2 ðxÞffi c1 ðxÞ=2tSi .
Introducing these three boundary conditions in Eq. (2.4) we obtain
εox Φf ðxÞ ΦG 1 εox Φf ðxÞ ΦG 2

Φðx; zÞ ¼ Φf ðxÞ þ z ; ð2:6Þ
εSi tox 2tSi εSi tox
Combining Eqs. (2.4) and (2.6) and setting z = 0, at which depth the surface potential can
be defined as Φf ðxÞ ¼ ΦG ðx; z ¼ 0Þ results in
d 2 Φf ðxÞ εox Φf ðxÞ ΦG qNa

¼ : ð2:7Þ
dx2 εSi tSi tox εSi
Once Φf ðxÞ is determined from Eq. (2.7), Φðx; yÞ can be calculated using Eq. (2.6).
Equation (2.7), however, can be used for another purpose. Define
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
εSi
λ1 ¼ tox tSi ; ð2:8Þ
εox
and
qNa 2
φðxÞ ¼ Φf ðxÞ ΦG þ λ; ð2:9Þ
εSi 1
which permits Eq. (2.7) to be rewritten as
d 2 φðxÞ φðxÞ
2 ¼ 0: ð2:10Þ
dx2 λ1
This equation has a solution in the form φðxÞ ¼ φ0 expðx=λ1 Þ where λ1 is a para-
meter that represents the spread of the electric potential in the x direction. Note that φ(x)
differs from Φf ðxÞ only by an x-independent term. The parameter λ1 is defined to be the
“natural length” of the device. It depends on the gate oxide thickness and the silicon film
thickness [26]. The thinner the gate oxide and/or the silicon film, the smaller the natural
length and, hence, the influence of the drain electric field on the channel region.
Numerical simulations show that the effective gate length of a MOS device must be
larger than 5 to 10 times the natural length to avoid short-channel effects and a good rule
of thumb is 6 times the natural length to assure good electrostatic control of the channel.
2.3.2 Double-gate MOSFET

Assume the two gates are perpendicular to the z direction (i.e. the gates are at the top and
bottom of the channel in Fig. 2.1). Again using the depletion approximation for
Poisson’s equation, the parabolic potential distribution in the channel can be written as
in Eq. (2.5):
Φðx; zÞ ¼ c0 ðxÞ þ c1 ðxÞz þ c2 ðxÞz2 : ð2:11Þ
The boundary conditions to Poisson’s equation for the case of Eq. (2.4) are:
1. assuming the device is infinitely wide in the y direction leads to dΦ=dy ¼ 0;

2. Φðx; 0Þ ¼ Φf ðx; tSi Þ ¼ c0 ðxÞ whereΦf ðxÞ is the front surface potential;
3. dΦðx; zÞ=dzjz¼0 ¼ εSi Φf ðxÞ ΦG =εSi tox ¼ c1 ðxÞ where ΦG ¼ VG VFB is the
front gate voltage, Vgs, minus the front gate flat-band voltage VFBF;
4. dΦðx; zÞ=dzjz¼tSi =2 ¼ 0 and thus c2 ðxÞffi 4c1 ðxÞ=tSi ; where tSi is the SOI film
thickness.
Substituting these boundary conditions into Eq. (2.11) yields
εox Φs ðxÞ ΦE 1 εox Φs ðxÞ ΦG 2

Φðx; zÞ ¼ Φf ðxÞ þ z z : ð2:12Þ
εSi tox tSi εSi tox
In a double-gate device, short-channel effects will take place at the center of the silicon
film at z ¼ tSi =2 since that is the region that is furthest away from the gates. The potential
at the center of the film/fin Φc ðxÞ is obtained by writing y ¼ tSi =2 in Eq. (2.12), which
yields

1 εox tSi
Φf ðxÞ ¼ εox tSi Φc ðxÞ þ 4εSi tox ΦG : ð2:13Þ
1þ
4εSi tox
Expressing Φðx; zÞ as a function of Φc ðxÞ results in

0 εox tSi 1
2
Φc ðxÞ þ ΦG
εox y εox z B 4εSi tox C εox y εox z2
Φðx; zÞ ¼ 1þ :@ εox tSi A ΦG ΦG :
εSi tox εSi tox tSi 1þ εSi tox εsi tox tSi
4εSi tox
ð2:14Þ
Substituting Eq. (2.14) into Eq. (2.4) allows Poisson’s equation to be re-expressed as
d 2 Φc ðxÞ ΦG Φc ðxÞ qNa

þ ¼ : ð2:15Þ
dx2 λ22 εSi
This expression is of the same form as Eq. (2.7) with the natural length λ in this case
given by [27]
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
εSi εox tSi
λ2 ¼ 1þ tSi tox : ð2:16Þ
2εox 4εSi tox
2.3.3 Triple- and quadruple-gate MOSFETs

In the case of a quadruple-gate device with a square cross-section, symmetry imposes
d 2 Φðx; y; zÞ=dy2 ¼ d 2 Φðx; y; zÞ=dz2 in the center of the nanowire such that Poisson’s
equation (2.1) can be written
d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ q Na
2
þ2 ¼ : ð2:17Þ
dx dy2 εSi
Following similar steps to those outlined above leads to the natural length for the
symmetric quadruple gate device to be expressed as [28]
ffi
εSi εox tSi
λ4 ¼ 1þ tSi tox : ð2:18Þ
4εox 4εSi tox
There is no simple derivation of the natural length for triple-gate devices, but numerical
simulations suggest that the expression
ffi
εSi εox tSi
λ3 ¼ 1þ tSi tox ð2:19Þ
3εox 4εSi tox
is a good approximation for the case where the channel is surrounded on three sides by
the gate electrode [29].
2.3.4 Cylindrical gate-all-around MOSFET

In the case of a cylindrical gate-all-around MOSFET, the natural length can be calculated
using Poisson’s equation in cylindrical coordinates:

1d dΦðx; rÞ d 2 Φðx; rÞ q Na
r þ ¼ : ð2:20Þ
r dr dr dx2 εSi
Using a similar approach as for the double-gate device, a parabolic potential distribu-
tion in the radial direction is assumed:
Φðx; rÞ ¼ co ðxÞ þ c1 ðxÞ r þ c2 ðxÞ r2 : ð2:21Þ
The boundary conditions to Poisson’s equation for the case represented by

Eq. (2.20) are:
1. The potential in the center of the nanowire is a function of x only: Φðx; 0Þ ¼ c0 ðxÞ;
2. dΦðx; rÞ=drjr¼0 ¼ 0 and thus c1 ðxÞ ¼ 0;
3. Φ ðx; RÞ ¼ Φf ðxÞ ¼ c0 ðxÞ þ c1 ðxÞ R þ c2 ðxÞ R2 where Φf ðxÞ is the surface potential
and R is the radius of the nanowire;
4. The electric field at the nanowire/gate oxide interface can be written as
0 1

dΦðx; rÞ εox B ΦG Φf ðxÞ C
¼ @ A ¼ tSi c2 ðxÞ; ð2:22Þ
dr εSi tSi ln 1 þ tox
r ¼ R
2 R
where ΦG ¼ VG VFB is the front gate voltage Vgs minus the gate flat-band voltage VFB,
and Φf ðxÞ is the surface potential in the channel.
Substituting these boundary conditions into Eq. (2.21) yields
0 1
2
1B εox r Φc ðxÞ ΦG C
Φðx; rÞ ¼ Φf ðxÞ @ A: ð2:23Þ
2 ε R2 ln 1 þ tox þ ε R2
Si ox
R
Using this potential distribution, Poisson’s equation can be solved at the center of the
nanowire, where the short-channel effects are the strongest because this is the place
furthest away from the gate:
d 2 Φc ðxÞ ΦG Φc ðxÞ qNa

þ ¼ ; ð2:24Þ
dx2 λ2GAA εSi
where
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

u
u2ε R2 ln 1 þ tox þ ε R2
t Si R
ox
λGAA ¼ ð2:25Þ
4εox
is the natural length for a cylindrical channel in a gate-all-around (GAA)

configuration [30].
The drain-induced barrier lowering (DIBL) and subthreshold swing in cylindrical
GAA nanowire transistors with different diameters and gate oxide thickness values are
shown in Fig. 2.3 as a function of the normalized gate length LG/λGAA.
The natural lengths for the different gate architectures are listed in Table 2.1. Simple
observation of the expressions for the natural length in double-, triple-, and quadruple-
gate devices with a square cross-section suggests defining an “effective number of
250 110
200 Subthreshold slope 100

Subthreshold slope
DIBL
DIBL (mV)
150 90
(mV/dec)
100 80
50 70
0 60
0 10 20 30
Normalized gate length, LG / lGAA
Figure 2.3 Drain-induced barrier lowering (DIBL) and subthreshold swing in cylindrical GAA nanowire
transistors as a function of the normalized gate length, LG/λGAA. Adapted from [30].
Table 2.1 Natural length λ, for different gate architectures. R is the nanowire radius (cylindrical case),
tSi is the nanowire width and height (square section case), and tox is the gate oxide thickness.
Gate architecture Natural length Ref.

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
εSi
Single gate, planar device λ1 ¼ tSi tox [26]
εox
ffi
εSi εox tSi
Double gate, λ2 ¼ 1þ tSi tox [27]
2εox 4εSi tox
rectangular cross-section
ffi
εSi εox tSi
Triple gate, λ3 ¼ 1þ tSi tox [29]
3εox 4εSi tox
square cross-section
ffi
εSi εox tSi
Quadruple gate, λ4 ¼ 1þ tSi tox [28]
4εox 4εSi tox
square cross-section vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u
u2εSi R2 lnð1 þ tox Þ þ εox R2
t R
Cylindrical GAA λGAA ¼ [30]
4εox
gates,” n, which is equal to 2, 3, or 4 for double-, triple-, and quadruple-gate devices with
a square cross-section, respectively. The natural length for a square-section device with
n gates is then given by the general expression
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
εSi εox tSi
λn ¼ 1þ tSi tox : ð2:26Þ
nεox 4εSi tox
Interestingly, the “effective number of gates” can be extended to Π-gate and Ω-gate
devices with a non-integer value of n ranging between 3 and 4 [30,31].
Figure 2.4 shows the subthreshold slope (or subthreshold swing) and the drain-
induced barrier lowering (DIBL) in multigate transistors as a function of the gate length
normalized to the natural length LG =λn . The data in these plots are extracted from
numerical simulations. The fact that all types of devices fall on the same curve once
gate length is normalized to λn validates the concept of an “effective number of gates”
expressed in Eq. (2.26) [30].
Figure 2.5 shows the minimum gate length that is permissible for the different gate
architectures while avoiding short-channel effects. The curves are plotted as a function
of nanowire thickness/width or diameter in single-gate and multiple-gate devices. The
double-gate, triple-gate, and quadruple-gate MOSFETs have a square cross-section. The
gate oxide thickness in modern devices is scaled with the silicon thickness in such a way
that equivalent oxide thickness (EOT) is the silicon thickness/diameter divided by 5.
One assumes that the minimum channel length is equal to six times the natural length in
order to avoid short-channel effects (Lmin ¼ 6λ). Increasing the effective number of
gates clearly improves short-channel effects and allows one to achieve shorter gate
lengths for a given silicon thickness. The cylindrical device offers the best gate control
and, hence, the lowest short-channel effects of all devices. Since the models developed
130 350
(a) (b)
Double gate (n = 2) Double gate (n = 2)
Subthreshold slope (mV/dec)
120 Tri-gate (n = 3)
300 Tri-gate (n = 3)
P-gate (n = 3.14) P-gate (n = 3.14)
110 W-gate (n = 3.4) 250 W-gate (n = 3.4)
GAA (n = 4) GAA (n = 4)
DIBL (mV)
100 200
90 150
80 100
70 50
60 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12
LG/l LG/l
Figure 2.4 (a) Subthreshold slope (or swing) and (b) drain-induced barrier lowering (DIBL) in multigate
transistors as a function of the normalized gate length LG/λn.
70 Single gate
Double gate
60
Minimum gate length (nm)
Triple gate
50 Quadruple gate
Cylindrical GAA
40
30
20
10
0
2 4 6 8 10 12 14
Silicon thickness/width or diameter (nm)
Figure 2.5 Minimum gate length as a function of nanowire thickness/width or diameter. Double-gate,
triple-gate, and quadruple-gate MOSFETs have a square cross-section. The equivalent oxide
thickness (EOT) is taken as one-fifth the silicon thickness/diameter. One assumes that the
minimum channel length is equal to six times the natural length in order to avoid short-channel
effects (Lmin ¼ 6λ).
above for the natural length do not account for quantum confinement effects, silicon
thickness/width/diameter values lower than 4 nm are not considered. However, this can
be treated using more complex models [32].
It is worth noting that the improved electrostatic control brought about by the GAA
architecture not only improves short-channel effects, but also improves reliability by
reducing hot-carrier degradation by minimizing the impact of interface trap generation
on the electrostatics in the channel [33]. It also reduces negative-bias temperature
2.4 Quantum confinement effects 29
instability (NBTI) degradation, as well as threshold variability and transistor mismatch

[34,35,36].
2.4 Quantum confinement effects in nanoscale multigate transistors
The cross-section of nanowire multigate MOSFETs can be quite small. When nanowire
transistors have heights and widths smaller than between 5 and 20 nanometers, depen-
dent on the semiconductor material, one-dimensional quantum confinement effects
begin to appear. These effects are manifested in the formation of energy subbands,
variation of band gap energy with diameter, and the reduction in the number of conduc-
tion channels available for charge transport (quantum capacitance).
2.4.1 Energy subbands

In a “large” silicon crystal electrons can move in the three directions of space. In a
nanowire with a very small cross section, the electrons can only move along the length of
the wire (x direction) and form standing waves along the directions perpendicular to
this motion. The electrons forming these standing waves have discrete energy values.
Assuming a nanowire with rectangular cross-section (height = tSi, width = WSi), solving
the 2D particle-in-a-box problem using Schrödinger’s equation yields the energy
values [37]:

ℏ2 πny 2 ℏ2 πnz 2
Eny ;nz ¼ þ ; ð2:27Þ
2my tSi 2mz WSi
where ny ¼ 1; 2; 3; …; nz ¼ 1; 2; 3; …, and where mi is the effective mass of electrons in

the crystal ith direction of confinement. Adding to the values of Eny ;nz the energy of the
electron in the direction of motion along the nanowire Enx ¼ ðℏknx Þ2 =2mx , where ℏknx is
the momentum of the electron in the x direction. As the electron energy in the confine-
ment direction is quantized and the electron energy in the propagating direction forms a
quasi-continuum, it is found that the permitted energy levels for the electrons form a
series of continuum levels within the conduction bands, labeled “energy subbands.”
Each subband has its own minimum energy Eny ;nz with the lowest energy given for ny ¼
nz¼1 resulting in an energy
2 2
ℏ2 π ℏ2 π
E1;1 ¼ þ ð2:28Þ
2my tSi 2mz WSi
above the conduction band minimum. The density of states (DoS) in each subband is
infinite at each “resonance” energy level Eny ;nz due to the discontinuities due to the
subband quantized levels, but drops as a function of the square root of energy above the
onset marked by the subband levels [37]
(a) Energy, E (b)
Energy, E
Enx,ny
E2,2
E2,1
E1,2
DE
E1,1
Ec
Momentum, kx Density of states, DoS
Figure 2.6 (a) Energy vs. electron momentum in the transport direction x. Five subbands are shown in this
example. (b) Density of states vs. energy. ΔE is the energy separation between the two first
subbands with energy E1;1 and E1;2 .
dn 1 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
DoS ¼ ¼ 2mðE Eny nz Þ; ð2:29Þ
dE πℏ
where n is the number of electron levels within a narrow energy range. The energy
dispersion or E versus k band diagram and the density of states in the conduction band of
a semiconductor nanowire are shown in Fig. 2.6.
The electrons associated with the lowest energy E1;1 are located mostly in the center of
the nanowire [38,39]. In subthreshold operation, most of the electrons are in the lowest
subband and thus concentrated about the center of the nanowire. As gate voltage is
increased and additional subbands become populated, electrons become increasingly
attracted by the gate electrode such that peaks of electron concentration are found at the
edges, and especially near corners of the nanowire channel. It is, however, important to
notice that a substantial portion of the electrons are still found inside the nanowire,
unlike in classical bulk devices where the electrons are confined to a thin inversion
layer at the surface of the silicon. This phenomenon, called “volume inversion” (or
“bulk inversion”), is unique to low-dimensional devices such as thin SOI films and
nanowires [40].
The electron concentration in inversion-mode trigate nanowire FETs is shown in
Fig. 2.7. The profiles are shown under different gate bias conditions: flat-band (VG =
VFB), threshold (VG = VTH), and above threshold (VG = VTH + 0.7 V). The devices have a
square section (WSi = tSi), and width/height of 3, 5, 10, and 20 nm. In devices with a
relatively large cross-section (Fig. 2.7(l) and to a lesser extent Fig. 2.7(i)), inversion
channels are clearly formed at the interfaces between the silicon fin and the gate oxide at
VG >>VTH, but there is some level of volume inversion at the center of the device. Peaks
of inversion electron concentration can be found at the top corners. In devices with a
smaller section shown in Fig. 2.7(c) and (f), volume inversion is clearly observed at
strong inversion. All devices show some level of volume inversion at VG = VTH shown in
Fig. 2.7(b), (e), (h), and (k) [41].
Wsi = tsi = 3 nm Wsi = tsi = 3 nm Wsi = tsi = 3 nm
Electron concentration
tox = 2 nm tox = 2 nm tox = 2 nm

Na = 5×1015 cm–3 Na = 5×1015 cm–3 Na = 5×1015 cm–3
VG = VFB VG = VTH VG = VTH+0.7 V
(a) (b) (c)


Na = 5×1015 cm–3 Na = 5×1015 cm–3 Na = 5×1015 cm–3
(d) (e) (f)

Na = 5×1015 cm–3 Na = 5×1015 cm–3 Na = 5×1015 cm–3
(g) (h) (i)



Na = 5×1015 cm–3 Na = 5×1015 cm–3 Na = 5×1015 cm–3
(j) (k) (l)
Figure 2.7 Electron concentration in inversion-mode trigate nanowire FETs. The absolute scale of the
vertical axis (electron concentration) is arbitrary and different for all cases presented here.
The product of the density of states by the Fermi–Dirac function, DoSðEÞ fFD ðEÞ, at
room temperature is shown for silicon trigate devices of different physical dimensions in
Fig. 2.8. The density of states for a 3D crystal is also shown for comparison purposes.
The devices have a square section and are biased under flat-band conditions. The density
of states in each subband is given by Eq. (2.29), where the density-of-states electron
mass is defined by
0.2 0.2
(a) Wsi = tsi = 3 nm (b) Wsi = tsi = 4 nm
tox = 2 nm
Energy above Ec (eV)

tox = 2 nm
Na = 5×1015 cm–3
Na = 5×1015 cm–3
VG = VFB
VG = VFB
0.1 0.1
1D
3D
0.0 0.0
0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0
DoS x FFD(E) (x106 cm–3eV–1) DoS x FFD(E) (x106 cm–3eV–1)
0.2 0.2
(c) (d) Wsi = tsi = 10 nm
Wsi = tsi = 5 nm tox = 2 nm

tox = 2 nm
Na = 5×1015 cm–3
Na = 5×1015 cm–3 VG = VFB
VG = VFB
0.1 0.1
0.0 0.0
0 0.5 1.0 1.5 2.0 0 1.0 2.0 3.0
0.2 0.2
(e) Wsi = tsi = 20 nm
(f) Wsi = tsi = 40 nm
tox = 2 nm tox = 2 nm
Na = 5×1015 cm–3 Na = 5×1015 cm–3

VG = VFB VG = VFB
0.1 0.1
0.0 0.0
0 1.0 2.0 3.0 0 0.5 1.0 1.5 2.0
Figure 2.8 Product of the density of states by the Fermi–Dirac function in 1D silicon nanowire trigate devices
with different cross-sectional dimensions, at room temperature. The dashed line is the
corresponding product for a 3D “bulk” MOSFET. Nanowire width and height are 3, 4, 5, 10, 20
and 40 nm in (a), (b), (c), (d), (e), and (f), respectively.
2 1=3
mDS ¼ 62=3 mt ml ¼ 1:08 m0 ; ð2:30Þ
where mt and ml are the transverse and longitudinal electron masses in a three-
dimensional silicon crystal. In the larger device with WSi = 40 nm, the density of states
is similar to that of a 3D device, apart from its “spiky” appearance. In smaller devices,
the formation of subbands becomes quite clear and, for instance, the energy separation
between the first and second subband is 40, 60, and 100 meV in devices with WSi = tSi = 5,
4, and 3 nm, respectively [41]. The electron concentration in the channel is given by
Ð EC
the following integral: n ¼ ∞ DoSðEÞ fFD ðEÞdE:
According to Eq. (2.27), the smaller the cross-sectional dimensions of the nanowire
given by tSi and WSi, the larger the energy separation between the subbands. If both
temperature and drain voltage are low enough, only the subband with lowest energy
becomes populated with electrons as gate voltage is increased above threshold. Thus the
current right above threshold is constituted of electrons in the first subband with energy
E1;1 and, as the gate voltage is increased, subbands with higher energies E1;2 , E2;1 , E2;2
and so on start contributing to the total current. This results in observable current
“oscillations” as the gate voltage is increased [42,43,44]. In order for these oscillations
to occur the thermal energy kB T must be smaller or at least not much larger than the
energy separation between the subbands. In addition, the equivalent thermal energy due
to the acceleration of the electrons from source to drain, qVD, must also be smaller than
the energy separation between the subbands. As long as the cross-section of the
nanowires is on the order of 10 nm × 10 nm, these conditions impose the use of
cryogenic temperatures and small drain voltages of a few millivolts, but current oscilla-
tions may become a common effect in future devices with cross-sectional dimensions of
only a few nanometers. Figure 2.9 shows the density of states in nanowires with a larger
Energy, E
Energy, E
T=0K T>0K
EF EF
(a) (b)
Density of states, DoS Density of states, DoS
Energy, E
Energy, E
T=0K T>0K
EF EF
(c) (d)
Density of states, DoS Density of states, DoS
Figure 2.9 Density of states and occupied states (in grey) in a “wide” nanowire at T = 0 K (a) and T > 0 K
(b), and in a “narrow” nanowire T = 0 K (c) and T > 0 K (d).
400
300 T = 4.4 K
Drain current (nA)
8K
200
100 150 K
28 K
0
0.0 0.1 0.2 0.3
Gate voltage (V)
Figure 2.10 Oscillations of drain current in an n-channel silicon nanowire trigate transistor with gate
voltage, measured at different temperatures. Diameter is approximately 40 nm. VDS = 0.2 mV.
After [46].
(a, b) or smaller (c, d) cross-section, and at T = 0 K or T > 0 K. The energy separation

between subbands is larger in the nanowire with the smaller cross-section. In the wider
nanowire (a, b), the Fermi level is chosen such that part of the second subband is filled
with electrons shown grey in color, at T = 0 K. At T > 0 K, thermal energy spreads
electrons over the first four subbands. In the narrower nanowire (c, d), the Fermi level is
such that a fraction of the first subband is filled with electrons at T = 0 K. The energy
separation between subbands is large enough for the electrons to remain confined to the
first subband at T > 0 K.
Intersubband scattering occurs between electrons belonging to different energy
subbands. These scattering events reduce electron mobility. By definition, there is no
intersubband scattering if only one subband is occupied, which occurs slightly above
threshold. As the gate voltage and the electron concentration are increased, however, a
larger number of subbands become populated and scattering occurs between electrons
belonging to different subbands. If the temperature is not too high (such that kB T is
smaller than the energy separation between two subbands) and if the drain voltage is not
much larger than ΔE=q, intersubband scattering phenomena can be directly observed in
the form of oscillations of drain current amplitude when gate voltage is increased. This
effect can be seen in Fig. 2.10, in which each “dip” of the curve corresponds to a
reduction of mobility caused by scattering due to starting populating a new subband
[45,46].
Figure 2.11 shows clearly that drain current oscillations disappear as either the
temperature or the drain voltage is increased. Increasing measurement temperature or
electron temperature due to acceleration by a “high” drain voltage spreads the electrons
over many subbands, resulting in a smearing of the oscillations and eventually their
disappearance. It is worth noting that there are no oscillations in the subthreshold part of
the curves as a single subband is populated and there is, therefore, no intersubband
scattering [47]. The devices in Figs. 2.10 and 2.11 are n-channel MOSFETs, but
oscillations have also been observed in p-channel nanowire MOSFETs [48].
(a) 10–6 (b)

T = 293 K VDS = 400 mV
T = 200 K 10–6
10–7
10–7
10–8 VDS = 200 mV
ID (A)
ID (A)
T = 137 K
T = 77 K 10–8
T = 35 K VDS = 100 mV
10–9
T=5K 10–9
VDS = 50 mV
10–10 10–10
VDS = 50 mV T=5K
0
0.0 0.2 0.4 0.6 0.8 1.0 0.2 0.4 0.6 0.8 1.0
VG (V) VG (V)
Figure 2.11 Drain current oscillations measured on an n-channel silicon GAA nanowire transistor with a
diameter of 6 nm (after [47]). The oscillations disappear if either the temperature or the drain
voltage is increased. (a) VDS = 50 mV, different temperatures, (b) T = 5 K, different drain voltages.
1,000
DE = kBT
4.3 nm × 3.6 nm
Ø = 6 nm
Temperature (K)
100 10 nm × 10 nm
14 nm × 10 nm
35 nm × 35 nm
40 nm × 50 nm
10 Ø = 65 nm
1
0 20 40 60 80 100
Nanowire diameter or section width/height (nm)
Figure 2.12 Temperatures at which drain current oscillations were reported in n-channel silicon nanowire
MOSFETs. The dashed curve represents the temperature at which thermal energy is equal to the
separation between the two first (lowest energy) subbands.
Figure 2.12 shows the temperatures at which drain current oscillations were reported
in n-channel silicon nanowire transistors for rectangular cross-sections of 4.3 nm ×
3.6 nm [49], 10 nm × 10 nm [50], 14 nm × 10 nm [51], 35 nm × 35 nm [52], 40 nm ×
50 nm [53] or, in the case of cylindrical nanowires, for a diameter of 6 nm [54] and 65 nm
[55]. The same graph shows a curve representing ΔE=kB T ¼ ðE1;2 E1;1 Þ=kB T, that is,
the temperature corresponding to the energy separation between the first and the second
subband, calculated using Eq. (2.27). Oscillations are observed only if the energy is
lower than or comparable to kBT.
2.4.2 Increase of band gap energy

Using the effective mass approximation and a single effective mass value in all direc-
tions, for simplicity, the energy of an electron in the conduction band is given by
ðℏkr Þ2
Eðkr Þ ¼ Ec þ ; ð2:31Þ
2m
where r = (x,y,z) and ℏkr is the electron momentum, Ec is the energy of the conduction
band edge, and m is the effective mass of an electron. In a nanowire grown along the x
direction, electrons are confined in the x and y directions. Confinement adds an addi-
tional energy to the electrons such that the energy of an electron in the first (lowest
energy) subband of a nanowire becomes

ℏ2 π 2 ðℏkx Þ2
Eðkr Þ ¼ Ec þ þ ; ð2:32Þ
m a2 2m
where a is the width/height of the nanowire, which is here assumed to have a square
cross-section. One can observe that the minimum energy in the conduction band
increases as the cross-section of the wire is decreased. The energy of electrons in the
valence band increases less because of the higher effective masses typically found. The
smaller the diameter becomes, the larger the band gap [56,57]. The smaller the effective
mass, the larger the diameter at which confinement effects become apparent. Figure 2.13
shows the dependence of the band gap energy on nanowire diameter for different
semiconductors where bulk tin and bismuth may be thought of as semiconductors with
zero or negative band gap energies [58,59,60,61,62,63].
1.4
1.2 Si
Band gap energy (eV)
0.8 InGaAs
0.6 Ge
0.4 InAs
Sn
Sn [100]
0.2 [110]
Bi InSb
0
1 10 100
Nanowire diameter (nm)
Figure 2.13 Dependence of the band gap energy on nanowire diameter for different semiconductors and
semimetals (tin [61] and bismuth [62]).
2.4.3 Quantum capacitance

In a classical, long-channel planar bulk silicon MOS transistor the gate capacitance (i.e.
the capacitance between gate and channel) at low VDS is given by CGch ¼ Cox ¼ εox =tox
typically measured in units of F cm−2, where εox is the gate insulator permittivity and tox
is the thickness of the insulating layer. To include the effects of channel quantization, a
“dark space” capacitor can be added in series with the dielectric capacitance, which
1 1
accounts for the non-zero depth of the channel: CGch ¼ Cox þ Cx1 where Cx ¼ εSi =xch ,
with εSi being the permittivity of silicon and x being the depth of the channel. In both
cases the amount of electrons in the channel increases linearly with gate voltage and the
assumption is made that a large or “infinite” supply of electrons is available from the
source and drain regions.
In a nanowire of small diameter or/and with a low density of electronic states (DoS),
only a few energy subbands can accommodate the presence of channel electrons. The
resulting charge response and capacitance response to an applied gate voltage requires
the introduction of the “quantum capacitance” concept where the gate-to-channel
1 1
capacitance is given by CGch ¼ Cox þ CQ1. CQ represents the variation of charge in
the subbands, or lack thereof, to a variation of gate voltage [64,65]. The quantum
capacitance described here encompasses both variations in channel depth and shape,
as well as the finite DoS available in the subbands. Some publications, however, make a
distinction between a capacitor representing the channel depth contribution and capaci-
tors representing the charge in each individual subband [66].
Figure 2.14 shows the density of states in a narrow nanowire transistor with only two
subbands. For simplicity, assume a temperature of 0 K. Below the threshold, the Fermi
level is located below the first subband and there are no electrons in the channel (case A).
As the gate voltage is increased, the Fermi level increases in energy with respect to the
subbands populating the first subband and causing an increase in capacitance (case B).
Once the first subband is filled (case C), the charge no longer increases with gate voltage
and the gate capacitance decreases until the bottom of the second subband is reached
(case D). The second subband eventually starts to fill, resulting in a further increase in
capacitance (case E). It is worth noting that no charge is added to the channel when the
gate voltage is increased from C to D such that this range of voltage increase is “wasted.”
The quantum capacitance varies from zero in the case of an extremely narrow nanowire
to infinity in the case of a classical planar bulk transistor where CGch ¼ Cox . The case
where the quantum capacitance is infinite is called the “classical limit” (CL), whereas the
case CQ < Cox is called the quantum capacitance limit (QCL). The quantum capacitance
effect appears more readily in nanowires made of low-effective-mass semiconductors
such as InSb [67] and InAs [68,69].
A positive aspect of quantum capacitance is that it reduces the gate capacitance CG-ch
such that, in strict terms of CV/I performance, operating in the QCL regime rather than in
the CL regime offers advantages in terms of both gate switching speed and power × delay
product. The negative aspect of quantum capacitance resides in the fact that in a real device
there are fringing parasitic capacitances that must be added to CG-ch and the gate may have
to drive additional load capacitance. In this case, the reduced current due to the low
EF
Energy, E
EF
EF
EF
EF
DoS DoS DoS DoS DoS
D
B C
E
Charge in
A
channel
E
Gate voltage
C
B
capacitance
D
Gate
Gate voltage
Figure 2.14 Top: Filling of conduction subbands as gate voltage, and thus Fermi level (EF), is increased.
Bottom: Quantum capacitance vs. gate voltage.
number of conducting subbands becomes a performance handicap [70]. It is worth

noting that nanowire materials with high electron mobility usually have a low density
of states and few populated subbands. High mobility is largely due to a low effective
mass which according to Eqs. (2.24) and (2.25) gives rise to a large separation between
energy subbands and a low density of states in each subband. This effect is sometimes
referred to as the “DoS bottleneck” [24,71,72,73]. A low effective mass also increases
direct source-to-drain tunneling, increasing the leakage current, and degrades the sub-
threshold slope in short-channel devices [74]. It is worth noting that germanium and
most III-V semiconductors have a higher dielectric constant than silicon, which also
leads to an increase in short-channel effects, according to the equations in Table 2.1 [74].
2.4.4 Valley occupancy and transport effective mass

In bulk silicon, electrons in the conduction band are localized in valleys around the
minimum energy EC. The six valleys with minimum energy correspond to wave vectors
with a value of 0.85π/a in the [1 0 0], [−1 0 0], [0 1 0], [0–1 0], [0 0 1], and [0 0–1]
directions as in Fig. 2.15(a), where a is the lattice constant of silicon and given by
a = 0.543 nm. Holes are found around the maximum of the valence band EV . Holes with
two different effective masses referred to as light holes and heavy holes are found around
[100]
] (a)
0
01
Electron Energy
[ Electrons
EC
EG
G EV
Bulk
[100] Silicon
Bulk Silicon Holes
G Off-G
Wave number, k[100]
[100]
(b)
Electron Energy
D = 3 nm
D = 5 nm
[100]
D = 10 nm
EC
Wave number, k[100]
0] D = 3 nm
[11
Electron Energy
(c)
[110] 5 nm
D = 10 nm
EC
Wave number, k[110]
]
[111
[111]
Electron Energy
D = 3 nm
(d) D = 5 nm
D = 3 nm
EC
Wave number, k[111]
Figure 2.15 (a) Electron valleys in the conduction band of bulk silicon (left) and energy-band Ek diagram in
bulk silicon (right). (b) Electron valley folding (left) and resulting Ek diagram in <100>-oriented
nanowires with different diameters. (c) Electron valley folding (left) and resulting Ek diagram in
<110>-oriented nanowires with different diameters. (d) Electron valley folding (left) and resulting
Ek diagram in <111>-oriented nanowires with different diameters.
Table 2.2 Relative performance of silicon nanowire transistors in terms of current

drive in nanowire transistors with different orientations and diameters.
nMOS performance <100> <110> <111>
Small diameter (3 nm) High High Low

Large diameter (10 nm) High High Fair
PMOS performance <100> <110> <111>
Small diameter (3 nm) Low High High
Large diameter (10 nm) Low Fair High
EV , deriving from two energy dispersion Ek curves that are degenerate at k ¼ 0. The
point corresponding to k ¼ 0 is labeled the “Γ-point,” corresponding valleys at the
valence band edge are called “Γ valleys,” and the valleys for electrons at the conduction
band edge are called “off-Γ valleys.”
In a silicon nanowire, confinement effects have a profound effect on valley energies,
the location of the valleys in k-space, and on the curvature of energy dispersions, and
hence effective masses. These effects are illustrated using the example of electrons in
silicon cylindrical nanowires [75,76,77]. Figures 2.15(a)–(d) illustrate the “folding” due
to confinement in <100>-, <110>-, and <111>-oriented nanowires, respectively. In a
<100> nanowire, the two valleys in the confinement directions fold into a single
minimum located at k = 0 or to the Γ valley. The off-Γ valleys are now centered along
the <100> direction at a value equal to 0.4 π=a. When the diameter of the nanowire is
decreased, the energy of the off-Γ valleys increase such that the majority of electrons are
now found in the Γ valleys and the <100> nanowires become direct-band semiconductor
materials. A similar effect is observed in <110>-oriented silicon nanowires, but the off-Γ
valleys are now centered along the <110> direction at a value equal to 0.75π=a. In
<111>-oriented nanowires, on the other hand, all electron valleys fold into off-Γ valleys
and are centered along <111> at a value equal to 0.4π=a.
In the case of holes in silicon nanowires, the maximum of the valence band is always
centered at the Γ-point. In <110> and <110> nanowires the curvature of the Ek curves
increases significantly when the diameter is decreased, thereby significantly decreasing
the hole effective mass and increasing mobility in the transport direction. This effect is
not observed in <100>-oriented nanowires. The relative performance of silicon nano-
wire transistors in terms of current drive in nanowire transistors with different orienta-
tions is presented in Table 2.2. The current drives are compared taking into consideration
carrier mass, injection velocity, and density of states in the different valleys [76].
2.4.5 Semimetal–semiconductor nanowire transitions

Semimetals may be considered as semiconductors with a zero or negative band gap.
Using the effective mass approximation and a single effective mass value in all direc-
tions, for simplicity, the energy of an electron in a conduction band, as for a semicon-
ductor, is taken to be given by
(a) (b)
Energy, E
Energy, E
EF EG > 0
EF EG < 0
Momentum, k Momentum, k
Figure 2.16 Energy band diagram for a bulk semimetal (a) and for the same material in nanowire form (b).
ðℏkr Þ2
Eðkr Þ ¼ Ec þ ; ð2:33Þ
2m
where r = (x,y,z). In a nanowire grown along the x direction, electrons are confined in the
x and y direction. Confinement adds energy to the electrons, such that the energy of an
electron in the first (lowest energy) subband of a nanowire is written as

ℏ2 π 2 ðℏkx Þ2
Eðkr Þ ¼ Ec þ 2 þ ; ð2:34Þ
m a 2m
where a is the width/height of the nanowire (here assumed to have a square cross-
section). The minimum energy in the conduction band increases as the cross-section of
the wire is decreased. The smaller the diameter becomes, the larger the band gap [78,79].
Hence a negative band gap associated with a semimetal can become positive when the
semimetal is formed into nanowire as in Fig. 2.16 resulting in a semimetal-to-semicon-
ductor transition.
Bismuth is an example of a semimetal, and a semimetal-to-semiconductor transition
has been observed when the diameter of bismuth nanowires is decreased below approxi-
mately 53–63 nm [63,80]. Going one step further, one can fabricate Schottky diodes
using bismuth nanowires with varying diameter. The section of the nanowire with the
larger section is a semimetal and the section with the smaller diameter is a semiconduc-
tor. No doping is required to form these junctions [81] and they are formed with a single
material. Using a semimetal nanowire with a large-narrow-large diameter variation, it
may be possible to fabricate a MOSFET that does not require external doping. The wider
sections are semimetallic, enabling the provision to the central narrow section of a large
supply of electrons. Placing a gate around the nanowire allows for the control of the
electron density and current flow from source to drain. Bismuth has the highest electron
mobility of any known bulk material since the conduction band electron mass is
approximately 0.001me, where me is the mass of an electron in a vacuum, or a “free”
electron [82]. The electron mobility was measured in bismuth nanowires with a diameter
of 120 nm; even though these wires are semimetallic as opposed to semiconducting,
it is still possible to modulate the electron concentration using a gate electrode. Based on
a conductance measurement technique and using the formula μ ≈ dgm =dx ¼
ðdI=dVG Þ=VSD an electron mobility of 76,900 cm2 V −1 s−1 was measured [83].
Tin is another semimetal with interesting properties when formed in a nanowire.

Column IV of the periodic table contains the elements carbon, silicon, germanium, tin,
and lead. Crystalline C, Si, and Ge have a diamond structure with strong covalent bonds
and are insulators or semiconductors. The stable phase of Pb is metallic and has a face
centered cubic (fcc) crystal structure. Crystalline Sn bonds are borderline between
covalent and metallic. Below a temperature of 13.2°C, Sn crystals have a diamond
cubic structure with a zero band gap (grey tin or α-tin). When heated, tin undergoes a
phase transition at 13.2°C and becomes metallic white tin. First-principle electronic
structure methods (density functional theory, DFT) were applied to determine the
electronic structure and electrical properties of tin nanowires with the diamond crystal
structure. The effects of both nanowire orientation and diameter on the electronic
structure were determined. It is shown that tin, consistent with other semimetals, exhibits
a transition from semimetal to semiconductor as the diameter of the nanowire is
decreased. The band gap energy varies with the diameter and can become larger than
2 eV at diameters below 2 nm. Based on the different electronic properties of Sn in both
the bulk and the nanowire forms, a new candidate for future “end-of-the-roadmap”
transistors has been introduced that relies only on the use of band gap engineering via
nanofabrication and relies solely on the properties of a single material, tin, when
patterned on the nanoscale. The resulting proposed transistor design, the “confinement
modulated gap transistor” (CMGT), follows by forming the source, channel, and drain
regions using atoms of a single element (tin, or other semimetals), unlike in conventional
MOSFETs which require dopant atoms to define different device regions. The resistivity
of tin is only double that of tungsten, an appropriate metal to form low-resistance source
and drain regions. The electronic and electrical properties of the channel are engineered
by varying the nanowire cross-section to achieve modulation of the energy bands.
This creates metallic source and drain regions and a semiconducting channel. Such a
transistor has been simulated using ab-initio DFT (density functional theory) techni-
ques. The device is schematically shown in Fig. 2.17. It consists of a gate-all-around
architecture, a gate length of 2.3 nm, and a channel diameter of 1 nm. The resulting
Narrow nanowire Gate

semiconductor channel
Wide nanowire Wide nanowire

metal source metal drain
Figure 2.17 Confinement modulated gap transistor made out of tin. No doping is used. The wider source and
drain are electron-rich metal and the central channel narrow nanowire is a semiconductor.
subthreshold slope is 72 mV/dec, and the ON current is 3000 μA/μm for VG − VTH =
0.35 V and VDS = 250 mV [84].
2.4.6 Topological insulator nanowire transistor

A topological insulator is a material with time reversal symmetry that behaves as an
insulator in the bulk and as a metallic conductor at its surface, due to the presence of
surface conducting states [85]. In the bulk of a non-interacting topological insulator, the
electronic band structure resembles an ordinary band insulator, with the Fermi level
between the conduction and valence bands. On the surface of a topological insulator,
however, there are special states that fall within the bulk energy gap and allow surface
metallic conduction. Transistors made from VLS-grown Bi2Se3 nanowires were first
reported in 2013 [86]. These nanowires present a well-defined single-crystal rhombohe-
dral phase and the growth direction is close to ½1120; the wires have a hexagonal cross-
section with a diameter of approximately 50 nm. An Ω-gate transistor was fabricated by
placing one such Bi2Se3 nanowire on an oxidized silicon wafer and by depositing HfO2
as a gate oxide and palladium as metal gate. The resulting transistor shows excellent
drain current vs. gate voltage transfer characteristics with an OFF current close to zero,
strong-inversion-like ON-state current and current ON/OFF ratio larger than 108 for a
gate voltage swing of 1.0 V (at T = 77 K), the backside silicon wafer being grounded
during the measurements. The Bi2Se3 nanowire MOSFET exhibits unipolar current
characteristics dominated by electron conduction, and a well-saturated output current
indicates surface metallic conduction. The device behavior is similar to that of a
conventional long-channel Schottky-barrier MOSFET with either electron or hole con-
duction determined by the unipolar Schottky junctions at the source and drain. In the
present case, the Schottky junctions are formed by the contact between the metallic
source/drain and the gated channel. The measured electron effective mobility decreases
with increasing gate voltage and ranges from 200 cm2 V −1 s−1 to 1300 cm2 V −1 s−1 at
77 K. In contrast to conventional semiconductor nanowires, the saturated current in the
ON state is linear in gate voltage, indicating metallic conduction, and is most likely
flowing at the surface of the nanowire. In the OFF state, the gate voltage is large enough
to deplete the electrons from the nanowire. The small, temperature-dependent OFF-state
current is due to thermal excitations across the energy band gap of the bulk of the Bi2Se3
nanowire. It also indicates that the electric field generated by the gate voltage below the
threshold is likely to be strong enough to modify the spectrum of the nanowire and
destroy the surface conduction channels.
2.4.7 Nanowire-SET transition

A single-electron-transistor (SET) is a nanoscale MOSFET where the channel is sepa-
rated from the drain by thin tunnel barriers. The dimensions of the channel region must
be small in order to have a small intrinsic capacitance, such that the injection of an
electron in the channel can raise the potential of the channel region by a significant
(measurable) voltage. This voltage needs to be larger than the thermal energy,
Constrictions
Source Channel Drain
Electrons
Figure 2.18 Nanowire MOSFET with constrictions between the source and the channel and between the
channel and the drain; the gate electrode around the channel is not shown for clarity.
ΔV > kB T=q, to observe single-electron transport [87]. Since confinement increases the
energy of an electron as shown in Eq. (2.24), the formation of “constrictions” in a
nanowire locally forms small potential barriers. Looking at Fig. 2.18, electrons in the
two constrictions at the channel ends will have higher energies than the electrons in the
channel or in the source and drain. In other words, the constrictions give rise to potential
barriers which electrons can tunnel through. The channel is no longer connected to
source and drain; rather, channel electrons congregate in the center of the channel
“island,” as represented in Fig. 2.18. At high enough temperatures the electrons can
easily flow from source to channel and from channel to drain because thermionic
emission allows them to overcome the potential barriers. In that case the device operates
as a regular nanowire MOSFET. At lower temperatures, however, electrons can only
tunnel through the barriers, giving rise to single-electron-transistor behavior. This effect
has been predicted by non-equilibrium Green function (NEGF) simulations in 2011 [88].
The formation of a potential barrier at the channel ends can be achieved by injecting
charges in gate spacers or by diameter variations caused by surface roughness. Devices
with such potential barriers have been fabricated and tested. They clearly show single-
electron behavior with Coulomb oscillations at cryogenic temperatures. SET behavior
decreases as the temperature is increased but can still be observed at room temperature in
some samples [89].
2.5 Other multigate field-effect devices
The excellent electrostatic control offered by the Ω-gate and GAA architectures allows
one to either simplify MOSFET design (e.g. eliminating pn junctions in junctionless
transistors) or improve important device characteristics, such as the subthreshold slope
of tunnel FETs.
2.5.1 Junctionless transistor

The junctionless transistor is a thin and narrow, heavily doped (typically in the 1019 cm−3
range) semiconductor resistor with a gate electrode that controls the flow of current
2.5 Other multigate field-effect devices 45
between source and drain. Turning the device off is achieved by fully depleting the
channel of majority carriers [14,15,16]. Device design is extremely simple as there are
no pn junctions. Device operation relies on fully depleting the semiconductor using the
work function of the gate material to turn the device OFF. When the device is turned ON,
current flows through the bulk of the thin film and can be augmented by an accumulation
current contribution. Junctionless transistors are characterized by reduced short-channel
effects and present excellent subthreshold slope and low DIBL. A review of junctionless
transistors can be found in [90]. Ω-gate silicon nanowire transistors with a gate length of
13 nm, width of 15 nm, and height of 9 nm exhibit excellent short-channel character-
istics, extremely low leakage current and a ION/IOFF ratio larger than 106 at VDD= 1 V
[91].
Recently n-channel junctionless transistors with a gate length of 3 nm have been
reported. These devices bear a remarkable resemblance to the original device patented
by Lilienfeld in 1925 [92] and exhibit an ION/IOFF ratio larger than 106 for a drain voltage
of 1 Vand a subthreshold slope of 95 mV/decade [93]. Because a single-gate SOI device
process is used, it is necessary to use a silicon film thickness of 1 nm to effectively be
able to turn the device OFF.
2.5.2 Tunnel field-effect transistor

Conventional MOSFETs cannot switch with subthreshold slopes below
59:6 mV=dec at T = 300 K; see Eq. (1.3). This is due to the shape of the Fermi–Dirac
distribution of electrons in the valence and conduction bands and to the thermally
activated mechanism by which carriers overcome the potential barrier in the channel
below threshold. Unlike gate oxide thickness and gate length, the subthreshold slope is
not scalable unless the operating temperature is decreased – which is not practical for
most applications. This sets a lower limit to the supply voltage VDD at which a circuit can
operate with acceptable speed performance and, therefore, a limit to power consumption
reduction. Designing devices with a “sub-thermal” subthreshold slope has become a
“Holy Grail” for semiconductor device engineers [94].
A sub-thermal subthreshold slope can in principle be attained by two techniques, both
based on quantum mechanical tunneling effect and which are not temperature depen-
dent. The first approach relies on filtering out the high-energy electrons in the conduction
band (assuming an n-channel device) using resonant tunneling techniques as it these
electrons that are responsible for the subthreshold current. Based on simulations, filter-
ing can be obtained using a superlattice as an “axial multiple heterojunction” nanowire
in the source extension of a MOSFET [95], or by making tunneling barriers at the
source–channel and drain–channel “junctions.” This can, for example, be achieved by
making constrictions in the nanowire using a geometry similar to that in Fig. 2.18 [96].
Energy filtering devices have the potential to display low subthreshold slope and
MOSFET-like current drive, but depend on extremely precise device geometry control,
which makes them rather impractical in manufacture. Another way of achieving sub-
thermal subthreshold slopes is based on band-to-band tunneling (BTBT). Operation of
an n-channel BTBT field-effect transistor or “tunneling FET” (TFET) is based on
180
150
SS (mV/decade)
120
90
60
30
20 35 50
Figure 2.19 Variation of subthreshold slope in silicon TFETs with nanowire diameter. After [100].
extracting electrons from the valence band of a p+-doped source and injecting them into
an electron channel connected to an n+ drain. This can be achieved by using the field
effect from a gate electrode to induce a very sharp band curvature at the source junction
[97]. This enables BTBT and injects valence electrons from the source valence band into
the channel region [94]. Improving electrostatic control of the region where BTBT
occurs is a key factor for improving TFET performance. The gate-all-around nanowire
transistor architecture is the most promising for good electrostatic control of TFETs [98].
Room-temperature subthreshold slopes of 30 mV/decade have been demonstrated in
both n-channel and p-channel vertical GAA silicon nanowire transistors. Subthreshold
slope has been shown to improve with the reduction of the nanowire diameter, which
improves electrostatic control by the gate as in Fig. 2.19 [99,100]. The excellent
electrostatic control provided by the Ω-gate and GAA nanowire architecture also allows
one to reach higher ON current levels than using other TFET geometries reported to be
770μA/μm as reported in [101]. The main drawback of carrier generation by the BTBT
mechanism is that it is very difficult to generate high current levels. As a result, the
current drive of TFETs is typically much lower than that of MOSFETs. Improving the
current drive of TFETs is a very active research area and improvements can be obtained
by forming heterojunctions in the nanowire [102], or by using bipolar amplification of
the tunnel current [103].
2.6 Summary
A survey of multigate transistors is provided progressing from a single gate, to double

and quadruple gates. Practical implementations of MOSFETs are often intermediate to
these idealized structures and Π-gate and Ω-gate devices have been described. The
important concept of a natural length is introduced and leads to the conclusion that the
most effective electrostatic control of a MOSFET channel is achieved from a gate-all-
around configuration. As devices scale to the length scales of a few nanometers,
References 47
quantum mechanical effects become apparent and can be observed in the current–
voltage characteristics. As opposed to being something to be avoided, quantum effects
can be used to engineer promising new devices such as single-electron devices, tunnel
field-effect transistors, and the confinement modulated gap transistor. Small physical
device dimensions also offer simplified device geometries such as the junctionless
transistor.
Further reading
S.M. Sze, Modern Semiconductor Device Physics, Wiley-Interscience (1997)

M. Lundstrom, J. Guo, Nanoscale Transistors: Device Physics, Modeling and
Simulation, Springer (2006)
J.-P. Colinge (ed.), FinFETs and other Multigate Transistors, Springer (2008)
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3 Synthesis and fabrication
of semiconductor nanowires
Semiconductor nanowires can be fabricated using a variety of techniques. Techniques

based on the semiconductor industry legacy of using lithography patterning and
material removal methods to etch semiconductor layers into nanowires are called
“top-down” fabrication techniques. A typical example is the patterning of photoresist
lines on top of a silicon-on-insulator layer followed by the removal of excess silicon
using a plasma etch tool in order to create silicon nanowires. Another example is the
patterning of an array of “dots” on a silicon substrate and the use of plasma etching to
fabricate vertical silicon columns. Techniques based on the direct epitaxial growth of a
nanowire from a seeding substrate without using material removal techniques
are called “bottom-up” growth techniques. The classical example is the vapor–
liquid–solid (VLS) growth of silicon nanowires on a silicon substrate using gold
eutectic droplets [1,2].
3.1 Top-down fabrication techniques
In this section, the more common “top-down” fabrication techniques are described.
They are typically based on process steps used following the semiconductor industry
legacy by combining patterning using lithography and material removal using etching
tools allowing the shaping of thin semiconductor films into nanowire structures.
3.1.1 Horizontal nanowires

Semiconductor nanowires can be fabricated using either semiconductor-on-insulator
wafers or bulk semiconductor wafers. In the case of silicon, nanowires can be made
using a silicon-on-insulator (SOI) wafer. The silicon film thickness can be trimmed
down to the desired value using oxidation and wet oxide strip in a buffered hydrofluoric
acid (HF) solution [3,4]. The lateral dimensions of the nanowire are usually defined
using e-beam lithography permitting patterning of very narrow lines [5,6,7]. Other
techniques, such as the use of block copolymer self-assembly, can be used to define
narrow polymer parallel lines and use them as a template for pattern transfer onto a
semiconductor. Directed self-assembly of block copolymers is capable of achieving
high-density patterning with critical dimensions approaching 5 nm. High-density
arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA
block copolymer has been demonstrated. The wires are formed with a pitch of 42 nm
resulting in dense arrays (5 × 106 wires/cm) of unidirectional and isolated parallel silicon
nanowires on an insulator substrate. This technique demonstrated the fabrication of
nanowires with critical dimension ranging down to less than 10 nm [8,9].
Thin dielectric spacers formed on the sidewalls of a sacrificial (or “dummy”) pattern
can also be used to define fine lines that can be used to etch nanowires [10,11]. For
these approaches, a dummy pattern such as a polysilicon line is formed using standard
optical lithography. A dielectric layer, usually silicon dioxide or silicon nitride, is then
deposited and etched away using vertical anisotropic reactive ion etching (RIE). These
steps create dielectric “spacers” on the sidewalls of the dummy polysilicon pattern.
The dummy polysilicon is then etched away and a pair of dielectric lines remain. These
can then be used as a hard mask for etching the underlying semiconductor. The
advantages of this technique are that the width of the spacer hard mask is defined
not by lithography but by the thickness of the deposited dielectric layer, and that the
width of the spacer can readily be made uniform (it shows less line width variation than
lines with similar dimensions defined by lithography). The disadvantage of the process
lies in the fact that the spacer forms a hard mask line all around the polysilicon patterns
yielding less design flexibility than direct-write e-beam lithography. The spacer
process is illustrated in Fig. 3.1. The stacking of alternate layers such as oxide/
nitride/oxide/oxide can be used to form multiple spacers, enabling the fabrication of
nanowires with small pitches [12,13]. Using multiple spacer technology in two
perpendicular directions using one direction to form semiconductor nanowires and
the perpendicular direction to pattern gates, nanowire transistor crossbar arrays can be
realized. Small arrays with a density of 1010 transistors/cm2 have been demonstrated
using this technique [14].
(a) (b) HM HM (c) HM HM

Si Si
SiO2 SiO2 SiO2
Si Si Si
Si Nanowires
(d) (e) (f)
Si
SiO2 SiO2 SiO2
Si Si Si
Figure 3.1 Formation of patterns using spacer technology: (a) silicon-on-insulator (wafer); (b) hard mask
patterning and dielectrics deposition; (c) anisotropic plasma etch to form spacers; (d) removal of
hard mask; (e) silicon etch; (f) removal of spacers leaving pattern behind.
56 Synthesis and fabrication of semiconductor nanowires
Nanowires can also be fabricated from a bulk semiconductor substrate. Using silicon,
horizontal nanowires and horizontal nanowire gate-all-around (GAA) transistors have
been made by RIE etching of a silicon wafer. A succession of anisotropic (vertical) and
isotropic plasma etching steps can be used to form suspended silicon nanowires, and
even stacked nanowires, from a bulk silicon wafer. The isotropic etch step is aimed
at removing some of the silicon lying underneath the nanowire. These nanowires can
later be processed into GAA transistors [15,16]. A combination of RIE etching, local
oxidation and isotropic etching can also be used. The latter technique has been used to
fabricate GAA transistors with a nanowire diameter of 6 to 7 nanometers. Such devices
for both n- and p-channel transistors exhibit very good properties with ON/OFF current
ratios greater than 108, a subthreshold slope of 64 mV/dec and a DIBL of 6 mV/V for a
gate length of 40 nm [16,17].
The removal of semiconducting material from underneath the nanowire can be
facilitated by using Si/SiGe/Si epitaxy. This technique was first pioneered by
M. Jurczack et al. under the name of the “silicon-on-nothing (SON) process” [18]. A
layer of silicon germanium (SiGe) is epitaxially grown on a silicon wafer and then a thin
layer of silicon is epitaxially grown on the SiGe layer. The role of SiGe consists in
transferring the continuity of the lattice from the bulk to the silicon top layer thus
maintaining a single-crystal structure. After patterning the top silicon layer, an isotropic
plasma etch step is used to selectively etch away the SiGe layer. The SiGe layer can be
selectively removed using pure carbon tetrafluoride (CF4) in a remote plasma, high
pressure, and low microwave power tool, in which case an etching selectivity of 100:1
for Si0.8Ge0.2:Si can be obtained [19]. Since the SiGe is being etched at the same rate
underneath channel, source, and drain, one has to design narrow channels and wide
sources and drains in order to form a free-standing nanowire channel while keeping
enough SiGe below the source and drain to ensure mechanical support; see Fig. 3.2.
Using stacked Si/SiGe/Si/SiGe/Si epitaxial layers, multiple nanowire transistors
can be fabricated on top of one another and in parallel, that is, with a common gate
electrode. This multiplicity of channels increases the current drive per footprint but also
complicates the fabrication process [20]. The epitaxial growth of multiple, stacked
active, and sacrificial semiconductors is not limited to Si and SiGe; it can also be applied
to III-V semiconductors and multiple InGaAs layers with InP sacrificial layers have
been used to fabricate stacked InGaAs GAA nanowire transistors [21].
The etching of the SiGe from underneath the nanowire can be restricted to the
channel region (i.e. the etching of the silicon germanium layer underneath the source
and drain can be inhibited) if a Damascene “gate-last” process is used. For this process,
the SiGe is etched after removal of the dummy gate and before deposition of the metal
gate stack; n- and p-channel GAA transistors with a gate length of 10 nm have been
made using this technique [22].
Two examples of horizontal nanowire transistor processing using SiGe etching are
given in Figs. 3.3 and 3.4. SiGe epitaxy, patterning, and etching are first used to form
silicon nanowires suspended between source and drain pads in a process similar to
that depicted within Fig. 3.2. After the gate dielectric deposition, a gate material and
a hard mask are deposited and etched to form gate-all-around structures shown in
(a) (b)
Si
SiGe
Si
(c) (d)
(e) (f) Si Nanowire
Si
Figure 3.2 Formation of a silicon nanowire using silicon germanium (SiGe) epitaxy and etching: (a) growth
of the SiGe and Si epitaxial layers; (b) resist pattern formation using lithography; (c) etch Si and
SiGe and removal of resist; (d) protect anchor points (future source and drain in a nanowire
transistor); (e) selective SiGe etch; (f) remove resist. A suspended silicon nanowire has been
formed between the two anchor areas.
Fig. 3.3(b). Spacers are then formed at the sides of the gate as in Fig. 3.3(c) to
enable the epitaxial growth of raised sources and drains shown in Fig. 3.3(d); this
latter step is necessary to reduce source and drain resistance. The source and drain
epitaxial regions are then doped using ion implantation and Fig. 3.3(e) shows a
cross-section of the finished device [23]. Ion implantation through the relatively
thick epitaxial sources and drains generates some lateral scattering of the dopants
into the nanowires under the gate spacers, which tends to somewhat deteriorate
device characteristics. An improved process sequence is shown in Fig. 3.4, where
the parts of the nanowires outside the gate spacers are cut off using RIE presented in
Fig. 3.4(c) and doped epitaxial growth is seeded directly from the nanowire “stubs”
that slightly protrude out of the gate spacers, as shown in Fig. 3.4(d) [24].
3.1.2 Vertical nanowires

Vertical nanowires can be readily formed by forming an array of dots by lithography and
subsequent etching into the semiconductor using anisotropic reactive ion etching (RIE).
This technique is exemplified in [25] where a single-step deep reactive ion etching
(SDRIE) is used to transfer a photoresist template to silicon or a silicon-on-insulator
substrate. With the SDRIE etching process, both a high silicon to mask selectivity and
a high etching rate can be achieved. The sidewall angle of resultant patterns can be
adjusted by tuning the composition of the gases in the etching process through a
controlled mixture of Ar, SF6, and C4F8. This straightforward top-down nanowire
fabrication technique, combined with nanowire trimming by oxidation and hydrogen
anneal, has been used to fabricate a variety of vertical gate-all-around nanowire transis-
tors on silicon substrates [26,27,28], as well as on III-V semiconductor substrates [29].
SiNW Hard mask

Gate
(a) (b)
Si
SiGe
Si
S/D epi
Spacers
(c) (d)
SiNW
(e)
Epi Epi
Si Si
Gate
SiGe SiGe
Si
Figure 3.3 Fabrication of a horizontal GAA nanowire transistor. (a) Formation of suspended silicon
nanowires between the source and drain anchor areas as in Fig. 3.2. (b) Gate dielectric material and
hard mask deposition and patterning to form the gate-all-around structure. (c) Formation of lateral
spacers. (d) Epitaxial growth of raised source and drain. Source and drain epitaxial regions are
then doped using ion implantation. (e) Cross-section of the finished device. After [23].
3.2 Bottom-up fabrication techniques
“Bottom-up” nanowire fabrication techniques are based on the epitaxial growth of high
aspect ratio crystals. These crystals are usually vertical but growth in other directions
can be achieved, either fortuitously or by design. The first growth of silicon wires dates
back to the end of the 1950s. A paper from 1957 by Treuting et al. describes the growth
of <111>-orientated silicon “whiskers” [30]. The term “whisker” has now been largely
abandoned and replaced by the more familiar terminology “nanowire.” A variety of
nanowire growth techniques can be found in the literature, including the vapor–liquid–
solid (VLS) mechanism, selective epitaxial growth (SEG), chemical vapor deposition
(CVD), evaporation of SiO, molecular beam epitaxy (MBE), laser ablation, and electro-
less metal deposition and dissolution (EMD) [31]. The most widely used techniques are
vapor–liquid–solid (VLS) and selective epitaxial growth.
SiNW Hard mask

(a) (b) Gate
Si
SiGe
Si
S/D epi
(c) (d)
Spacers
(e) SiNW
Epi Epi
Gate
SiGe SiGe
Si
Figure 3.4 Fabrication of a horizontal GAA nanowire transistor. (a) Formation of suspended silicon
nanowires between the source and drain anchor areas as in Fig. 3.2. (b) Gate dielectric gate
material and hard mask deposition and patterning to form the gate-all-around structure.
(c) Formation of lateral spacers and etching of nanowires outside the gate spacers. (d) Epitaxial
growth of doped source and drain. (e) Cross-section of the finished device. After [24].
3.2.1 Vapor–liquid–solid growth technique

One of the most successful growth techniques is the vapor–liquid–solid (VLS) mechan-
ism, first proposed by Wagner and Ellis in 1964 [32]. The method was first applied to the
growth of silicon nanowires with diameters down to 300 nm, but has since been used on
a variety of other semiconductor materials. The VLS mechanism can best be explained
as the gold catalyzed growth of a silicon wire on a silicon substrate by means of
chemical vapor deposition (CVD) using a silicon-containing gas (precursor) such as
silane (SiH4). Gold is the most popular nanowire growth catalyst, although VLS
growth using other metals including Cu, Al, Ti, Ga, In, Cd, Zn, Ag, and Pt has been
reported [33].
The physics of VLS growth was first explained by Givargizov in 1975 [34,35] and is
well illustrated in an article from 2010 by Schmidt et al. [33]. The Au–Si binary phase
diagram has a distinctive feature: the melting point of the Au–Si alloy strongly depends
1500
1200
Liquidus
Temperature (˚C)
900
Au
Si
600 VL
363 °C
300 19%
0
0 20 40 60 80 100
Atomic percent silicon (%)
Figure 3.5 Phase diagram for the gold–silicon system. The shaded area represents the range of
temperatures and alloy compositions at which VLS growth can occur.
on composition. The lowest melting temperature for the Au–Si eutectic is obtained for a
composition 19 atom% Si and 81 atom% Au and is equal to 363°C, which is approxi-
mately 700ºC lower than the melting point of gold and over 1000°C lower than the
melting point of silicon. Thus, heating a gold film deposited on a silicon substrate to a
temperature of 363°C or higher results in the formation of liquid Au–Si alloy droplets.
If these Au–Si alloy droplets are placed in an ambient containing a gaseous silicon
precursor such as silane (SiH4), the precursor molecules decompose (SiH4 → Si + 2H2)
at the surface of the droplets, thereby supplying additional Si to the Au–Si alloy. Under
equilibrium conditions (see phase diagram in Fig. 3.5) only a limited amount of Si can
be dissolved in the Au–Si droplets. The additional supply of Si from the gas phase forces
the droplets to “dispose of” excess silicon. This causes the growth of solid-phase silicon
at the bottom droplet-silicon interface. Continuous supply of silicon from the precursor
to the droplets therefore results in the growth of nanowires with a gold–silicon alloy
droplet at their apex [33]. The growth mechanism of a silicon nanowire catalyzed by a
gold–silicon alloy droplet is illustrated in Fig. 3.6.
As a rule of thumb, narrow nanowires grow faster than wider wires as the surface-to-
volume ratio of small droplets is larger than for larger diameter droplets. Au droplets
have a large wetting angle with the silicon substrate but a smaller contact angle with the
growing nanowires. As a result, VLS-grown nanowires are usually characterized by a
“footing” or enlarged nanowire base as shown schematically in Fig. 3.6.
As mentioned previously a wide variety of metals can be used as catalysts for the
growth of silicon nanowires. These different metals can be classified according to the
characteristics of the binary phase diagram they form with silicon [33,36]. The catalytic
materials can be classified into three different categories: type A, type B, and type C.
Type-A catalysts are metals forming with silicon a system characterized by a phase
diagram that is dominated by a single eutectic point. This eutectic contains a relatively
large concentration of silicon of more than 10 atom percent Si. Type-A catalysts do not
H Si H
H
Au
(a) (b)
Si
H Si H
H
(c) (d)
Figure 3.6 Growth mechanism of a silicon nanowire catalyzed by a gold–silicon alloy droplet. (a) Deposition
of gold droplet on silicon. (b) Silane precursor gas dissolves silicon in the Au–Si eutectic droplet
and growth of a silicon nanowire begins. (c) This process continues until the desired nanowire
length is obtained. (d) The gold droplet is removed.
react with silicon to form a silicide. In the case of silicon nanowire growth there are
only three type-A metal catalysts: Al, Ag, and Au. Type-B catalysts also show a single
dominant eutectic point and no silicide phases, but have a low Si solubility limit, lower
than 1 atom percent Si. In the case of silicon, In, Ga, and Zn are typical type-B catalysts.
Type-C catalysts are the silicide-forming metals. Their phase diagram indicates the
presence of one or more silicide phases. Cu, Pt, and Ti are typical type-C catalysts.
Nanowires formed by the VLS technique typically grow vertically, preferentially
perpendicular to the surface of a (111) wafer in the case of silicon. Since the nanowires
grow where metal droplets are present, the position of the nanowires can be controlled
by positioning the droplets in a particular arrangement such as a regular array, using
classical deposition, lithography, and etching techniques. It is, however, possible to
produce horizontal silicon nanowires using a guided growth technique.
By etching trenches or grooves in a silicon or SOI wafer one can produce vertical
or slanted walls with <111> orientation. After performing angled deposition of metal
catalyst droplets, nanowires can be grown perpendicular to these walls. Etching <111>
vertical walls in a (110) silicon wafer produces horizontal nanowires. These can be
grown to bridge the gap between two vertical walls up to a distance of several micro-
meters as in Fig. 3.7 [37]. This technique has been used to fabricate horizontal nanowire
transistors GAA-FETs integrated into an array of Si nanowire bridges. The bridges are
suspended over pairs of pre-patterned p-type Si electrodes in a SOI wafer that serve as
source and drain for the transistors. Nominally undoped Si nanowires are VLS grown on
the sidewalls of the electrodes with gold nanoparticles having a diameter between
150 and 200 nm, using SiH4 as precursor. After removal of the gold impurities from
Si nanowires, standard dry oxidation and polysilicon deposition can be applied to form
gate oxide and electrodes [38].
Au droplet
(a) (b)
Si Si
(c) (d)
Si Si
Figure 3.7 VLS growth of a horizontal nanowire. (a) Etching <111> vertical walls in a (110) silicon wafer.
(b) Angled deposition of catalyst (Au droplet). (c) Horizontal VLS growth catalyzed by the droplet
until reaching the other side of the trench (d).
Alternatively, the VLS process can be guided by forcing the nanowire to grow along
an oxide surface. The nanowires still grow by addition of <111> planes to the structure,
but the overall growth direction can be engineered to grow in other directions such as
<100>. This allows for the fabrication of horizontal nanowires on a (100) wafer and
subsequent processing of the nanowires into transistors [39].
Gold is a well-known contaminant or “poison” in silicon and is usually avoided at all
costs in integrated circuit processing lines. In silicon, gold atoms introduce deep trap
levels that greatly increase the carrier generation-recombination rate. This reduces
minority carrier lifetime and renders pn junctions very leaky, although the physics of
the electronic states of gold in very narrow nanowires remains largely unexplored.
Metals other than gold have been shown able to catalyze VLS growth of silicon and
germanium nanowires, among which are aluminum [40] and titanium [41].
Unfortunately, length uniformity control and effect density in these nanowires are not
as good as in those grown using gold nanoparticles. Tin (Sn) nanoparticles have
successfully been used to catalyze VLS growth of silicon nanowires using a plasma-
enhanced chemical vapor deposition technique at temperatures ranging from 300 to
400ºC. This opens up the possibility of a unique in situ approach to fabricating metal
contamination-free nanowire arrays since tin is a IV-column element like silicon and
germanium, and is not considered as a contaminant in silicon processing [42].
To fully eliminate metallic contamination hazards, “homoparticle growth” can be
used in some instances. In that case, the droplet that is seeding the nanowire growth is
formed of one or all elements used for wire growth as opposed to the case of
“heteroparticle growth,” where the seeding droplet is a different element such as gold.
The homoparticle growth technique has been demonstrated capable of growing InAs
nanowires on substrates including InAs, InP, GaAs, GaP, or Si. Growth was obtained
using trimethylindium (TMIn) and arsine (AsH3) as precursors. The substrates were
heated under an H2 atmosphere to a growth temperature of between 520 and 660ºC, at
which both precursors were activated simultaneously. InAs nucleation first forms and
then decomposes, yielding indium droplets. These droplets act as a catalyst to the vertical
growth of InAs wires without the risk of contamination from foreign elements [43,44].
3.2.2 Growth without catalytic particles

The VLS growth method uses metallic droplets or particles as a catalyst to absorb
gaseous precursors and precipitate them into a solid form to permit crystal growth.
Some semiconductors such as InAs and InGaAs can be grown without the need for
a catalytic particle [45,46]. Selective-area metallorganic vapor phase epitaxy
(SA-MOVPE) allows one to grow semiconductor crystals with a high height-to-width
ratio [47]. Using this technique, InAs nanowires can be grown on (100) silicon. The
location of the nanowires can be controlled by lithography. In [48], a 20 nm thick SiO2
film was thermally grown on an n-type Si (111) substrate. Subsequently, circular open-
ings with a diameter of 100 nm were made in the oxide using electron beam lithography
and wet chemical etching. Next, cylindrical InAs nanowires were selectively grown on
the partially masked substrate in a low-pressure horizontal metal-organic vapor phase
epitaxy (MOVPE) system, supplying trimethylindium (TMIn) and arsine (AsH3) as
precursors. To achieve vertical III-V nanowires on the Si substrates, special care was
taken to prepare As-terminated (111) surfaces on the Si substrates prior to the growth.
Details of the growth process can be found in [47]. The length of each NW was 2.5 μm
and diameters were 100 nm, which is the same as the mask opening size.
Silicon, germanium, and SiGe can be grown without the need for catalytic particles as
well. Silicon can be epitaxially grown selectively on silicon while avoiding nucleation
and polycrystalline growth on SiO2. This can be achieved in an epitaxial chemical vapor
deposition (CVD) reactor by alternating deposition cycles and etching cycles. Consider
a silicon wafer partially covered by oxide on top of which a thin layer of silicon is
deposited by pyrolysis (thermal decomposition) of silane or dichlorosilane. The silicon
grows epitaxially on the exposed silicon, while it forms crystallites on the oxide which
act as nucleation sites or “seeds.” An etching step is then applied in-situ, usually using
HCL gas. The etching process is optimized to remove the crystallites on the oxide
while minimizing the removal of the epitaxial grown silicon. The deposition/etching
cycles are then repeated until the desired thickness of epitaxial silicon has been reached.
This growth technique is known as “selective epitaxial growth” (SEG) [49,50]. The
growth of (100) vertical Si and SiGe nanowires can be found in [51]. In this example,
SEG is used to grow cylindrical nanowires with a diameter of 85 nm. These are grown
in cylindrical holes etched into a SiO2 layer deposited on silicon. This technique is thus
not entirely “bottom-up” since lithography and material (SiO2) removal are used to
etch the holes in the oxide. These holes serve as a “mold” for silicon growth during the
SEG step. In the particular example of [51], the nanowires contain a heterojunction
and a first 100 nm growth of pure silicon is followed by the growth of SiGe. Before
SEG steps are performed, a mask template is prepared by patterning via the holes in a
SiO2/Si3N4 film stack on Si (100) wafers. The stack is composed of a 25 nm nitride
capped by a 300 nm thick plasma-enhanced chemical vapor deposition (PECVD) of an
oxide. After dry etching of the SiO2, a hole is etched in the bottom Si3N4 using hot
phosphoric acid, during which approximately a 10 nm lateral overetch of the nitride
is created to promote a facet-free Si epitaxy. The holes are subsequently filled by
selective epitaxial grow of an intrinsic, 100 nm tall Si segment followed by deposition
of a segment of Si0.85Ge0.15 deposited by CVD. The heterojunction is thus formed by
changing the chemistry gases during CVD growth. Such a heterojunction structure can
be used to fabricate gate-all-around (GAA) vertical nanowire tunnel field-effect
transistors (TFETs) [51].
3.2.3 Heterojunctions and core-shell nanowires

As hinted in the previous section, heterojunction nanowires can be grown by varying
precursor chemistry during growth. Heterojunctions can be formed axially, i.e. perpen-
dicular to the length of the nanowire, or radially, i.e. perpendicular to the radius of the
nanowire as shown in Fig. 3.8 [52].
Many types of vertically grown nanowires with axial heterojunctions are reported in
the literature, including Si/Ge [53,54], InAs/InP [55], InAs/Si [56], and InSb/InAs
[57] nanowires. Atomically sharp junctions and defect-free crystals are usually
achieved. It is worth mentioning that nanowire devices comprising both radial and
axial heterostructures can be made (InAS/InGaAs/GaAs/GaSb) using the InAs(Sb)
(a) (b) (c)
Semiconductor 1
Semiconductor 2
(d) InAs(Sb) shell

InGaAs
InAs GaAs GaSb
Figure 3.8 Different types of heterojunction nanowires. (a) Axial heterojunction. (b) Multiple axial
heterojunctions. (c) Radial heterojunction (core-shell nanowire). (d) Combination of radial and
axial heterojunctions. After [58].
material system as in [58]. This allows for the design of tunnel diodes and tunnel field-
effect transistors with a larger current drive than that of axial-only devices. Multiple
layer core-shell nanowires can be grown as well. Vertical III–V semiconductor
nanowires grown on (111) silicon substrates with up to five successive layers grown
on top of one another around a core, in a similar fashion to Russian nested dolls, have
been demonstrated by K. Tomioka et al. [59], resulting in the formation of
In0.7Ga0.3As (core)/InP/In0.5Al0.5As/d-doping layer/In0.5Al0.5As/In0.7Ga0.3As (outer
shell) or InGaAs (core)/InP/InAlAs/InGaAs (outer shell) structures.
A “core-shell” nanowire is a nanowire where a central semiconductor region or
core is radially encased within a semiconductor outer shell. Core-shell nanowires
have been studied since the early 2000s; in particular, the Sicore/Geshell and
Gecore /Sishell systems have been studied in detail by the group of C.M. Lieber
at Harvard University [60,61]. Quantum confinement from the quasi-1D structure
characteristic of a nanowire can be reinforced by the formation of a radial
heterojunction. This property enables core-shell nanostructures to produce very
“clean” one-dimensional gases of charge carriers and fabrication with these
structures of nanowire transistors allows for ballistic transport through 1D sub-
bands to be clearly observed [62]. High-performance nanowire p-channel transis-
tors have been made using Gecore/Sishell nanowires with a diameter of 18 nm and
using high-κ HfO2 and ZrO2 gate dielectrics. In this configuration, a transconductance
of 3300 µS/µm and an ON-current of 2100 µA/µm at VDS = –1.0 Vand VG = VTH – 0.7 V
was measured. These values are three to four times higher than in planar MOSFETs and
correspond to a hole mobility of 730 cm2 V−1 s−1 [63]. Transport simulations confirm
that Si/Ge core-shell heterostructures with engineered energy band offsets can exhibit
enhanced ON currents and transconductances over traditional device designs and deliver
a two-fold improvement in hole mobility, transconductance and ON current [64].
The electronic properties of strained Si/Ge core-shell nanowires can be evaluated
using first-principles calculations based on density functional theory (DFT, see
Chapter 5). The semiconductor parameter of core-shell wires with a diameter up to
5 nm were calculated along the <110> direction in [65]. The simulations reveal that the
band gap of the core-shell wire is smaller relative to both pure Si and Ge wires with the
same diameter. This reduced band gap is ascribed to the intrinsic strain between Ge and
Si layers, which partially counters the quantum confinement effect. The studied Si/Ge
core-shell nanowires all have a core diameter of approximately 1.5 nm, which is
equivalent to 30 atoms per cross-section. Core-shell nanowires with diameters of
2.5 nm, 3.7 nm, and 4.7 nm were simulated, which corresponds to a shell thickness of
0.5, 0.75, 1.1, and 1.6 nm, respectively. The resulting strain in both the core and the
shell is shown in Fig. 3.9 [66].
An unstrained core-shell Si/Ge nanowire forms a type-II staggered-band
heterostructure. In other words, EV (Ge) > EV (Si) and EC (Ge) > EC (Si) [67]. As a
result, the valence band charge carriers (holes) of a core-shell Si/Ge nanowire are
mainly found in the germanium and the conduction band charge carriers (electrons)
are mainly located in the silicon, regardless of whether the core is Si and the shell is Ge
or vice versa [66].
4
Sicore /Geshell
3 Gecore /Sishell
Sishell
2
Strain (%)
Sicore
1
0 Gecore
–1
Geshell
–2
0 0.5 1 1.5 2
Shell thickness (nm)
Figure 3.9 Strain in core and shell of core-shell Si/Ge and Ge/Si nanowires of different diameters. Core
diameter is 1.5 nm. After [66].
In terms of generating strain in a semiconductor, a technique that is widely used to

enhance carrier mobility, the epitaxial core-shell nanowire structure offers two advan-
tages over the standard planar heterostructure. The first advantage is that the strain
energy per interfacial area is lower in a core-shell nanowire than for the analogous
planar heterostructure. The strain energy due to lattice mismatch builds up with thick-
ness when a heteroepitaxial layer is grown. The usual way the system releases that
energy is through the generation of misfit dislocations. The strain energy being lower
in a core-shell nanowire than in a planar epitaxial system, thicker defect-free
shell heteroepitaxial layers can be grown as compared to planar heteroepitaxial layers.
The second advantage is that the core-shell system allows the achievement of higher
strain levels than planar heteroepitaxy, which can be a benefit for mobility enhancement.
These advantages are attributed to the greater ability of the core-shell geometry to relax
the strain at the surface [68].
3.3 Silicon nanowire thinning
The diameter or cross-section of silicon nanowires produced by either top-down tech-

niques using lithography and etching or bottom-up methods such as VLS growth may be
too large for some applications, in which case it is desirable to reduce the nanowire
cross-section in a controlled manner. Two techniques can be employed to achieve this
aim: hydrogen annealing and thermal oxidation.
3.3.1 Hydrogen annealing

Hydrogen annealing can be used to slowly etch and smooth out silicon surfaces. The
operation is usually carried out in an epitaxial reactor under a low-pressure (10–30 Torr)
H2 ambient. The anneal temperature usually ranges between 800°C and 900°C for Si
nanowires and 700°C for SiGe nanowires [69,70]. Hydrogen annealing has been used
Hard mask
Top NW
Middle NW
Bottom NW
S D
SiO2
Si
Figure 3.10 Left: Three-dimensional tomography image of three stacked horizontal SiGe
nanowires. Right: Schematics of the complete device. The hard mask is used to etch the
structure vertically. (Courtesy D. Cooper, CEA-LETI.)
during FinFET processing to round the corners of the silicon fins prior to gate
oxidation and to smooth the surface of the fin sidewalls. This procedure has been
shown to greatly improve gate leakage and to improve channel mobility [71,72].
Hydrogen annealing is effective for rounding of silicon nanowires. Line width rough-
ness (LWR) and line edge roughness (LER) of silicon nanowires patterned on an SOI
wafer have been shown to decrease by approximately 25% and 50% after hydrogen
annealing for 2 minutes at a pressure of 20 Torr and temperatures of 800ºC and 850ºC,
respectively. This technique can be used to produce nearly circular nanowires from
initially rectangular shaped nanowires [69]. Hydrogen annealing presents, however, a
serious drawback for its use in the formation of small-diameter nanowires: the diffu-
sion of silicon atoms at the surface of the nanowires, which is responsible for
smoothing and rounding the wires, causes pinch-off of the wires near anchor points.
This leads to unwanted excess thinning of the nanowires that can cause an increase of
source and drain resistance in transistors, and even breakage of the nanowires at the
anchor points [69,73]. Figure 3.10 shows a 3D picture of stacked horizontal SiGe
nanowires. The image was constructed using a scanning transmission electron micro-
scope (STEM) tomography technique. Details on the hardware and software used to
produce such a picture can be found in [70].
3.3.2 Oxidation
It was realized in 1994 that the oxidation rate of silicon nanowires decreases with
time or oxide thickness up to the point where oxidation is virtually stopped. This is in
contrast with the Deal–Grove model for oxidation of planar silicon surfaces where
the oxide growth continues with a rate proportional to square root of time [74]. It is
possible to model the oxidation of silicon nanowires (NWs) based on a modification of
the Deal–Grove equation written for a cylindrical geometry which takes into account
stress effects associated with non-uniform deformation of the oxide by viscous flow
[75]. The Deal–Grove equation written for a cylindrical silicon sample gives the
following oxidation rate [76]:
∂x 1 C 1 C
¼ ¼ a þ x ; ð3:1Þ
∂t N 1 1 a a b N1 1 a a
þ þ log þ þ log
ks h b D a ks h a þ x D a
where a is the radius of the silicon nanowire, x = b – a is the thickness of the already
grown oxide, b is the outer radius of the oxide, N is the number of oxidizing molecules
required to form one unit volume of SiO2, ks is the surface reaction rate constant at the
SiO2/Si interface, h is the surface mass transfer constant of the oxidizing agent (O2 in the
case of dry oxidation and H2O in the case of wet oxidation), D is the diffusivity of
oxidizing species in SiO2, and C* is the solubility of the oxidizing species in SiO2. In
addition to the Deal–Grove equation one assumes that the oxide shell is a viscous
incompressible fluid at the oxidation temperature of 950ºC or higher. Thus the SiO2
flow can be approximated as purely viscous and the non-linear effects of shear stress on
oxide viscosity can be neglected. Under these assumptions, it can finally be shown that
the growth of the oxide results in the buildup of a tensile hydrostatic pressure P inside the
bulk of the oxide volume and of a compressive surface stress σ at the Si/SiO2 interface.
Using stress- and pressure-dependent coefficients for ks, D, and C*, viscosity studies
show that the presence of a tensile P and compressive stress σ decrease the oxide
viscosity and the reaction coefficient, as well as increase the diffusivity and the oxide
solubility. The oxide growth can therefore be accelerated or decelerated depending on
whether the reaction is controlled by the oxidant diffusion or by its reaction velocity at
the interface. More importantly, the model gives some interesting insights into the
physics of the oxidation process. In particular, it shows that the compressive stress at
the Si/SiO2 interface results in the self-limitation of the oxidation rate for long oxidation
times, in good agreement with experimental data [77,78,79]. The self-limiting nature of
nanowire oxidation can be used to tighten the diameter distribution of nanowires defined
by lithography and plasma etching as plotted in Figs. 3.11 and 3.12.
60
Silicon nanowire (model)
50
Oxide thickness (nm)
40 Bulk silicon
30
20
10 Silicon nanowire (experiment)

0
0 500 1000 1500
Time (s)
Figure 3.11 Oxide thickness as a function of oxidation time for dry oxidation at 1100ºC. Data and model
for nanowire oxidation taken from [75].
0.3
After oxidation
0.25
Probability (a.u.)
0.2
Before oxidation
0.15
0.1
0.05
0
0 20 40 60 80
Figure 3.12 Histogram of nanowire diameter before and after dry oxidation for 20 minutes at 1100ºC. The
initial diameter distribution is centered at 50 nm before oxidation and the post-oxidation diameter
distribution is centered at 20 nm. The self-limiting nature of nanowire oxidation has tightened the
diameter distribution. Adapted from [75].
3.3.3 Mechanical properties of silicon nanowires

The Young’s modulus E of a material is a measure of the stiffness or elasticity of that
material. It is defined as the ratio of the stress over the strain applied to the material.
Young’s modulus is also called the “modulus of elasticity.” It is usually measured by
pulling on a sample and measuring the relationship between the increase of the sample
length and the applied force. Mathematically it is defined by the following
relationship:
σ F=A0 FL0
E¼ ¼ ¼ ; ð3:2Þ
ε ΔL=L0 A0 ΔL
where σ is stress and ε is the strain, which are re-expressed using F the force exerted on a
sample, A0 the pre-stress cross-sectional area of the sample, ΔL the length increase or
elongation due to the applied stress, and L0 the original length of the sample. Young’s
modulus is usually given in units of gigapascals (GPa). The higher the value of Young’s
modulus, the stiffer a material or the greater its resistance to deformation under force.
Lower values of the modulus indicate that a material can be expected to be more elastic.
For example, the Young’s modulus of rubber, steel, and diamond are 0.01–0.1, 200, and
1220 GPa, respectively. The Young’s modulus of bulk silicon ranges between 130 and
185 depending on crystal orientation [80,81].
The Young’s modulus and fracture strength of silicon nanowires have been measured
experimentally by several groups [82,83]. Nanowires with diameters ranging between
15 and 60 nm and lengths of between 1.5 and 4.3 µm were grown by the VLS process
resulting in various crystal orientations along the growth direction. <110>-, <111>-, and
<112>-orientated nanowires were subjected to in situ tensile tests inside a scanning
electron microscope. The measurements reveal that the Young’s modulus of the silicon
nanowires is close to that of bulk silicon at 187 GPa for the <111> orientation when the
nanowire diameter is larger than 30 nm. When the diameter is decreased below 30 nm,
200
Bulk <111>
180
Young’s modulus (GPa)
Bulk <110>
160
140
120
100
80
0 20 40 60 80
Figure 3.13 Young’s modulus measured on silicon nanowires with different diameters. The horizontal
dashed lines represent the Young’s modulus of bulk silicon. Adapted from [82].
0.14
0.12
Fracture strain (DL/L)
0.1
0.08
0.06
0.04
0.02
0
0 20 40 60 80
Figure 3.14 Fracture strength measured on silicon nanowires with different diameters. The range of
fracture strength values found in thin silicon films is given for reference. Adapted from [82].
the Young’s modulus decreases monotonically with the wire diameter, indicating a
softening of the silicon to values as low as 50% of the bulk value Young’s modulus
for wires within a diameter range of 10 to 15 nm, as shown in Fig. 3.13. Similar results
have been obtained for Ge and GaAs nanowires [84,85]. The decrease of Young’s
modulus in silicon nanowires at small diameters has been confirmed by first-principle
studies. It is found that the modulus scales proportionally to the surface area to volume
ratio, as long as the wire diameter is not smaller than 1.5 nm [86,87]. A second important
finding from tensile stress measurements concerns the fracture strength of the nano-
wires, which increases as the diameter is decreased. A strength of 12 GPa is found in
wires with a diameter of 30 nm or below, which is significantly higher than in bulk
silicon or silicon thin films with the maximum strains as a function of diameter shown in
Fig. 3.14. For reference, the fracture strengths of aluminum, silicon, stainless steel, and
diamond are 0.17, 1–7, 2.1, 53 GPa, respectively [88,89]. The lowering of the Young’s
modulus and the increase of fracture strength allows for the generation of strain levels
14
12
Fracture strength (GPa)
10
4
Thin silicon films
2
0
0 20 40 60 80
Figure 3.15 Fracture strain measured on silicon nanowires with different diameters. Adapted from [82].
L/L0 of up to 12% as seen in Fig. 3.14 and 3.15. Repeated loading and unloading tests
performed during the stress experiment demonstrated that the nanowire deformation is
linear and elastic without any appreciable plasticity until fracture is reached.
Molecular dynamics simulations predict that the fracture mechanism of Si nanowires
depends on both temperature and the diameter of the nanowire. Nanowires with a
diameter smaller than 4 nm exhibit a ductile fracture (shear fail) mechanism at all
temperatures, while wider wires tend to fail through a brittle failure mechanism unless
the temperature is higher than 1200 K. For a diameter larger than 4 nm, cleavage
fractures are predominantly observed on transverse (110) planes at temperatures
below 1000 K. At higher temperatures, the nanowires shear mostly along inclined
<111> planes prior to fracture, analogous to what happens in the brittle-to-ductile
transition in bulk Si. Surprisingly, nanowires with diameter less than 4 nm fail by
shear regardless of temperature. Detailed analysis reveals that cleavage fracture is
initiated by the nucleation of a crack from the nanowire surface, while shear failure is
initiated by the nucleation of a dislocation, also from the nanowire surface. The overall
fracture behavior of silicon nanowires is controlled by competition between crack
and dislocation nucleation from the nanowire surface, contrary to the dislocation
mobility-controlled model for describing brittle to ductile transition in bulk silicon.
The preference of the shear failure mechanism in very thin nanowires, even at low
temperatures, is probably caused by the low energy barrier for dislocation nucleation in
thin nanowires [90].
It is worth noting that simulation techniques, such as molecular dynamics, predict a
drop of Young’s modulus in silicon nanowires only for diameters smaller than 5 to
10 nm, while experimental results reveal that lower values of Young’s modulus occur at
diameters smaller than 50 to 100 nm. The molecular dynamics simulations apply to
defect-free nanowires without surface oxides, hence the discrepancy between simulation
and experiment can presumably be explained by the presence of crystalline defects in the
nanowires and by the presence of a thin native oxide at the surface of the nanowires used
in the experiments [91].
3.4 Carrier mobility in strained nanowires
In bulk or thin-film silicon, compressive strain increases hole mobility and decreases
electron mobility, while tensile strain increases electron mobility and decreases hole
mobility. This phenomenon has been known since the 1960s and has been observed in
silicon layers grown by heteroepitaxy on spinel [92] and on sapphire [93]. Strain was
introduced as a performance-boosting technique in bulk silicon and SOI CMOS in the
early 2000s [94,95,96,97,98,99]. These variations of mobility are due mainly to a change
of effective mass brought about by the change of interatomic distance resulting from
strain [100,101].
Strain can be uni-, bi-, and tri-axial in bulk silicon, and uni- or bi-axial in SOI films;
it is essentially uniaxial in nanowires. The evolution of electron and hole mobility in
strained silicon nanowires has been calculated by Niquet et al. using an atomistic tight
binding treatment of the electronic structure [102]. The calculations reveal that silicon
nanowires are sensitive to strain and that mobility can be enhanced or reduced two-fold
for strain values in the ± 2% range. The effects of strain on the transport properties are,
however, very dependent on the crystal orientation of the nanowires. Tensile strain
increases the mobility of electrons in <100>- and <110>-orientated nanowires where
the orientation is referred to the direction along the axis of the nanowire or, in a
transistor, the transport direction, while compressive strain degrades electron mobility.
Electron mobility degrades with both compressive and tensile strain in <111>-
orientated nanowires, as can be seen in Fig. 3.16. Hole mobility displays a behavior
that is essentially the opposite of that observed for electrons: compressive strain
increases hole mobility in <110>- and <111>-orientated nanowires, and both tensile
and compressive strain enhance hole mobility of holes in <100> nanowires, as also
shown in Fig. 3.16 [102].
In germanium nanowires, the overall response of mobility to strain is similar to that of
silicon, in that electron mobility increases with tensile strain and hole mobility increases
with compressive strain. In strained Ge nanowires the electron mobility can reach values
1600 Electrons
3500 Holes
1400 [100]
3000 [100]
Mobility (cm2V–1s–1)
1200 [110]
2500 [110]
1000 [111]
[111]
2000
800
1500
600
400 1000
200 500
0 0
–3 –2 –1 0 1 2 3 –3 –2 –1 0 1 2 3
Uniaxial strain (%) Uniaxial strain (%)
Figure 3.16 Phonon-limited mobility of electrons and holes as a function of uniaxial strain magnitude in
silicon nanowires with a diameter of 8 nm and orientated in the <100>, <110>, and <111>
directions.
3.5 Summary 73
4000 Electrons 14000

Holes
3500 [100] 12000 [100]
3000 [110] 10000 [110]
2500 [111]
8000 [111]
2000
6000
1500
1000 4000
500 2000
0 0
–3 –2 –1 0 1 2 3 –3 –2 –1 0 1 2 3
Uniaxial strain (%) Uniaxial strain (%)
Figure 3.17 Phonon-limited mobility of electrons and holes as a function of uniaxial strain magnitude in
germanium nanowires with a diameter of 8 nm and orientated in the <100>, <110>, and <111>
directions.
higher than 3000 cm2 V−1 s−1 and the hole mobility can reach 12,000 cm2 V−1 s−1.
Tensile strain increases the mobility of electrons in nanowires of all orientations but this
increase is small for the <100> direction. As in the case of silicon, compressive strain
degrades electron mobility as seen in Fig. 3.17; also seen in Fig. 3.17 is that compressive
strain increases hole mobility in nanowires of all orientations, whereas tensile strain
decreases hole mobility [103].
Tensile strain has experimentally been observed to increase electron mobility
in trigate and Ω-gate silicon nanowire transistors. A tensile strain of 0.75% increases
the mobility in nMOS nanowire transistors by up to 55%, and decreases mobility by
30% for pMOS transistors for devices with a <110> transport direction [104]. An
increase in mobility has also been observed in heavily doped n- and p-channel
junctionless nanowire transistors as a function of applied uniaxial tensile and com-
pressive stress, respectively [105]. To probe further, the dependence of mobility in
silicon nanowires has been calculated by atomistic methods as a function of different
parameters, among which are nanowire diameter [106] and doping impurity concen-
tration [106,107].
3.5 Summary
Top-down and bottom-up strategies for the synthesis and fabrication, respectively, of
semiconductor nanowires were introduced with the techniques used to grow, or etch and
pattern nanowires described. Vertical nanowires can be grown by the vapor–liquid–solid
(VLS) growth technique or confined epitaxy, or alternatively can be patterned by using
lithography and etching. Methods for forming horizontal nanowires grown using the
VLS technique, by patterning an SOI layer, or by patterning heteroepitaxial layers, such
as Si/SiGe/Si, were also presented. Similarly, patterning techniques used for the fabrica-
tion of nanowire transistors were described in a step-by-step fashion including a
discussion on methods for smoothing and thinning of silicon nanowires. Novel hetero-
junction nanowires were described with axial and core-shell junctions, and the
advantages of these configurations for device applications were explored. As for planar
technologies, strain in fins and nanowires can be intentionally introduced to enhance
mobilities for charge carriers, hence the use of strain as a technology booster is equally
appropriate for FinFETs and nanowire transistors. The chapter concluded with a discus-
sion of the variation of nanowire mechanical properties such as Young’s modulus and
fracture strength as a function of diameter.
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4 Quantum mechanics
in one dimension
4.1 Overview
Solid-state physics is primarily concerned with the quantum mechanics of bulk

materials and surfaces. Molecular physics and quantum chemistry are similarly the
application of quantum mechanics to molecular problems. Bulk materials may be
described as three-dimensional objects, and their spatial dimensions have a significant
influence on the allowed solutions for quantum mechanical energy states or levels.
These quantum mechanical levels in three dimensions give rise to electronic band
structures which are commonly used to define a material as a metal, insulator, or
semiconductor. Energy bands are formed from quantum mechanical states that are
nearly continuous in energy. If the states that comprise a band are only partially filled
with electrons, a metal is formed. For a fully occupied band separated by a relatively
small energy gap, a semiconductor is the result. If the energy gap between a filled
band and an empty band is large, the material is described as an insulator. Molecules
are zero-dimensional objects with vanishing of the wave function in all three spatial
directions and the bound electrons do not propagate. This gives rise to a discrete
energy spectrum that is characteristic of molecules; the spacing between energy levels
is large and there is no corresponding band picture of the electronic spectrum.
Modern epitaxial growth, lithography, chemical synthesis, self-assembly, and scan-
ning probe techniques allow for the fabrication of material systems that are intermediate
in dimensionality to solids and molecules. When electrons or holes are confined in a
single direction and are free to propagate in two directions, a two-dimensional electron
or hole gas (2DEG or 2DHG) is formed. If electrons or holes are confined in two
dimensions and electrons or holes are free to move in a single spatial direction, a
nanowire or one-dimensional (1D) structure is formed. In the following, quantum
mechanics is introduced with a focus on the physics of 1D or nanowire structures with
emphasis on the concepts relevant to engineering transistor structures on the nanoscale.
4.2 Survey of quantum mechanics in 1D
Quantum mechanics relies on the use of state vectors to describe a physical system and
operators are used to determine physical properties that are measurable. In quantum
mechanics, the systems that are subject to measurement are of the same scale as the
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82 Quantum mechanics in one dimension
smallest experimental probes that can be devised. Hence the act of measurement
perturbs the state of a system in a non-negligible fashion and limits the amount of
information that can be extracted from a state vector. The fact that an arbitrarily precise
measurement cannot be extracted from a quantum system is highlighted by the famous
Heisenberg position-momentum uncertainty principle,
Δx Δp ≥ ℏ=2; ð4:1Þ
which states that the uncertainty in a position measurement x times the uncertainty in a
momentum measurement p is greater than or equal to Planck’s constant h divided by 4π,
where the constant “h bar” is given by ħ = h/2π. Planck’s constant is the fundamental
physical constant that sets the scale on which quantum mechanical phenomena are
important and is given in units of action, or energy × time.
4.2.1 Schrödinger wave equation in one spatial dimension

To understand the applications of quantum mechanics in subsequent chapters, the
Schrödinger equation is considered for an electron with mass m constrained to
move in one dimension in a potential energy described by a spatially varying
function UðxÞ where the position of the electron satisfies –∞ < x < + ∞. In other words,
the electron can be found anywhere along a 1D line. According to the Schrödinger
formulation of quantum mechanics, the state vector is described by a wave function in
the position representation ψ(x,t) at time t which is given by the solution of the wave
equation
" #
ℏ 2 ∂2 ∂
þ UðxÞ ψðx; tÞ ¼ iℏ ψðx; tÞ: ð4:2Þ
2me ∂x2 ∂t
The differential operator acting on the wave function on the left-hand side of Eq. (4.2),
ℏ 2 ∂2
H¼ þ UðxÞ; ð4:3Þ
2me ∂x2
is known as the energy operator or Hamiltonian, and is given by the sum of the kinetic
energy and potential energy terms. Thus in quantum mechanics the kinetic energy is
given in one spatial dimension by the second-order differential operator
ℏ 2 ∂2
T¼ : ð4:4Þ
2me ∂x2
As the Hamiltonian represents the energy of the system, the time derivative of the wave
∂
function iℏ is identified as the energy of the system at time t.
∂t
The probability density ϱ of finding an electron at position x and at time t is related to
the wave function by
4.2 Survey of quantum mechanics in 1D 83
ϱðx; tÞ ¼ ψ ðx; tÞψðx; tÞ: ð4:5Þ
However, in technology applications and charge transport problems it is more conve-

nient to refer to the charge probability density; this refers to the probability density
multiplied by the unit electron charge q:
ρðx; tÞ ¼ qψ ðx; tÞψðx; tÞ: ð4:6Þ
The charge probability density is commonly referred to as simply the “charge density” in
analogy to a continuous charge distribution in classical electromagnetic theory.
The Schrödinger equation, Eq. (4.2), is a linear differential equation and hence the
wave function ψ is determined up to an arbitrary multiplicative constant, or normal-
ization. Requiring the probability of finding an electron anywhere at a given time t to be
unity specifies the normalization of the wave function
ð þ∞
ψ ðx; tÞψðx; tÞdx ¼ 1: ð4:7Þ
∞
4.2.2 Electron current in quantum mechanics

The probability of finding an electron somewhere in the one-dimensional space is a
constant, but the probability density for finding an electron in a given region can change
with time. Hence a continuity equation for the charge density follows from Eq. (4.2) as
∂ ∂
ρðx; tÞ þ jðx; tÞ ¼ 0; ð4:8Þ
∂t ∂x
where jðx; tÞ denotes the charge probability current density, which is found from
Eqs. (4.2) and (4.6) to be

qℏ ∂ ∂
jðx; tÞ ¼ ψ ðx; tÞ ψðx; tÞ ψðx; tÞ ψ ðx; tÞ : ð4:9Þ
2ime ∂x ∂x
The charge current density specifies the probability of charge flowing in or out of a
region per unit time, and hence the identification as the electronic current density and, in
1D, the electron current and the electron current density are equal. The charge density
can be thought as the diagonal of the “density matrix,” which is defined for a single
electron in a pure state as
ρðx; x0 ; tÞ ¼ qψðx; tÞψ ðx0 ; tÞ: ð4:10Þ
In the general formulation of quantum mechanics, the density matrix is useful to

describe sub-systems, mixed states and for the definition of entropy, in the context of
the present discussion it allows the charge current to be written in terms of the “off-
diagonals” of the density matrix

qℏ ∂ ∂
jðx; tÞ ¼ 0 ρðx; x0 ; tÞjx¼x0 ; ð4:11Þ
2ime ∂x ∂x
0
where the differential operator acts prior to setting x ¼ x . If the energy E of a system is
constant, the wave function is separable in space and time:
ψðx; tÞ ¼ eiEt=ℏ ψðxÞ: ð4:12Þ
This allows the time-independent Schrödinger equation to be written as

" #
ℏ 2 ∂2
þ UðxÞ ψðxÞ ¼ EψðxÞ; ð4:13Þ
2me ∂x2
or in terms of the Hamiltonian energy operator H, it may be simply expressed as
HψðxÞ ¼ EψðxÞ: ð4:14Þ
The time-independent Schrödinger equation is seen to be an eigenvalue problem for

the differential operator H with eigenfunctions ψ and eigenvalues E. The eigenvalues
and eigenfunctions determine the allowed energy levels and their associated electronic
charge distributions can be determined using Eq. (4.6). Note that by using the separable
form of the wave function as defined by Eq. (4.12), the charge density, density matrix,
and current density likewise become time independent.
4.2.3 Quantum mechanics in momentum space

This introduction to quantum mechanics focuses on the position representation of the
Schrödinger equation; however, there are other forms or representations in which the
equations of quantum mechanics may be expressed. A form that can be useful for
electron scattering and charge transport is the momentum representation. A momentum
space representation for the (time-independent) wave function is given as the Fourier
transform of the wave function in the position representation
ð þ∞
1
φðpÞ ¼ pffiffiffiffiffiffiffiffi ψðxÞeipx=ℏ dx: ð4:15Þ
2πℏ ∞
Hence the momentum and position are conjugate variables for the Fourier transform.
Similarly, use of the Fourier transform can be made to rewrite the time-independent
Schrödinger Eq. (4.13) as
" ð þp0 #
p2
þ uðp p0 Þdp0 φðpÞ ¼ EφðpÞ ð4:16Þ
2me p0
in momentum space. To obtain this form, the property of the Fourier transform

∂ 2πi
ℱp ψðxÞ ¼ pφðpÞ ð4:17Þ
∂x ℏ
was used to rewrite the kinetic energy term. The Fourier transform of a product of two
functions is a convolution, which leads to the expression for the potential energy in
momentum space. Equation (4.17) allows us to identify the momentum operator in
position space as
∂
p ¼ iℏ ; ð4:18Þ
∂x
whereas in momentum space the momentum operator leads to multiplication by p. This

latter fact allows for the quantum mechanical kinetic energy operator to be identified as
T ¼ p2 =2m in analogy to the classical kinetic energy. From the momentum representa-
tion, it is found that a potential function UðxÞ local in position space becomes a non-local
potential in momentum space. Conversely, a local potential function uðpÞ in momentum
space becomes a non-local potential function in position space.
4.3 Momentum eigenstates
An electron propagating in vacuum in the absence of external electric or magnetic fields

is referred to as a free electron. In this case, the Schrödinger equation takes the form
ℏ 2 ∂2
TψðxÞ ¼ ψðxÞ ¼ EψðxÞ: ð4:19Þ
2me ∂x2
Two solutions can be readily found, ψk ¼ expð ikxÞ where p ¼ ℏk with k known as
the wave number (in 2D and 3D, k is a vector) with corresponding energy eigenvalues
E ¼ ðℏkÞ2 =2me . The Schrödinger equation is a linear differential equation for the cases
studied here and the general solution to Eq. (4.19) is
ψðxÞ ¼ Aeþikx þ Beikx ; ð4:20Þ
where the constants A and B must be determined by specifying boundary conditions.

Immediately it is seen that specifying the value of the wave function at ∞ is ambiguous
due to the oscillatory character of the complex exponential. However, it is possible to
specify that the electron be in a pure momentum eigenstate by noting that
∂ þikx
pψðxÞ ¼ iℏ e ¼ þℏk eþikx ð4:21Þ
∂x
describes a single electron with an exactly defined momentum p ¼ þℏk in the positive
direction. Similarly,
cos(kx)
sin(kx)
Ψ∗Ψ
1
−1
−1 0 1
kx / 2π
Figure 4.1 Real ℜ½ψ ¼ cosðkxÞ and imaginary Á½ψ ¼ sinðkxÞ components of a momentum eigenstate
and the associated charge density ρ½ψ ; ψ. The momentum eigenvalue is defined exactly resulting
in the wave function being delocalized over all space. The charge density for a plane wave state is
uniform.
∂ ikx
pψðxÞ ¼ iℏ e ¼ ℏkeikx ð4:22Þ
∂x
describes an electron with a momentum p ¼ ℏk propagating in the opposing direction.

Hence it is seen that the solutions ψk are eigenstates of the momentum operator.
It is worthwhile at this point to recall the Heisenberg uncertainty relation for position
and momentum, and to reconsider the wave function normalization for momentum
eigenstates. In Fig. 4.1, the real and imaginary components for the momentum eigenstate
with þk are displayed. Consistent with the Heisenberg uncertainty relation there is a
consequence of sharply defining the momentum: the electron is completely delocalized
throughout the 1D space. As a result, using Eq. (4.7) to determine the wave function
normalization for a momentum eigenstate is impossible as the integral diverges over all
space. There are two common conventions for plane wave normalization. The first is
referred to as continuous normalization and in this convention the wave function is
written
1
ψk ðxÞ ¼ pffiffiffiffiffi eikx : ð4:23Þ
2π
The normalization condition then becomes
ð þ∞ ð þ∞
1 0 0
ψk0 ðxÞψk ðxÞdx ¼ eiðkk Þx dx ¼ δðk k Þ ð4:24Þ
∞ 2π ∞
0
where δðk k Þ is a Dirac delta function. Continuous normalization can be convenient
for scattering problems; however, in technology applications it may be preferable to
consider a given charge density on a finite region of space and therefore “box normal-
ization” is useful. In this case, the wave function is only considered on a finite interval
½0; L. For a single electron confined on this interval the normalization condition can be
written
ðL
ψ ðxÞψðxÞ dx ¼ 1; ð4:25Þ
0
pffiffiffi
leading to a wave function ψk ðxÞ ¼ expðikxÞ= L and a constant charge density on the
interval of ρðxÞ ¼ q=L. To ensure orthogonality between wave functions with different
wave numbers, it is also necessary to quantize the wave numbers on the finite region
such that kn ¼ 2πn=L with n ¼ 0; 1; 2; . . . yielding a discrete set of states. This
form of the wave vector is achieved through Born–von Kármán boundary conditions
where it is assumed that the wave function is periodic by mathematically wrapping the
end points of the interval onto each other. The periodic boundary condition is distinct to
quantization on a finite region with confining potentials where the particle-in-a-box
solution arises; both boundary conditions will subsequently be applied to the different
physical models encountered as appropriate. In either case when treating large systems,
it is often useful to take the limit L ¼ ∞ at the end of a calculation. In many technology
applications, device or scattering regions are typically finite in extent and the quantiza-
tion of the wave number is characteristic of finite systems; in many cases non-periodic
boundary conditions will be applicable, or a combination of boundary conditions
confining a particle in one or two dimensions will be used when a particle is free to
propagate in either two or a single spatial dimension(s), respectively.
Returning to Eq. (4.20) and the selection of the coefficients A and B for a given set of
boundary conditions, one possibility is to select a momentum eigenstate with wave
number þk incoming at x ¼ 0 with positive momentum resulting in the selection
pffiffiffi
A ¼ 1= L and B ¼ 0. An alternative suggestion is to select a momentum eigenstate
entering the scattering region at L with wave number –k and negative momentum. In
pffiffiffiffi
this case the coefficients are chosen to be A ¼ 0 and B ¼ 1= L: It is worthwhile
observing that these two solutions are related to one another through time reversal
symmetry, t→ t: From the time-dependent Schrödinger equation, time reversal can
be shown to be equivalent to the transformation ψ→ψ , or in the momentum representa-
tion φðpÞ→φðpÞ: pffiffiffi pffiffiffi
The two solutions selected for Eq. (4.20), A ¼ 1= L, B ¼ 0 and A ¼ 0, B ¼ 1= L
are related to each other through time reversal and with opposing momenta ℏk as seen
from Eqs. (4.21) and (4.22). The electronic current, remembering that current and
current density are equivalent in 1D, is readily found from Eq. (4.9) and for the time-
independent momentum eigenstates the current is
q
I¼ ℏk: ð4:26Þ
me L
The relation can be written in a familiar form by recalling that velocity is related to
momentum as v ¼ p=m ¼ ℏk=m and that the charge density is ρðxÞ ¼ q=L or, inter-
preted classically, the charge at a given point in space is q=L. Hence the current relation
Eq. (4.26) is the quantum mechanical analogy to the classical relationship that electronic
current is the local charge × velocity.
Returning again to the free electron solution, Eq. (4.20), a constraint on the solution
can be imposed that the wave function is invariant under time reversal symmetry, a
condition expressed as ψ→ψ as t→ t: A solution satisfying time reversal symmetry
pffiffiffiffiffiffi
and the box normalization condition is A ¼ B ¼ i= 2L, which leads to a real wave
function
pffiffiffiffiffiffiffiffi
ψk ðxÞ ¼ 2=L sin ðkxÞ: ð4:27Þ
Equation (4.27) is recognized formally as the eigenfunction for the “particle-in-a-box”

problem for which the boundary conditions are normally specified as the vanishing of the
wave function at x ¼ 0 and x ¼ L. In this case, the quantization conditions for k differ
between Born–von Kármán and “particle-in-a-box” boundary conditions leading to a
wave vector in the latter case satisfying kn ¼ πn=L with n = 1, 2, 3,. . .. The quantum
mechanical current for the wave function Eq. (4.27) is I ¼ 0 and it can be shown that the
current calculated from any real wave function will be zero; this is also true of any wave
function that can be made real by a complex rotation expðiθÞ. It follows that to have a
current-carrying state on a finite region, it is necessary to introduce boundary conditions
that break time reversal symmetry, or what are otherwise known as open system
boundary conditions [1].
The energy for a free electron in Eq. (4.19) is E ¼ ðℏkÞ2 =2me and a plot of the energy
versus wave number k or energy dispersion is shown in Fig. 4.2. The parabolic relation-
ship between energy and momentum is characteristic of a free electron and this relation-
ship will be made use of when defining effective masses for “quasi-free” charge carriers.
4.4 Electron incident on a potential energy barrier
A standard problem when introducing the quantum mechanical theory of scattering is

the treatment of an electron incident onto a piecewise linear potential energy barrier. A
“rectangular barrier” as shown in Fig. 4.3(a) is often considered to introduce the concept
of quantum mechanical tunneling; here the related problem of electron transmission at a
“step potential” as depicted in Fig.4.3(b) is examined. In contrast to the case of a
rectangular barrier where the incident and transmitted electrons see the same potential
6
Energy [h 2/2ma 2]
0
−4 −3 −2 −1 0 1 2 3 4
Wave vector [2π/a]
Figure 4.2 Free electron dispersion: parabolic energy vs. wave number characteristic of free or
“quasi-free” electrons.
for regions far away from the center of the scattering region (usually taken to be U ¼ 0),
for the step potential there is a difference in potential between the incident and trans-
mitted electrons which is more representative of the boundary conditions applied to a
transistor channel where the source and drain regions are held at different voltages. A
slightly better approximation to a physical device is the case of a linear ramp voltage as
depicted in Fig. 4.3(c), where the voltage drop along a channel region is approximated as
a linear voltage or constant electric field; this case is studied in detail in [2]. The step
potential is presented here as the essential features of the scattering problem are provided
and introduces the concept of scattering states needed in the description of charge
transport in nanometer-scale transistor structures.
In the following, it is convenient to consider a scattering region ½L=2; þL=2 and to
place the potential step at x ¼ 0. The step potential is described by

0 x < 0;
UðxÞ ¼ ð4:28Þ
U x > 0:
A general solution of the 1D Schrödinger equation with the potential Eq. (4.28) is

Aeþikx þ Beikx x < 0;

ψðxÞ ¼ 0 0 ð4:29Þ
Ceþik x þ Deik x x > 0;
and continuity of the wave function is ensured by requiring A þ B ¼ C þ D: The

fact that energy eigenvalue is a constant independent of where the electron is located
implies
(a)
(b)
(c)
Figure 4.3 Electrons incident on a potential barrier. (a) Rectangular potential – describes as a first
approximation a device with a gate bias applied at zero drain–source voltage. (b) Step potential –
the difference in energy between left and right corresponds to application of a drain–source
voltage. The discontinuous jump in voltage at x ¼ 0 does not represent well the voltage profile in a
channel. However, the model is useful for considering the implications of non-zero drain–source
voltage, and is useful for investigating the asymmetric scattering between source and drain
electrons. (c) Ramp potential – the linear voltage profile in the channel represents a better
approximation to the channel voltage in the absence of a gate electric field. The scattering problem
in this case is described in detail in [2].
rffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2me 0 2me
k¼ 2
E and k ¼ ðE U Þ; ð4:30Þ
ℏ ℏ2
indicating that the electron momentum and velocity change across the regions where the
potential energy is changing value, as is true for classical mechanics.
Consider an electron incoming from the left in Fig. 4.3(b). The electron can be
backscattered or transmitted through to the region x > 0. However, as there is no further
scattering potential in the region x > 0, the electron cannot reverse direction and have an
incoming component from the right. Hence from physical boundary conditions we
can ascertain for a single incoming electron that A ≠ 0 and D ¼ 0. If the incoming
electron flux is chosen such that the charge density on the scattering region is ρ ¼ 1=L
when U ¼ 0 (on average, one electron on ½L=2; þL=2 in the absence of scattering),
pffiffiffi
then A ¼ 1= L. From the continuity condition and imposing that the first derivative of
the wave function be continuous leads to
A þ B ¼ C;
0 ð4:31Þ
ðA BÞk ¼ C k :
From Eq. (4.31) the two coefficients B and C can be deduced:

0
B kk
¼ ≡rl ;
A k þ k0
C 2k
¼ ≡tl ; ð4:32Þ
A k þ k0
with rl and tl defined as the reflection and transmission scattering amplitudes, respec-
tively, for a plane wave incident on the step potential barrier from the left. These
coefficients are defined relative to the incoming electron flux normalization coefficient
A. The resulting solution is known as a scattering wave function

Aðeþikx þ rl eikx Þ x < 0;

ψl ðxÞ ¼ 0 ð4:33Þ
Atl eþik x x>0
The same form for a scattering wave function is obtained for an electron incident
from the right, but now the electron experiences a potential drop as it traverses
from right to left. The reflection and transmission coefficients take on different
values in this case, and determining their values is left as an exercise for the
reader.
Using the expression Eq. (4.11) for the electron current, and recalling that current and
current density are the same in one dimension, the electron current can be calculated to
the left of the potential step to obtain
qℏ
I ¼ jðx < 0Þ ¼ ð1 jrl j2 Þk; ð4:34Þ
me L
pffiffiffi
where the incoming wave function normalization has been chosen to be A ¼ 1= L.
Similarly, the current on the right-hand side of the step barrier is found to be
qℏ
jtl j2 k :
0
I ¼ jðx > 0Þ ¼ ð4:35Þ
me L
Current conservation implies
ð1 jrl j2 Þℏk ¼ jtl j2 ℏk :

0
ð4:36Þ
This equation relates the scattering amplitudes rl and tl that determine the scattering wave
function. The left-hand side of Eq. (4.36) represents the incoming momentum of a plane
wave being partially cancelled by the reflected component of the electron’s momentum due
to the presence of the potential barrier. Relabeling the reflected component of the incoming
momentum as Rl ¼ jrl j2 , which gives the probability that an electron is reflected, then the
transmitted fraction of the incoming momentum can be defined as
ð1 Rl Þℏk ¼ Tl ℏk; ð4:37Þ
with a transmission probability defined as

0
k
Tl ¼ jtl j2 : ð4:38Þ
k
This allows current conservation to be expressed concisely as
Rl þ Tl ¼ 1; ð4:39Þ
and likewise the current is readily expressed in terms of the incoming momentum and the
transmission as
qℏ
I¼ Tl k: ð4:40Þ
me L
Although not explicitly expressed as such, transmission is a function of both the

incoming electron energy and the height and shape of the potential barrier. Equation
(4.40) is a fundamental relationship, relating electronic current to transmission and to the
boundary conditions; in this example, the flux normalization and momentum of the
incoming plane wave.
4.5 Electronic band structure
Nanowires are strictly speaking not one-dimensional objects: even an atomic chain
has two spatial dimensions normal to the chain axis. However, many of the proper-
ties of nanowires can be understood by considering electrons as though they are
confined to one spatial dimension. Later in this chapter, the effect of including the
two additional degrees of freedom normal to a nanowire’s principal axis and the
effects of quantum confinement will be considered. But to begin discussion of band
structures in nanowires, the simpler problem of a chain of “atoms” in strictly one
spatial dimension is studied. In this model, atoms are spaced at a distance a and, in
analogy with two- and three-dimensional crystal structures, a is labeled the lattice
spacing. Due to the construction of the model, it is inherent that the potential seen by
an electron arising due to the nuclei and charge cloud of the “other” electrons satisfies
Uðx þ aÞ ¼ UðxÞ. This is certainly true for an infinite crystal, but real materials are finite
in extent and have surfaces. To avoid considering the effects of a surface is one of the
4.5 Electronic band structure 93
reasons to introduce the Born–von Kármán boundary conditions previously mentioned.

The idea is to introduce a finite number of atoms N creating a chain of length L ¼ Na and
then introduce periodic boundary conditions. In essence, this is equivalent to wrapping
the atomic chain onto a ring and assuming that for large enough N the local curvature
does not deviate significantly from that of a linear chain. This choice of boundary
condition introduces an additional symmetry to the potential Uðx þ LÞ ¼ UðxÞ. In the
limit N; L→∞ an infinite linear atomic chain model with periodic boundary conditions is
obtained.
4.5.1 Brillouin zone

As a first approximation, the atomic structure and lattice spacing is ignored, or in other
words the potential is initially selected to be U ¼ 0, and the solution of the Schrödinger
equation in the one-dimensional space becomes the plane wave solutions already
encountered
1
ψkn ðxÞ ¼ pffiffiffi eikn x ; ð4:41Þ
L
with the periodicity L giving rise to the quantization of the wave vector
2πn
kn ¼ where n ¼ 0; 1; 2; 3; …: ð4:42Þ
L
The result Eq. (4.42) was taken as defined on a finite region and it is now seen that the
quantization condition for the wave vector implies periodicity on L. The atomic lattice
spacing can be re-introduced by insisting that the length is an integer multiple of the
lattice spacing L ¼ Na, although for the time being the potential is assumed to be U ¼ 0.
The wave vector can be rewritten
kn ¼ Gm þ k: ð4:43Þ
Labeling a new integer m ¼ Intð2n=NÞ, and recalling that the integer n may be zero,
positive, or negative, implies that likewise m ¼ 0; 1; 2; 3; …. The first term in Eq.
(4.43) is called the reciprocal lattice number and may be expressed as
2π
Gm ¼ m : ð4:44Þ
a
It is straightforward to show that

π π
≤ k ≤þ : ð4:45Þ
a a
Due to the periodicity of the wave function, replacing kn →k in Eq. (4.41) leaves the
value of the wave function, and hence other properties, unchanged. Equation (4.45)
defines the first Brillouin zone in a one-dimensional lattice and plays a special role in the
Energy [h2⁄ 2ma2] 3
0
–0.5 0.0 0.5
Wave vector [2π/a]
Figure 4.4 Free electron energy dispersion in the reduced zone scheme: the energy band diagram becomes
mapped back to the first Brillouin zone and the energy becomes multi-valued at a given k-point.
theory of electronic band structures. Any wave vector such that jkj > π=a can be mapped
back to the first Brillouin zone by the transformation
k ← k Gm ; ð4:46Þ
allowing for a scheme representing the simple parabolic band structure given in Fig. 4.2
within the first Brillouin zone. In Fig. 4.4, the free electron’s dispersion or energy versus
wave vector curve is plotted in a reduced zone scheme with the wave numbers mapped
back into the first Brillouin zone using Eq. (4.46), and the energy becomes multi-valued
for each value of k:
ℏ2
E m
k ¼ ðk þ Gm Þ2 : ð4:47Þ
2me
4.5.2 Bloch wave functions

A point to be made about the electron dispersion is that although the points at the edge of
the first Brillouin zone reflect the symmetry due to the lattice spacing, the plane wave
solutions at an arbitrary value of k do not. For the present discussion, the periodicity of
the Brillouin zone has been chosen to reflect the spacing of the atoms in a linear chain.
The effect of a periodic potential Uðx þ aÞ ¼ UðxÞ arising from the atoms at the lattice
points on the form of the electronic wave functions is considered next. For a non-zero
and varying potential, it is seen immediately that the plane wave solutions are no longer
solutions to the Schrödinger wave equation and the parabolic dispersion relating the
energy to the wave vector will no longer hold. However, due to the periodic form for the
potential, wave functions satisfying the condition
ψðx þ aÞ ¼ CψðxÞ ð4:48Þ
are sought with C a constant. Recalling that the Born–von Kármán boundary conditions
require that ψðx þ LÞ ¼ ψðxÞ and L ¼ Na, implies that
ψðx þ LÞ ¼ C N ψðxÞ: ð4:49Þ
This requires that C N ¼ 1 and is satisfied by C ¼ expði2πn=NÞ with n ¼ 0; 1; 2; ….

Periodicity of the wave function is then maintained for any solution that satisfies
ψðxÞ ¼ uk ðxÞ exp ði2πnx=NaÞ; ð4:50Þ
as x=a is an integer by construction at atomic lattice points. An additional requirement
uk ðx þ aÞ ¼ uk ðxÞ ð4:51Þ
is imposed to ensure that Eq. (4.48) is maintained. Rewriting Eq. (4.50) allows the wave
function to be expressed in the Bloch form as
ψk ðxÞ ¼ uk ðxÞ exp ðikxÞ: ð4:52Þ
A Bloch wave function is the product of a function symmetric in the lattice spacing
and a plane wave component. As the plane wave component is not required to have the
symmetry of the underlying lattice, the overall wave function for an arbitrary value of
the wave number does not reflect the lattice symmetry. The Bloch form is suggestive in
that the wave function is given by a plane wave solution modulated by a function that is
lattice periodic. It is straightforward to show that the lattice periodic term in the wave
function satisfies a Schrödinger-like equation
" 2 #
ℏ2 d
i þ k þ UðxÞ uk ðxÞ ¼ Ek uk ðxÞ: ð4:53Þ
2me dx
The plane wave component of the Bloch function acts as a “boost” to the momentum
operator p→p þ ℏk and hence the wave number is associated with a “crystal momen-
tum.” To understand the energy bands that result from the above equations in more detail
and to determine a band structure for a simple physical model of an atomic chain, the
tight binding approximation is introduced next.
4.6 LCAO and tight binding approximation
4.6.1 Linear combination of atomic orbitals (LCAO)

A common means for numerically solving the Schrödinger equation is to intro-
duce the linear combination of atomic orbitals (LCAO) approximation [3]. When
solving the Schrödinger equation of the hydrogen atom, the spherical symmetry of
the atom gives rise to a set of electronic states that can be categorized by their
principal quantum number n, angular momentum number l, magnetic quantum number
ml , and spin quantum number ms [4]. Each of these single-electron states can be labeled
as an electron orbital, magnetic effects will not be considered, so only the quantum
numbers ðn; l; ms Þ will be needed. Similarly for a general description of atoms, electron
orbitals can be generated as single-electron states that are found by treating all other
electrons in an atom by a mean field approximation. A set of single-electron states or
hydrogen-like orbitals can be computed. These states are typically categorized in
numerical calculations using spectroscopic notation for angular momentum as s-type
for l ¼ 0, p-type for l ¼ 1, d-type for l ¼ 2, and so forth. These single-electron states are
those that are used to define the electronic configurations for atoms and their occupan-
cies are given by the Aufbau principle. The LCAO uses these atomic orbitals to build
solutions for molecular and solid state electronic structures. The wave function ψn ð~ rÞfor
n
the nth electronic state is expanded in terms of a set of m atomic orbitals φij placed at the
ith atomic position ~R i as
XN Xm
ψn ð~
rÞ ¼ i¼1 j¼1 ij ij
r ~
cn φ ð~ R i Þ; ð4:54Þ
which expresses the LCAO in equation form. All the information about the nth eigen-
function is contained within the expansion coefficients cnij . The number of orbitals per
atomic site m determines the quality of an approximation. In selecting a set of orbitals a
minimum basis would be a single s-type orbital and three p-type orbitals to describe
silicon’s valence electron structure of [Ne]4s2 4p1x 4p1y , and by convention a “minimal
basis set” is a single atomic orbital for each angular momentum state occupied in the
atom. By adding additional atomic orbitals per atomic site, the approximation can be
improved. Atomic orbitals with angular momenta higher than that occupied in the atom
are referred to as polarization functions and add to the variational freedom needed to
describe chemical bonding in solids and molecules. Indeed for treating silicon’s con-
duction band, it is found necessary to introduce polarization functions which
provide additional flexibility to the trial wave function by adding excited s-type states
(denoted s [5]) or through the addition of functions with higher angular momentum
(d; f ; g; …). As an alternative to the use of a localized basis, such as atomic orbitals, the
problem may be formulated in terms of a plane wave basis and indeed it is this latter
approach which is followed in many modern electronic structure methods [6]. However,
for our purposes of introducing the electronic structure of nanowires, a localized basis
approach highlights the essential features of the problem and reflects the requirement for
localized orbitals, as opposed to plane waves, as required by commonly applied methods
for the calculation of charge transport in nanowires.
To simplify the problem, a chain of atoms with a single atomic orbital per site is
considered. The LCAO is rewritten in this case as
XN
ψn ð~
rÞ ¼ i¼1 i i
r ~
cn φ ð~ R i Þ: ð4:55Þ
The example of the single-electron Hamiltonian H is considered, and the eigenvalue

equation is projected onto a single atomic orbital as
ð ð
3
φi ð~ ~
r Ri ÞHψn ð~
rÞd r ¼ En φi ð~r R rÞd 3 r
~i Þψn ð~
XN ð XN ð
n ~ ~ 3 n ~i Þφj ð~ ~j Þd 3 r: ð4:56Þ
c
j¼1 j
φi ð~
r Ri ÞHφj ð~
r R j Þd r ¼ En c
j¼1 j
φi ð~
rR rR
It is convenient to define the matrix elements

ð ð
3
Hij ¼ φi ð~ ~
r Ri ÞHφj ð~ ~ r ~
r R j Þd r; Sij ¼ φi ð~ R i Þφj ð~ R j Þd 3 r;
r ~ ð4:57Þ
where Hij is referred to the LCAO Hamiltonian matrix (also referred to as a Fock matrix)
in the atomic orbital basis and Sij is the overlap matrix for the atomic orbitals.
Projecting onto each distinct atomic orbital as in Eq. (4.56) results in a set of
linear equations that may be written as a generalized eigenvalue problem given in
matrix form as
c ¼ En S~
H~ c: ð4:58Þ
The formulation as a generalized matrix eigenvalue problem is one of the primary

motivations for the LCAO approximation as the problem becomes readily accessible to
numerical methods and solution using computers. Since there are N expansion func-
tions: the matrix eigenvalue problem is N N: The N eigenvalues and eigenvectors
obtained from the numerical solution of the matrix eigenvalue problem form approx-
imations to the N lowest energy levels and their wave functions. In general, solution of
Eq. (4.58) will scale as the order OðN 3 Þ unless additional approximations or simplifica-
tions are made.
4.6.2 Tight binding approximation

At this point it is convenient to make such a further approximation. The first is to assume
the overlap matrix is diagonal Sij ¼ δij , reducing the generalized matrix eigenvalue
equation to the more familiar matrix eigenvalue form
c ¼ En~
H~ c: ð4:59Þ
The diagonals of the overlap matrix for normalized atomic orbitals are unity but there are
non-zero off-diagonal terms due to the overlap between the atomic basis functions at
different sites. However, the wave functions can be made orthonormal through a
procedure called Boys localization [7], or similarly chosen to be Wannier functions
[8]; for these choices the overlap matrix is strictly diagonal and details constructing
maximally localized basis sets can be found in [9]. As will be seen, the explicit form of
the atomic orbitals does not need to be specified in a tight binding approximation, hence
the assumption the overlap matrix is diagonal is justifiable when working with localized
orthonormal basis sets. The next set of approximations is to express the energy matrix
elements in the tight binding approximation; within this approximation there are only
two types of non-zero Hamiltonian matrix elements for the case of identical atoms
Hii ¼ αi ;
ð4:60Þ
Hij ¼ βij ;
where the αi are referred to as the on-site matrix elements and the βij are the hopping
matrix elements and are taken to be zero unless j ¼ i 1, or in other words, the hopping
matrix elements are assumed to be zero unless the interactions are between neighboring
sites. Within the tight binding approximation of a linear atomic chain with a single basis
function per site, the matrix eigenvalue problem takes a particularly simple form and the
secular equation for the eigenvalues can be written
0 1
αE β 0
B β αE β 0 C
B C
B 0 β αE C
B C
B C
B .. .. .. C ¼ 0: ð4:61Þ
B . . . C
B C
B αE β 0 C
B C
@ 0 β αE β A
0 β αE
The parameters α; β can be calculated, but are often fitted to empirical data or used as
adjustable parameters to consider the effects of different hopping and on-site matrix
elements. The matrix eigenvalue problem in this form is easily solved. Solution of the
secular equation yields the N energy levels for the atomic chain, which are given by
N N
En ¼ α 2β cosð2πn=NÞ; n¼ ; …; 0; …; þ 1; ð4:62Þ
2 2
with the resulting energy band plotted in Fig. 4.5. From the matrix eigenvalue problem, a
recursion relation for the expansion coefficients is found and is given by
βcnj1 þ ðα En Þcnj þ βcnjþ1 ¼ 0: ð4:63Þ
The Born–von Kármán boundary conditions can be implemented by the requirement

that c nj ¼ c njþN and the expansion coefficients are then found to be
1
cnj ¼ pffiffiffiffi ei2πnj=N ; ð4:64Þ
N
which when multiplied by the atomic orbitals is a discrete version of the plane wave
modulation of a Bloch wave function. The integer j can be thought of as labeling each
atomic position through xj ¼ ja, with a the lattice spacing and the length of the chain
given by L ¼ Na. Then the wave number kn ¼ 2πn=L can be again introduced, allowing
the energies and wave functions to be expressed as
3
Energy [β]
0
–1 0 1
Wave number [π ⁄a]
Figure 4.5 Energy dispersion for the tight binding model of a finite atomic chain for α ¼ 2β without
periodic boundary conditions.
n=1
n=2
n=3
n=6
Figure 4.6 Examples of the wave functions for a linear atomic chain. The nodal structure of the wave function
corresponds to the sinusoidal envelope given for the case of a “hard wall” confinement potential as
opposed to the case of a “periodic” linear chain. Lighter regions depict values where the wave
function is positive and darker regions represent regions where the wave function is negative (or
vice versa as energies and other properties are invariant with respect to a constant phase of the
wave function).
N N
En ¼ α 2β cosðkn aÞ; n¼ ; …; 0; …:; þ 1;
2 2
1 Xn ikn xj
rÞ ¼ pffiffiffiffi
ψn ð~ j¼1
r ~
e φj ð~ R j Þ: ð4:65Þ
N
Although a simple example, the tight binding model for an atomic chain displays
many of the features inherent in the electronic structure of more realistic systems. The
bandwidth (the difference between maximum and minimum energies within a single
band) is 4β, hence weaker interactions cause weaker splitting in the energy levels and
stronger interactions cause larger splitting between levels. At fixed interaction strength
and increasing number of atoms, the band width remains the same whereas the energy
separation between levels decreases. If the interaction between sites is completely
decoupled by letting β→0, all the energy levels become equal or degenerate and reduce
to En ¼ α. In this case, the energy dispersion is described as a “flat band” as the energy is
constant as function of wave vector. Hence a flat band is indicative of a weakly
interacting set of atoms or defects, whereas bands with large curvatures are indicative
of strong interactions between atoms. Another feature of the tight binding band structure
for the atomic chain is the fact that unlike the free electron dispersion relationship, the
band is not parabolic. However, expanding the energy for small values of the wave
vector, the energy can be approximated as
En ≈ α 2β þ βðkn aÞ2 ; ð4:66Þ
which for sufficiently small displacements in the wave vector about the energy minimum
is parabolic. Of course for larger values of the wave number “non-parabolicity” (higher-
order terms in the Taylor series expansion of the cosine term) are required to describe the
electronic structure. However, for any energy band with a minimum there will always be
a region about the minimum that is parabolic. For this parabolic region the dispersion is
similar to the free electron dispersion and the electrons in the vicinity of a minimum may
be treated as free electrons with a modified or effective mass. If electrons only occupy
energies within the region where the band can be described as approximately parabolic,
then the “quasi-free” electron description is a suitable approximation. Recalling the free
electron dispersion relation, it is noted that the mass is related to the curvature of the
energy band or equivalently the second derivative of the energy with respect to wave
number. Generalizing this relationship to the vicinity of an energy minimum with
arbitrary curvature, the effective mass m is defined by
∂2 E ℏ 2
¼ : ð4:67Þ
∂k 2 m
In the effective mass approximation and for energies that are sufficiently close to the
minimum, all effects arising from the interactions between the atoms are included in the
parameter m ; in all other respects the electron behaves as a free electron.
4.7 Density of states and energy subbands
4.7.1 Density of states in three spatial dimensions

The 3D Schrödinger equation in the absence of a potential energy term is
ℏ2 2
∇ ψðx; y; zÞ ¼ Eψðx; y; zÞ: ð4:68Þ
2m
Using the technique of separation of variables the wave function can be written as the
product of independent wave functions, with each solving a free electron problem,
resulting in
1 ikx x iky y ikz z
ψðx; y; zÞ ¼ e e e ; ð4:69Þ
L3=2
with the wave numbers in each spatial dimension satisfying Eq. (4.42). The energy is
given by
ℏ2 2
E¼ ðk þ ky2 þ kz2 Þ: ð4:70Þ
2m x
If a system of many non-interacting electrons or what is known as the free electron gas
is considered, then a sphere of volume
4
Volume ¼ πk 3 ð4:71Þ
3
can be defined where the norm of all the wave vectors within the sphere satisfy
j~
kj ¼ jðkx ; ky ; kz Þj ≤ k. Along the three axes, the spacing between the different discrete
k-points is given by Δk ¼ 2π=L: Hence each distinct point representing a wave vector
can be considered to occupy a volume of ð2π=LÞ3 . The number of distinct states within
the sphere is given by
N ¼ 2 Volume=ð2π=LÞ3 ; ð4:72Þ
where a factor of two has been introduced to account for the two spin states of an
electron. The number of states in the sphere is given by
k 3 L3 ð2m EÞ3=2 L3
N¼ ¼ : ð4:73Þ
3π2 ℏ3 3π2
The density of states (DoS) is now defined as the number of states per unit energy per
unit volume of a material sample
1 dN
DoS ¼ ; ð4:74Þ
L3 dE
where in this example the volume of the sample is L3 : Then for a 3D electron gas the
density of states is found to be
1 ð2m Þ3=2 pffiffiffiffi

DoSj3D ¼ E: ð4:75Þ
2π2 ℏ3
The key feature of the DoS for the 3D free electron gas is a continuous, monotonic
pffiffiffiffi
increase as E. The unit for the 3D DoS is number of states per unit energy and per unit
volume. Other units to described the 3D DoS is number of states per unit energy obtained
by omitting the division by volume in Eq. (4.74).
4.7.2 Density of states in two spatial dimensions

Next the case of a two-dimensional electron gas is considered. A two-dimensional
system can be, for example, obtained by growing a thin layer of aluminum gallium
arsenide (AlGaAs) on a gallium arsenide (GaAs) substrate by molecular beam epitaxy or
related methods [10]. The conduction band offset between the substrate and the thin
AlGaAs layer acts as a confining potential as does the surface of the AlGaAs layer itself.
In this case, electrons can be confined within the thin layer parallel to the substrate. If the
layer is sufficiently thin (typically 10 nm or less), it is possible to produce a 2DEG for
use in high electron mobility transistors (HEMTs). In this case, the Schrödinger equation
can again be written using the method of separation of variables, but with the two spatial
degrees of freedom parallel to the substrate treated with periodic boundary conditions,
whereas the spatial coordinate normal to the substrate axis may be modeled as a
confining potential as for the case of a particle-in-a-box. The Schrödinger equation in
this simplified model may be written as
" #
ℏ2 2
∇ þ UðxÞ ψðx; y; zÞ ¼ Eψðx; y; zÞ; ð4:76Þ
2m
where the confining potential has been introduced as UðxÞ: The energies for the particle-
in-a-box problem with vanishing of the wave function at the boundaries of a hard wall
potential with width L are given by
n2 h2
En ¼ n ¼ 1; 2; 3; …; ð4:77Þ
8m L2
with wave functions

rffiffiffi
2 nx π
ψnx ðxÞ ¼ sin x ; ð4:78Þ
L L
where L is the thickness of the confining region. The solutions with negative n
are related to positive n by a sign change and therefore have equal energies and the
wave functions are related by a phase rotation. Hence the solution with n are not
linearly independent and the convention is to take the solutions with n ¼ 1; 2; 3; … as
the set of eigenfunctions for the particle-in-a-box problem. With knowledge of the free
particle and the particle-in-a-box eigenfunctions, the solution to Eq. (4.76) may be
written
U = |q|V U = |q|V
n=3
n=2
n=1
–x +x
Figure 4.7 Energy levels in a one-dimensional confinement potential. The hard wall potential corresponds to
the limit where the potential well depth U ¼ jqjV becomes infinite. The energy levels within a
well of finite depth are indicated by the dashed lines.
sffiffiffiffiffiffiffiffiffiffiffiffiffi
2 nx π
ψðx; y; zÞ ¼ sin x eiky y eikz z ; ð4:79Þ
Lx Ly Lz Lx
leading to energies
nx 2 h2 ℏ2 2
E¼ þ ðk þ kz2 Þ
8m L2x 2m y ð4:80Þ
ℏ2
¼ Enx þ ðky2 þ kz2 Þ:
2m
Each new energy Enx defines the onset of a contribution from a subband to the DoS, with
each subband corresponding to the energy levels in the confinement direction as
depicted in Fig. 4.7. Following the same set of steps as leading to the three-dimensional
density of states but now applied to the case of the two-dimensional electron gas leads to
the following expression for the density of states:
X m
DoSj2D ¼ ΘðE En Þ; ð4:81Þ
n πℏ2
where the Heaviside step function satisfies ΘðE ≥ 0Þ ¼ 1 and ΘðE < 0Þ ¼ 0: The den-
sity of states for a 2DEG displays a staircase-like structure, with the steps corresponding
to the onset of additional contributions to the DoS from each subband as the energy is
increased. The units are given as number of energy states per unit energy per unit area or
simply number of energy states per unit energy for a given 2D sample.
4.7.3 Density of states in one spatial dimension

If confinement potentials are introduced in two spatial dimensions, a one-dimensional
electron gas or nanowire is formed. As discussed in Chapter 3, such nanowire structures
may be formed from top-down lithographic techniques or by chemical self-assembly
methods. The Schrödinger equation for a nanowire constraining a free electron gas to
one dimension is in analogy with the 2DEG case written as
" #
ℏ2 2
∇ þ UðxÞ þ UðyÞ ψðx; y; zÞ ¼ Eψðx; y; zÞ; ð4:82Þ
2m
where the confinement potential has been separated into the two terms UðxÞ and UðyÞ
constraining propagating electrons to the z direction. In the case of a free electron gas
confined to one spatial dimension, the eigenfunctions are
rffiffiffiffiffi
4 nx π ny π ikz z
ψðx; y; zÞ ¼ sin x sin y e ; ð4:83Þ
L3 L L
leading to energies
ℏ2 2
E ¼ Enx þ Eny þ k : ð4:84Þ
2m z
Each ðnx ; ny Þ pair corresponds to an energy subband and a conduction channel in the
z direction. The lowest subband is found for nx = ny = 1. Following again the steps
leading to the calculation of the DoS but in this instance for a nanowire leads to
X ðm Þ1=2 1
DoSj1D ¼ nx ;ny
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Θ½E ðEnx þ Eny Þ; ð4:85Þ
πℏ 2½E ðE þ E Þnx ny
and is given in units of number of states per unit energy per unit length or, similar to the
3D and 2D cases, as number of states per unit energy for a given one-dimensional
system.
4.7.4 Comparison of 3D, 2D, and 1D density of states

The behavior for the 3D, 2D, and 1D electron gas DoS as a function of energy is
pffiffiffiffi
shown schematically in Fig. 4.8. The 3D DoS as noted behaves as E; whereas
in the 2D and 1D case the DoS within a subband is constant or decreases as
pffiffiffiffi
1= E, respectively. Clearly the ability to structure materials on nanometer-scale
lengths results in dramatic changes in the electronic band structure of a material,
which can be to advantage or disadvantage when considering transistor designs.
4.8 Conclusions 105
(a) (b)
3D Density of States
Energy 2D Density of States

Energy
(c)
1D Density of States
Energy
Figure 4.8 Density of states for an electron gas in (a) three dimensions, (b) two dimensions, and (c) one
dimension. For the 2D DoS shown in (b), the first subband associated with the confinement
potential acting on the electrons in one spatial dimension has an onset at E1 and the onset of the
second subband is at E2 . For the 1D system the confinement potential restricts the electrons in two
spatial dimensions, and due to confinement in two dimensions the first subband occurs at energy
E1;1 and the second subband begins at E2;1 as shown in (c).
4.8 Conclusions
This chapter is intended to highlight key points for the physics of low-
dimensional systems, emphasizing quantum mechanics in one dimension.
Fundamental relationships related to device physics such as electron momentum
and velocity, electronic current, electron scattering, electronic band structure, and
the density of states have been introduced and demonstrated using simple phy-
sical models. These concepts are built upon in more detail in Chapters 5 and 6,
where they are applied to a more realistic description of semiconductor nanowire
structures as relevant to technology design.
Further reading
Quantum mechanics
E. Merzbacher, Quantum Mechanics, New York: John Wiley, 1998.
Physics in one dimension

R. Gilmore, Elementary Quantum Mechanics in One-Dimension, Baltimore, MD: The
Johns Hopkins University Press, 2004.
References
[1] W.R. Frensley, “Boundary conditions for open quantum systems driven far from
equilibrium,” Rev. Mod. Phys., vol. 62, pp. 745–791, 1990.
[2] M.J. Kelly, “Transmission in one-dimensional channels in the heated regime,”
J. Phys.: Condens. Matter, vol. 1, pp. 7643–7649, 1989.
[3] C.C.J. Roothaan, “New developments in molecular orbital theory,” Rev. Mod.
Phys., vol. 23, pp. 69–89, 1951.
[4] G. Herzberg, Atomic Spectra and Atomic Structure, New York: Dover Books,
2010.
[5] J.C. Slater and G.F. Koster, “Simplified LCAO method for the periodic potential
problem,” Phys. Rev., vol. 94, pp. 1498–1524, 1954.
[6] M.C. Payne, M.P. Teter, D.C. Allan, T.A. Arias, and J.D. Joannopoulos, “Iterative
minimization techniques for ab initio total energy calculations: molecular
dynamics and conjugate gradients,” Rev. Mod. Phys., vol. 64, pp. 1045–1097,
1992.
[7] J.M. Foster and S.F. Boys, “Canonical configuration interaction method,” Rev.
Mod. Phys., vol. 32, pp. 300–302, 1960.
[8] G.H. Wannier, “The structure of electronic excitations in insulating crystals,”
Phys. Rev., vol. 52, pp. 191–197, 1937.
[9] N. Marzari, A.A. Mostofi, J.R. Yates, I. Souza, and D. Vanderbilt, “Maximally
localized Wannier functions: theory and application,” Rev. Mod. Phys., vol. 84,
pp. 1419–1475, 2012.
[10] B.A. Joyce, “Molecular beam epitaxy,” Rep. Prog. Phys., vol. 48, pp. 1637–1697,
1985.
5 Nanowire electronic structure
5.1 Overview
The electronic structure of a semiconductor nanowire can vary substantially with respect
to bulk material properties due to orientation, diameter, strain, quantum confinement,
and surface effects. Before introducing the electronic structure of nanowires, the
crystal structures of common group IV and III-V binary compounds are introduced.
Semiconductor nanowires, even for diameters of a few nanometers, can retain the
bonding characteristic of their bulk crystalline forms. This permits classification of
nanowires by the crystal orientation aligned to the nanowire long, axial, or “growth”
axis. To determine electronic structures of materials generally requires a combination of
experimental and theoretical approaches in a fruitful collaboration whereby the strengths
of several methods are used to complement one another. Elementary analysis of band
structures is considered in relation to the observed properties of materials leading to
their categorization as insulators, semiconductors, semimetals, and metals. These basic
material categories are the fundamental building blocks for nanoelectronic devices. A
brief discussion of experimental and theoretical methods for the determination of
electronic properties is given to provide background on the state-of-the-art for electronic
structure characterization and calculations. The electronic band structures of common
bulk semiconductors are presented for reference. Atomic scale models for nanowires
oriented along different crystal directions are introduced with the relationship between
confinement normal to a nanowire’s long axis and electronic structure expressed in terms
of band folding. Representative electronic band structures are then introduced for
different nanowire systems based on diameter and orientation to highlight the key effects
of reduced dimensionality on electronic structure.
5.2 Semiconductor crystal structures: group IV and III-V materials
5.2.1 Group IV bonding and the diamond crystal structure

Silicon crystallizes in a cubic crystal structure that has the same symmetry as the
diamond form of carbon. This structure is referred to as the diamond cubic crystal
structure or sometimes more colloquially as the “diamond lattice.” The local bonding
characteristic of the diamond crystal structure is largely retained when nanowires are
patterned from crystalline silicon or grown from bottom-up processes such as those
described in Chapter 3. In the diamond structure, each atom is tetrahedrally bonded to
four nearest neighbor atoms. Many materials can also exist in amorphous form whereby
the long-range order of a crystal is lost. There is a degree of short-range order in these
materials, but for the amorphous forms of the Group IV materials carbon, silicon, and
germanium, the local bonding environment deviates from tetrahedral bonding, and all
atoms are not necessarily four-fold coordinated. Although the amorphous form of silicon
and germanium do find applications such as in low-cost photovoltaic cells and amor-
phous carbon in diamond-like carbon (DLC) form finds application in thin film coatings
to harden materials for use in tooling, the vast majority of nanometer-scale transistor
designs rely on the use of highly crystalline materials and hence the crystalline form of
various semiconductors and nanowires is the focus in this chapter.
Tetrahedral bonding gives rise to the diamond lattice structure and is a result of atomic
orbital hybridization. The atomic ground state of the valence electrons in silicon has a
configuration ½Ne3s2 3p1x 3p1y where ½Ne denotes the 10 inert core electrons of the silicon
atom with occupancy isoelectronic with neon. In the silicon atomic ground state, there
are two unpaired electrons readily available for bonding. The first electronic excited
state of silicon is denoted as Si and is represented by the electronic structure
½Ne3s1 3p1x 3p1y 3p1z whereby a valence 3s-orbital is excited to a higher energy, unoccupied
3pz -orbital. Quantum mechanically it is found that the energy gained by making an
additional two unpaired electrons available for bonding can exceed the energy required
to promote an electron from a 3s-orbital. In this situation, the four atomic orbitals
3s; 3px ; 3py , and 3pz can hybridize to form four equivalent linear combinations of atomic
orbitals or molecular orbitals giving rise to the four equivalent bonds, resulting in the
tetrahedral bonding structure depicted in Fig. 5.1(a). This bonding motif is designated as
sp3 hybridization and the resulting diamond crystal structure shown in Fig. 5.1(b) is the
3D crystalline form of carbon, silicon, and germanium. The diamond form for the group
IV materials carbon, silicon, and germanium is due to their similar valence electronic
structures. The carbon atom’s valence electronic structure is given by ½He2s2 2p1x 2p1y and
germanium’s valence electronic structure is represented as ½Ar4s2 4p1x 4p1y ; for silicon,
(a) (b)
109.47°
Figure 5.1 (a) Tetrahedral bonding. (b) Diamond crystal structure.
5.2 Semiconductor crystal structures 109
(a) (b) (c)
Y
Z X
Figure 5.2 Diamond crystal structure viewed along the (a) <100>, (b) <110>, and (c) <111> directions in
the direct lattice vectors (coordinate space).
these atoms form sp3 hybridized bonds and can thus crystallize in the diamond structure.
Carbon, silicon, and germanium are all semiconductors with band gaps of 5.48 eV,
1.17 eV, and 0.74 eV [1] at 0 K, respectively. At room temperature these energies
become 5.47 eV, 1.11 eV, and 0.66 eV, respectively. Following the sequence down the
group IV column in the periodic table, the next element is tin (Sn) with a valence
electronic structure ½Kr4d 10 5s2 5p1x 5p1y . At room temperature, tin crystallizes in a tetra-
gonal structure known as β-tin and is a metal. At temperatures below 13 °C, tin crystallizes
and is stable in the diamond lattice [2]. This phase is known as α-tin and it is neither a
semiconductor nor a metal, but rather is a semimetal. There is no band gap as the valence
and conduction bands meet but there is a low density of states at the Fermi level resulting
in lower conduction than typical for the coinage metals gold, silver, nickel, and copper.
Other bonding motifs are possible for group IV elements and these are seen often in
materials and compounds containing carbon. If it is energetically favorable for an
s-electron to be excited to form C then the carbon atom will also bond through sp3
hybridization. However, other possibilities for mixing of the atomic orbitals can be
energetically favorable, particularly in the case of carbon materials. If with excitation to
the C state, only two of the valence p-orbitals mix with the valence s-orbital, sp2
hybridization results. Bonds formed by sp2 hybridization are characteristic of the planar
forms of carbon such as the hexagonal structure of benzene, the hexagonal layers that
form graphite, the isolated, two-dimensional, single-atom-thick sheets of graphite
known as graphene, and the closed, cylindrical sheets of graphene that result in carbon
nanotubes; other examples of two-dimensional materials will be introduced in
Section 5.2.3.
Given the similar chemical structures of the group IVelements, it is not surprising that
they may be alloyed and that they remain energetically and thermodynamically stable
over a range of compositions. Silicon and germanium can be alloyed together in
arbitrary composition and a random lattice structure is formed which remains approxi-
mately in the diamond crystal form. Each atomic site is occupied by either a Si or Ge
atom with a probability that is proportional to the crystal’s stoichiometry and with each
atom forming four nearest neighbor bonds. For an alloy composition Six Gey with
x þ y ¼ 1, the fractional probability of a site being occupied by a silicon atom is x and

the fractional probability that the site is occupied by germanium is y. Since the local
environment in terms of nearest neighbors is random, there is some distortion from a
perfect crystal resulting in a loss of symmetry and small splitting in the energy bands [3].
Similarly, Sn can be alloyed with Ge: Introduction of atoms of different atomic radii
into a crystal introduces local stress fields. Hence alloying is often used as a “stressor” to
remove degeneracies in the electronic band structure to achieve reduction in intravalley
scattering and thereby increase mobility, or alternatively as a means for matching lattice
constants between two layers to reduce strain across interfaces in heterostructures.
Solids composed of silicon and carbon produce a wealth of structures referred to as
silicon carbide polymorphs; in general these structures are not random alloys but are
crystalline. Common polymorphs of silicon carbide (SiCÞ form hexagonal lattices,
although there is a stable structure that forms a structure similar to diamond known as
the zincblende structure, which will be discussed next in the context of gallium arsenide
and other group III-V compounds.
5.2.2 III-V compounds and the zincblende structure

The compound semiconductor gallium arsenide (GaAs) forms a zincblende crystal
structure whereby group III gallium atoms and group V arsenic atoms arrange on two
distinct sub-lattices. The overall structure is similar to diamond in that each atom in the
crystal forms four nearest neighbor tetrahedral bonds as shown in Fig. 5.3. However, in
the zinc blend structure each gallium atom bonds to four nearest neighbor arsenic atoms
and each arsenic atom bonds to four nearest neighbor gallium atoms. Charge is trans-
ferred from the group III atoms to group Vatoms in a Lewis picture of chemical bonding,
Figure 5.3 Tetrahedral bonding in the zincblende structure. Dark grey atoms occupy the gallium (cation)
sub-lattice and light grey atoms occupy the arsenic (anion) sub-lattice. Each Ga atom bonds to four
nearest neighbor As atoms, and each As atom bonds to four nearest neighbor Ga atoms.
Figure 5.4 Schematic representation of (a) an indirect band gap semiconductor and (b) a direct band gap
semiconductor. The grey regions indicate the occupied electron states near the valence band
maximum and the empty parabola represents the unoccupied conduction band states for an
intrinsic semiconductor at low temperature.
hence in GaAs the gallium atoms are said to form a cation sub-lattice and the arsenic
atoms form an anion sub-lattice.
Unlike silicon and germanium, GaAs is a direct band gap material. In a direct band
gap material, the conduction band minimum and valence band maximum energies occur
at the same point in the Brillouin zone as depicted in a simplified representation of the
electronic structure of indirect and direct transition semiconductors in Fig. 5.4. In an
intrinsic semiconductor with a band gap energy significantly larger than the thermal
energy kB T, the valence band states will be occupied and the conduction band states will
be unoccupied. To promote an electron from a valence to a conduction state requires
additional energy. If the electron is excited by the absorption of a photon with an energy
Eg , to reach the bottom of the conduction band from the valence band maximum in an
indirect band gap semiconductor also requires a change in crystal momentum as
depicted in Fig. 5.4(a). Changes in crystal momentum must be included to preserve
overall momentum conservation. At the threshold for light absorption there is no
momentum available to be transferred to the crystal lattice to allow an electron to be
excited to the band gap minimum in an indirect band gap material. Hence two processes
are necessary to promote an electron from the valence band maximum to the conduction
band minimum such as photon absorption and coupling to phonon modes. The prob-
ability for a two-step process is much lower than for a single, direct process as depicted
in Fig. 5.4(b) where no change in crystal momentum is required. Hence the probability
of light absorption at the band gap energy is generally much higher in a direct band gap
material such as GaAs, and it is the case that many other III-V materials also possess a
direct band gap. The same considerations apply to the complementary process of
electron-hole recombination. For a direct band gap material, electron-hole recombina-
tion accompanied by the emission of a photon for energy conservation is a direct process
not requiring coupling to phonons or other degrees of freedom to conserve momentum,
and can therefore occur with a larger probability amplitude relative to indirect processes.
Hence the III-V materials are often the material of choice for designing semiconductor
lasers, light emitting diodes, and optical amplifiers [4].
An electron mobility in highly crystalline bulk GaAs of 240 000 cm2 =Vs at a
temperature of 77 K [5] has been reported; this is significantly higher than mobilities
for silicon at comparable conditions. It remains true that the GaAs mobilities at room
temperature and for doped materials remain multiples larger than the values for compar-
able silicon samples. Electron mobility arises from many competing effects as will be
discussed in Chapter 6; in a polar solid such as GaAs there are influences from polar
optical phonon, acoustic phonon, piezoelectric, ionized, and neutral impurity scattering.
These effects can be heuristically categorized by a relaxation time and a spatially
averaged isotropic electron effective mass. Mobility is proportional to the ratio of the
effective relaxation time to the charge carrier’s effective mass. Hence in GaAs the
conduction band edge electron effective mass of m ¼ 0:067me [6] offers a simple
explanation for the improved electron mobility in GaAs relative to Si or Ge when
coupled with the assumption of similar scattering effects leading to similar magnitudes
for relaxation times. The corresponding isotropic effective masses for electrons near
conduction band minimum in silicon and germanium are quoted to be typically 1:08me
and 0:56me , respectively. Note, however, that the values for hole effective masses in
III-V materials are not dramatically different from those found for Si and Ge, and in fact
the lower hole effective mass in germanium implies there is no significant advantage to
the use of III-V materials to enhance hole mobilities. The higher electron mobility of
GaAs combined with a band gap of 1.43 eV at 300 K [6] suggests its potential use to
increase mobility and switching times for use in n-channel field-effect transistors [7].
However, there are both technological and fundamental obstacles to the use of III-V
materials in modern integrated circuit manufacturing. The first of these relates to
material science: the native oxides of most III-V materials do not form a low defect
density interface to the semiconductor when compared to the very low defect densities
that can be achieved for the silicon/silicon dioxide interface of 1011/cm2 or lower,
roughly corresponding to a single surface defect per 105 surface bond sites. However,
(a) (b) (c)
Figure 5.5 Zincblende structure depicted for the case of the gallium arsenide structure viewed along the
(a) <100>, (b) <110>, and (c) <111> directions in the direct lattice vectors (coordinate space). For
nanowires, the truncation of the infinite crystal leads to different surface compositions varying
between arsenic “rich” to gallium “rich.”
processing recipes for depositing high-κ oxides onto silicon substrates and multi-gate
structures have been developed. It is possible that material combinations and advanced
processing conditions will be found that can eliminate the high interface defect densities
found at III-V/oxide interfaces [8]. A second issue for transistor design is that a lower
effective mass as mentioned implies a higher mobility and a faster switching time for
transistors; however, a lower effective mass also implies a lower density of states, which
can be seen for example in Eq. (4.85) for a 1D system. As will be seen in Chapter 6, the
lower density of states in nanowire transistor design leads to limitations for current
drive. As transistor channels become extremely small, direct source–drain tunneling
becomes a serious impediment to the ability to turn a transistor to an OFF state and thus
smaller effective masses can also lead to higher tunneling currents in the OFF state.
Notwithstanding the potential challenges and limitations, the search to find a high
mobility n-channel material for high-speed electronics leads to the III-V ternary alloy
In0.53Ga0.47As as a possible candidate to replace silicon [9,10]. This alloy composition is
lattice matched to InP and InP substrates are available to allow growth of high-quality
In0.53Ga0.47As layers. The ternary compound InxGa1-xAs is stable in a zincblende-like
structure with the indium and gallium atoms distributed randomly on the cation sub-
lattice and the room-temperature band gap of 0.75 eV is well suited for electronic
applications. The low effective mass of the conduction electrons of 0:041me [6]
leads to a room-temperature electron mobility of 8450 cm2 =V s at 300 K and 27,700
cm2 =V s at 77 K [10] in processed samples.
5.2.3 Two-dimensional materials

Semiconductor nanowires are quasi-one-dimensional systems; however, the actual
three-dimensional structure of a semiconductor nanowire can retain properties of its
parent bulk structure in terms of chemical bonding and crystal symmetry, although the
latter is of course reduced due to the introduction of confinement in directions normal to
the nanowire long axis. The chemical bonding in semiconductors is three-dimensional in
structure as reflected in the tetrahedral bonding arrangement depicted in Fig. 5.1(a) and
this three-dimensional bonding network is found in many nanowires fabricated by either
top-down or bottom-up methods. Similarly, two-dimensional electron and hole gases
may be thought of as semiconductor materials that have been thinned or grown to the
nanometer range in one spatial dimension, but these layers largely retain the chemical
bonding characteristics of the bulk.
Not all materials have strong three-dimensional bond networks. For example, some
solids are composed of “layers” with strong chemical bonds in essentially two-
dimensional sheets with weak interlayer interactions or van der Waals forces holding
the layers together in the bulk form. Perhaps the best known example of this class of
material is graphite, composed of carbon layers in a hexagonal sp2 hybridized bonding
arrangement as shown in Fig. 5.6(a). Until recently it was believed that a two-
dimensional isolated material of single-atom thickness would be thermodynamically
unstable, but in 2004 a team was able to isolate by mechanical exfoliation (effectively by
(a)
(b) (c)
(d) (e)
Figure 5.6 (a) The planar hexagonal structure of graphene, (b) side view of an (8,8) armchair carbon
nanotube, (c) perspective view of an (8,8) armchair carbon nanotube, (d) side view of an (8,0)
zigzag carbon nanotube, (e) perspective view of an (8,0) zigzag carbon nanotube.
“peeling”) single layers from graphite to form an isolated single monolayer or graphene.
This discovery led to the awarding of the Nobel prize in 2010 to Novoselov and Geim
[11]. A single layer carbon sheet or graphene is of interest due to its stability and the
capability to study the atomic scale limit of a material. Graphene is therefore of interest
for exploring the ultimate limits to nanoelectronics scaling. This 2D material gives rise
to novel physics due to its semimetal character, with nearly linear dispersion at the
bottom of the conduction band and top of the valence band, yielding very low
mass charge carriers and extremely high carrier mobilities [12]. Although a band gap
can be induced in a graphene sheet by forming “ribbons,” the application of graphene in
conventional transistor design is limited. However, there are novel strategies for devel-
oping new nanometer scale device designs with graphene. For example, the use of
self-assembly of organic molecules such as alkanes without significant disruption to a
single atomic layer graphene channel can be used to introduce a stable dielectric layer to
substitute the role of an oxide layer in a transistor gate stack [13]. However, potentially
the most attractive feature of graphene materials is to explore non-classical switching
elements that do not rely on electric field effects to control switching, that is for transistor
designs that are not dependent on the field effect.
Carbon nanotubes (CNTs) are graphene strips rolled onto hollow cylinders and are
therefore effectively closed-form two-dimensional materials [14]. The CNTs shown in
Fig. 5.6 are formed by wrapping a single graphene sheet into itself and onto a cylindrical
shape. Nanotubes formed in this way are referred to as single walled carbon nanotubes
(SWCNTs). Although not difficult to produce, SWCNTs were not observed experimen-
tally until 1991 [15], but pre-date the discovery of graphene. Graphene can be wrapped
into a cylindrical shape in different ways, referred to as the chirality or “handedness” of
the nanotube. Specific chiralities give rise to different structures that are categorized as
“armchair,” “zigzag,” or simply “chiral”; see Fig. 5.6. The different structures give rise
to different electronic properties for a specific CNT which may be insulating, semicon-
ducting, or metallic. A lack of a high degree of control over the chirality during growth is
the critical limiting factor for introducing these materials into nanoelectronics manu-
facturing. SWCNTs can have diameters of less than 1 nm but are typically found within a
range of 1 to 3 nm, whereas their lengths can be on the order of centimeters. The atomic
structure of a carbon nanotube is essentially defect-free. This nearly perfect structure
results in quasi-ballistic transport for charge carriers with little or no scattering along the
tube length and even in the presence of defects scattering lengths can remain orders of
magnitude larger than modern transistor lengths [16]. Similarly, their defect-free struc-
ture make CNTs efficient for phonon transport resulting in high thermal conductivities
along the tube axis. The high charge carrier capability and phonon transmission in CNTs
make them attractive for nanoelectronics applications. Nanotubes are able to carry
current densities up to three orders of magnitude larger than typical conductors such
as copper and aluminum making them extremely attractive for applications in nanoelec-
tronic interconnects if issues surrounding their controlled growth and integration into
manufacturing processes can be found.
There are processes for fabricating CNTFETs within laboratory settings including
deposited gate oxides and gate electrodes with metallic source drain regions leading to
Schottky junction formation [17,18]. CNTFETs have been fabricated and compared to
silicon MOSFETs and it is found that the CNTFETs can have lower switching delays
compared to transistors with other material sets and with similar ON–OFF current ratios.
CNTFET device layout and fabrication has not been fully optimized for high-frequency
behavior. There are theoretical predictions for high carrier velocities achievable with
CNTs, and measurements for high-frequency performance on non-optimized structures
indicate that ballistic limited CNTFETS should outperform ballistic limited Si FETs
[19]. A comparison for the performance of junctionless gate-all-around silicon nanowire
transistors with similar transistors with the channel material replaced with a semicon-
ducting CNT indicates that due to the smaller band gaps in the CNTs and resulting
ambipolar effects, junctionless transistors with a Si nanowire channel will have lower
OFF state currents and comparatively better subthreshold slopes [20]. In order to achieve
the promise of CNTs, however, in any large-scale integration scheme, progress is
required in the placement and controlled growth of nanotubes with pre-selected electro-
nic character.
(a)
(b)
(c)
Figure 5.7 Three views of a single layer of molybdenum disulfide: (a) an off-axis perspective of a single
layer, (b) a top view normal to a single layer, (c) a side view of a single layer.
Graphene is not the only two-dimensional material that can be exfoliated from
graphite bulk to form isolated monolayers. Any material that displays strong in-plane
bonding but with layers held together by weaker van der Waals forces is a candidate for
isolation of stable monolayers [21]. An example of this class of materials are transition
metal dichalcogenides (TMDC) and single layers of MoS2, WS2, MoSe2, and WSe2, for
example, have been prepared by exfoliation. Due to the bonding in these layers, the
TMDC monolayers are not a single atomic thickness as shown in Fig. 5.7 for the case of
molybdenum disulfide. Viewed normal to the monolayer surfaces a hexagonal-like
pattern is seen as in Fig. 5.7(b), whereas a side view into the layer reveals that the
bonding of the sulfur atoms to transition metal is such that a central metal layer bonds to
sulfur layers above and below, as revealed in Fig. 5.7(c). Unlike graphene, these two-
dimensional materials can have significant energy band gaps, and the indirect band gaps
observed for some bulk TMDCs become direct band gaps in their two-dimensional form.
The reasonable values found for their band gap energies has spurred interest in the use of
these materials for nanoelectronics applications, and the emergence of a direct band gap
suggests the materials may be useful in photonic devices such as photodetectors and
electroluminescent devices. However, fabrication of layers of the quality needed for
large-scale nanoelectronics integration and the ability to form reliable electrical contacts
to these materials remain a challenge and an area for continued exploration.
5.3 Insulators, semiconductors, semimetals, and metals 117
5.3 Insulators, semiconductors, semimetals, and metals
Electrical resistance can vary by up to 24 orders of magnitude ranging from effectively

zero in a superconductor to a yotta-ohm in insulators. Classification of a material as a
metal, semimetal, semiconductor, or insulator is primarily related to the ability to
conduct electricity. A fundamental measure of a material’s ability to conduct electricity
is the density of states at the Fermi energy. Electronic structure can be described in
“reciprocal vector” or “k-space” as energy bands. The allowed quantum mechanical
energy states in a material collectively describe a material’s “band structure.” At 0 K, the
lowest lying electronic states are filled up to the Fermi energy. As temperature is
increased, the lowest lying unoccupied energy states can become filled as governed by
the Fermi–Dirac distribution function.
In a band model of a material, an energy range about the minima or maxima of the
dispersion, or band energy versus wave vector, can be described as parabolic. The range
over which this approximation is valid depends on the explicit form of a band at energies
higher and lower than the band minima and maxima, respectively. However, given the
fact the band edges are extrema, they can always be approximated as parabolas over
some energy range. In Fig. 5.8 a qualitative representation of the electronic structure of
different materials is presented with models consisting of two parabolic bands or, in the
case of a metal, a single band. The grey areas within the dispersion curves depict the
occupied states that are filled at a temperature of 0 Kelvin.
Insulator Semimetal Semimetal Metal

(SiO2, HfO2) (graphene a-tin) (bismuth, antimony) (aluminium, copper)
Semiconductor
(Ge, Si)
Figure 5.8 Simple energy band models for insulators, semiconductors, semimetals, and metals. The grey
regions denote energy levels that are filled at temperatures of 0 K. At the two extremes are
insulators and metals, and intermediate to these are semiconductors and semimetals. There are two
categories of semimetals. The first of these may be thought of as a direct semiconductor with a
“zero band gap” energy, and the second category may be viewed as an indirect semiconductor with
a “negative band gap” energy.
For insulators and semiconductors, there exists a forbidden energy range about the
Fermi level where there are no electronic states. The states below the energy gap that are
fully occupied at 0 K are the valence states and the states fully unoccupied at 0 K above
the energy gap are the conduction states. For materials such as silicon dioxide (SiO2) or
hafnium dioxide (HfO2) used as dielectric insulators, the band gap is relatively speaking
large, typically greater than 5 eV. The role of a dielectric in a MOSFET is to act as an
insulating layer and in general, in addition to chemical stability and a low number of
electrical defects, the ideal insulator has the largest possible band gap. A material is
typically considered a semiconductor if it has an energy band gap in the range of 0.1 eV
to 4 eV. Hence the distinction between a semiconductor and an insulator is somewhat
arbitrary with a material such as diamond used as an insulator or a semiconductor
depending on the application. Semiconductors have the property that their conductivities
can be changed by orders of magnitude by the introduction of defects, impurities or
dopants with energy levels near the conduction or valence band edges, but indeed many
insulators such as oxides can share this property too.
In a metal, the Fermi level lies in the middle of an energy band or there are many
overlapping energy bands at the Fermi level. The electrons in a partially filled band are
mobile. As electrons are delocalized in a metal and since many unoccupied states are
available to the electrons at the Fermi energy, metals have a high conductivity. The
conductivity of a good metallic conductor such as aluminum or copper is approximately
10 orders of magnitude higher than that of intrinsic silicon.
If the band gap energy is small compared to the value of kB T at a given
temperature, electrons will be thermally excited from the valence band to the conduction
band. In contrast to a good conductor, there would be a relatively low density of states at
energies near the Fermi level as the top of the valence band and the bottom of the
conduction band are the only states accessible. If the band gap were to become zero, the
valence and conduction band edges would meet and the density of states would remain
low. A “zero band gap” material with a low or vanishing density of states at the Fermi
level describes a semimetal. Like a metal, there is no energy band gap but unlike a metal
there are only a small number of electrons to conduct at the Fermi level. Graphene is a
semimetal, although it has the unusual property that its energy dispersion at the Fermi
level is not parabolic but rather is linear. A similar band structure is found for tin in the α-
phase.
Another type of band structure that can lead to semimetal behavior can be found in
materials such as bismuth and antimony. This category of semimetal may be considered
as an indirect band gap semiconductor, but where the conduction band minimum is
below the valence band maximum. Clearly as seen in Fig. 5.8 the definition of valence
band and conduction band has been blurred as there are unoccupied “valence states” and
occupied “conductance states” at a temperature of 0 K. Often these types of metals
are referred to as having a “negative band gap,” although this is intended only to be
descriptive of the band structure, as technically the band gap is zero. The band structure
results in two partially filled bands at the Fermi level and a density of states that is higher
than the density of states in graphene or α-tin which approach zero at the Fermi level.
The low density of states at the Fermi level implies a lower conductivity than for good
metallic conductors, and indeed the conductivity found for semimetals at room tem-
perature can be two to four orders of magnitude smaller than for copper. However, for a
material like graphene with a linear dispersion at the Fermi level, the effective masses
for charge carriers are approximately zero. Hence very high mobilities matching or
exceeding good metallic conductors can in principle be achieved with semimetals.
This is a simplified representation of a material’s electronic band structure and
the relationship to conductivity. Detailed band structures for materials will be
considered in Sections 5.6 and 5.7. Nonetheless, the simplified models do capture
the essential physics that permits a distinction between insulators, semiconductors,
semimetals, and metals based solely on characteristics of their electronic band
structures. To understand the differences between, for example, two semiconduct-
ing materials requires an explicit knowledge of the differences between their
individual band structures.
5.4 Experimental determination of electronic structure
The experimental determination of electronic band structure for a material can infer
properties either by extracting parameters to describe a measurement, or by direct
measurement of quantities that can be interpreted in terms of the electronic band
structure. In general, experimental determination of the electronic structure of materials
can be characterized as either electrical or optical measurements. Electrical and optical
data can be used to extrapolate data and to estimate a band gap and infer whether a band
gap is direct or indirect. Other methods or techniques allow for a direct determination
of a band gap such as scanning probe microscopy (SPM) or photoelectron spectroscopy.
For detailed mapping of the electronic structure throughout the Brillouin zone, optical
measurements in the form of angle resolved photo-emission spectroscopy can be
applied. A complete determination of the electronic structure of a material may be
measured at a few physically important regions in the Brillouin zone or at points of
high symmetry. Experimental measurements combined with theoretical calculations can
provide a detailed understanding of electronic bands and the physical properties that can
be extracted from a band structure. In the following, a short survey of experimental
techniques is provided to provide a glimpse at how various methods can be applied and
the type of information that can be obtained from the measurements. In Section 5.5, the
subject of calculating electronic structure from the principles of quantum mechanics will
be discussed.
5.4.1 Temperature variation of electrical conductivity

Straightforward means for estimating band gaps in semiconductors can be obtained
from extrapolation approaches relying on the measurement of the temperature
variation of conductivity. Electrical conductivity for a semiconductor sample may
be obtained through two-point and four-point probe measurements, or by Hall
measurements. For an intrinsic semiconductor with a band gap one to two orders
of magnitude larger than the thermal energy at room temperature, the conductance
of a sample increases moderately as the temperature is raised from low values
primarily due to the thermal excitation of electrons from the valence band into the
conduction band. In doped semiconductors, electrons are excited into the conduc-
tion band from the impurity or dopant states, and free-flowing elections are
created. Conversely for impurities accepting electrons from the valence band
edge, hole states are created. As temperature increases, impurity states occurring
in the band gap will become fully ionized and the conductivity will remain
constant as a function of temperature. As the temperature increases further, elec-
trons can be thermally excited from the valence band across the energy band gap
to the conduction band. At the onset of this process, the conductivity begins to
increase again with temperature. The probability of an electron being occupied is
given by the Fermi–Dirac distribution function, which will be discussed further in
Chapter 6. The electron distribution function is then expressed as
1
fD ðEÞ ¼
eðEμF Þ=kB T þ 1 ; ð5:1Þ
where E is the electron energy, μF is the Fermi energy which for an intrinsic material is
midgap or at Eg =2 relative to the valence band edge taken as the zero of energy, and kB T
is the thermal energy. For reasonable values of the band gap energy (i.e. sufficiently large
with respect to kB T) and at typical measurement temperatures of 300–500 K, the
probability of an electron being occupied at the conduction band edge EC can be
approximated by a Boltzmann factor
fB ðEC Þ ∝ expðEg =2kB TÞ: ð5:2Þ
As the conductivity is proportional to the number of free carriers, the temperature

dependence of the conductivity can be expressed as
σðTÞ ¼ σ 0 expðEg =2kB TÞ: ð5:3Þ
For semiconductor materials typically used in electronics, this approximation applied

to the temperature range between 300 and 500 K serves as a reasonable description.
Plotting the natural logarithm of the conductivity versus the inverse temperature leads to
extraction of a value for the band gap energy. It is assumed in this simple derivation the
energy band gap is independent of temperature whereas it varies, albeit relatively slowly,
over the temperature ranges over which the measurements are typically performed.
Within the approximations made, this simple approach can lead to energy band gap
estimates that are typically within tens of millielectron-volts of values as determined
from more accurate experiments.
The extraction of band gaps for doped materials is not as straightforward as for
intrinsic semiconductors. However, if a pn junction can be formed, a similar approach
can be applied to the determination of the energy band gap. A pn junction’s ability to
rectify is expressed by the Shockley or diode equation

qV
IðV Þ ¼ I0 exp 1 ; ð5:4Þ
kB T
which describes the characteristic that there is a large flow of charge with a forward
voltage bias but limited charge in the reverse bias direction given by the reverse
saturation current I0 . The reverse saturation current arises from different mechanisms:
diffusion currents, carrier generation inside the depletion region, surface leakage effects,
and tunneling of carriers between states in the band gap. The latter two effects can be
eliminated or reduced and may be in a first approximation neglected and carrier genera-
tion is generally much lower than the diffusion currents, thus the reverse saturation
current can be primarily attributed to the minority carriers entering the depletion region
and being swept across the junction by the built-in electric field. In this case, the
expression for the reverse saturation current can be expressed as
I0 ¼ AT 3 þ γ=2 expðEg =kB TÞ; ð5:5Þ
where A is a material related constant, γ is related to the temperature dependence of the

mobility, and all other variables and parameters are as previously defined [22]. Re-
expressing the Shockley equation using Eq. (5.4) for the reverse saturation current leads
to
γ
qV þ 3 þ kB T lnðTÞ ¼ Eg þ kB T lnðI=AÞ: ð5:6Þ
2
As lnðTÞ is a slowly varying function over the temperature range of interest, a plot of
qV at fixed current versus temperature is approximately linear with the zero temperature
intercept approximating the band gap energy. For more accurate approximations, the
second term on the left-hand side can be used to correct the voltage expression leading
again to estimates of the band gap within tens of millielectron-volts of energies obtained
from more accurate measurement techniques.
The electrical measurements presented provide relatively straightforward means for
extracting band gap energies and provide reasonable accuracy. However, relying on an
extrapolation procedure can introduce relatively large experimental uncertainties in the
band gap energies. Furthermore, extracting more detailed electronic structure beyond
the band gap energy from electrical characterization data is difficult.
5.4.2 Absorption spectroscopy

If the value of a band gap for a semiconductor is required, absorption spectroscopy is
often a preferred choice to obtain a measurement as the experiments are relatively
straightforward and reasonable accuracy for band gap energies can be obtained. If a
more accurate determination is required, additional techniques such as reflection spec-
troscopy and measurement of photo-diffusion currents can be used in conjunction
with absorption spectroscopy to improve the accuracy of measured band gaps. The
fundamental assumption in absorption spectroscopy is that a material follows the
entrance
slit
monochromator
broad frequency
light source
exit
slit
sample
detector
Figure 5.9 A graphical depiction of an absorption spectrometer. The monochromator is used to direct light
with varying frequency onto a sample with transmitted light measured at a photodetector. The
difference between intensities with and without the absorbing sample allows for determination of
the absorption.
Beer–Lambert law, which states that the amount of light transmitted through a material
decays exponentially with a material’s thickness. Thus the light transmittance defined to
be the intensity of incident light to light transmitted through a thin sample is given by
T ¼ I=I0 ¼ expðαlÞ; ð5:7Þ
where T is the light transmittance, I0 is the incident light intensity, I is the transmitted
intensity, α is the absorption coefficient governed by the mechanisms for light interac-
tions with a sample, and l is the length the light travels through the material, i.e. the
thickness of the material sample. The exponential law is simply the mathematical
statement that the probability for absorption of light within a differential length dl is
assumed constant throughout the sample. A simplified view of an absorption experiment
is shown in Fig. 5.9 for a single beam configuration. However, most experiments will
have a dual beam set-up to measure the incident and transmitted beams simultaneously
to compensate for instrumental drift during the course of a measurement [23].
In many absorption measurements, a powder form of a material is prepared and
dissolved into a solvent with corrections to the Beer–Lambert law to account for the
size of the cell containing the solution and to account for the concentration of the
solvated sample. Clearly for nanoelectronics applications, absorption through thin
films on transparent substrates can in many cases be readily achieved but similar
experiments for general nanostructured materials can be much more challenging. In
these cases sophisticated experimental set-ups are required to perform an absorption
measurement; however, for dense nanowire arrays similar experiments can be per-
formed. In some instances, reflection spectroscopy can simplify the measurements.
However, it is instructive to consider the fundamental concept of relating light
transmission through a sample to band gap energies, as well as to ask if additional

information about a sample’s electronic structure can be extracted from absorption
measurements.
The fact that a band gap energy can be extracted by repeating electrical measurements
as a function of temperature was discussed in Section 5.4.1. In an optical absorption
experiment, the band gap is determined by varying the energy of the incident light using
a monochromator as shown in Fig. 5.9. For a semiconductor, if the energy of the incident
photons are less than the material’s band gap, there are no electronic states accessible to
which the light can interact and hence the light cannot be absorbed. The incident and
transmitted intensities for this energy range will ideally be equal. For incident photon
energies greater than the material’s band gap, the transmitted light intensity becomes
attenuated and the absorption coefficient increases. A plot of the absorption coefficient
versus incident photon energy then shows a threshold that indicates the onset of
absorption. This onset threshold corresponds to the material’s band gap energy. Above
the band gap energy, the behavior of the absorption coefficient can also be used to
determine if the sample is a direct or indirect semiconductor. For an incident photon
frequency of ν or energy hν where h is Planck’s constant, the following relation can be
used for determining both the band gap energy and whether band gap is either direct or
indirect
αhν ∝ ðhν Eg Þn ; ð5:8Þ
where it can be shown an exponent of n ¼ 1=2 corresponds to a direct gap material with
allowed transitions at the band gap energy, and n ¼ 2 is for transitions involving an
indirect band gap [24]. A graph of Eq. (5.8) is known as a Tauc plot and is commonly
applied to determine both the value of the band gap and the nature of photo-excitations
occurring at the band gap energy. The difference in the value of the exponent between
direct and indirect photo-transitions arises from energy conservation and the fact that
for a direct transition no accompanying momentum change is required at the onset of
absorption, whereas an indirect transition requires additional quasi-particle momentum
changes to account for the accompanying crystal momentum change as indicated in
Fig. 5.4.
5.4.3 Scanning tunneling spectroscopy

There are electrical measurements that can be performed on a semiconductor to directly
determine the band gap energy without relying on a numerical extrapolation and these
measurements belong to a family of techniques known as scanning tunneling spectro-
scopy (STS). In Chapter 4, scattering off a step potential was considered. A related
problem is scattering through a potential barrier with finite spatial extent such as for the
rectangular potential barrier depicted in Fig. 4.3(a) that is often used to demonstrate the
quantum mechanical phenomenon of tunneling. Tunneling processes occur when
the energy of an incident electron is lower than the energy of a potential barrier for
which the corresponding classical process it would be found the probability of finding an
electron crossing the barrier region would be zero. In quantum mechanics, there is a
finite probability that an electron incident from one side of the potential barrier can
“tunnel” through the classically forbidden region under the potential energy barrier and
emerge on the opposite side. The calculation outlined in Section 4.4 for the scattering
off a step potential can be repeated for the case of a rectangular potential profile with
incident electron energies less than, equal to, and greater than the potential barrier
height. These three energy ranges each lead to different behavior for the electron
transmission. Focusing on the quantum mechanical solution for the transmission of
electrons with incident energy less than the height of a rectangular potential, it is found
that in contrast to the classical case the transmission probability for electrons with
energies less than the barrier height is non-zero and the tunneling component of the
wave function increases exponentially as the barrier width is decreased.
In scanning tunneling microscopy (STM), a conducting probe is brought within less
than a nanometer of a surface. The conducting probe is typically a metal that is fashioned
into an apex or “tip,” although conducting carbon nanotubes can also be used as probes.
The spatial gap between the probe tip and sample gives rise to a potential barrier to
electron flow. If the tip approaches close enough to a surface, electrons from either the tip
or the surface can tunnel across the barrier from occupied states into empty states. Figure
5.10 demonstrates the basic idea. In Fig. 5.10(a), the metal probe with a continuous
density of states is shown on the left and an intrinsic semiconductor with a Fermi level at
mid-band gap is shown on the right. A potential barrier due to the spatial gap is situated
between probe and sample. The different work functions for the materials result in an
energy offset between the materials, and at zero voltage bias there are no empty states for
electrons from the probe tip to tunnel into the semiconductor, or vice versa. In
Fig. 5.10(b), a voltage is applied across the junction. If the reference voltage is taken
to be the probe tip, then it is seen that the semiconductor states are shifted down in energy
resulting in the empty semiconductor conduction band aligning to the Fermi level of the
metal and a tunnel current can flow. As the electrons flow from the metal tip to the
semiconductor, the semiconductor has a forward voltage bias applied with respect to
the probe tip. Reversing the voltage bias results in the configuration of Fig. 5.10(c),
whereby the semiconductor states shift upwards with respect to the metal probe tip
states, and the highest energy filled valence states in the semiconductor can tunnel into
the unoccupied metal states of the probe tip with energies above the Fermi level.
A defining feature of scanning probe techniques is the tunneling current is exponen-
tially sensitive to the spatial gap between the probe tip and sample. Even though a probe
tip may possess roughness on an atomic scale, it is only the protrusions of the tip nearest
the surface that lead to significant tunneling currents. Hence STM methods can measure
with atomic scale resolution and, with use of the technique, the local density of states at
surfaces can be determined. Many different applications of SPM methods have led to an
incredible variety of surface images or related measurements whereby probe tips are
scanned or “rastered” across a sample to map surface atomic positions as inferred from
the local density of states as measured at the Fermi energy [25]. Using scanning probe
techniques, the emergence of the parabolic energy dispersion in atomic chains of
increasing length has been determined [26], and it is even possible to image
(a) E E
U
–x +x
(b)
U
–x +x
(c) U
DOS(E)
DOS(E)
–x +x
Figure 5.10 Schematic of a scanning tunneling microscope (STM). On the left is the density of states for a
metallic STM tip and on the right is the density of states for a semiconductor surface. Black
regions in the density of states signify occupied states and grey areas indicate unoccupied states.
The central region indicates the tunneling barrier due to the gap between the tip and surface. (a) No
voltage bias applied between probe tip and sample. (b) The semiconductor sample is positively
biased with respect to the tip. (c) The semiconductor sample is negatively biased with respect to
the tip.
energy-resolved local density of states allowing the charge density associated to single-
electron orbitals to be observed [27,28].
This qualitative description of scanning tunneling microscopy can be given a theore-
tical basis by considering the transfer Hamiltonian approach developed by Bardeen for
the description of tunneling between two metal films separated by a thin oxide layer [29].
In this approach, a many-electron state for the metal regions is constructed from
quasi-particles localized in the metals on either side of the oxide tunneling barrier. A
transition from an electron in an occupied state on one side of the barrier to an
unoccupied state on the other side of the barrier is treated as a small perturbation to
the overall many-electron state. The analysis leads to an expression for the tunneling
current that may be written for the case of a probe tip and surface as
ð þ∞
4πjqj
I¼ fD ðEF qV þ EÞ fD ðEF þ EÞ ρS ðEF qV þ EÞρT ðEF þ EÞjMj2 dE;
ℏ ∞
ð5:9Þ
where fD are the Fermi–Dirac distribution functions for the electrons in the sample and
tip, and ρS and ρT are the density of states in the sample and tip, respectively. M is the
transition probability matrix element that governs the probability an electron will tunnel
from a state in the STM tip to the sample or vice versa. Bardeen argued that this matrix
element can be assumed approximately constant for many relevant tunneling conditions.
At low temperatures the tunneling current can be expressed as
ð qV
I∝ ρS ðEF qV þ EÞ ρT ðEF þ EÞ dE; ð5:10Þ
0
which is the convolution of the tip and sample density of states over the energy range
determined by the voltage applied between the probe and sample. For metal probe tips
and for small voltage biases, it is often reasonable to approximate the STM tip density of
states as constant. Hence the current is found to be proportional to the sample density of
states summed over the voltage bias window. As the probe tip can achieve sub-atomic
resolution, the tunneling current can be directly related to the local density of states in a
sample.
Scanning tunneling microscopies are extremely powerful methods for the character-
ization of nanowire structures. The ability to resolve atomic positions allows a determi-
nation of the faceting of semiconductor nanowire surfaces allowing the deduction of the
crystal orientation along a wire’s long axis. And as can be anticipated from the preceding
discussion, the onset of current peaks when scanning with forward and reverse voltage
biases results in large current onsets that are signatures of the valence and conduction
band edges allowing for a direct determination of the band gap energy [30]. Using this
technique, a study of silicon nanowires with diameters in the 1 to 7 nm range with the
native oxide removed and the surface subsequently re-passivated with hydrogen [31]
was performed. Using scanning tunneling techniques, the surfaces of grown nanowires
were imaged and the surface facets and nanowire orientations determined. The band
gaps for the materials were determined with the 7 nm wires having essentially a bulk
silicon value with a band gap energy of 1.1 eV, increasing due to quantum confinement
monotonically up to 3.5 eV for 1.3 nm diameter nanowires. The measurements are
consistent with theoretical expectations for the confinement effect. In addition to
obtaining structural and electronic information, the stability of the surfaces was also
investigated by performing the measurements under vacuum and in atmosphere over
time, suggesting that the surface chemistry of the nanowires can be more stable
in atmosphere relative to similarly treated planar silicon surfaces.
5.4.4 Angle resolved photo-emission spectroscopy

To go beyond determining band gap energies and limited additional information such as
if a band gap is direct or indirect requires a technique that can simultaneously determine
the energy and momentum change of an excited electron or hole during a photo-
transition. A method that allows mapping of the energy dispersion for a given crystal
orientation is angle resolved photo-emission spectroscopy (ARPES). The photoelectric
effect is a well-known technique for determining the work function of material by
measuring the energy of photons incident to the surface at which the onset of photo-
emitted electrons is observed. By measuring both the kinetic energy and angular
distribution of photo-emitted electrons from a sample, the energy and momentum of
electrons propagating within a sample can be deduced, and hence can be used to infer a
material’s electronic band structure.
Light incident on a sample can photo-excite electrons, some of which may gain
enough energy that electrons can travel to the surface and escape. At the threshold for
this process, the emitted electron kinetic energy is given by
EKE ¼ hν Φ; ð5:11Þ
where EKE is the electron kinetic energy, hν is the incident photon energy, and Φ is the
material’s work function. This is the maximum kinetic energy for a photo-emitted
electron for a given incident photon energy. If an electron is excited from a lower
bound state, the kinetic energy of the emitted electron will be given by
EKE ¼ hν Φ jEB j; ð5:12Þ
where EB is the bound state energy of the electron in the solid referenced to the Fermi
energy. Momentum conservation requires that
ℏ~
k hν ¼ ℏ~
k f ℏ~
k i; ð5:13Þ
where ℏ~ k hν is the incident photon momentum, ℏ~ k f is the photo-emitted electron’s or

final momentum, and ℏ~ k i is the momentum of the electron in the sample or initial
momentum. Hence if the photo-emitted electron’s kinetic energy and momentum can be
measured, the energy dispersion of single electrons in a solid can be determined. The
equations describe photo-emission from valence states, assumptions can be made
regarding the nature of conduction states and the method can be extended to describe
unoccupied bands. For a more accurate determination of conduction band states, inverse
photo-emission spectra can be applied whereby electron attachment processes are
studied.
The experimental configuration for an ARPES measurement [32] is shown in
Fig. 5.11. A beam of monochromatized light is introduced incident upon a material
entrance
slit
monochromator
broad frequency
light source
exit
slit
hemispherical
analyzer
electron
lens
sample
2D detector
Figure 5.11 Schematic for an angle resolved photo-emission spectroscopy measurement. Note that the solid
lines leading to the sample from the light source indicate photons, whereas the lines leaving the
sample denote photo-emitted electrons. Electrons emitted by the photo-electric effect are guided
by an electrostatic lens and enter a hemispherical energy analyzer. The measurement allows for a
determination of the energies and momenta of emitted electrons and this information is sufficient
to build a picture of a material’s band structure.
sample. Most ARPES measurements are performed in the vacuum ultraviolet spectrum
(photon energies of approximately 6–124 eV) and hence the most common light sources
used are synchrotron radiation. High-quality, crystalline materials carefully aligned to
the incident photon beam along a chosen symmetry axis are required for characterization
of the dispersion. The incident light is of sufficient energy to photo-excite electrons and
those with sufficient kinetic energy can escape from the surface in directions governed
by momentum conservation and symmetry. An electron lens is used to collect emitted
electrons at a given solid angle relative to the sample and to focus the electrons onto a
hemispherical analyzer. The analyzer acts as a filter for electrons of a given kinetic
energy by holding plates of a hemispherical capacitor at a constant voltage allowing only
electrons within a narrow range of kinetic energies to traverse between the plates and
onto a two-dimensional electron detector situated at the exit of the kinetic energy
analyzer.
Having determined the kinetic energy of the emitted electrons, the magnitude of the
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
emitted electrons’ momentum p ¼ ℏkF ¼ 2mEKE is also known. The experiments are
designed to allow the azimuthal φ and polar ϑ angles of the detector with respect to the
sample to be varied, allowing the components of the electron momentum to be
determined:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2mEKE sin ϑ cos φ;
ℏkx ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ℏky ¼ p2mE KE sin ϑ sin φ;
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð5:14Þ
ℏkz ¼ 2mEKE cos φ:
Given these relations and the energy and momentum conservation laws, Eqs. (5.12) and
(5.13) allow for the determination of both the binding energy and crystal momentum of
electrons in a solid sample yielding electron dispersion relationships. By selecting
different crystal orientations to align with the incoming light beam, the energy band
diagram throughout the Brillouin zone can be resolved.
The application of ARPES to nanowire structures is in its infancy. There are sig-
nificant experimental difficulties associated with measurement of arrays of nanowires,
signal strength and background signals, adsorption depths, and the fact that surface
emission is a 3D problem in nanowires. However, the information that ARPES can
potentially provide is valuable for understanding how nanowire electronic structures
vary with confinement dimensions. Although it can be tedious and difficult to determine
electronic structures throughout a Brillouin zone from a set of samples, having accurate
experimental data at key values such as in the vicinity of band maxima and minima in
energy ranges close to the Fermi level to validate and calibrate theoretical calculations is
anticipated to provide a valuable contribution for development of new technologies
using nanowires, once experimental challenges are overcome.
5.5 Theoretical determination of electronic structure
Modern electronic structure methods can complement experimental determination of

band structures for solids and low-dimensional systems. A combined experimental and
theoretical study of a material’s electronic properties and band structures can lead to a
comprehensive knowledge of both macroscopic and microscopic behavior and
responses of materials to external probes such as light, pressure, voltage, and heat.
Theoretical electronic structure methods also allow the changes in a material’s proper-
ties to be determined as physical dimensions are scaled. To complement the introduc-
tion of experimental methods that can determine electronic structure properties, this
section provides an overview of theoretical means to study many-electron systems.
Computation of material properties using the laws of quantum mechanics invariably
involves making simplifying assumptions and approximations to reduce the overall
time needed to complete a calculation. Several of the more common theoretical
approximations are described, as well as limitations inherent in the approximations
are presented.
A valuable principle that underpins many of the theoretical treatments of many-
electron systems is the variational theorem. The principle is a powerful statement and
allows for the exact solution of a problem by considering arbitrary variations Ψtrial ¼
Ψ0 þ δΨ about an exact solution Ψ0 . It can be shown that a reasonable trial wave
function will satisfy the following relationship:
ð ð
dτ Ψtrial ðτÞH Ψtrial ðτÞ= dτ Ψtrial ðτÞΨtrial ðτÞ ≥ E0 ; ð5:15Þ
where E0 is the exact energy. In Eq. (5.15), τ represents all relevant degrees of freedom in
a wave function such as spatial coordinates and spin. The variational principle leads to
assessment of the quality of various approximations and leads to equations to determine
approximate solutions that are accessible by computation.
5.5.1 Quantum many-body Coulomb problems

Up to this point, treatment of electron energies has been from a single-electron approx-
imation in which electrons are assumed to move under the influence of a fixed, external
potential: the motion of an individual electron in no way alters the value of the potential
energy governing the solution of the Schrödinger equation. Clearly this is an approx-
imation as the potential energy must arise from the presence of other electrons and
nuclei. The motion of an electron will couple back to the other particles thereby
influencing the potential energy each electron “sees.” The quantum mechanics of the
mutual interactions of many electrons and nuclei is one example of a quantum
many-body problem.
The non-relativistic Coulomb Schrödinger equation for the hydrogen atom can be
written
h i
TN þ Te þ Uð~re; ~ re; ~
R N Þ Ψð~ r e; ~
R N Þ ¼ EΨð~ R N Þ; ð5:16Þ
where the total electronic and nuclear energy is E; the kinetic energy operators are
TN ¼ ½ℏ2 =2MN ∇ ~~2 and Te ¼ ½ℏ2 =2me ∇
RN
~ 2 for the nucleus of mass MN and position
~re
~
R N , and electron of mass me and position~
r e , respectively. The two-body equation for the
hydrogen atom displays important characteristics of quantum many-body Coulomb
problems: the system’s total kinetic energy operator is the sum of the individual
one-particle kinetic energies
Xno: of particles
Ttotal ¼ i¼1
Ti ; ð5:17Þ
and the total potential energy operator is given by the two-body Coulomb potential
governing the pair-wise interactions between the negatively charged electron and
the positively charged nucleus, in general for an arbitrary number of charged
particles
Xno: of particles Xno: of particles
Utotal ¼ i¼1 j>1
Uij : ð5:18Þ
Neutral atoms consist of a nucleus with a positive charge Z and number of electrons
Ne ¼ Z, where Z is the atomic number. Using the above prescription for writing the
Hamiltonian operator, the energy operator for an atom is
XNe X Ne
H ¼ ½ℏ2 =2MN ∇
~~2
R i¼1
½ℏ2 =2me ∇
~2 þ
~
ri i¼1
ri; ~
Uen ð~ RNÞ
N
XNe XNe
þ i¼1 j>i
Uee ð~ r j Þ;
r i ;~ ð5:19Þ
where~ r i denotes the ith electron and the potential energy terms are given by the Coulomb
interaction between the nucleus with all electrons and between all pairs of electrons,
respectively. Explicitly, the electron–nucleus Coulomb interactions are given by
Zq2
ri; ~
Uen ð~ RNÞ ¼ ; ð5:20Þ
4πε0 j~
R N ~
r ij
where the interaction is negative, indicating that it is attractive, and ε0 is the permittivity
of free space. The electron–electron interactions are given by
q2
Uee ð~ rjÞ ¼ þ
r i ;~ ð5:21Þ
4πε0 j~
r i ~
r j j;
where the interaction between the ith and jth electrons is positive as their interaction is
repulsive. It is straightforward to extend the Hamiltonian operator to the case of
molecular systems by allowing for multiple atoms:
X NN h i XNe h 2 i X NN X NN
H ¼ A¼1 ℏ2 =2MA ∇ ~~2
R
ℏ =2m e
~2 þ
∇~
r U ð~ RA; ~RBÞ
i¼1 A i A¼1 B>A nn
X Ne X NN X Ne X Ne
þ i¼1 A¼1
ri; ~
Ue n ð~ RAÞ þ i¼1 j>i
Uee ð~ r j Þ;
r i ;~ ð5:22Þ
with NN nuclear positions labeled by the indices A; B. The explicit form for the Coulomb
interaction between two nuclei is
2
ZA ZB q
Unn ð~
RA; ~
RBÞ ¼ þ ; ð5:23Þ
4πϵ 0 j~
RA ~
RBj
and since the nuclei are both positively charged, the interaction is repulsive. For a solid,
the Hamiltonian Eq. (5.22) is extended to an infinite set of atoms. Using the symmetry of a
crystal applied to the wave function, the many-body problem for an infinite set of atoms
can be replaced by a Hamiltonian defined in a Brillouin zone with an infinite number of
k-points. It is the latter form that is used in electronic structure calculations with periodic
boundary conditions, along with further approximations as required to reduce the com-
plexity of the problem. The Schrödinger equation can be expressed concisely as

HΨ f~ r i g; f~
R A g ¼ ET Ψ f~ r i g; f~
RAg ; ð5:24Þ
where f~r i g and f~

R A g denote the set of 3Ne and 3NN spatial electronic and nuclear
degrees of freedom and ET is the total energy for the system of interacting electrons and
nuclei described by the many-body wave function Ψ. Analytical solutions for quantum
mechanical many-body problems interacting through two-body Coulomb potential have
not been found. Hence much of the effort in solving problems in atomic, molecular, and
solid state physics focus on reducing the number of degrees of freedom that need to be
explicitly treated and to introduce simplifying physical approximations and efficient
methods for numerical solutions. The need to reduce the degrees of freedom in quantum
Coulomb problems was recognized early during the development of quantum mechanics
and the Born–Oppenheimer approximation was formulated to separate the electronic
and nuclear degrees of freedom [33]. The approximation is motivated by the fact that the
ratio of the mass of a proton to that of an electron is roughly 1836:1. Hence the time
scales governing the motion of the nuclei are expected to be much longer than that of the
electrons, suggesting that the kinetic energy of the nuclei can be decoupled from the
electronic degrees of freedom as a first approximation. This simple physical argument
suggests the separation of the nuclear and electronic degrees of freedom in the many-
body wave function as

Ψ f~ r i g; f~ r i g; f~
R A g ≈ Ψe f~ R A g ΦN f~
RAg : ð5:25Þ
It can be shown that, under appropriate conditions, a Schrödinger equation can be

defined to treat the position of the nuclei as “fixed,” or what is sometimes referred to as
the clamped atom approximation, and this is given by
h XN XNN XNN XNe XNN
i¼1 ½ℏ2 = 2me ∇ ~2 þ U ð~ RA; ~ r ;~
e
~ri A¼1 B>A nn
RBÞ þ i¼1
U ð~
A¼1 en i
RAÞ
XNe XNe i
þ U ee ð~
r i ;~
r j Þ Ψe f~
r i g; f~R A g ¼ E e f~R A g Ψ e f~
r i g; f~R A g ; ð5:26Þ
i¼1 j>i
where Ee denotes the total electronic energy plus nuclear–nuclear repulsions. Equation
(5.26) is known as the electronic Schrödinger equation and it should be noted that the
nuclear degrees of freedom are fixed, and hence act as scalar quantities as they are
not operators. The attractive electron–nuclei potential function Uen ð~ri; ~
R A Þ becomes a
one-electron operator and the nuclear–nuclear repulsion Unn ð~ RA; ~
R B Þ terms are scalars
and can simply be added to the solution of the equation at the end of the calculation. The
nuclear degrees of freedom act as parameters to the eigenvalues and eigenfunctions
within the Born–Oppenheimer approximation to the electronic energy. The solution of
the eigenvalue problem leads to an effective equation for the quantum mechanical
behavior of the nuclei:
h XN i
A¼1 ½ℏ2 =2MA ∇ ~~2 þ Ee f~
N
R A g ΦN f~R A g ¼ EBO Φ N f ~
R A g ; ð5:27Þ
R A
where EBO is the Born–Oppenheimer approximation to the totalenergy including the

nuclear kinetic energy. Note that the electronic energy Ee f~
R A g serves the role of a
potential energy for the nuclei. Hence vibrational and phonon spectra can be obtained
through second-order differentials with respect to the atomic positions (nuclear coordi-
nates) of the electronic energy at local minima leading to determination of “force
constants.” The electronic energy defines a potential energy surface (PES) as a function
of the atom positions f~R A g for a molecule or solid, with minima on the PES determining
stable configurations.
Although motivated by the ratio of the mass of the proton to the electron, if this was
the only condition for the validity of the Born–Oppenheimer approximation Eq. (5.27)
would be a good approximation in all circumstances. However, this is not the case. For
the approximation to be valid, the following conditions must also hold:

∂=∂~R A Ψe f~ r i g; f~
R A g ≈ 0; ∂=∂~R A ΦN f~
R A g ≈ 0: ð5:28Þ
Of course, what is meant by “approximately zero” defines the quality of the approx-
imation. In general, for most electronic structure calculations the Born–Oppenheimer
approximation is accurate if the kinetic energy of the nuclear degrees of freedom (i.e. the
motion of the atoms) is small relative to the kinetic energies of the electrons. There are
circumstances where the above terms are not negligible, and their proper treatment must
be addressed as for chemical reactions involving coupling between different many-
electron PESs and high-energy molecular scattering problems.
Measurements on materials systems are seldom concerned with total energies, but
determine differences in system energies after absorption/emission of photons, or
electrons, or changes in energy and momentum that can occur during scattering pro-
cesses. Defining the total electronic energy of a system of Ne electrons as EðNe Þ; the
energy to remove an electron or the ionization potential can be defined as
EIP ¼ EðNe 1Þ EðNe Þ; ð5:29Þ
similarly an electron attachment process yields the electron affinity as
EEA ¼ EðNe þ 1Þ EðNe Þ; ð5:30Þ
and an electronic excitation is the difference in energy between the initial and final N-
electron states,
E ¼ E ðNe Þ EðNe Þ: ð5:31Þ
From the many-electron states, excitations for single electrons and their properties can
be defined. The excitations and electron attachment and removal energies can often be
described as “quasi-particles.” These are not free electrons but electrons that are
“dressed” through the many-body interactions in the system. In many cases the quasi-
particles can be treated as solutions to an effective Hamiltonian energy operator, but due
to the interactions with the system these particles are characterized by an energy broad-
ening or resonance that results in a finite particle lifetime.
Although the Hamiltonian operators for Coulomb systems are straightforward to
write down, they have proven to be difficult to solve even using numerical methods.
The difficulty in solving quantum many-body terms can be traced back to the form of
the Coulomb interaction q2 =4πε0 j~ r j j. This form of potential energy does not allow
r i ~
for a separation of variables when attempting solution to quantum Coulomb problems,
hence for example in a two-electron problem the wave function is not separable:
H Ψð~ r 2 Þ ≠ H f ð~
r 1 ;~ r 1 Þgð~
r 2 Þ: ð5:32Þ
Nevertheless, making such an ansatz is a useful approximate method of proceeding and

will serve as the basis for many of the subsequent methods to be discussed that have been
devised to provide approximate solutions to quantum many-body problems: most
approximate solutions to the quantum many-body Coulomb problem rely on a single-
particle picture which is realized mathematically by factorizing a many-body wave
function into the product of functions of a single variable. Finally, it is noted that the
solution of the many-electron Hamiltonian, and therefore to obtain all electronic proper-
ties of a molecular or solid state system, is the ultimate goal of electronic structure
theory.
5.5.2 Self-consistent field theory

Following the introduction of quantum mechanics in its modern form during the years
1925–26 [34,35,36], Hartree introduced a procedure for the approximate solution of
many-electron atomic problems [37]. Hartree’s method is based upon Born’s interpreta-
tion of the square of the wave function as the probability density of finding a particle
within a region
rÞ ¼ qψ ð~
ρð~ rÞψð~
rÞ; ð5:33Þ
and the form for the classical potential energy for a charge distribution
ð
UH ð~rÞ ¼ q ρð~r 0 Þ=½4πε0 j~ r 0 jd 3 r0 ;
r ~ ð5:34Þ
where the charge density in the following discussion is for the Ne 1 “other” electrons
interacting with a given electron. This term is called the Hartree potential. Note that the
term Hartree potential is also used to describe the electrostatic potential arising from all
Ne electrons and the specific meaning must be applied within the appropriate context.
The Schrödinger equation for an electron moving in the potential field of the Ne 1
other electrons and the electrostatic potential arising from the atomic nuclei UN ð~ rÞ
nucleus can be written as
h i
½ℏ2 =2me ∇
~ 2 þ UN ð~
~
r rÞ þ U H rÞ
ð~ rÞ ¼ Eψð~
ψð~ rÞ; ð5:35Þ
where UN ð~rÞ is the potential of the single electron in the Coulomb field from all nuclei.
This is an approximation for a single electron of energy E moving in the electrostatic
potential of all other electrons and fixed nuclei in a molecule or a solid. As presented
there are three clear weaknesses in Eq. (5.35). The first is that to determine the
potential in which an electron moves requires knowledge of the charge distributions

for all the other electrons, and the second is that a frozen charge distribution for all
“other” electrons does not allow the “other” electrons to react to the charge distribu-
tion that emerges from the solution of the eigenvalue equation. Third, the potential is
different for each electron, hence the single-electron states are not eigenfunctions of
the same Hamiltonian operator and hence will not be mutually orthogonal in this
approximation.
To overcome the first two problems, Hartree proposed the self-consistent field
(SCF) approach for solution of the effective many-electron Schrödinger equation.
The SCF method allows for the charge distributions of all the electrons in an atom to
re-arrange in a “self-consistent” manner by refining the electronic wave functions and
the Hartree potential in an iterative way. To begin an SCF calculation, an initial guess
is made for each of the individual single-electron wave functions. For simplicity
consider an atomic problem. The initial guess could be hydrogen-like wave functions
scaled in a manner appropriate for the atom being studied, or another initial guess
could result from calculations on a related atomic system. Assuming the availability of
a reasonable initial guess, the contribution to the Hartree potential from each electron
in the atom and for the electron charge cloud interacting with the nucleus is calculated.
For atomic systems in the absence of magnetic fields, the quantum numbers labeling
the electrons will be the principal quantum number, the angular momentum and spin
state α ¼ ðn; l; ms Þ collectively denoted by a single Greek letter, and the atomic levels
are occupied according to the Aufbau principle. The effective Schrödinger equation for
occupied electron states is solved holding the potential energy due to the other electrons
fixed
hX i 0 0

H β≠α
ψ β ψ β ψα ð~
rÞ ¼ Eα ψa ð~
rÞ; ð5:36Þ
where in this form it is highlighted that the Hamiltonian is a function of the charge
density arising from all the other occupied electrons. The prime on the new wave
function indicates that the new set of wave functions is determined from a
Hamiltonian calculated using the wave functions from a previous iteration. It is seen
that the SCF equation is not a linear differential equation. Given the new set of wave
0
functions fψα g, a new potential energy is constructed for each electron using either the
new wave functions, or a “mixture” which is a weighted average of the old and new
solutions. The procedure is iterated until the new and previous wave functions agree to
within a prescribed tolerance. In this way, the electronic wave functions and potential
energies are brought into self-consistency. Without embarking on a mathematical dis-
cussion of the convergence properties for SCF procedures, it may be remarked that for
reasonable initial guesses, the procedure converges well for most atomic, molecular, and
solid state systems.
It can be shown that Hartree’s approximation follows from a variational principle
[38]. The many-electron wave function is written as a simple or Hartree product
Ψe ð~
r 1 ;~ r Ne Þ ¼ ∏Ni e ψαi ð~
r 2 ; . . . ;~ r i Þ: ð5:37Þ
The total energy is written as usual as an expectation value of the Hamiltonian

operator
ð

Ee ¼ ∏Ni e dri3 Ψe ð~
r 1 ;~ r Ne ÞH Ψe ð~
r 2 ; . . . ;~ r 1 ;~ r Ne Þ
r 2 ; . . . ;~
ð

= ∏Ni e dri3 Ψe ð~
r 1 ;~ r Ne ÞΨe ð~
r 2 ; . . . ;~ r 1 ;~ r Ne Þ;
r 2 ; . . . ;~ ð5:38Þ
with the denominator included to assure normalization. It is convenient to introduce the

Dirac “bra” and “ket” notation where the integration over space and implicitly over spin
is written concisely as
Ee ¼ 〈Ψe jHjΨe 〉=〈Ψe jΨe 〉: ð5:39Þ
The idea is to minimize the total electronic energy with respect to arbitrary variations
of the single-electron wave functions
δEe =δψαi ¼ 0: ð5:40Þ
Each variation leads to an equation of the form of Eq. (5.35) once the constraint of
orthonormality of the single-electron wave functions is introduced.
It is instructive to explicitly write the energy for a wave function being approximated
as a Hartree product. For appropriately normalized wave functions, the classical electro-
static or Hartree energy can be written for the example of an atom, in which for
convenience the nucleus is assumed to be situated at the origin, as
" #
X Ne ð ℏ2 2 Z
3
〈Ψe jHjΨe 〉 ¼ d r ψα ð~rÞ ∇ þ ψ ð~
rÞ
α 2me ~r 4πε0 j~ rj α
XNe XNe ð 0 q2
þ α d 3 r d 3 r ψα ð~ r0Þ
rÞψβ ð~ 0 ψ α ð~ r 0 Þ:
rÞψβ ð~ ð5:41Þ
α<β 4πε0 j~
r ~
rj
The first summation of the right-hand side is over a one-electron operator in the square
brackets that is denoted h1 and the second term is over a two-electron operator, the
Coulomb interaction, which is written simply as v2 . Dirac notation is introduced for the
one-electron terms as
ð " #
2 2
ℏ Zq
〈αjh1 jα〉 ¼ d 3 r ψα ð~
rÞ ∇2 þ ψ ð~
rÞ; ð5:42Þ
2me ~r 4πε0 j~ rj α
and for the two-electron terms the notation is
ð
q2
〈αβjv2 jαβ〉 ¼ d 3 r d 3 r0 ψα ð~ r0Þ
rÞψβ ð~ ψ ð~ r 0 Þ:
4πε0 j~ r 0j α
r ~
The total energy can be rewritten as

XNe XNe XNe
〈Ψe jHjΨe 〉 ¼ α
〈αjh1 jα〉 þ α α<β
〈αβjv2 jαβ〉: ð5:44Þ
The Hartree single-electron energy can be expressed as

X Ne
Eα ¼ 〈αjh1 jα〉 þ β≠α
〈αβjv2 jαβ〉: ð5:45Þ
The sum of the single-particle energies is not equal to the energy of the many-
electron state due to the over-counting of two-body terms that occurs in a sum over
eigenvalues.
The Pauli exclusion principle is introduced in an ad hoc manner in non-relativistic
quantum mechanics: two electrons are simply forbidden to occupy a state with the same
set of quantum numbers. This simple rule has far-reaching implications. Electrons are
fermions and, unlike bosons, are not able to condense into a single low-energy state; the
appropriate quantum statistics for fermions is the Fermi–Dirac distribution. It should be
noted that the fermion nature of particles can be attributed to the fact that the classical
limit of a quantum theory of fermions is essentially a particle theory, whereas the
classical limits for quantum theories of bosons governed by Bose–Einstein statistics
are classical field theories. Although both fermions and bosons display the well-known
quantum phenomenon of wave-particle duality, it should be held in mind that the correct
behavior, either particle or wave, in the classical limit is preserved by the imposition of
quantum statistics.
An equivalent expression of the Pauli exclusion principle for electrons is obtained by
requiring the many-electron wave function to be anti-symmetric under exchange of
electrons:
Ψe ð~
r 1 ;~ r Ne Þ ¼ Ψe ð~
r 2 ; . . . ;~ r 2 ;~ r Ne Þ:
r 1 ; . . . ;~ ð5:46Þ
Dirac [39] and Slater [40] suggested a simple function that exhibits the correct anti-
symmetric behavior under exchange of particle labels:
X
Ψe ð~
r 1 ;~ r Ne Þ ¼
r 2 ; . . . ;~ perm
ð1Þ℘ ∏Ni e ψαi ð~
r i Þ; ð5:47Þ
where the symbol ℘ expresses the order of a permutation of the single-electron wave
functions. A more transparent way of writing Eq. (5.47) is as a determinant of the single-
particle wave functions. A normalized many-body wave function so constructed is
referred to as a Slater determinant:

ψα ð~ r1 Þ ψβ ð~ r1 Þ ψ ð~ r1 Þ

1 α 2 ψ ð ~r Þ ψ ð~
β r2 Þ ψ ð~ r2 Þ

Ce ð~
r1 ;~ rNe Þ ¼ pffiffiffiffiffiffiffi
r2 ; . . . ;~ .. .. .. .. : 5:48
Ne ! . . . .

ψ ð~
r
α Ne Þ ψ β ~
ð r Ne Þ ψ ð~r Ne Þ
The Slater determinant is obtained by applying the anti-symmetrizing operator to a

Hartree product and normalizing. Just as for the Hartree approximation, a Slater
determinant relies on approximating a many-electron wave function by separation
of variables in the electronic positions. Hence the Slater determinant cannot be an
exact solution to a many-electron problem. The superiority of approximating the
wave function by a Slater determinant as opposed to a Hartree product is that it
displays the correct fermion anti-symmetry properties. It will be shown that the
Slater determinant shares with the Hartree product that it too introduces a single-
particle picture.
Using the many-electron Hamiltonian, it is straightforward to calculate the
energy of a system whose wave function is being approximated by a Slater
determinant
X Ne XNe XNe
Ee ¼ α
〈αjh1 jα〉 þ α β>α
½〈αβjv2 jαβ〉 〈αβjv2 jβα〉: ð5:49Þ
The anti-symmetry has introduced a notable difference as compared to the

corresponding expression arising from the Hartree approximation: the third sum-
mation includes exchange terms arising from the anti-symmetry of the wave
function. The exchange terms are purely quantum mechanical in nature and result
from the fact that electrons are indistinguishable particles. Within the Hartree
approximation, a set of quantum numbers are attached to an electron label. The
Slater determinant removes this limitation by considering all possible permutations
of electrons assigned to all quantum numbers labeling the various states while
respecting the anti-symmetry constraint required by the Pauli principle. The result
is the exchange terms. The origin of the name exchange terms is perhaps best seen
explicitly. A Coulomb two-body term is
ð
q2
〈αβjvjαβ〉 ¼ d 3 r d 3 r0 ψα ð~ r0Þ
rÞψβ ð~ ψ ð~ r 0 Þ;
4πε0 j~ r 0j α
r ~
whereas the corresponding exchange term is written

ð
q2
〈αβjvjβα〉 ¼ d 3 r d 3 r0 ψα ð~ r0Þ
rÞψβ ð~ ψ ð~ r 0 Þ:
rÞψα ð~ ð5:51Þ
4πε0 j~ r 0j β
r ~
The difference in the two terms is shown in the diagram of Fig. 5.12. In Fig. 5.12(a), a
Coulomb or Hartree diagram is depicted, and these terms are also sometimes referred to
as direct interactions. The electrons interact with each other through the Coulomb
α β α β
Figure 5.12 Diagrammatic representation of (a) Coulomb and (b) exchange integrals. The circles represent
electrons propagating and interacting via a Coulomb interaction given by the “wavy” line. Note
the exchange terms are only non-zero when the states α and β have parallel spins.
potential shown as a “wavy” line. If the coordinate of the electron wave functions under
the integral are matched, the states labeled by either α or β remain unchanged and the
diagram corresponds to Eq. (5.50). The diagram in Fig. 5.12(b) depicts an exchange
integral. If the coordinates under the integral are matched, it is seen that the states of the
electrons are “exchanged,” i.e. α↔β. This is purely a quantum mechanical effect arising
from indistinguishability and Fermi–Dirac statistics. The Coulomb interaction is
spin independent; it follows that the states of electrons with different spins cannot
be exchanged in the single Slater determinant approximation. Hence a spin con-
vention is introduced within the two-electron integrals. If performing the integra-
tion for a direct term, the single-electron wave functions under the integral with
the same spatial coordinate will also have the same quantum state and thus there
will be no change in the electron’s spin. Within an exchange integral, integrating
over space attaches two orbital terms with different quantum states to the same
spatial coordinate. The spin convention states that an integral is zero if the
integration over a spatial coordinate connects two orbitals or states of different
spin. Hence the integral Eq. (5.51) depicted graphically in Fig. 5.12(b) will be non-
zero only when α and β have parallel spins.
The total electronic energy in a single Slater determinant can be rewritten as
XNe X Ne X Ne
ESD ¼ α
〈αjh1 jα〉 þ 1=2 α β
½〈αβjv2 jαβ〉 〈αβjv2 jβα〉; ð5:52Þ
where the restriction on the two-electron summation is relaxed, but a factor of 1=2 is
introduced with respect to Eq. (5.49) to eliminate over-counting of integrals arising from
the two-body nature of the Coulomb interaction and making use of the fact that
〈αβjv2 jαβ〉 ¼ 〈βαjv2 jβα〉 and 〈αβjv2 jβα〉 ¼ 〈βαjv2 jαβ〉. Another key point about the
form of Eq. (5.52) is that when α ¼ β, the direct and exchange integrals are equal and
exactly cancel. The interaction of an electron with itself is unphysical and is termed the
self-interaction energy. A key feature of the Hartree–Fock approximation to be intro-
duced next is that self-energy interactions cancels exactly.
Given the energy of a system described by a Slater determinant as an approximate
wave function, the question becomes: how to solve for the best set of single-particle
wave functions or orbitals which minimize the total energy? A procedure of minimizing
the total energy with respect to the single-particle orbitals by applying the variational
principle is again followed. The constraint that the orbitals are normalized and ortho-
gonal is introduced:
ð
d 3 r ψα ð~
rÞψβ ð~
rÞ ¼ δαβ : ð5:53Þ
Equation (5.53) is imposed by adding a set of Lagrangian multipliers to the variational

procedure for the total energy ESD in a Slater determinant:
X ð
3
δ=δψα ESD αβ
Eαβ d rψα ð~rÞψβ ð~
rÞ δαβ ¼ 0: ð5:54Þ
Variation with respect to the single-electron wave functions leads to a set of equations that
define the Hartree–Fock approximation. It can be shown that the matrix of Lagrangian
multipliers is a Hermitian matrix and can therefore be brought into diagonal form as
Xocc ð q2
h1 ψα ð~
rÞþ d 3 r0 r 0 Þψβ ð~
ψ ð~ r 0 Þψα ð~
rÞ
β 4πε0 j~ r0j β
r ~
Xocc ð q2
d 3 r0 r 0 Þψα ð~
ψ ð~ rÞ ¼ EαHF ψα ð~
r 0 Þψβ ð~ rÞ; ð5:55Þ
β 4πε0 j~ r 0j β
r ~
where the summations are restricted to electron states that are occupied in the Slater
determinant. At first glance, the equations do not appear to be eigenvalue equations due
0
to the third term on the left-hand side. However, introducing an operator Pð~ r Þ which
r↔~
exchanges the positions of two electrons allows the Hartree–Fock equations to be
written as
2 ð 0 0
Xocc
3 0 q2 ψβ ð~
r Þψβ ð~
rÞ
4 h1 þ d r 0
β 4πε0 j~
r ~
rj
ð 0 0 0 #
Xocc 0 q2 ψβ ð~
r ÞPð~ r Þψβ ð~
r↔~ rÞ
d3 r rÞ ¼ EαHF ψα ð~
ψα ð~ rÞ; ð5:56Þ
β 4πε0 j~ r0j
r ~
which is shorthand notation for Eq. (5.55). The Hartree–Fock eigenfunctions can be
made orthonormal.
The Lagrangian multipliers may be identified as single-particle energies. The physical
motivation for treating them in this way is due to a property known as Koopmans
theorem [41]. Consider the energy obtained from a Slater determinant constructed from
Ne orbitals and denote this energy EðNe Þ. A single electron is removed and the energy for
the Ne 1 electron system is calculated. Denote this energy as Eα ðNe 1Þ. Koopmans
showed that the ionization potential or energy required to remove a single electron from
state α is given by
EαHF ¼ Eα ðNe 1Þ EðNe Þ: ð5:57Þ
Energy differences between the approximate many-electron states allow for identifi-
cation of the Lagrangian multipliers as single particles or “quasi-particles.” Similar
relations hold for the electron affinities when adding electrons into unoccupied orbitals.
Koopmans’ interpretation, although useful conceptually, is flawed in that the same set of
orbitals must be used in the calculation of the ðNe 1Þ and Ne electron states. However,
in a physical system the remaining orbitals re-arrange upon ionization to account for the
change in charge introduced to a system. Hence the energy calculated through
Koopmans theorem overestimates the ionization potential and underestimates the elec-
tron affinity as it does not account for orbital relaxation or, perhaps more accurately,
reorganization in the ionized system [42].
The Hartree–Fock approximation has been widely applied in quantum chemistry and
solid state physics. It has shortcomings, but the errors introduced are well documented
and in most instances well understood. The Hartree–Fock approximation generally
serves as a low-order or “zeroth-order” approximation in many-body theories for
more accurate treatments of the electronic structure problem such as in the GW approx-
imation, many-body perturbation theory, coupled cluster, or configuration interaction
methods [43]. The Hartree–Fock method is still widely employed in practical calcula-
tions and as a reference point from which to gauge other calculations and as a theoretical
description from which much of the language of electronic structure theory is based. One
very useful definition is identification of the difference between the exact non-relativistic
energy for a system of electrons and the energy calculated from the Hartree–Fock
approximation as
Ecorr ¼ Eexact EHF ; ð5:58Þ
and is referred to as the electron correlation energy. Much of the modern work in
electronic structure theory is focused on calculation of the correlation energy accurately
but within a tractable computational time. To determine accurate electronic band
structures, treatment of the electron correlation energy is required.
For a homogeneous electron gas it can be shown that the majority of the correlation
energy can be attributed to electrons sharing the same quantum numbers except for their
spins [44]. This fact can be anticipated from the Hartree–Fock equations: the Coulomb
terms include interactions with electrons of all spins whereas the exchange terms are
non-zero only for electrons with parallel spins. There is an asymmetry in the treatment of
electrons with parallel and anti-parallel spins inherent in the Hartree–Fock approxima-
tion. Electrons of parallel spin can interact through the “exchange charge density,” which
acts to reduce the charge density in the vicinity of an electron. This behavior gives rise to
a phenomenon known as the Fermi hole. In this sense, distributions of electrons with
parallel spin are more “correlated” than electrons of anti-parallel spin. Improvement of
the interactions between electrons with anti-parallel spin requires explicit treatment of
the electron correlation energy.
It was noted in the early days of quantum mechanics that the wave function, a function
of all 3Ne electronic coordinates, seemed to contain much more information than needed
for the solution of the quantum mechanics of systems interacting via two-body poten-
tials. The Thomas–Fermi model is an attempt to write the Hartree energy in Eq. (5.41)
solely as a function of the electron density. It is straightforward to write the total

electrostatic energy of an Ne -electron system as
ð 0
1 3 3 0 q2 ρð~ rÞ
rÞρð~
EH ½ ρ ¼ d rd r 0 ; ð5:59Þ
2 4πε0 j~
r ~
rj
and likewise the total energy of an electron charge density interacting with the collective
potential arising from NN atomic nuclei is
XN ð Zq2 ρð~ rÞ
Eext ½ ρ ¼ N
d3r : ð5:60Þ
A 4πε0 j~
R A ~ rj
The potential in Eq. (5.60) is labeled as “ext” energy as it is due to the interaction of
electrons, not with other electrons, but with the fixed, external potential of the
“clamped” nuclei. The energies have been written explicitly as functionals of the total
electron density to highlight that the charge density is the only dependence.
The Thomas–Fermi model relies on approximating the electronic kinetic energy in
atoms by the known kinetic energy of a system of non-interacting electrons [45,46]. A
kinetic energy density may be defined as
ð
TKE ½ ρ ¼ d 3 r tKE ½ρ; ð5:61Þ
and can be obtained from applying the kinetic energy operator directly to free electron
wave function in three dimensions and relating the result to the charge density. The total
kinetic energy can be shown to be
ð
TKE ½ ρ ¼ CTF d 3 r ρ5=3 ð~
rÞ; ð5:62Þ
where CTF is a constant. The idea is to minimize the energy as a functional of the density
while maintaining a constant total number of particles. A Lagrangian multiplier μ is
introduced and variations with respect to the charge density are considered
ð
δ=δρ E½ ρ μ d 3 rρð~ rÞ Ne ¼ 0: ð5:63Þ
Unlike the Hartree and Hartree–Fock approximations, a single-electron Schrödinger

equation does not result. Rather an equation for the total charge density follows, which
can be written compactly as
δ=δρ E½ ρ ¼ μ: ð5:64Þ
The Lagrangian multiplier again enters the theory in a physical way – it is the chemical
potential for the charge distribution. The Thomas–Fermi model can be expressed as a
Poisson’s equation which is amenable to numerical solution. Although the
approximation had some success in expressing atomic properties solely in terms of the
electronic density, there are several severe limitations: the electronic shell structure of
atoms is not reflected in the charge density and, perhaps most severely, the approxima-
tion cannot be extended as it does not predict binding of atoms to form molecules. Aside
being of historical interest, the method highlights the motivation for the density func-
tional theory (DFT) formulation of electronic structure in which it can be mathemati-
cally shown that the total energy can be given exactly as a functional of the charge
density [47].
As noted, only having to find the charge density for many-electron problems is a great
simplification as it reduces the problem from having to solve for a many-electron wave
function (3Ne spatial degrees of freedom) to that of solving for the total charge density
(three spatial degrees of freedom) to determine the total electronic energy. This goal is
formally achieved in density functional theory. However, in practical calculations a set
of single-electron equations known as the Kohn–Sham equations [48] is introduced such
that when the charge densities of the individual electron solutions are summed, the exact
total charge density for the Ne electron system is obtained. These single-electron
equations are often taken to be “quasi-particles” for the interacting many-electron
system and their energies and eigenfunctions are often used to determine approximate
band structures for solids and lower dimensional systems such as nanowires. As will be
seen, the total electronic energy can be exactly expressed as a functional of the charge
density, but to solve for the energy requires an exchange-correlation functional whose
explicit form is unknown. This introduces a level of approximation into practical DFT
calculations. Furthermore, the single-particle energies in Kohn–Sham theory are a
theoretical tool to help arrive at the exact charge density and they are not “quasi-
particles” in the sense of providing approximations to differences in many-electron
energies, other than for the eigenvalue of the highest occupied state which can be shown
to give the first ionization potential in a metal. Nonetheless, their general interpretation
as excitation and ionization energies is widespread and can be a useful interpretation, if
the limitations to their use are borne in mind.
There are two basic tenets to DFT. The first of these is that for a system of interacting
electrons moving in an external potential Uext ð~ rÞ, the ground-state electronic density
ρð~rÞ uniquely determines the external potential up to an additive constant. The immedi-
ate implication is that the energy is fully determined up to the same constant. The second
is that if the total energy is a functional of the charge density, then variation of the energy
with respect to density will lead to the exact ground state energy. A functional of the
density for the total energy is written as
ð
E½ ρ ¼ FHK ½ ρ þ d 3 r Uext ð~ rÞ þ Unn ;
rÞρð~ ð5:65Þ
where the Hohenberg–Kohn universal functional FHK ½ρ is introduced and contains all
internal energies of the interacting electron system and Unn is the scalar nuclear–
nuclear Coulomb repulsion. In practice, approximate energy functionals which have
been constructed from studies of the many-electron problem accounting for the effects
of the Coulomb interactions, exchange, and correlation between electrons are used to
develop accurate approximations to FHK .
The universal exchange correlation functional is not specified in the theory and
remains unknown. Kohn and Sham subsequently introduced the idea of replacing the
original many-electron problem with an auxiliary system of non-interacting electrons
[48]. The Kohn–Sham approach enables approximations to be developed for an
exchange-correlation functional as the difference between the exact universal functional
and a functional consisting of the kinetic and electrostatic, or Hartree, potential terms:
" ð 0
#
1 3 3 0 q2 ρð~ rÞ
rÞρð~
EXC ½ ρ ¼ FHK ½ ρ TKE ½ ρ þ d r d r 0 : ð5:66Þ
2 4πε0 j~
r ~rj
Kohn and Sham made the assumption that the ground state density of an auxiliary
non-interacting set of electrons is approximately equal to that of the interacting system.
This leads to a set of soluble independent-particle equations in which all the many-
electron effects are partitioned into EXC ½ρ and that are known as the Kohn–Sham (KS)
equations. The KS auxiliary Hamiltonian contains a kinetic energy operator and an
effective potential UKS ð~rÞ given by
ℏ2 2
hKS ¼ ∇ þ UKS ð~
rÞ; ð5:67Þ
2me
where
UKS ð~
rÞ ¼ Uext ð~
rÞ þ UH ð~
rÞ þ UXC ð~
rÞ: ð5:68Þ
The first term is the external or Coulomb potential for the electrons excluding
electron–electron interactions, i.e. the interactions of the electrons with the charges of
the nuclei, and UH ð~
rÞ is the Hartree potential for all electrons. The last term on the right-
hand side is the exchange-correlation (XC) potential and is found from the variation of
the XC energy with respect to the density:
δEXC
UXC ð~
rÞ ¼ : ð5:69Þ
δρ
Solutions of the KS equation define a set of orbitals φα , with corresponding eigenva-

lues Eα . The ground state density corresponds to the lowest eigenvalues of the auxiliary
Hamiltonian and with one electron per spin orbital, the ground state density can be
written in terms of the eigenfunctions as
XNe
rÞ ¼
ρð~ α
rÞj2 :
jφα ð~ ð5:70Þ
Since the potentials are determined by the solutions of the KS equations through the total
densities, the eigenvalue problems must be solved self-consistently. The kinetic energy
takes the form
ð
ℏ2 XNe 3
TKS ¼ rÞ∇~2r φα ð~
d r φα ð~ rÞ: ð5:71Þ
2me α
Note that the kinetic energy is calculated from the set of fictitious Kohn–Sham electrons
and the error made in making this assumption is taken to be included into the XC
functional as an additional “correlation” effect. The total energy is obtained from
ð ð 0
1 q2 ρð~ rÞ
rÞρð~
E½ ρ ¼ TKS ½ ρ þ d 3 rUext ð~ rÞ þ d 3 rd 3 r0
rÞρð~ 0 þ EXC ½ ρ þ Unn : ð5:72Þ
2 4πε0 j~
r ~rj
Therefore, if the exact XC functional EXC ½ρ is known including corrections to the
kinetic energy term, then the exact ground state density and total energy of the true
many-electron system can be found. Unfortunately, the exact EXC ½ρ is not known but
approximate forms have been developed. The KS approximation to DFT provides in
many instances reasonable predictions for many-body ground state properties. A widely
used approximation is made by noting that in limited cases, solids can be treated as close
to the limit of a homogenous electron gas and within this limit, exchange and correlation
effects can be considered local in character. Hence, the XC energy can be written as an
integral over space of the product of density and XC energy per electron ϵ XC ½ ρ as
ð
EXC ½ ρ ¼ d 3 r ϵ XC ½ ρρð~
rÞ; ð5:73Þ
where ϵ XC ½ρ equals the XC energy per electron of a homogenous electron gas computed
using the local density about a point. This is the local density approximation (LDA) for
the XC functional. As a first approximation, LDA reproduces many measurable chemi-
cal properties accurately, especially if local variations in the density are small. There are
several different approximations to XC functionals such as generalized gradient approx-
imation (GGA) and hybrid functionals. The former rely on expansions about the LDA to
better describe inhomogeneity in the charge density while the latter functionals empiri-
cally mix in “exact” exchange to correct predictions against a measured physical
parameter such as the band gap energy for a specific semiconductor.
Due to ignorance of the exact XC functional, DFT suffers from a number of weak-
nesses which lead to systematic errors in the computation of physical properties. There
are two main sources of these limitations: self-interaction of electrons and a derivative
discontinuity in approximate XC functionals. Unlike in Hartree–Fock theory, the LDA
cancellation between the unphysical self-interaction term in the Hartree potential in Eq.
(5.66) which uses the total charge density and the exchange interaction is only approx-
imate. The spurious self-interactions can be partially corrected for in the LDA XC
functional. These self-interaction corrections (SIC) do not fully resolve the limitations
of approximate DFT and there remain elements of semi-empiricism to the corrected
calculations. Typically approximate DFT methods lead to an underestimation of band
gaps in semiconductors such as Si, Ge, and GaAs, and in many cases predict a small band
gap semiconductor to be metallic. Just as the Hartree–Fock approximation can serve as a
zeroth-order approximation to many-electron calculations, approximate DFT electron

energies and wave functions obtained from the Kohn–Sham procedure can be used as the
input to more accurate methods such as the GW approximation, which can be successful
in correcting band gap energies in semiconductors toward experimental values.
Approximate DFT theories are also poor at describing charge transfer at interfaces and
thus lead to poor predictions for band alignments in heterostructures. Unfortunately both
knowledge of the band gap energy due to confinement effects and the electronic proper-
ties of interfaces and contacts are important for the development of nanowire transistors.
Approximate DFT is a fruitful starting point for electronic structure investigations
of nanowires but in some instances empirical calibrations or additional work is required
to refine theoretical results to the point of being predictive or for direct comparison to
experiment.
5.5.3 Optimized single determinant theories

The Hartree–Fock approximation yields the lowest total energy for a many-electron
system described by a single determinant ansatz. In a similar vein, the Kohn–Sham
approximation yields the best electron density from a single determinant in the sense that
the sum of orbital densities in Eq. (5.70) is the same as would be obtained from a
determinant constructed with the Kohn–Sham orbitals – although calculating the energy
in a single Slater determinant consisting of Kohn–Sham orbitals as in Eq. (5.49) would
yield an energy higher than that obtained from a single Slater determinant composed of
Hartree–Fock orbitals as ensured by the variational principle. Hence the Hartree–Fock
approximation is the single determinant theory that minimizes the total energy and the
Kohn–Sham theory is the single determinant theory that provides the best charge
density.
A fundamental goal of the theoretical study of nanowire transistors is to achieve an
accurate treatment of the electronic structure of nanometer scale structures together with
the ability to describe charge transport. As discussed, Hartree–Fock theory predicts band
gaps that are too large whereas approximate density functional theories tend to predict
band gaps that are too low. Typically in charge transport problems these deficiencies
translate into electrical currents that are predicted to be too low from Hartree–Fock
theory and too large when obtained by using Kohn–Sham states as quasi-particle states
[49], often by an order of magnitude or more. This implies that the ability to describe the
ionization potentials and electron affinities that determine band gaps and electronega-
tivity accurately within single-electron theory, or single-determinant theory, is important
for the prediction of currents on nanometer length scales.
Single determinant theories constructed to optimize other properties in a many-
electron problem can be devised. Of particular relevance to predictions for nanowires
and other nanometer scale structures is the correlated independent particle model
developed from many-electron wave function considerations [50]. The model proceeds
by insisting that the principal ionization potentials (IPs) and electron affinities (EAs) are
described correctly in terms of a reference many-electron theory such as coupled cluster
theory. Theories such as coupled cluster theory are the most accurate, predictive
quantum mechanical methods for many-electron systems that exist and are based upon
explicit consideration of the intrinsic two-electron interactions. In most cases the
accuracy of a many-electron electrostatic Hamiltonian relies on the accuracy of the
description of the two-electron interactions. In the alternative approach of the correlated
independent particle model, the equations and properties from coupled cluster theory are
used to develop a single-electron Hamiltonian whose eigenvalues correspond to the
exact principal IPs and EAs, such that the electronegativity (IP-EA)/2 is correct. This
property not only corrects the band gaps for a material, but it is also the electronegativity
that controls charge transfer at heterostructure interfaces. Hence this “correlated” single
determinant method offers the opportunity to retain the computational advantages of
single-electron theory [51] while optimizing the quantities of interest for designing
nanowire technologies.
5.5.4 GW approximation
The correlated independent particle model highlights that in many applications, a good
approximation to quasi-particle excitations can be sufficient to describe important
physical properties. If an accurate description of a single electron interacting within a
many-electron environment can be defined and correctly give electron excitations to
define the band gaps, electron ionization potentials, and electron affinities to describe
electronegativity, many of the important properties needed to describe many-electron
systems for nanoelectronics applications then become available.
Quasi-particles can be defined for a weakly interacting system of particles and can be
used with appropriate conditions to describe the excitation, ionization, and electron
attachment spectra that emerge from a system of strongly interacting particles. A bare
electron inside a solid repels other electrons and becomes surrounded by a net positively
charged polarization cloud. If the correct conditions are met, the bare electrons and their
interactions can be described as quasi-particles interacting via a screened Coulomb
potential and their eigenenergies and eigenstates are solutions of an effective
Hamiltonian [52]. As the Hamiltonian can be non-Hermitian, quasi-particle energies
can be complex signifying that their lifetimes are finite, with the state lifetime inversely
proportional to the imaginary part of the complex eigenenergy. The finite lifetime arises
due to the residual interaction between quasi-particles and also potentially from the
boundary conditions applied to a system. The complex energy arises as a non-local,
energy dependent, non-Hermitian self-energy Σ that describes the exchange and correla-
tion interactions of a single electron in a many-electron system. The self-energy
describes the difference between a quasi-particle or “dressed” electron and a non-
interacting or “bare” electron. An equation governing the behavior of the quasi-particles
can be written with the aid of the self-energy as
" # ð
ℏ2 2
∇ þ VH ð~ rÞ þ Vext ð~
rÞ Φα ð~rÞ þ d 3 r0 Σð~ r 0 ; Ωα ÞΦα ð~
r;~ r 0 Þ ¼ Ωα Φα ð~
rÞ; ð5:74Þ
2me
where Ωα is a complex energy and Φα is a quasi-particle eigenfunction. The self-energy

can be related to a Green’s function G that describes the injection or removal of an
electron into a many-electron state and a screened interaction W that replaces the
electron–electron interactions to the self-energy by
ð
r 0 ; Ωα Þ ¼ i dΩ0 Gð~
r;~
Σð~ r 0 ; Ωα þ Ω0 ÞW ð~
r;~ r 0 ; Ω0 Þ;
r;~ ð5:75Þ
and this form of the self-energy is seen to be the origin of the name “the GW approx-
imation.” The propagation of particles and quasi-particles through space and time can be
described by a single-particle Green’s function G with more to be said about the use of
Green’s functions in Chapter 6. From G one can obtain the quasi-particle excitation
spectrum, life times, and expectation values of single-particle operators in the ground
state including the electron density and kinetic energy expectation values, and Green’s
functions can be related to the calculation of electronic currents. The screened interac-
tion describes the way the environment about electrons acts to screen the bare Coulomb
interaction and can be described with the use of the inverse dielectric function ε1 as
ð
W ð~ r 0 ; ΩÞ ¼ d 3 r″ε1 ð~
r;~ r;~
r ″; ΩÞvð~ r 0 Þ:
r ″;~ ð5:76Þ
Most of the effort in the GW approximation is in the theoretical determination and

calculation of the screened interaction. Practical implementations of the method do not
attempt to solve for W directly, but use physically motivated arguments to find the
contributions to the screening based on many-electron perturbation expansions.
Quasi-particle energies can be determined directly through solution of
Eq. (5.74). Just as the Hartree–Fock approximation can serve as a first- or
zeroth-order approximation to many-electron calculations, DFT in the LDA or
similar approximations can also provide a starting point for more accurate
methods such as the GW approximation. The resemblance between Eq. (5.74) and
the KS equations suggests a means for achieving improvements to LDA eigenvalues and
to enable their use as quasi-particle energies. Assuming the overlap between a Kohn–
Sham wave function φα and a quasi-particle state Φα is large 〈φα jΦα 〉ffi1 enables a first-
order perturbation correction to be applied, leading to the following approximation for
the GW energies:
Ωα ffi εα þ Z〈φα jΣðεα Þ UXC jφα 〉; ð5:77Þ
where the “quasi-particle weight Z” is given by

1
Z ¼ 1
∂Σα ðΩÞ
∂Ω
j Ω¼εα
: ð5:78Þ
Using the GW approximation corrections for the self-energy, band gaps in sp bonded
semiconductors can be improved systematically to be within a few percent of
experimental values [53]. For example, the fundamental energy band gap using quasi-
particle corrections for GaAs results in a value of 1.77 eV compared to an experimental
band gap of 1.52 eV at 0 K, whereas DFT/LDA predictions can result in values as low as
0.21 eV. The use of the GW approximation to correct energy level alignments between
molecular levels at metal electrodes has been explored in the context of correcting
current flow through one-dimensional systems and shown to be important to capture
corrections to align energy levels between materials, and thus enabling accurate predic-
tions of conductivity. The level of improvement for charge transport can be by an order
of magnitude or more relative to uncorrected conductivities obtained using energy levels
corrected by GW [54,55] compared to the use of approximate DFT/LDA or DFT/GGA
energy levels.
5.6 Bulk semiconductor band structures
Figure 5.13 shows a calculated band structure for silicon obtained from a density
functional theory (DFT) calculation in the local density approximation (LDA) – approx-
imate DFT theories typically underestimate the band gap for semiconductors.
Remarkably, the Kohn–Sham (KS) procedure with approximate exchange correlation
functionals can provide a reasonable description of semiconductor band structures by
interpreting the eigenvalues of the “fictitious” KS electrons as quasi-particles if the band
(a) 5 (b)
(001)
3
Energy (eV)
(100)
–1
–3
(010)
–5
L G X
Figure 5.13 (a) Energy band diagram for bulk silicon from an approximate DFT calculation. In the figure, the
band gap has been corrected to 1.1 eV by shifting all the conduction band states by a constant to
correct for the XC error. Other than this well-known deficiency associated with typical
approximations to DFT, the method leads to a good description of the conduction and valence
bands with reasonable estimates for electron and hole effective masses. The zero of energy is
referenced to the top of the valence band energy. The conduction band minimum occurs in the
direction of the X symmetry point and the indirect nature of the band gap is seen. Data courtesy of
Dr. L. Ansari. (b) Energy ellipsoids at the six equivalent conduction band minima in silicon located
along the ð100Þ and equivalent directions in reciprocal space. The band minima, corresponding to
the centers of the ellipsoids, are 85% of the way to the Brillouin-zone boundaries. The long axis of
an ellipsoid corresponds to the longitudinal effective mass of electrons in silicon of ml ¼ 0:92me
while the short axis corresponds to the transverse effective mass of mt ¼ 0:19me .
gap energy is empirically corrected. The correction of the band structures in this way is
sometimes referred to as the “scissors operator,” as the correction consists of adding a
constant energy shift to the unoccupied conduction states as though the band structure
had been “cut” in the energy gap and then conduction states shifted upwards in energy.
Approximate DFT methods can provide reasonable estimates for electron effective
masses, and in general these estimates are best when the conduction and valence
bands are not strongly interacting, such as can happen in direct semiconductors with
small energy band gaps. Hence the curvature of the energy bands and their relative
positions with respect to each other either in the conduction bands or within the valence
bands can serve as a useful approximation. For more accurate representations of the
bands, application of the GW approximation or other many-body perturbation correc-
tions can often provide the appropriate level of accuracy required.
The X and L labels in Fig. 5.13(a) indicate symmetry axes through the bulk silicon
lattice in three-dimensional k-space [56].The silicon band structure is characterized by a
valence band maximum at ~ k ¼ ð0; 0; 0Þ or “Γ-point.” At the valence band maximum,
there are two degenerate “heavy hole” (HH) bands and a single “light hole” (LH) band.
The HH band refers to the fact that the curvature of the degenerate bands is less than the
LH band, resulting in larger effective masses for the HH band. The conduction band
minimum in bulk silicon is along the ½100 direction towards the X symmetry point
giving an indirect band gap. From the symmetry of the silicon crystal lattice, the
following six directions are equivalent: ð100Þ; ð010Þ; ð001Þ; ð100Þ; ð010Þ, and ð001Þ,
where a bar is introduced per convention to denote the negative of a unit vector in
k-space. Around these energy minima, surfaces of constant energy can be identified. For
small displacements away from the minima, the energy dispersion is parabolic.
However, for displacements normal to and along the symmetry axis, the curvatures
about the minima are different, hence the effective masses for different directions about
the minima vary (in general, a mass tensor is defined and the preceding statements hold
off-axis). This allows for constant energy ellipsoids to be defined about the minima and
these surfaces are given by the following relationship for minima along the ð001Þ and
(001Þ directions:
ℏ2 ½ðkx kx0 Þ2 þ ðky ky0 Þ2 ℏ2 ðkz kz0 Þ2

Eð~
kÞ ¼ Eð~
k 0Þ þ þ ; ð5:79Þ
2mt 2ml
where Eð~ k 0 Þ is the conduction band minimum at the point ~ k 0 ¼ ðkx0 ; ky0 ; kz0 Þ and
~
k ¼ ðkx ; ky ; kz Þ is a point on the ellipse, mt and ml are the effective masses transverse
to and longitudinal to the symmetry axis, respectively. The band minima
about ð010Þ; ð010Þ and ð100Þ; ð100Þ are similarly expressed. For silicon, the values
for the effective masses for the conduction band minimum are typically quoted to be
mt ¼ 0:19me and ml ¼ 0:92me : The energy ellipsoids for the silicon bulk band structure
are shown in Fig. 5.13(b). At a higher energy, there is also a conduction band minimum
along the L symmetry direction which describes the eight equivalent directions given by
ð111Þ; ð111Þ; ð111Þ; ð111Þ; ð111Þ; ð111Þ; ð111Þ; and ð111Þ.
(a) (b) ––
(111) –
5 (111)
–
(111)
3 (111)
Energy (eV)
–1
–3
–5
L G X
Figure 5.14 (a) Energy band diagram for germanium from an approximate DFT calculation. In the figure, the
band gap has been corrected to its experimental value of 0.67 eV by shifting all the conduction
band states by a constant to compensate for the XC error. Note due to the smaller band gap in
germanium, many approximations to germanium predict a metallic or semimetallic band structure
and there can be unwanted coupling between the conduction and valence band energies. Note that
although a conduction band minimum is correctly predicted along the L symmetry axis, the Γ point
or direct gap is predicted to be too low in energy. Data courtesy of Dr. L. Ansari. (b) Energy
ellipsoids at the conduction band minima in germanium along the ð111Þ and equivalent directions
in reciprocal space. The constant energy ellipses in germanium lie along the body diagonals of the
cubic Brillouin zone in reciprocal space.
In Fig. 5.14(a) the band structure for germanium is shown. The valence band structure
is similar to silicon with the energy maximum occurring at the Γ-point with doubly
degenerate HH bands and a single LH band, although the energy differences between the
bands near the valence edge are larger than for silicon. Similar to silicon, the location of
the conduction band minima results in an indirect band gap but unlike the silicon
conduction band, the minima lie along the L symmetry directions. This leads to eight
equivalent energy ellipsoids or valleys for the germanium conduction band minima
along the eight symmetry equivalent L axis.
Alloys of silicon germanium will display either a “silicon-like” behavior with a
conduction band minimum near the X -valley or “germanium-like” with the conduction
band minimum occurring at the L-valley as shown in Fig. 5.14(b). The transition
between these two regimes occurs for alloy compositions 15% silicon and 85% germa-
nium. For alloy compositions with less than 85% germanium content the material is
“silicon-like” whereas for alloy compositions with greater than 85% germanium con-
tent, the material becomes “germanium-like.”
The band structures for gallium arsenide (GaAs) along the high symmetry directions
X and L are shown in Fig. 5.15(a). In contrast to the silicon and germanium band
structures, GaAs displays a direct band gap occurring at the Γ-point. The valence band
also displays heavy and light hole energy bands. A notable distinction relative to the
silicon and germanium band structures is the much higher curvature at the conduction
band minimum. This leads to an effective electron mass of 0:067me . This very low
effective mass leads to a large electron mobility in gallium arsenide leading to con-
sideration of III-V materials for nanoelectronics applications. However, it should be
(a) (b) (001)

5
3
Energy (eV)
1
(100)
–1
–3
(010)
–5
L G X
Figure 5.15 (a) Energy band diagram for gallium arsenide from an approximate DFT calculation. In the figure,
the band gap has been corrected to its experimental value of 1.43 eV by shifting all the conduction
band states by a constant to compensate for the XC error. The direct band gap for GaAs is
predicted although the positions of other low lying conduction states or “satellite valleys” are not
predicted to the accuracy needed for accurate device simulation. Data courtesy of Dr. G. Greene-
Diniz. (b) The energy isosurface at the conduction band minimum is approximately spherical and
centered about the Γ-point.
noted that the low effective mass implies a higher band curvature, which also implies a
lower density of states at the conduction band minimum. Hence use of materials such as
GaAs, particularly in nanometer scale transistors with limited scattering in the channel,
must consider design trade-offs between low charge carrier masses and hence higher
electron velocities against a lower density of states and hence a lower number of electrons.
5.7 Applications to semiconductor nanowires
The electronic properties of semiconductor nanowires are examined for the example of
silicon. A key feature of a nanowire is a large surface-to-volume ratio which influences
mechanical, chemical, thermal, and electrical properties. The Fermi wavelength of
charge carriers in silicon is of the order of 10 nm and hence when a nanowire is
grown or fabricated on length scales below this, confinement effects set in due to the
potentials introduced by the surface and the effects of surface chemistry. The electronic
structure changes substantially with respect to the bulk band structures, and fundamental
quantities such as energy band gaps and charge carrier effective masses are altered. In
the case of silicon and other indirect semiconductors, the effects of quantum confine-
ment can lead to an electronic band structure with a direct band gap. In this sense silicon,
other semiconductors, and in general all materials patterned with dimensions of a few
nanometers “are” effectively different materials from their corresponding bulk forms.
5.7.1 Nanowire crystal structures

Although nanowires are grown or patterned with structures that reflect the bonding
between semiconductor atoms in the bulk, three distinct new features arise when making
[110]
– –
[111] –
[111]
– [001]
[001]
–– –
[111] [111]
Figure 5.16 Facets on a [110]-oriented silicon nanowire as identified by STM imaging in [31].
finite structures. The crystal symmetry is broken, surfaces or facets are created, and the
infinite bonding of the crystal is interrupted leaving unsaturated or dangling bonds at the
surface of the nanowire.
The formation of a nanowire implies that the repeating pattern of atoms found in the
crystal can only occur in one direction and this is the nanowire’s long axis. The
orientation of the parent crystal aligned along the nanowire’s long axis is referred to
as the orientation and is denoted by a direction in position space per the standard
crystallographic notation ½x; y; z.
Different nanowire orientations result in different surfaces, and in many cases these
planes of atoms will have the characteristics of the corresponding surface cleaved from
the bulk. The facets are denoted by the direction vector normal to the surface and the
equivalent set of facets is denoted by fx; y; zg. In Fig. 5.16, the surface facets for a
<110>-oriented nanowire are given for the case of a silicon or germanium nanowire as
identified in [31] by STM imaging. The faceting of a nanowire can depend strongly on
the fabrication or growth method and surface preparation. The stability of different
nanowires with different facets depends on a balance between the bulk energy, surface
energy including the borders between facets or edges, and strain. Note that the surface
energy will include a chemical component when surface bonds are saturated or bonded
to a dielectric or other encapsulating layer.
Figure 5.17 shows small diameter semiconductor nanowires oriented along the <100>
and <110> crystal directions with tetrahedral bonding and hydrogen used to saturate or
“passivate” surface dangling bonds. The surfaces for the nanowires with different
orientations have different densities of silicon surface atoms, and hence different
densities of surface bonds when passivated. The nanowire orientations shown in Fig.
5.17 for the ½100 and ½110 orientations are shown with all surface bonds passivated by
hydrogen atoms and it is seen that different surfaces have different densities of the
surface bonds. For smaller nanowires the curvature of the surface or at the edges
between facets introduces steric effects and strains that are generally not present at an
ideal surface. Hence even for a highly idealized nanowire structure, bonding configura-
tions to a surrounding oxide or steric hindrance for surface passivation can vary
substantially with respect to the corresponding planar surfaces. Clearly, as a nanowire’s
diameter is increased an approach to bulk surfaces behavior occurs. In FinFET struc-
tures, the surfaces can often be approximately considered as planar surfaces or tapered
layers with consideration of the geometry of the edges.
(a) (b)
Figure 5.17 Examples of cross-section views of nanowires with hydrogen surface passivation. Dark grey:
silicon atoms, light grey: hydrogen atoms. (a) <100>-oriented silicon nanowire of approximately
1 nm diameter. (b) <110>-oriented silicon nanowire with a diameter of approximately 2 nm.
For binary and ternary semiconductors or in general for alloys the surface termina-
tions and composition can vary based upon the nanowire’s orientation and growth
conditions. Different orientations of alloyed semiconductor nanowires can lead to
significant variations in the surface composition, and strong variations in surface
composition can exist between different nanowires ostensibly fabricated or grown
with the same composition. For example, gallium arsenide nanowires can be grown
with either gallium-rich or arsenic-rich surfaces. Control of the surface composition of
the nanowires can enhance the ability to grow specific oxides or to eliminate defects
occurring due to bonding to an oxide or other layer in which a nanowire is embedded.
5.7.2 Quantum confinement and band folding

When forming a two-dimensional system, one spatial dimension is formed on a scale
less than the electron or hole Fermi wavelength λF ¼ 2π=kF ; where kF corresponds to
wave vector or wave number at the Fermi energy. For a nanowire, two spatial dimen-
sions are such that the electrons are confined to a region less than a Fermi wavelength.
This phenomenon is known as quantum confinement and significantly influences the
electronic structure of a nanometer scale system. As will be seen subsequently, the
energy minimum in the direction of the confining potential can be “folded” back to
the center of the Brillouin zone or “Γ-point,” fundamentally altering the behavior of a
material when formed or patterned as a nanowire.
An example of a low-dimensional electron gas can be found at the semiconductor-
oxide interface in a planar MOSFET. If the channel length is taken aligned to the x
direction, and the width of the channel is aligned to the y direction, the gate stack will be
oriented along the z direction. As a gate voltage is applied, inversion occurs near the
semiconductor-oxide interface and electrons become trapped in a potential well at the
interface that is often approximated as a triangular potential well. In this approximation,

the semiconductor-oxide interface forms a “hard wall” potential and the electric field in
the channel is linear forming a well that traps charge carriers near the interface. For the
purposes of discussion, the channel length and width will be assumed to be large with
respect to the inversion layer thickness. Hence the electrons are effectively trapped in a
plane parallel to the interface with a continuum of states available for propagation
in-plane. For the confinement potential perpendicular to the interface with a width
small compared to the Fermi wavelength of the charge carriers, the electronic states
are quantized and subbands form. The inversion layer is an example of a two-
dimensional electron gas (2DEG).
One way to view the formation of the 2DEG is to consider that in the directions
parallel to the semiconductor-oxide interface the charge carriers in the inversion layer
retain their bulk band structures, but in the z direction normal to the interface the
electronic band structure is folded back onto the Γ-point creating non-propagating,
standing wave states that give rise to energy subbands [57]. Figure 5.18 provides a
graphical view of the resulting electronic band structure for the 2DEG formed at a silicon
½001 surface. The constant energy ellipses about the conduction band minima or valleys
in bulk silicon along the X symmetry lines are shown in Fig. 5.18(a). The confining
potential due to the semiconductor-oxide interface and the gating voltage act to confine
the valleys in the ð001Þ k-space direction restricting them to the Γ-point. The resulting
electronic structure is depicted in Fig. 5.18(b) as viewed normal to the plane of the
2DEG. The two concentric circles at the Γ-point reflect the degeneracy due to the
confinement of the two valleys originating from the ð001Þ and ð001Þ conduction
minima. The resulting band structure will give rise to a two-dimensional density of
states as presented in Chapter 4.
(a) (001) (b) (010)
(010)
(100) (100)
Figure 5.18 Band folding in silicon to form a 2DEG. Confining planes are introduced in the planes normal to
the ð001Þ and ð001Þ directions. (a) The isosurfaces of constant energy around the conduction band
minima along the X symmetry axis. (b) After introduction of the confinement potential the energy
minima along the ð001Þ and ð001Þ are folded onto the Γ-point in the center of the Brillouin zone.
The concentric circles at the Γ-point represent the two degenerate energy bands that have been
“folded.”
(a) (010) (b) (010)

kx = ky
(100) (100)
Figure 5.19 Formation of a quasi-one-dimensional nanowire. (a) Starting from the 2DEG electronic structure
shown in Fig. 5.18(b), confinement potentials are introduced in planes normal to the ð110Þ and
ð110Þ directions. (b) The confinement potentials fold the energy minima located in the
ðkx ; ky Þ-plane along kx ¼ ky but displaced from the Γ-point.
Taking the example of the 2DEG as starting point, the electronic band structure for a
silicon nanowire oriented in the ½110 direction is considered next. The ½110 orientation
for silicon nanowires is of note for several reasons: it can have a higher mobility relative
to other orientations for diameters of a few nanometers, it is a common orientation, along
with ½112, that readily forms for silicon nanowires grown with bottom-up techniques,
and it can be readily fabricated on silicon wafers by top-down fabrication techniques. A
nanowire oriented along the ½110 direction will have confining potentials in planes
defined by directions normal to the long axis. In the Brillouin zone, these can be taken to
be the surfaces normal to the ½001 and ½001 directions. The effect of confinement
normal to these directions is given in Fig. 5.18. The directions ½110 and ½110 are also
normal to ½110. In Fig. 5.19(a) the folding of the conduction band minima due to
confinement in planes normal to the ð001Þ and ð001Þ directions in reciprocal or
k-space is shown in a top view with the planes normal to ð110Þ and ð110Þ included as
the dashed lines in the figure. The effect of these additional confinement planes forces
the nanowire electronic structure to become one-dimensional with the energy minima all
situated along kx ¼ ky . The resulting band structure in the nanowire bears only a passing
resemblance to the original silicon bulk band structure. There are two-fold degenerate
band minima at the Γ-point and two-fold degenerate minima folded onto the ð110Þ and
ð110Þ axes. The relative energies of the band minima with respect to one another can be
estimated by the effective masses of the electrons in the confinement directions. For the
bands folded back to the Γ-point, the relevant electron mass being confined is the
longitudinal or heavy conduction mass. The minima folded onto ð110Þ and ð110Þ
directions involve coupling of the longitudinal and transverse masses resulting in a
lighter effective mass relative to a strictly longitudinal mass. This leads to the expecta-
tion that confinement energies for the minima displaced away from the Γ-point will be
greater than the confinement energies for the minima folded back onto the Γ-point.
Hence it can be anticipated that the quantum confinement effect will lead to a
direct band gap semiconductor for a silicon ½110-oriented nanowire based upon a
band folding argument. The concept of band folding is a useful tool for understanding
the effects of confinement in lower dimensional systems. To provide accurate informa-
tion for effective masses, location of energy minima, and the energy separation of
minima as needed for transistor design requires more detailed electronic structure
information obtained from either experimental measurements or theoretical
calculations.
5.7.3 Semiconductor nanowire band structures

Band folding is a result of quantum confinement and the simplest model to
describe the effect of confinement on single-electron states is the particle-in-a-
box problem discussed in Chapter 4. From Eq. (4.80), it is seen that an energy
subband will be created with energy inversely proportional to the effective mass of
a charge carrier and inversely proportional to the square of the length associated
with the confining potential well. In a semiconductor nanowire, the confinement
potential is due to a surface of a nanowire or an interface potential barrier between
the wire and for example an oxide. As the cross-section or diameter of a nanowire
is reduced, the subband energy increases in an effective mass approximation. For
an approximately circular nanowire of diameter d, the increase in band gap energy
may be expressed as
Eg ðdÞ ¼ Eg;bulk þ constant=d α ; ð5:80Þ
where Eg ðdÞ is the band gap energy, Eg;bulk is the bulk band gap of the material, and
α ¼ 2 for an ideal system. The exponent α together with the multiplying constant are
parameters usually fit to experiment or calculations. The fact that values different from
α ¼ 2 can be found is related to the fact that the confinement potential in a nanowire is
only approximately described by the particle-in-a-box problem, but also simply due to
the fact that defining the diameter of a nanowire of a few nanometers is an ambiguous
procedure due to the discrete atomic structure of materials on this length scale. For
example, for a hydrogen terminated silicon nanowire, some reports in the literature
quote as the radius the maximum distance between hydrogen atoms across a cross-
section or as the maximum distance between silicon atoms to define a cross-sectional
area. The increase in energy for the conduction band electrons and the relative lowering
of energy for the valence band holes leads to the increase in the band gap energy with
reducing nanowire cross-sectional area.
Band gap widening as a function of nanowire diameter is shown using a combination
of experimental data and electronic structure theory in Fig. 5.20. The band gap of silicon
nanowires was measured for ½112 and ½110 orientations with hydrogen passivation
using scanning tunneling microscopy (STM) for diameters between 1 and 7 nm [31].
Also included in the figure are theoretical calculations using the GW approximation
for ½112-oriented [58] and ½110-oriented silicon nanowires with hydrogen
(a)
5.0
4.5
4.0
Band gap (eV)
3.5
3.0
2.5
2.0
1.5
1.0
–1 0 1 2 3 4 5 6 7 8
d (nanometer)
(b)
5.0
4.5
4.0
3.5
Band gap (eV)
3.0
2.5
2.0
1.5
1.0
–1 0 1 2 3 4 5 6 7 8
d (nanometer)
Figure 5.20 Examples of band gap widening as a function of nanowire diameter due to quantum confinement.
• Experimental data from STM measurements of the band gap obtained in [31]. ■ Theoretical data
obtained from the GW approximation from [58,59,60], for (a) [112]-oriented silicon and (b)
[110]-oriented silicon nanowires.
passivation [59,60]. The onset of band gap widening becomes significant in silicon
nanowires for diameters below 5–6 nm. For diameters above 3 nm, there is a smaller
difference in the confinement effect between the two nanowire orientations whereas for
diameters below 3 nm there is a pronounced difference in the values of the energy band
gaps – although, as previously noted, there is some ambiguity in defining diameters for
nanowires with smaller cross-sections. A summary of primarily theoretical calculations
for silicon nanowire band gaps is compiled in [61] with many of the values presented in
the tabulations obtained from density functional theory (DFT) within the local density
approximation (LDA) or with the generalized gradient approximation (GGA). Hence
some care in interpreting the DFT/LDA or DFT/GGA predictions for the electronic band
structures is required. As previously noted, common approximations from approximate
DFT methods underestimate bulk semiconductor band gaps by 50% or more. For bulk
silicon, this implies corrections to approximate DFT predictions of approximately
0.5 eV. The GW calculations and their comparison to experiment indicate that these
corrections are much larger in nanowires as confinement effects become important. The
GW corrections for the energy band gaps can be greater than 2 eV relative to approx-
imate DFT calculations for the smallest diameter nanowires. Approximate DFT methods
commonly reported underestimated semiconductor band gaps and this remains true for
nanowires. It can be expected that the band gap widening predicted from approximate
DFT methods for semiconductor nanowires will actually occur at larger diameters.
Calculations for the effect of quantum confinement on band gap widening in ½110
silicon nanowires are shown in Fig. 5.21 as found from approximate DFT. As noted,
these methods underestimate the size of the nanowires at which the confinement effects
arise, hence the band structures provide a lower limit to the size of the energy band gap at
a given diameter. The nanowires presented in Fig. 5.21 have surface silicon atoms
passivated by hydrogen. For silicon and other semiconductor nanowires, the effect of
the surface bonding can have a large impact on the value of energy band gaps. For a
silicon ½110-oriented nanowire with a diameter of approximately 1 nm, changing the
surface termination from hydrogen (-H) to hydroxyl groups (-OH) leads to a greater than
1 eV red shift (reduction) in the band gap as predicted from DFT/GGA calculations [62].
The electronegativity of the surface passivating species can be used to modify the
electronic structure of the nanowire, for example the −NH2 group is predicted to have
a band gap intermediate to −H and −OH surface passivants, consistent with its inter-
mediate value of electronegativity. The closer the passivating species matches the
electronegativity of the surface silicon atoms, the less charge transfer occurs between
the surface and passivating groups. For a more electronegative species such as hydroxyl,
more charge transfer occurs creating a larger surface dipole. The surface can be viewed
as a hollow cylindrical capacitor with the effect that the potential in the center of the
capacitor will have a constant voltage offset with respect to the potential external to the
nanowire [63]. Hence due to the large surface-to-volume ratio and the electrostatics of
surface bonding, modification or “tuning” of the band gaps in nanowires of diameters of
a few nanometers can be achieved through surface chemistry.
Closely related to the influence of surface dipoles on the overall nanowire electronic
structure is the effect on the band gap that arises when a nanowire is embedded in a
dielectric material. Nanowires grown by bottom-up techniques are often embedded in an
oxide material or dielectric. To form transistor structures with the gate-all-around
geometry, a gate oxide is grown or deposited around the nanowire to maintain electrical
isolation from the gate electrode. A dielectric mismatch between the semiconductor
channel region and the gate dielectric leads to a dielectric confinement effect [64]. The
effect on the band structure in nanowires can be pronounced, and in contrast to the
quantum confinement effect which formally varies as the inverse of the diameter
(a)
1.8
1.5
1.2
0.9
E–EV (eV) 0.0
–0.3
–0.6
–0.9
G x
Figure 5.21 Electronic band structure for [110]-oriented silicon nanowires with hydrogen passivation and
varying diameters of approximately (a) 2 nm, (b) 4 nm, and (c) 6 nm. Cross-sections of the
nanowires corresponding to each band structure are shown for reference. The larger nanowires
show approximately the band gap as underestimated by DFT for bulk silicon and the confinement
effect becomes more noticeable for the 4 nm and 2 nm nanowires. Better estimates to the band gap
energies can be obtained from Fig. 5.20 but the DFT calculations capture the general trend. Band
folding leads to a direct band gap for the three nanowires but for the 6 nm nanowire there is a near
degeneracy between the Γ and off-Γ valleys. Energies are referenced with respect to the valence
band edge. Images and data courtesy of Dr. L. Ansari.
squared, the dielectric confinement effect on band gap energies varies as the inverse of
the nanowire diameter. The effective potential due to mismatch between a semiconduct-
ing nanowire and dielectric is not negligible and tends to correct against correlation
corrections to approximate DFT band gap energies.
5.8 Summary
This chapter has reviewed some basic concepts related to nanowire structures and the
electronic properties associated with nanowires with critical dimensions below 10 nm,
5.8 Summary 161
(b) 1.6
1.4
1.2
1.0
0.8
E – EV (eV)
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
G x
(c) 1.5
1.2
0.9
E – EV (eV)
0.6
0.0
–0.3
–0.6
–0.9
G x
Figure 5.21 (cont.)
with pronounced quantum effects becoming strongly evident below 6 nm critical

dimensions. The principles guiding the behavior of the electronic structure of semicon-
ductor nanowires is well understood. However, there remains relatively little experi-
mental data on the electronic properties of a wide variety of nanowire orientations and
with different surface chemistries, or on the properties of dopants and the effects of local
disorder on material properties in nanowires. Small variations in geometry or surface
chemistry are seen to have a large impact on electronic properties for nanowires with
small cross-sections. Relating these variations to performance of transistors and to
understand the complexity this introduces into circuit design is a key goal for studying
the physical properties of nanowire transistors below 10 nm critical dimensions.
Physical and electrical characterization data for material properties across a range of
length scales and geometries, and for different material sets remain limited. This is at
least partially due to the difficulties associated with fabricating uniform and reproduci-
ble nanostructures and the difficulties in performing electrical or optical characterization
measurements on nanoscale samples. Conversely, accurate theoretical calculations for
semiconductor nanowire electronic structure for diameters greater than a few nan-
ometers quickly becomes prohibitive. Most calculations to date are for highly idealized
structures without dopants or surface roughness. Improved approximations are needed
to scale to larger structures to provide design information for more realistic structures as
required for development of new device technologies. In addition, the calculation times
need to be reduced to provide design information on a time scale that is relevant to
design cycles in technology design. There remains much to be learned about the material
science and electronic structures of sub-10 nm semiconductor nanowires. Given the goal
to continue scaling of transistors into sub-10 nm length scales, a dramatic growth in the
knowledge and expertise for fabricating nanowire transistors is anticipated and is
already underway.
Further reading
Electronic structure theory

J. H. Davies, The Physics of Low-dimensional Semiconductors: An Introduction,
Cambridge: Cambridge University Press, 1998.
W. A. Harrison, Electronic Structure and the Properties of Solids, New York: Dover,
1989.
R. M. Martin, Electronic Structure: Basic Theory and Practical Methods, Cambridge:
Cambridge University Press, 2004.
R. McWeeny, Methods of Molecular Quantum Mechanics, London: Academic Press,
1993.
I. Shavitt and R. J. Bartlett, Many-Body Methods in Chemistry and Physics, Cambridge:
Cambridge University Press, 2009.
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6 Charge transport in quasi-1D
nanostructures
6.1 Overview
This chapter introduces how electron and hole currents can be described in nanostruc-
tures with emphasis on how quantum mechanical effects arise when treating charge
transport in small cross-section semiconductor nanowires. Discussion of the voltage
sources that drive electrical behavior alongside the relationship of voltage to current in
quantum mechanical systems leads to the property of conductance quantization. An
overview of the relationship of charge carriers (electron, hole) scattering to mobility and
the relationship to mean free paths is introduced. Transistor channels with length scales
below or comparable to the mean free paths for electrons or holes are considered leading
to quasi-ballistic transport. In the quasi-ballistic regime only a few scattering events can
occur resulting in macroscopic properties such as mobility, diffusion, and drift velocity
becoming inapplicable and charge carrier transport is no longer described by classical
drift and diffusion mechanisms. The chapter concludes with an introduction to Green’s
function approaches, which are suitable for describing charge transport in the scattering
regimes ranging from purely ballistic, to quasi-ballistic, to ohmic conduction.
6.2 Voltage sources
6.2.1 Semi-classical description

Before embarking on a discussion on how to calculate electron and hole currents in
nanowire structures, it is useful to consider the physical description of a voltage source.
A non-equilibrium condition is required to be built up across the nanowire or “device”
region to provide the charge imbalance that gives rise to electric current. To understand
how a battery or power supply acts to create such a non-equilibrium condition, the result
of a voltage applied by a battery between two disconnected (open circuit) electrodes is
examined. Within a battery, electrochemical cells provide a potential difference that
results in a deficiency of electrons on the cathode (positive terminal) and an excess of
charge on the anode (negative terminal). Figure 6.1 provides a simple depiction of a
battery connected to two electrodes shown as metal regions with wires connecting them
to a battery or other voltage source. It is assumed the wires are ideal conductors and the
electrodes are metallic. Hence in a cathode electrons are pulled away from the metal
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168 Charge transport in quasi-1D nanostructures
→
ε
µL µR
V
+ –
Figure 6.1 Electrodes connected to a battery in an open circuit configuration. The electric field lines
between the electrodes are schematically shown. The electrostatic force of a positive charge
carrier (hole) is directed along the field lines whereas the electrostatic force on a negative charge
carrier (electron) is in the direction opposing the field lines.
electrode leaving a net positive charge behind, whereas an excess of negative charge is
built on the anode. Typical charge screening lengths in metals are on the order of or less
than 0.1 nm; hence any charge imbalance in the electrodes resides at the surface as
electrostatic screening ensures mobile electrons rearrange to maintain charge neutrality
within the bulk of a conductor. The fact that electrostatic screening is efficient in
conductors implies that the electric field is effectively zero beyond a few charge screen-
ing lengths into a metallic surface, or equivalently it can be concluded that the voltage is
constant within the metal or conducting electrodes since the electric field and electro-
static potential are related by
~
Εð~ ~~r V ð~
rÞ ¼ ∇ rÞ: ð6:1Þ
Thus effectively all the potential energy difference or voltage drop is between the
electrodes plus a few screening lengths into both electrodes. The resulting field lines
depicted in Fig. 6.1 represent the electric field that arises across a gap situated between
charged electrodes. Evaluating the line integral of the electric field between any points
yields an electrostatic potential independent of the path taken, revealing that the field is
“conservative.” Hence the potential energy change of the electrons travelling between
the two electrodes is independent of the path that the charge carriers follow; the potential
energy gained or lost is determined by the initial and final positions taken for the charge
carriers. The resulting voltage difference between two points taken within several charge
screening lengths within the anode and cathode thus equates to the open source voltage
of the battery. The point to be made is that the electrodes are each separately in
equilibrium with the anode and cathode of the battery. Due to the charge balance induced
in the electrodes arising from the electrochemical potential maintained by the battery, the
two electrodes are held at differing but constant voltages.
Next consider a nanowire or similar structure connected between the electrodes. The
charge imbalance and corresponding potential difference between the electrodes gives
rise to a current flow with electrons from the anode flowing toward the cathode. As is
convention, the current flow in the direction opposite to the electron trajectories is taken
to be positive and hence current is positive when measured from the positive cathode
terminal to the negative anode terminal. As current flows, the battery during its normal
operating life is able to maintain a constant electrochemical potential across its
terminals and likewise is able to independently maintain equilibrium within each of
the electrodes. Indeed the ability to maintain a constant voltage difference for arbitrary
currents is the defining feature of an ideal voltage source. The ability of the battery or
other voltage source to maintain equilibrium with the electrodes implies that the
cathode and anode act as reservoirs for the electronic charge carriers. In this context, a
charge reservoir is a large supply of either mobile electrons or holes locally in thermo-
dynamic equilibrium and at a constant voltage. However, overall the circuit is in a non-
equilibrium state due to the potential difference created across the nanowire as the two
electrodes are held locally in equilibrium but are forced away from equilibrium with
respect to each other by the battery or voltage source.
To explore the consequence of the cathode and anode acting as charge reservoirs, let’s
follow what happens to an electron as it exits the anode, traverses the nanowire, and exits
into the cathode for the case of no scattering or ballistic transport, and ask: what are the
implications for operation of an ideal voltage source? Although the anode electrons
are at a lower voltage with respect to the cathode, recall this implies they are at a higher
energy due to the electron charge sign convention. In the open circuit of Fig. 6.1, the
zero voltage reference or ground may be chosen arbitrarily. One choice is to assume
the electrons in the positive cathode terminal are at a voltage of þV =2 and electrons at
the negative anode terminal are at a voltage of V =2. Note that any zero voltage
reference may be chosen as long as the voltage difference between the two electrodes
is V , for example the more conventional circuit choice is to choose the cathode terminal
to be at þV and the anode at “ground” or V ¼ 0, a choice which will be used in the
following sections. The force on an electron is related to electric field by
~ rÞ ¼ q~
F ð~ Eð~
rÞ; ð6:2Þ
expressing mathematically that the force acting on the (negatively charged) electrons
drives them from anode to cathode. Electrons exiting the anode experience acceleration
due to the electrostatic force, and since transport through the nanowire in this example is
assumed to be without scattering or ballistic, the charge carriers exit the nanowire and
enter the cathode with an increase in kinetic energy that equates to the potential energy
difference maintained between the electrodes. In the case of ballistic transport all the
electrons find their way into the cathode and for the battery‘s terminals to remain in
equilibrium with the electrodes, the electrons entering the electrode after traversing
a potential energy drop must lose the kinetic energy gained to “equilibrate” with the
electrons residing at the cathode. For this to happen, the electrons with excess kinetic
energy must experience inelastic scattering events within the electrode connected to the
battery’s positive cathode terminal; such events are primarily ascribed to electrons
scattering off lattice vibrations or “phonons” whereby the excess energy is dissipated
through heating of the electrode material. Through these inelastic events the excess
kinetic energy is dissipated and the arriving electrons achieve a local equilibrium with
the cathode. These energy loss events give rise to power dissipation and a study of
heating mechanisms and heat transfer on the nanometer-scale remains a subject of active
investigation [1,2]. Although transport in the nanowire may be ballistic, the introduction
of voltage sources by application of open system boundary conditions requires that
energy losses occur in the cathode terminal to maintain local equilibrium.
A similar picture is found if scattering in the nanowire region is allowed but a new
condition on the behavior of the electrodes is introduced. If elastic scattering is con-
sidered, electrons entering the nanowire region have a probability of being transmitted
to the cathode or being reflected back into the anode. Electrons entering the cathode
region still acquire additional kinetic energy due to the potential energy drop along the
nanowire and again must equilibrate with the other electrons through inelastic processes,
whereas electrons reflected back will return with the same kinetic energy as they re-enter
the anode with the same potential energy at which they exited. However, in the models of
transport to be discussed next it is assumed that electrons or holes once exiting from
the nanowire region into either electrode are not able to emerge back into the nanowire
before entering the electrode and becoming re-equilibrated. This condition is typically
maintained when electrons exit a narrow constriction such as a nanowire and enter a
wider region such as a large metal electrode. However, it is worthwhile to mention that
this essentially geometric constraint is not maintained in all nanoelectronic structures
and some care is required when defining electrodes and electron reservoirs for charge
transport applications. Finally, if inelastic scattering is allowed in the nanowire region,
the conditions on the electrodes remain but additionally energy loss and consequently
heating occurs in the nanowire or device region, but otherwise the boundary conditions
required for the electrodes remain the same.
The nanowire or device region connected to the electrodes is an example of an
open system for which appropriate boundary conditions must be specified to describe
the response to applied voltages. As current flows, electrons or holes are exchanged
with the reservoirs and an exchange of particles is one characteristic trait of an open
system. For the specific case of a device region connected to a voltage supply, the
previous discussion suggests that boundary conditions for each electrode are similar
to an ideal black body in that, like a black body, the electron reservoirs are in
thermodynamic equilibrium [3]. A black body emits a fixed energy distribution of
electromagnetic radiation whereas the electrons are emitted with a fixed energy
distribution determined by the equilibrium condition in the electrodes. An ideal
black body also is capable of absorbing all incident radiation which then equilibrates
before being re-emitted: this condition is in analogy to the condition that the
electrodes can absorb all electrons incident from the device region without reflection,
and that all electrons achieve equilibration with all other electrons in the electrode
before being emitted into the nanowire. The essential feature of the electrode
reservoirs is that the charge carriers emerge with an energy fixed by a local
equilibrium condition, but that they can absorb incoming charge carriers with any
energy or momentum distribution.
6.2.2 Electrode Fermi–Dirac distributions

Up to this point the description of the electrodes and voltage source have relied primarily on
classical electrostatic arguments, statements about thermodynamic equilibrium, and the
condition of reflectionless electrodes to define boundary conditions for an open system, for
present purposes, a nanowire transistor connected between two electrodes. The boundary
conditions are next translated to a quantum mechanical description to allow a first-principles
description of charge transport in nanowire transistors. To begin, if each electron in the
metallic electrodes are in equilibrium or have undergone enough scattering events to forget
or to “decohere” from their previous non-equilibrium state after they are either transmitted
through or reflected by the device region, they may be, once equilibrated, described in the
cathode by a single-particle Hamiltonian that is shifted in voltage by h0 jqjV =2 and for
anode electrons the shift is upward in energy by h0 þ jqjV =2. In Fig. 6.1 the cathode is on
the “left” and the anode is on the “right.” As it is conventional to speak about left and
right electrodes, in the following the cathode will be labeled the left (l) electrode and the
anode the right (r) electrode. Left- and right-moving electron or hole states are intro-
duced depending on the direction of a charge carrier’s momentum incident to the
nanowire region. The effective mass approximation is being applied in the electrode
regions allowing the single-particle energies for the electrons to be given as
ℏ2 2
El ¼ k ;
2m l ð6:3Þ
2
ℏ 2
Er ¼ k :
2m r
It is useful to define the local electrochemical potentials μ in each reservoir in the

presence of a voltage difference as
μl ¼ EF þ jqjV =2;
ð6:4Þ
μr ¼ EF jqjV =2;
where the Fermi energy is still referenced to the zero voltage equilibrium system. The
electrode electrons sufficiently far from the device region are assumed to be equilibrated,
and for the single-particle picture of electrons their energy distribution will be given by
Fermi–Dirac statistics. For the cathode and anode, the energy distributions for the
electrons are
1
fl ðEl Þ ¼ ðE μ Þ=k T ;
e l l B þ1 ð6:5Þ
1
fr ðEr Þ ¼ ðE μ Þ=k T ;
e r r B þ1
Figure 6.2 Fermi–Dirac distribution f ðE; TÞ shown for temperatures T = 0 K (dashed line) and for a finite
temperature T > 0 K (solid line). At low temperatures, the Fermi–Dirac distribution approaches a
step function with electronic states with energies less than the Fermi energy EF occupied with
unity probability. At finite temperatures, electrons can occupy higher energy states above the
Fermi energy. States “near” the Fermi level can have fractional probabilities for occupation. The
relevant energy scale for fractional occupations is for states with energies within a few kB T of the
Fermi level and room temperature or 298 K corresponds to a value of kB T= 25.6 meV. The area
under the curve gives the total number of occupied electrons and the maximum occupation per
energy level is two due to spin degeneracy.
respectively, where kB is Boltzmann’s constant and T is the temperature with the product
kB T approximately equal to 25.6 meV at T = 298 K or room temperature. In Fig. 6.2, the
Fermi–Dirac distribution is plotted at T ¼ 0 and at an arbitrary non-zero temperature.
Assuming that the metallic electrode states are well described by free electrons of
effective mass m (a reasonable approximation for metals), it is seen from the cathode
or left electrode in Fig. 6.3 that only right-moving states will enter into the nanowire or
transistor region and that, conversely, from the anode or right electrode it is only the left-
moving states that will enter into the nanowire or transistor region.
Figure 6.3(a) shows schematically the energy dispersions for the cathode (left) and
anode (right) electrode electrons at zero applied voltage. In this case, the numbers of
right-moving and left-moving electrons are equal and there is no net current. Another
point of view is that electrons entering into the device region are unable to exit into
either electrode as the available states are “blocked” as all available electron states in
the opposing electrode are occupied thereby prohibiting current flow. Figure 6.3(b)
shows how the situation is altered once a potential difference is applied between the
two electrodes. The energy levels in the cathode (left) electrode become lower in
energy relative to the anode (right) electrons which are shifted higher in energy.
Electrons from the anode are now able to enter the nanowire and due to the potential
drop across the device region move across into the cathode. As mentioned previously,
the electrons moving across from the anode convert their excess potential energy into
(a)
E E
E EF
E
(b) E
EF + | q |V
EF
| q |V
(c)
f(k) f (k)
+k F −k F
Figure 6.3 Ideal behavior of electrodes described by a single parabolic energy band and locally in
equilibrium. Electrons are assumed occupied up to the Fermi energy as depicted by the filled area
in the energy dispersion curves for the electrons incident on a scattering region. The Fermi
momentum is indicated by the vertical dashed line. (a) No applied voltage bias. (b) With an applied
voltage bias. (c) The potential energy shifts the electrons energies in the right electrode as
ℏ2 k 2 =2m þ jqjV leaving the electron (or hole) momentum distributions unchanged.
kinetic energy and then are required to equilibrate with the cathode electrons. Note that
the energy difference between the electrodes implies a potential energy profile in the
nanowire region that serves as a barrier to left-incident electrons, whereas it presents a
potential energy drop for the right-incident electrons. Finally in Fig. 6.3(c), the
momentum distributions for the left and right electrodes are plotted. It is noted that the
single-electron energies in Fig. 6.3(b) are shifted by a constant jqjV in the right
electrode, but that the momenta are not likewise shifted. Referring back to Chapter 4,
the introduction of a constant potential energy term is seen to be equivalent to adding a
constant to the Hamiltonian operator in the Schrödinger equation for a plane wave. A
constant potential term only serves to shift the energy eigenvalues but does not change
the wave function. Hence the electrons in the electrodes remain momentum eigenstates
with momentum distributions independent of the applied voltage. Hence the application
of open system boundary conditions may be also expressed in terms of the incoming
momenta from the electrodes incident on the nanowire region being maintained at their
equilibrium distributions as an electric field is applied across the nanowire driving the
two electrodes away from equilibrium with respect to one another.
6.3 Conductance quantization
In information theory and communications, if data are sent down a transmission channel
it is said to be ideal when no information is lost, or conversely is described as noisy when
information is lost or obscured. Similarly, in nanoelectronics reference is commonly
made to conduction “channels.” For the case of quantum charge transport, a conductance
channel may be thought of as an energy subband with a propagating mode in contrast to
non-current-carrying localized states or a standing wave state, although the precise use
of conductance channel as a terminology can vary somewhat. Note that a scattering
wave such as presented in Chapter 4 is typical of transmission for a given energy within a
conductance channel. In the absence of scattering, an ideal conductance channel is
achieved with transmission T ¼ 1 and is “lossy” if electrons can be elastically or
inelastically scattered, in which case the transmission will be such that T < 1. The
concept of conduction channels arises in conjunction with open system boundary
conditions.
6.3.1 Subbands in a hard wall potential nanowire

In Chapter 4, a simple model of a nanowire was introduced with hard wall confining
potentials in the x and y directions leading to a product wave function with particle-in-a-
box (PiB) solutions in the confinement directions and with free particle wave functions
describing the electron states propagating along the nanowire’s axis. This model is
generalized slightly to allow different confinement lengths in the x and y directions.
To begin, the Schrödinger equation for three spatial dimensions in the absence of a
potential energy is
ℏ2 2
∇ ψðx; y; zÞ ¼ Eψðx; y; zÞ: ð6:6Þ
2m
y
z
x
L
h
t
Figure 6.4 A hard wall potential nanowire. On the walls of the box parallel to the yz and xz planes, the
potential energy U ¼ ∞ resulting in a vanishing of the electron wave function at the walls and zero
probability of finding an electron outside of the wire. Charge carriers are free to propagate along
the z direction within the confining potentials. The hard wall potentials normal to the direction of
electron or hole propagation give rise to the subband energies given in Eq. (6.9).
Confinement is modeled as hard wall potentials in the x and y directions as depicted in

Fig. 6.4, and these can be represented by two potential energy functions in a form that
allows for a separation of the wave function in the three spatial variables
ψðx; y; zÞ ¼ φx ðxÞφy ðyÞφz ðzÞ: ð6:7Þ
The wave functions in the confinement direction take on the form of PiB wave functions,
and their product can be written as
πn πn
x y
φx ðxÞφy ðyÞ ¼ Nx;y sin x sin y ; ð6:8Þ
t h
where the confinement length in the x direction is taken to be t and is h in the y direction,
hence a rectangular cross-section nanowire is assumed. Taking t ¼ h the nanowire
model of Chapter 4 is regained. In Eq. (6.8), Nx;y is constant and is chosen based on
the overall wave function normalization. The energy due to the confinement normal to
the nanowire axis is given by

ℏ2 πnx 2 πny 2
Enx ;ny ¼ þ ; ð6:9Þ
2m t h
with nx ¼ 1; 2; 3; … and ny ¼ 1; 2; 3; …. To each ðnx ; ny Þ pair corresponds an energy

subband with a conduction channel in the z direction. The lowest energy subband is
found for nx ¼ ny ¼ 1.
Along the nanowire axis, the 1D Schrödinger equation is
ℏ 2 ∂2
φ ðzÞ ¼ Enz φz ðzÞ; ð6:10Þ
2m ∂2 z z
and if Born–von Kármán boundary conditions are applied to describe propagating states,
then the solution is
φz ðzÞ ¼ Aeþiknz z þ Beiknz z : ð6:11Þ
The constants A and B also are related to the overall wave function normalization and
can be chosen to select right- or left-moving states, or a superposition of the two. The
energy is related to the momentum through the familiar parabolic energy dispersion
characteristic of free electrons

ℏ2 2 ℏ2 2πnz 2
Enz ¼ k ¼ ; ð6:12Þ
2m nz 2m L
with the length of the nanowire taken to be L leading to the quantization of the wave
number nz ¼ 1; 2; 3; … and the energy is independent of the direction of motion. The
total energy for an electron in a subband of the hard wall nanowire is then given as
" #
ℏ2 πnx 2 πny 2 2πnz 2
E¼ þ þ : ð6:13Þ
2m t h L
Notice in this simple model that an isotropic effective mass has been assumed;
however, this is not a necessary assumption and in more realistic models of semicon-
ductor nanowires a strongly anisotropic effective mass is the norm. For conductance
across the nanowire, the nanowire is connected to a voltage source by connecting to
electrodes as presented in Section 6.2.
Conductance in the nanowire is considered next from three equivalent standpoints but
where different physical features of the problem are highlighted. Conductance for a
single subband is examined with the only relevant degree of freedom for the transport
direction of the nanowire axis; for simplicity, subscripts denoting the transport direction
are dropped and quantities are understood to be referred to the nanowire axis.
6.3.2 Conductance in a channel without scattering

The wave number in the direction of electron propagation is
2π
k¼ n; ð6:14Þ
L
and thus
dn L
¼ : ð6:15Þ
dk 2π
The dispersion relation Eq. (6.12) can be rewritten as
pffiffiffiffiffiffiffiffiffiffiffi
2m E
k¼ ; ð6:16Þ
ℏ
leading to
rffiffiffiffiffiffi
dk 1 m
¼ : ð6:17Þ
dE ℏ 2E
Allowing for spin degeneracy (spin up and down) for each energy level, the density of
states DoSðEÞ for a single parabolic subband per unit energy (see discussion on density
of states in Chapter 4) may be expressed as
rffiffiffiffiffiffiffiffi
dn dn dk L 2m
DoSðEÞ ¼ 2 ¼2 ¼ : ð6:18Þ
dE dk dE h E
The density of states gives the number of electrons that can be found at a given energy E,
and for plane wave states the charge density of each of these states is uniform. Hence the
charge density for an electron in a region of length L at a given energy is
DoSðEÞ
ρðEÞ ¼ q : ð6:19Þ
L
The group velocity of an electron propagating at energy E is defined by
dE
vg ðEÞ ¼ ; ð6:20Þ
dk
which for a “quasi-free” electron of effective mass m is

rffiffiffiffiffiffi
p ℏk 2E
vg ðEÞ ¼ ¼ ¼ : ð6:21Þ
m m m
In analogy to a classical charge current given as the product of the charge and number
of charge carriers with the carrier velocity yielding I ¼ qnv, the quantum mechanical
current for a plane wave with energy E may be written as
IðEÞ ¼ ρðEÞvg ðEÞ; ð6:22Þ
which from Eqs. (6.19) and (6.21) is a constant,
2q
IðEÞ ¼ : ð6:23Þ
h
It is seen that the DoS and group velocity conspire to keep the current contribution from
all energies constant for a free electron dispersion relation, and the constant is only
related to fundamental physical quantities: namely, the spin degeneracy per channel, the
charge on an electron q, and Planck’s constant h:
Considering the electron reservoir model of the electrodes as depicted in Fig. 6.3
and at a temperature of 0 K with a voltage V applied across a nanowire, the energy
(electrochemical potential) for the electrons in the left and right reservoirs are μl and μr
with |qjV ¼ μr μl . In the case of ballistic transport, i.e. in the] absence of scattering,
the current flowing in the nanowire is given by
ð μr ð μr
2jqj 2jqj 2q2
I¼ IðEÞdE ¼ dE ¼ ðμr μl Þ ¼ V: ð6:24Þ
μl h μl h h
Therefore the conductance contributed by a single subband to charge transport across a

scattering region is given by
2q2 1
G0 ¼ I=V ¼ ≈ : ð6:25Þ
h 12:9 kΩ
This property for the conductance of a subband is termed conductance quantization,

although as we will see in the following the actual conductance per subband is not
quantized. In the absence of scattering, the conductance per subband is a maximum
and it is this maximum that obeys a “quantization” condition. In Fig. 6.5, the con-
ductance as a function of voltage is shown for the nanowire model with w ¼ t ¼ 6 nm,
and remarkably the quantized conductance steps are independent of the length of the
nanowire or its material composition, which in the transport model would correspond to
a dependence on the effective mass m . Both the nanowire’s length and effective mass of
the charge carriers are conspicuously absent from the final conductance formula. It is
5
Conductance [2q2/h ]
0
0 100 200 300 400
Energy [ meV ]
Figure 6.5 Conductance quantization for the nanowire model with t ¼ h ¼ 6 nm. The individual steps in the
conductance curve correspond to new subbands entering the bias window as the voltage drop
along the nanowire’s long axis is increased. Effective mass for the charge carriers is taken to be
m ¼ 0:5
also seen that if the “voltage bias window,” V ¼ ðμr μl Þ=jqj, is sufficiently large to
encompass n subbands, their conductances add in parallel as G ¼ nG0 . Alternatively, if
the voltage is sufficiently small that only one conducting quantum state is within the bias
window, the differential conductance g0 ¼ ∂I=∂V for a single state is also found to be
g0 ¼ 2q2 =h. Hence the “conductance quantum” is a fundamental characteristic for a
single ideal (i.e. in the absence of scattering) conductance channel or single-electronic
state [4].
The independence of an ideal ballistic conductor’s conductance, or similarly its
resistance, on length gives rise to the concept of a “contact resistance.” Essential to
the formulation of the resistance per subband is the assumption of a dense set of
electrode states connected to both ends of a narrow constriction that in our examples
is a nanowire. Hence the denser set of states associated with the electrodes is always
capable of “feeding” charge carriers into the lower DoS in the constriction. It is the
physical picture of the “wide” electrodes providing electrons into the “narrow” nanowire
combined with the fact that the ballistic resistance is independent of the length of the
nanowire that gives rise to the term “contact resistance,” thereby leading to the associa-
tion of the ballistic resistance to the electrode–nanowire interfaces.
6.3.3 Time reversal symmetry and transmission

The previous calculation for the conductance quantum given above implicitly assumes
that no charge carrier scattering in the nanowire occurs, or equivalently that the carrier
transmission is unity. The transmission model depicted in Fig. 6.3 is reconsidered to
allow for scattering in the conductance channels of a nanowire. Before moving directly
to the calculation of the conductance when scattering occurs, the electron or hole
transmission function for arbitrary potential profiles is considered. The reason for this
detour is to establish the condition of detailed balance, which ensures that no current
flows in the absence of a voltage difference across a nanowire.
Time reversal symmetry was discussed in Chapter 4 in relation to momentum
eigenstates and the ability to form a current-carrying state, where it was stated that
time reversal symmetry must be broken to give rise to a current flow. The converse
statement that if time reversal symmetry is not broken a current cannot flow is also
true. To explore this claim in more detail, a more general potential profile in one
dimension is examined as depicted in Fig. 6.6. In Fig. 6.6(a) an arbitrary symmetric
potential barrier is depicted and it is clear by making the transformation x→ x that
the transmission will be equal for left- or right-incident electrons of equal energies. In
Fig. 6.6(b) an arbitrary but asymmetric potential is sketched. It is not obvious that the
transmission will be equal for left and right electrons of equal energy but it can be shown
that it is indeed the case.
For distances sufficiently far away from the central scattering potential, the wave
functions for propagating electrons from either the left or the right will have the form of
scattering states. For an electron incident from the left, the wave function will have
the form
Figure 6.6 Time reversal symmetry ensures that the transmission for left-moving and right-moving electrons
at the same energy will be equal for symmetric or asymmetric voltage profiles. (a) Symmetric
voltage profile in one dimension. (b) Asymmetric voltage profile in one dimension.
eþikx þ rl eikx x 0;
ψl ðxÞ ¼ 0 ð6:26Þ
tl eþik x x
0;
where for simplicity the incident electron flux is chosen to be unity and the form of the
wave function inside the potential barrier is not specified. The explicit form of the wave
function in the barrier will not be needed for the following discussion. Similarly a right-
incident electron is described by

0 0
ψr ðxÞ ¼ eik x þ rr eþik x x

0; ð6:27Þ
tr eikx x 0
again ignoring the explicit form of the wave function within the potential barrier.
Returning to the time-dependent Schrödinger equation given in Chapter 4, it is seen
that time reversal t→ t is equivalent to the substitution i→ i. Taking the complex
conjugate of the time-dependent Schrödinger equation results in
" #
ℏ 2 ∂2 ∂
þ UðxÞ ψ ðx; tÞ ¼ iℏ ψ ðx; tÞ: ð6:28Þ
2me ∂x2 ∂t
Thus if ψ is a solution of the time-dependent Schrödinger equation, then ψ is a solution

if time is allowed to “run backwards,” or for time reversal. It follows for the time-
independent Schrödinger equation that the time reversed solution ψ will be an eigen-
function with the same energy as ψ. Returning to the asymmetric potential barrier, the
time reversed solution for an electron incident from the right becomes

0 0
ψr ðxÞ ¼ eþik x þ rr eik x x

0; ð6:29Þ
tr eþikx x 0;
again ignoring the solution within the potential barrier region. As is expected, the
currents in the wave function are reversed but the solution does not respect the physical
boundary conditions for a left- or right-incident electron being scattered from a potential
barrier. Hence time reversal yields a new solution to the Schrödinger wave equation but
as the solution does not satisfy the appropriate scattering boundary conditions, the
solution at this point is a mathematical artifact. The Schrödinger equation is a linear
differential equation hence a linear combination of solutions is also a solution. Using the
time reversed solution and a right-incident electron scattering state, the following wave
function is constructed:
8
> rr tr ikx
>
< e þikx
e x 0;
1 rr tr
ψ ðxÞ ψ ðxÞ ¼
1 rr rr þik 0 x ð6:30Þ
tr r tr r >
> e x
0:
:
tr
The form of Eq. (6.30) is recognized as the same form of a left-incident electron with
unit incoming electron flux. Thus the identifications
rr tr
rl ¼ ;
tr

1 rr rr ð6:31Þ
tl ¼
tr
can be made. In Chapter 4 current conservation in a scattering state is considered, and for
a right-incident scattering state current conservation can be expressed as
ð1 jrr j2 Þℏk ¼ jtr j2 ℏk;

0
ð6:32Þ
which can be used to define the transmission for an electron incident from the right in
terms of the wave function amplitudes as
k
Tr ¼ 1 jrr j2 ¼ jtr j2 : ð6:33Þ
k0
Using Eqs. (6.31) and (6.33), a relationship for the transmission amplitudes is found to be
k
tl ¼ tr : ð6:34Þ
k0
It follows that
0
k k
Tr ¼ 0 jtr j2 ¼ jtl j2 ¼ Tl : ð6:35Þ
k k
The relationship states that electrons with equal energies incident from the left and
right upon any potential barrier will have equal electron transmissions, and this fact is a
consequence of time reversal symmetry.
6.3.4 Detailed balance at thermodynamic equilibrium

The case of an arbitrary scattering voltage profile between two equivalent electrodes at
zero voltage bias is shown in Fig. 6.6(b). As there is no external applied voltage, the
electrochemical potential of the left electrode, scattering region, and right electrode are
equal to the Fermi energy of the equilibrated (zero bias) system. Detailed balance is a
statement that for a system of charges in thermodynamic equilibrium that leads to the
condition there is no net current flow. As electrons incident from the left or right with
equal energies will enter into the scattering region with the same value of momentum
consistent with the condition of no voltage bias between left and right electrodes, the net
current flow can be written as
2jqjℏ XnF
I¼ ½T ðEn Þ Tl ðEn Þkn ¼ 0;
n¼1 r
ð6:36Þ
m L
where nF is the wave number at the Fermi level and a factor of 2 has been introduced
to account for spin degeneracy. Independent of the scattering potential between the
electrodes, the transmissions between left- and right-incident electrons of the same
energy are equal. Hence at zero voltage bias, time reversal symmetry ensures the current
is zero. Note that for asymmetric electrodes, charges will redistribute between the
electrodes and scattering region until detailed balance is achieved establishing an
equilibrium state.
6.3.5 Conductance with scattering

The presence of a potential difference between the electrodes results in asymmetric
scattering between electrons entering from either the cathode or the anode and they
are scattered as they enter into the nanowire. It is the asymmetry in the carrier
scattering that occurs between the left and right electrodes due to the potential
difference along the nanowire that gives rise to a net current flow. To demonstrate
this behavior in the presence of scattering, the simple step potential is again
considered. Electrons incident from the left see a step up potential whereas
electrons incident from the right encounter a step down potential. The electrons
incoming from the left and right can be represented as scattering states which are
given again for convenience:
8
> 1 þikx
>
<pffiffiffi ðe þ rl eikx Þ x < 0;
ψl ðxÞ ¼ L ð6:37Þ
>
> 1 0
: pffiffiffi tl eþik x x > 0;
L
and
8
> 1 0 0
<pffiffiffi ðeik x þ rr eþik x Þ
> x > 0;
ψr ðxÞ ¼ L ð6:38Þ
>
> 1
: pffiffiffi tr eikx x < 0;
L
with box normalization on the scattering region re-introduced to emphasize that the wave
vectors will be considered to be quantized. Referring back to Fig. 6.3, it is seen that as the
voltage step is applied between the electrodes, the energies of the electrons on the right are
shifted upward by a relative energy of þjqjV . However, the momentum distributions of
the electrons within the electrodes are not affected by the introduction of the voltage
step. The currents for the incoming electrons can be rewritten conveniently as
2jqjℏ XnF h 2

2
i
I¼ Tr Er;n ¼ ðℏk n Þ =2m þ jqjV Tl El;n ¼ ðℏk n Þ =2m kn :
mL n¼1
ð6:39Þ
It is important in this example that, due to the voltage difference, the energy for an
electron in the left electrode and right electrode are not equal for a given wave vector.
Hence for a given incoming momentum (index n) the transmissions are no longer equal
in the presence of a potential difference
Tl ðkn ; V Þ ≠ Tr ðkn ; V Þ ð6:40Þ
when V ≠ 0: Thus as a voltage difference is introduced between the left and right
electrodes, detailed balance is no longer maintained and a current begins to flow.
Figure 6.7 presents the behavior of the transmission as a function of energy for step up
and step down potentials, which corresponds in the present discussion to the case of the
left and right incoming electrons, respectively. It is straightforward to demonstrate that
the step up transmission function given in Section 4.4 is equal to the step down
0
transmission by exchanging x↔ x and k↔k ; the proof is left as an exercise.
However, the physical cause for the region of zero transmission at low energies is
different for the left and right incoming electrons. For the left incoming electrons with
energies less than step potential height, electrons can tunnel into the classically for-
bidden region under the barrier. However, due to the semi-infinite extent of the barrier,
electrons cannot propagate yielding an exponentially decaying or evanescent wave
function under the barrier as qualitatively presented in Fig. 6.8. As there is no propaga-
tion in the forward direction, current conservation requires that the incident electron is
fully reflected for energies less than the step barrier height yielding a net zero current
flow. As electron energies for the left-incident electrons become greater than the barrier
1.0
Transmission
0.5
0.0
0 1 2 3 4 5
Energy [Units of potential barrier height]
Figure 6.7 Transmission for a step up or a step down potential. The energy axis is normalized to the
height of the step up/step down potential barrier height jqjV.
|q|V
incident ®
evanescent
® reflected
Position
Figure 6.8 A schematic view of tunneling into the classically forbidden region for a step up potential. The
transmission is zero hence the reflection R = 1, ensuring the current incident to the step up potential
is cancelled by the current carried by the reflected component of the wave function. The
evanescent wave carries no current but there is a finite probability of finding the electron beyond
the classical turning point.
height, the transmission function increases rapidly until approaching unity for energies
of a few multiples of the step potential. Conversely, the right incoming electrons
encounter a step down potential, and in this case the minimum energy of an electron
in the right electrode is jqjV due to application of the potential difference; see Fig. 6.3(b).
For right-incident electrons with energies just slightly larger than the barrier energy,
there is some reflection for states with lower momenta but the transmission for electrons
incident from the right also quickly approaches unity with increasing energy.
The characteristics of the electron transmission functions for left- and right-incident
electrons permit the following approximate calculation of conductance. Electrons inci-
dent from the left are blocked by the step potential for energies
ðℏkn Þ2
≤ jqjV ; ð6:41Þ
2m
allowing the number of the left incoming states blocked by the potential step to be
expressed as
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2jqjm V
nV ¼ ; ð6:42Þ
ℏΔk
where Δk ¼ 2π=L. The transmission for electrons with energy less than or equal to the
potential barrier is zero, but for electrons incoming from the left with energy greater than
the potential barrier it is approximated as unity. For electrons incoming from the right, all
electrons are taken to have transmission approximately equal to one. This allows the
current including spin degeneracy to be written as
" #
2jqjℏ X nF XnF
Ie kn kn
m L n¼1 n¼nV
2jqjℏ XnV
ð6:43Þ
e m L kn
n¼1
ð nV
2jqjℏ 2q2
→ Δk ndn ¼ V:
mL 0 h
The conductance is found to be G0 ¼ I=V ¼ 2q2 =h and the conductance quantization

condition is again established [5].
The expression for the conductance quantum expressed as the difference
between the transmitted momentum distributions seems at first glance at odds
with the traditional view that it is the electrons at the Fermi energy that contribute
to electrical conduction. In the preceding calculation, electrons with low momenta
incoming from the right are summed corresponding to states incoming from the
left that are blocked by the potential step. However, recalling that in Eq. (6.23), for
a parabolic band, the energy resolved current is a constant q=h, it follows that the
magnitude of the integral over the energy resolved current blocked by the potential
height will be equal to the integral over the states shifted in energy above the zero
voltage Fermi level, i.e.
ð ð
jqjV EF þjqjV

iðEÞdE ¼ iðEÞdE ð6:44Þ
0 EF
Hence the current blocked by the potential barrier is equal in magnitude to the current
carried by the states that are shifted above the zero voltage Fermi level by application of
the potential difference. It is the difference between the left and right current-carrying
states that generates net current flow, and this difference may be expressed either as the
component of the current reflected leaving the anode, or as the difference between the
transmitted components from anode and cathode. Either approach yields the deviation
from detailed balance introduced by the open system boundary conditions.
6.3.6 Landauer conductance formula: scattering at non-zero temperature

In the previous treatment of conductance in a one-dimensional nanowire, the current
contributions iðkn Þ ¼ 2jqjℏTðkn ; V Þkn =m L are summed for left incoming and right
incoming electrons, and the difference between the two sums yields the net current flow.
Implicit in the derivation is that each electron state is occupied with a probability of one or
zero within the electrodes, which is true for electronic states at absolute zero. However, at
finite temperatures, the Fermi–Dirac distribution for the electron states in the electrodes
allows for fractional occupations as shown in Fig. 6.2. The electrons remain integral
particles, but the probability of finding an electron in a given state can be non-integer.
Hence in addition to the current due to an electronic state, the probability of finding an
electron in a given state within an electrode needs to be included into the calculation of
current flow across a nanowire. The problem of left and right electrons incident on a
potential step is again considered, but now with the probability of a given state being
transmitted across the nanowire multiplied by the probability a state is occupied in an
electrode. Thus electrons entering the scattering region are summed to give
2jqjℏ XnF
I¼
f r;n Tr ðk n ; V Þ f l;n T l ðk n ; V Þ kn : ð6:45Þ
mL n¼1
The Fermi–Dirac distribution functions fr;n and fl;n give the probability that an electron
with a given energy is occupied in the left and right electrodes, so it is useful to rewrite
the current expression with energy arguments for the distribution functions and electron
transmissions
2jqjℏ XnF
I¼
fr ðEr;n ÞTr ðEr;n Þ fl ðEl;n ÞTl ðEl;n Þ kn ; ð6:46Þ
mL n¼1
and for this example, the voltage is referenced asymmetrically between the electrodes as
ℏkn ℏkn
Er;n ¼ þ jqjV and El;n ¼ . Equation (6.46) is a general form for the celebrated
2m 2m
Landauer formula which relates current to transmission in a one-dimensional conductor.
Using the expressions for the left and right energies, the wave vector can be written as
m
kn ¼ ð∂En =∂kn Þ; ð6:47Þ
ℏ2
where the subscripts denoting left and right have been omitted as the expression is valid
in both cases. The continuum limit is again taken by replacing the summation by an
integral through the substitution
X ð ð
L
→ dn→ dk; ð6:48Þ
n 2π
allowing the Landauer formula to be expressed as integrals over the electron energy
ð∞ ð∞
2jqj
I¼ f ðE þ jqjV EF ÞTr ðE þ jqjV ÞdE f ðE EF ÞTl ðEÞdE; ð6:49Þ
h 0 0
Using the approximations for the left and right transmission functions for the case of a
step potential as in the preceding example, the current is rewritten as
ð∞
2jqj
I≈ ½f ðE þ jqjV EF Þ f ðE EF ÞdE: ð6:50Þ
h qV
The low temperature limit for the Fermi–Dirac functions of Eq. (6.50) yields in agree-
ment with Eqs. (6.24) and (6.43) the conductance quantum. As seen in Fig. 6.2, the low
temperature limit of the Fermi–Dirac function behaves as a step function with all
electrons below the Fermi level occupied
Figure 6.9 Difference between the Fermi–Dirac distribution functions at 0 K leading to Eq. (6.52).
lim f ðE EF Þ ¼ ΘðEF EÞ; ð6:51Þ

kB T→0
and all states above EF become unoccupied. The Fermi–Dirac distribution functions can
then be approximated for low temperatures as step functions as in Fig. 6.10 leaving the
following expression for the current:
ð∞ ð EF þjqjV
2jqj 2jqj 2q2
I¼ ½ΘðEF þ jqjV EÞ ΘðEF EÞdE ¼ dE ¼ V : ð6:52Þ
h jqjV h EF h
The expression for the conductance quantum G0 ¼ 2q2 =h emerges as the low tempera-
ture limit. It is this picture relating electrons in a “voltage bias window” with energies
between EF and EF þ jqjV that gives rise to the concept that it is the contribution from
the electrons at the Fermi energy that contribute to the current.
6.4 Charge mobility
In a cathode ray tube, electrons are emitted from a metal surface into a region with a
voltage difference maintained by a cathode and an anode. Within the tube a vacuum is
created so that electrons emitted near the anode region are accelerated by the electric
field arising from the voltage difference between the two electrodes. Due to the fact that
there is a vacuum, there are no atoms or molecules with which the emitted electrons can
collide resulting in the electrons traversing between anode and cathode without scatter-
ing. The force exerted on the electrons is proportional to the constant electric field ℰ
(a cursive ℰ is used in this section to avoid confusion with energy)
dp
F¼ þ jqjℰ; ð6:53Þ
dt
and integrating allows the velocity at time t of an electron entering the region between
the electrodes with initial or emitted velocity v0 to be expressed as
jqj
v ¼ v0 þ ℰt: ð6:54Þ
me
The velocity of the accelerated electron increases linearly with time. However, in
material systems the relationship between a charge carrier’s velocity and applied electric
field is observed to be different, at low values of electric field the relationship between an
electron’s or hole’s drift velocity is found to be
jvd j ¼ μℰ: ð6:55Þ
The proportionality constant μ gives the mobility for the charge carriers and is an
important figure of merit in transistor design. The mobility measures how the drift velocity
of electrons or holes in a material increases with applied electric field and the value of the
mobility can vary significantly for different materials. Note, however, that the drift
velocity becomes constant at a given electric field and does not increase with time.
6.4 Charge mobility 189
Figure 6.10 Random scattering events of an electron in a bulk material leading to equilibration of charge
carriers, and that work to compensate against the force due to an electric field yielding a net drift
velocity.
It is useful to consider the charge carrier velocities in a bulk material in the absence of
an applied voltage. Electrons and holes in a material are moving with velocities
associated with their kinetic energies, and the charge carriers have an energy distribution
as given by the Fermi–Dirac distribution. However, unlike the example of the electron in
a cathode ray tube, electrons in a material will undergo scattering events due to
displacement of atoms due to lattice vibrations (phonon scattering), the presence of
impurities and dopants, lattice defects, as well as with other electrons.
A series of scattering events can be visualized as generating a random walk resulting
in no net flow of charge carriers at equilibrium consistent with the condition of detailed
balance. This random motion of charges in a solid and the random scattering events at
equilibrium result in the thermal velocity of the charge carriers. Application of the
electric field biases the random walk in the direction of the force acting on the charge
carriers as depicted in Fig. 6.10 resulting in a net drift velocity.
Since the scattering events are assumed random, the probability of a scattering event
for electrons or holes will be a constant in time, so if there are n0 electrons and NðtÞ is
defined to be the number of electrons that have not undergone a scattering event, the rate
of change will be proportional to the number of electrons not having experienced a
scattering event at time t
dNðtÞ 1
¼ NðtÞ; ð6:56Þ
dt τ
where the proportionality constant τ is labeled the relaxation time. The idea of the
relaxation time as characteristic time for scattering events can be seen from the solution
of Eq. (6.56) which can be written as
NðtÞ ¼ n0 et=τ : ð6:57Þ
Thus the probability an electron scatters in a time interval dt is approximately equal to

dt=τ and the differential change in net momentum for the electrons will be
dt
dp ≈ p : ð6:58Þ
τ
Thus the decelerating force of the scattering events can be expressed as
dp p
≈ : ð6:59Þ
dt τ
For a constant applied voltage, steady state will be achieved and this will occur
when the force due to electric field balances with the changes in momenta due to
scattering
p
þ jqjℰ ¼ 0; ð6:60Þ
τ
introducing the effective mass for the electrons in the material allows the drift velocity to
be expressed as
jqjτ
vd ¼ ℰ ¼ jqjμℰ; ð6:61Þ
m
with the electron mobility given by μ ¼ τ=m ; similarly, hole mobility can be defined
taking into account their positive charge. Unlike the case for the cathode ray tube,
electrons in a solid do not experience a constant acceleration in an electric field, rather
electrons accelerate in an applied electric field and encounter scattering events. These
two mechanisms work against each other until the electrons achieve a steady state with a
constant mean drift velocity for a given electric field strength.
Up to this point, it is assumed the electrons’ kinetic energy is less than the thermal
energy. For large electric fields in a solid, the electrons achieve sufficient energy that
inelastic processes, i.e. processes such that electrons lose significant kinetic energy,
dominate. In semiconductors such as silicon and germanium, these processes are usually
associated with higher energy lattice vibrations or optical phonon scattering. In this case
as the electrons begin to accelerate, the probability of emitting a phonon is high and as a
consequence the electrons are unable to increase their net velocity with increasing
electric field due to repeated phonon emission. This phenomenon is known as velocity
saturation and Eq. (6.61) becomes invalid at high fields and a drift velocity emerges that
is only weakly dependent on the applied electric field.
A mean free path or scattering length for electron velocities corresponding to the
Fermi energy can be defined as ℓ ¼ vF τ, which is on average the length an electron at the
Fermi energy can travel before a scattering event occurs. At the very low temperatures
achievable with liquid helium, and for very, very crystalline materials, phonon scattering
lengths on the order of a few or even tens of centimeters have been reported. In weakly
doped silicon (2.8 × 1016 cm−3 phosphorus doped) at room temperature, electron
mean free paths can range from ~40 to ~50 nanometers, whereas for heavily doped
silicon (1.7 × 1019 cm−3, arsenic doped) the mean free paths are in the range ~10 to ~20
nanometers [6]. In nanoelectronics, surface effects become increasingly important as
nanostructure sizes are scaled downward and scattering related to surface chemistry and
roughness can play increasingly important roles in addition to bulk scattering mechanisms.
6.5 Scattering mechanisms
In the following various scattering mechanisms are briefly introduced, and differences
in their behavior between bulk semiconductors and semiconductor nanowires are
presented.
6.5.1 Ionized impurity scattering

Dopant atoms are introduced as substitutional impurities on a semiconductor lattice, for
example typical dopants in silicon are arsenic or phosphorous replacing a silicon atom
for n-type doping, or boron replacing a silicon atom for p-type doping. In a bulk
semiconductor, the n-type dopant introduces a state near the conduction band and the
dopant atom becomes thermally ionized, donating a mobile electron to the conduction
band and creating an immobile cation at the dopant site. Similarly a p-type dopant
introduces a state near the valence band allowing an electron to be excited creating a
mobile hole state and an immobile anion at the dopant site. In a bulk semiconductor, the
Coulomb interactions between the free charge carriers and the fixed charge dopant sites
have a pronounced effect on electron scattering and result in significant mobility
degradation. In silicon, at low doping levels of the order of 1014 to 1015 cm−3, the
electron mobility can be of the order of ~1400 cm2 V-s, and of the order of ~500 cm2 V-s
for hole mobilities which are lower primary due to larger hole effective masses.
However, at much higher doping level of 1019 cm−3 mobilities can be degraded to as
low as ~100 cm2 V-s and ~50 cm2 V-s for electrons and holes, respectively [7].
In addition to dopants, point defects such as substitutional impurity atoms incorpo-
rated into the semiconductor lattice can act as charge “traps,” or become ionized and
lose charge. Similarly, other point defects such as a single atom or several atoms can
form interstitial “clusters” that can also trap charge or be ionized. These point and
cluster defects can also have a significant influence on mobility. The charge states of
these point defects can change as a gate voltage is applied. The gate voltage sweeps the
Fermi level within a transistor channel between the conductance and valence band
edges resulting in charge transition energies that can be observed as peaks in capaci-
tance-voltage spectroscopy [8]. In addition to introducing mobility degradation, if
there are sufficient numbers of charged defects with energy levels in the band gap of
the material in the channel region, their net effect can result in a loss of electrostatic
control of the channel region by the gate voltage due to introduction of a large number
of electronic states. Hence significant charging is accompanied by small shifts in the
Fermi position within the band gap inhibiting electrostatic control of the channel by
the gate electrode, an effect referred to as Fermi level pinning.
In a semiconductor nanowire, ionized impurity scattering effects can be pronounced
as the charge carriers are restricted to a quasi-one-dimensional channel. The Coulomb
2
Conductance (q2/h)
0
–0.2 –0.1 0
Energy (eV)
Figure 6.11 Hole scattering due to p-type doping in small diameter silicon nanowires. The ideal transmission is
shown for comparison to the calculated scattering to indicate the relative effect of introducing
boron substitutional dopants into extremely small cross-section silicon nanowires (e1 nm2).
After [45].
potential due to the ionized dopants in a channel region can have a spatial extent on the
order of tens of nanometers leading to substantial effects for nanowires with diameters
below 10 nm. The electrons or holes injected into the nanowire will all “see” the
scattering potential due to the small nanowire cross-section. The effect of the ionized
dopant atoms will have different effects whether a device is being operated in inver-
sion or accumulation modes [9]. In inversion, minority carriers are drawn into the
channel. For example, the OFF state p-channel in an nMOS device becomes n-type as
the channel is “inverted” and a conducting channel is formed between the n-type
source and drain. The device’s threshold voltage is set by the p-doping of the channel
resulting in negative charge on the channel dopant sites. Hence the negative charge
carriers that are pulled into the channel in inversion see repulsive scattering sites, and
for narrow diameter narrow wires the ionized dopant sites result in significant voltage
barriers to injected minority carriers. For sufficiently small nanowire diameters ≲ 4
nm, minority carrier transmission can be strongly suppressed. In accumulation mode, the
situation is reversed in that majority carriers are pulled into the channel with the
opposing polarity of the ionized dopants. It follows that the repulsive barriers are not
formed, with the result the current conduction in accumulation is not as significantly
impacted as for an inversion device. This feature of ionized impurity scattering in
nanowires offers a potential advantage for junctionless transistor designs which rely
on accumulation in the ON state in contrast to more conventional inversion mode
devices.
Understanding charge carrier scattering off dopants in nanowire transistors remains
an area of active research. Recent experimental and computational studies suggest that
dopant atoms prefer to segregate at the surface in very small cross-section nanowires.
Hence processes for doping nanowires require further investigation as the feasibility in
which dopants can be uniformly introduced into semiconducting nanowires of diameters
of a few nanometers is unclear. In addition to the radial dependence of the dopant
distributions and the possibility of surface segregation, for small nanowire cross sections
the quantum confinement effect results in band gap widening. At small diameters the
impurity states introduced by dopant atoms may not shift with the conductance and
valence band edges, resulting in larger energy differences between the impurity state and
band edge compared to the energy levels achievable for bulk doping. There are indica-
tions that typical dopant atoms used in bulk silicon will then not be thermally ionized at
room temperature in the nanowires requiring new approaches to doping at extremely
small nanowire diameters [10,11].
6.5.2 Resonant backscattering

Ionized impurities in a lattice introduce Coulomb scattering but can also introduce
bound energy levels or “resonant states” within the energy range of electrons or holes
flowing as part of the net current. At these bound states electrons can be captured and
re-emitted, the transmission can drop to nearly zero implying that the incident charge
carriers are effectively reflected at the resonance energies. An example of a resonant
backscattering state arising from surface oxidation of a silicon nanowire is shown in
Fig. 6.12. The resulting loss of transmission within a voltage bias window results in a
reduction in current.
3
Conductance (q2/h)
0
–0.4 –0.3 –0.2 –0.1 0
Energy (eV)
Figure 6.12 Oxide scattering with resonant state. Due to oxidation of a silicon nanowire grown in the <110>
direction, surface states are introduced and are seen to give rise to surface scattering. A clear
resonant scattering state is seen as a dip in transmission between −0.4 and −0.3 eV. The resonance
in this case significantly reduces the conductance provided by the opening of a second subband.
The zero of energy is referenced to the top of the valence band and the ideal transmission (number
of channels) without scattering is shown as a dashed line. The resonant scattering acts to remove
the potential increase in conductance introduced by the opening of a second conductance channel
with applied voltage. After [34].
6.5.3 Remote Coulomb scattering

In a MOSFET, the semiconductor region is significantly influenced by an oxide
region deposited on or around the channel to electrically isolate the gate and
channel. The oxide/semiconductor interface introduces a different surface scatter-
ing mechanism but in modern transistors use of high-κ dielectrics can also result in
an increase in remote ion scattering [12,13]. High-κ dielectrics are typically oxides
containing metal atoms such as hafnium [14,15]. The oxygen atoms in the oxide pull
charge from the metal atoms resulting in the oxide appearing electrostatically as a matrix
of fixed charges, or when accounting for atomic vibrations or phonons in the oxide, as
oscillating charges. These remote charges in the oxide can significantly reduce the
mobility of channel charge carriers and this effect is referred to as remote Coulomb
scattering [12,13]. Alternatively, in semiconductor nanostructures such as a 2DEG, it
can be preferable to introduce dopants that provide charge carriers that are not located
directly within the 2DEG layer. This eliminates ionized doping in the 2DEG but there
remains the weaker scattering due to the remote immobile ionized dopant atoms. The
idea to locate a dopant layer nearby a 2DEG layer to reduce ionized dopant scattering is
successfully used to increase charge mobility in high electron mobility transistors
(HEMTs) [16].
6.5.4 Alloy scattering

Alloying semiconductors to produce materials such as SixGe1-x results in a random
distribution of atoms on the semiconductor lattice, or in the case of a ternary semi-
conductor such InxGa1-xAs on a sub-lattice. SixGe1-x is a compound semiconductor
consisting of group IV elemental semiconductors and due to the similar electronic
structures of silicon and germanium, their alloys form a diamond-like lattice. In the
alloys, lattice sites are randomly occupied by either silicon or germanium atoms with
the probability of a site being occupied by either Si or Ge in proportion to the overall
stoichiometry of the alloy. The diamond structure is locally distorted due to the
different radii of the two atoms and the random distribution of nearest neighbor
atom types. Hence scattering arises due to these two effects: the random lattice
potential arising from the random distribution of differing atom types plus scattering
caused by the perturbations due to the local distortions away from the ideal diamond
crystal structure. In the case of silicon germanium alloys the individual atomic sites are
only weakly charged due to the similar electronegativity of the constituent atoms. The
overall effect for SiGe alloys that deviate significantly from mostly silicon-like or
mostly germanium-like compositions, the alloy scattering mechanisms can provide a
substantial decrease in mobility [17]. Alloying is also commonly used as a technology
booster through introduction of strain in materials. For silicon germanium alloys
formed on a silicon substrate, the alloy lattice mismatch to the substrate will introduce
strain within the alloy layer. A silicon channel can be sandwiched between alloyed
source and drain regions to create strain in a transistor’s channel. Intentionally
introducing strain can be used to lift degeneracies in the valleys or energy minima in
the electronic structure of the semiconductor channel, thus reducing intervalley scat-
tering and thereby resulting in an increase in charge carrier mobility.
In a compound semiconductor such as gallium arsenide (GaAs) with a zinc blend
crystal structure, the group III atoms and group V atoms arrange on two distinct sub-
lattices. Charge is transferred from the group III atoms to group IV atoms in a Lewis
picture of the chemical bonding, hence in GaAs the gallium atoms are said to form a
cation sub-lattice and the arsenic atoms form an anion sub-lattice. The ternary compound
GaxIn1-xAs also crystallizes in the zincblende-like structure with the indium and gallium
atoms distributed randomly on the cation sub-lattice. The unit cell size of the ternary
compounds varies with composition and takes on values intermediate to the lattice
constants of the binary compounds [18]. The cubic lattice constant a for the zinc blend
structure when alloying can be estimated by Vegard’s law
a ¼ ð1 xÞaInAs þ x aGaAs ; ð6:62Þ
where aInAs ¼2.623 Å and aGaAs ¼ 2.448 Å are the unit cell parameters of the parent
binary compounds. Vegard’s law is a simple approximation that assumes the lattice
constant can be interpolated across a range of compositions based on estimates of “atom
sizes.” The use of alloying in III-V compounds is being explored to optimize electron
mobility in MOSFETs and to match the lattice constant of the grown material to
commonly used substrates.
6.5.5 Surface scattering

In low dimensional systems such as two-dimensional electron or hole gases (2DEG,
2DHG) and “quasi”-one-dimensional nanowires, the surface-to-volume ratio rapidly
increases as dimensions are reduced through introduction of confinement potentials.
Hence the effect of bonding at the semiconductor/oxide interface and disorder in the
bonding at the interface can have a proportionately larger influence on carrier scatter-
ing relative to larger, more bulk-like transistor structures. A particular cause of surface
scattering between a semiconductor and an oxide is the different charge states of
surface atoms due to differences in the local chemical bonding environment.
Figure 6.14 provides a graphical depiction of the different charge states that surface
silicon atoms can be found in due to interface, bridging and back bonds with oxygen.
The different charge states can give rise to different scattering and at a typical
oxide/semiconductor interface an ensemble of such bonding motifs can be found.
The collective effect of the different local chemical bonding environments gives rise
to surface scattering.
6.5.6 Surface roughness

Surface roughness scattering is caused by interfacial disorder on a length scale lower
than several atomic lengths and arises from the fact that typical semiconductor/oxide
interfaces are not abrupt on an atomic level. The position of the interface along a channel
O O O O
Si+1 Si+1 Si+2 Si+2

O
(a) (b)
O O
O
O
Si+2 Si+3
O
Si+4
O
Si+1
O O
(c) (d)
Figure 6.13 Schematic representation of oxidation states of silicon atoms at a silicon/oxide interface. Silicon
maintains four-fold coordination as in the diamond lattice but with n neighboring oxygen atoms
attracting electrons leaving a silicon atom in a +n formal charge state. The bonding examples
shown can be found at or near the interface between a semiconducting channel and a gate
dielectric. Hence surface atoms can be found in various charge states leading to a random surface
potential that gives rise to electron scattering. (a) Silicon atoms at an interface forming a single
covalent bond to oxygen atoms in the oxide leaving surface Si atoms in +1 formal charge state. (b)
Same as in (a) but with the addition of a bridging oxygen bond at the interface leading to surface Si
atoms in a +2 formal charge state. (c) Oxygen atoms can diffuse into the substrate creating back
bonds, in this configuration creating Si atoms in +1, +2, and +3 charge states. (d) A silicon atom in
silicon dioxide with four-fold coordination with oxygen atoms leading to silicon atoms in a +4
charge state.
axis can vary by several atomic layers as directly observed in high-resolution transmis-
sion electron micrographs (HR-TEM). This atomic scale “roughness” appears to be
random and gives rise to random fluctuations in the surface potential profile as seen by
the charge carriers, which results in carrier scattering. Considering non-ideal interfaces
in silicon nanowires exhibiting tapering [19,20,21] reveals that not only is the electron
scattering influenced, but also localized electronic states can arise due to the surface
topology. In effective mass simulations of nanowire transistors, roughness is introduce
by “slicing” along the axis of a nanowire and introducing random axial displacements to
the slices. Repeating transport simulations for an ensemble of randomly generated
channel configurations allows for estimates in the variation in transistor current–voltage
characteristics such as threshold voltage due to surface roughness.
6.5.7 Electron–phonon scattering

Atomic displacements in a crystal or vibrations are quantized and the collective quan-
tized motion acts like quasi-particles known as phonons. Just as charge carriers can
(a) B B
A A A
B B
A A
(b)
A A A
B B B B
Figure 6.14 Examples of (a) acoustic and (b) optical phonons in a one-dimensional lattice with two atom types.
Acoustic modes resemble the displacement of atoms due to a pressure wave in a gas, and hence the
analogy to sound or acoustic waves. Optical modes involve higher energy vibrations whereby
different sets of atoms oscillate against one another. If there is polar bonding in a solid, optical
modes can be excited by light through optical absorption, and hence the labeling as optical
phonons.
scatter off an electrostatic potential profile, they may also scatter with phonons. In the
case of a single electron or hole scattering from a fixed potential, scattering conserves
energy whereas in electron–phonon interactions, energy can be exchanged resulting in
inelastic scattering. Electron–phonon (e–ph) scattering is an important process in semi-
conductors and plays a decisive role in limiting a material’s mobility. As can be
anticipated, as a material is heated the lattice vibrations increase with more phonons
becoming occupied at higher temperatures resulting in increased e–ph scattering. In
semiconductors with a diamond-like structure there are two atoms in a primitive lattice
cell, the degrees of freedom associated with the two atoms give rise to two types of
phonons: acoustic and optical. In Fig. 6.14, examples of acoustic and optical phonon
modes in a one-dimensional diatomic chain are represented. For materials such as silicon
and germanium, acoustic phonon modes have energies of a few meV to 10 meV, whereas
optical phonons can have energies of several tens of meV, and it is these higher energy
optical modes that cause significant inelastic scattering at higher temperatures in bulk
semiconductors. Phonons are quasi-particles and carry momentum. As electrons and
phonons collide and scatter, their energy exchange gives rise to momentum differences.
This implies an electron’s momentum can change allowing scattering between different
energy valleys in the electronic band structure due to acoustic or optical phonon
scattering. These scattering process are divided into f-type and g-type processes
(0,0,kz)
intervalley
f scattering
(kx,0,0)
intervalley
g scattering
(0,ky,0) intravalley
Figure 6.15 Electrons scattering off of phonons near the energy minima of silicon. Three distinct processes can
be defined: (a) intravalley scattering where the change in momentum is low enough that the final
electron state remains in the same energy minimum. In silicon, intravalley scattering is due to
acoustic phonon modes. (b) f type phonon intervalley scattering where the electron’s change in
momentum is large enough to scatter into a neighboring valley along a different crystal axis.
Optical phonons and to a lesser extent acoustic phonons contribute to f type scattering. (c) g
phonon scattering whereby the momentum change in a scattering event is large enough to scatter
an electron’s momentum vector along a single axis, and again the optical phonons dominate but
with acoustic phonons also playing a role in silicon.
depending on the nature of the electron’s momentum change during a scattering event, as
shown graphically in Fig. 6.15.
In nanowires, confinement effects influence the band dispersion of phonons in a similar
fashion to what is observed for electronic structures [22,23,24,25]. Surface chemistry is
found to have a relatively small influence on e–ph coupling, whereas the reduced dimen-
sionality in the nanowires significantly alters the character of the phonons and their
scattering with electrons. Notably the application of bulk models for a specific orientation
or isotropically averaging bulk models to define effective couplings does not provide a
reasonable description of e–ph scattering when applied to small diameter nanowires. The
consequences of quantum confinement for physical properties such as scattering lengths
and mobilities are significant, although it should be noted that it can be the effective masses
in the nanowires rather than the relaxation times, which can have the dominant effect in
predicting a nanowire’s mobility. The process of e–ph scattering also governs heat transfer
as it is the lattice vibrations that transmit heat [1,2]. The study of nanoscale heating relates
both to the ability of removing heat from a device and power dissipation. Hence as charge
carriers flow through a device and lose energy by scattering with phonons, the nanowire
heats and increases the probability of additional scattering events.
6.5.8 Carrier–carrier scattering

In approximations such as the Kohn–Sham implementation of density functional theory
or as in the Hartree–Fock approximation, electrons move in the mean field of all
electrons. For the Hartree–Fock approximation, the Coulomb and exchange interactions
exactly cancel resulting in an electron moving in the mean field of “all other electrons.”
This cancellation is not exact in approximate DFT giving rise to many of the errors
associated with the approximate density functionals commonly applied in electronic
structure calculations. However, for both the Kohn–Sham and Hartree–Fock equations,
a single-electron wave equation is solved taking into account the effect of other electrons
as an averaged or mean field approximation. This mean field problem is solved self-
consistently, that is an approximation to the single-electron wave functions is generated
and the potential arising from the set of occupied electron states is calculated. This gives
rise to new single-electron wave functions, which in turn give rise to a new potential.
The Kohn–Sham and Hartree–Fock equations are iterated until the potential generated
from a set of electron wave functions yields the same set of wave functions used in the
construction of the potential. At this point in the calculation, the single-electron wave
functions and the potentials are said to be “self-consistent”: a solution for the single-
particle eigenfunctions and eigenvalues has been found. These are the single-particle
solutions, but what if a wave function for all the electrons is desired? The most common
approach is to take a product of the single-particle wave functions and to anti-symme-
trize them. Anti-symmetrization implies that the many-electron wave function will
change sign if two electrons are exchanged as required to enforce the Pauli exclusion
principle, which mandates that two electrons do not occupy the same state, the condition
that leads to Fermi–Dirac statistics describing the thermal occupation of electron states.
Thus the simplest many-electron wave function is constructed as an anti-symmetric
product of single-electron wave functions, or a Slater determinant. The Slater determi-
nant that yields the best approximation to the charge density satisfies the Kohn–Sham
equations, and the Slater determinant resulting in the lowest energy yields the Hartree–
Fock approximation.
Even though the Slater determinant is a many-electron wave function and is anti-
symmetric, it is a product of single-electron wave functions. However, the Coulomb
potential between two electrons is of the form
1
vðx; yÞ e ; ð6:62Þ
jx yj
with the result that the Hamiltonian operator for the many-electron problem does not
have exact solutions that are product wave functions. Expressed in the language of
differential equations, the solution to the problem is not separable. For example if in the
Kohn–Sham equations the exact energy functional was known, the exact total energy
would be predicted but the single determinant wave function built from the Kohn–Sham
orbitals remains only an approximation to the correct many-electron wave function.
Hence although a single Slater determinant approximation may provide a good approx-
imation to a wide range of properties for many-electron systems, it cannot provide an
exact solution to the many-electron wave function. Corrections beyond the single Slater
determinant solution are named electron correlations and describe electron–electron
scattering beyond the mean field approximation. Electron correlations are notoriously
difficult to describe, but their effects can be critical in many systems and become
increasingly important for systems approaching a few nanometer length scales and for
systems where there are many electronic states that are close in energy or “quasi”-
degenerate. In transition metal oxides, the correct band structure is often such that it
cannot be correctly described theoretically without going beyond mean field theories
and for very small structures such as considered in quantum dots or molecular electro-
nics, electron correlations can be critical for an accurate description of the physics. For
example, phenomena such as Coulomb blockade require treatment of electronic correla-
tions beyond a mean field theory.
Simulations including electron–electron scattering are more the exception than the
rule in nanowire transistor design, although there are indications that these effects can
become increasingly important in scaled nanoelectronics. In strictly one-dimensional
systems electrons cannot easily pass one another and the motion of the electrons
becomes a collective correlated excitation. The electrons in this case form a
Tomonaga–Luttinger fluid [26] and the collective excitations do not obey Fermi–
Dirac statistics but instead follow Bose–Einstein statistics. In this regime, electron
tunneling across a one-dimensional wire becomes suppressed [27]. For small nanowire
systems approaching molecular scales, electron–electron interactions must be accu-
rately described for even a qualitative description of the device physics. Methods
incorporating scattering boundary conditions which are formulated in terms of single
electrons as in Section 6.2 but compatible to the many-electron problem have been
developed that allow for a description of explicit electron–electron scattering [28];
these techniques have been applied to molecular tunnel junctions for which experi-
mental validation is available [29,30].
6.6 Scattering lengths
6.6.1 Scattering lengths and conductance regimes

The idea that mobility is governed by scattering was introduced and a survey of key
mechanisms that give rise to scattering events that can be experienced by charge carriers
in a nanowire were outlined. For charge carriers with a given drift velocity vd and
relaxation time τ, it is natural to define a length for which on average a charge carrier can
travel without experiencing a scattering event. Labeling this length a mean free path, it
may be expressed as
lMFP evd τ: ð6:63Þ
Different scattering mechanisms are characterized by different mean free paths,

and from these a collective effective mean free path can be defined. However, it is
useful to differentiate between elastic and inelastic mean free paths. The symbol
lMFP will be reserved for elastic processes whereas the symbol lθ will be used to denote
the characteristic length for inelastic processes. For Hamiltonian operators that conserve
energy, the electronic wave function is phase coherent, whereas for inelastic processes in
which energy is not conserved the phase of the wave function changes, breaking
coherence.
To define either a low field or saturation limited mobility requires many scattering
events to be averaged to establish the condition that the increase in carrier velocity due to
the presence of an electric field is balanced against many randomizing scattering events
resulting in the average net velocity remaining constant. Electron and hole mobilities are
as a consequence defined as ensemble or statistical averages over many dynamical
events. In the following, the effect of multiple scattering events will be considered to
relate transmission, mean free paths, and resistance for a conductor of length L. But first,
it is useful to differentiate between the ballistic, diffusive, and localization regimes in
terms of characteristic lengths.
Diffusive behavior is found when a length of a semiconductor nanowire or any
material is longer than the mean free paths for scattering events, but shorter than the
length scale ξ, which defines electron localization in a system of random scatters. In the
diffusive regime, charge transport can be described by semi-classical models such as
the Boltzmann transport equation and the electric current follows Ohm’s law.
The ballistic regime occurs either when there are no scattering sites such as in a
perfect crystal or when the length of a semiconductor nanowire or other material is
shorter than the mean free path for elastic or inelastic scattering events. The ballistic
regime also implies that the localization length ξ, to be discussed next, is also longer
than the length of the nanowire L. The ballistic regime is characterized by electrons or
holes propagating unimpeded through a material. A ballistic conductor with a single
channel is characterized by the quantum of conductance.
Anderson localization results in the presence of randomly distributed defects in the
absence of phase breaking or inelastic scattering events [31]. As electrons are reflected
from the defect sites, interference effects can result in standing waves. This implies
the electrons are localized by the scatterers and are no longer propagating, and hence
will not conduct current. This regime is described by the localization length ξ and
dominates when ξ < L < lθ such that inelastic scattering does not play a role. Anderson
localization typically occurs for a high density of scattering sites and the localization
length characterizes the region in which electrons have become trapped due to multiple
scattering events. In the Anderson localization regime, resistance increases exponen-
tially with the length of a nanowire or conductor.
6.6.2 Multiple scattering in a single channel

Scattering has been discussed in the context of single physical events. But in devices or
material samples with spatial extent much larger than scattering mean free paths,
multiple-impurity scattering occurs and determines the properties of a material. These
multiple scattering events also give rise to the overall transmission coefficient for
transport across a region in a material. For an ideal conductor with no scattering and
NC channels, the conductance is given by the contact resistance per channel as demon-
strated in Section 6.3:
Figure 6.16 Ideal and scattering transmissions for an arbitrary system. The ideal transmission is shown as the steps
given by the lines. For an ideal transmission channel the transmission is constant and additive. Hence
the first ideal channel onset is at E1 and a second channel is introduced at E2 . The transmission
with scattering is shown for the rounded curves (with solid fill underneath the curves). The
difference in the ideal transmission and the transmission with scattering at a given energy is a
measure of the scattering resistance introduced into a conductance channel defined in Eq. (6.66).
2q2
G ¼ NC G0 ¼ NC ; ð6:64Þ
h
which in the presence of scattering becomes

2q2
G ¼ NC G0 T ¼ NC T: ð6:65Þ
h
Figure 6.16 compares an ideal transmission curve without scattering and with scatter-
ing present, and at a given energy the difference between the two curves represents the
reduction in the conductance due to scatterers. Resistance is the inverse of conductance,
and the resistance can be partitioned as
1 h 1 h 1 h 1 1T
R¼ ¼ 2 ¼ 2 þ 2 : ð6:66Þ
NC G0 T 2q NC T 2q NC 2q NC T
Written this way, the contact resistance associated with ideal channels in the absence of
scattering is given by the first term and is separated from the scattering resistance
occurring within each channel as described through the second term. It is the second
term describing the scattering resistance that results in the reduction between the ideal
transmission and the transmission with scattering in Fig. 6.16.
To understand how the scattering resistance arises in the case of multiple scattering
sites in a one-dimensional system, it useful to first examine the case of two scattering
sites in series with transmissions and reflections T1 þ R1 ¼ 1 and T2 þ R2 ¼ 1 respec-
tively. The scattering sites govern the probability an electron (or hole) is transmitted or
reflected as graphically shown in Fig. 6.17.
(a) T1 T2
incident
T1
(b)
R2 T2
incident R1
(c) T1
R2
R1 T2
incident R2
R1
Figure 6.17 Two scattering sites in series. The various probabilities for an electron to be transmitted through
the two scattering sites denoted by ×s are given for the lowest order processes. (a) No reflection
between scattering sites. (b) Multiple reflections: the electron bounces back and forth once
between the scattering sites. (c) Multiple reflections: the electron bounces back and forth twice
before being transmitted.
As an incident electron approaches the two sites, the electron can pass through with
probability T1 T2 : Alternatively the electron can pass the first site with probability T1, be
reflected back at the first site with probability R2, and be reflected again by the symmetric
scatterer at site 1 with probability R1, and then be transmitted past the second site with
probability T2. The overall probability for the process is T1 R2 R1 T2 ¼ T1 T2 R1 R2 .
Multiple reflections can arise between the two scattering sites leading to processes
such as T1 R2 R1 R2 R1 T2 ¼ T1 T2 ðR1 R2 Þ2 , T1 R2 R1 R2 R1 R2 R1 T2 ¼ T1 T2 ðR1 R2 Þ3 and so
forth. The total probability for transmission across the two scattering sites is then
T12 ¼ T1 T2 þ T1 T2 R1 R2 þ T1 T2 ðR1 R2 Þ2 þ . . . ; ð6:67Þ
which can be summed to give

T12 ¼ T1 T2 =ð1 R1 R2 Þ: ð6:68Þ
Recalling the relationship between the transmission and reflection probabilities and
re-arranging, Eq. (6.68) can be re-expressed as
1 T12 1 T1 1 T2
¼ þ : ð6:69Þ
T12 T1 T2
Comparing with Eq. (6.66), it is found that individual scattering sites within a channel
add as series resistances. It follows for the transmission for N identical scattering sites
each with independent transmission T that the corresponding expression is
1 TN 1T
¼N ; ð6:70Þ
TN T
which yields the total transmission in terms of the individual scattering sites as
T
TN ¼ : ð6:71Þ
Nð1 TÞ þ T
This form of the transmission has been arrived at ignoring interference effects between
the scattering sites, implying the assumption that transport is not in the localization
regime.
The average distance between the N scattering sites is lS ¼ L=N for a conductor of
length L allowing the transmission to be written as
lS T=ð1 TÞ
TN ¼ : ð6:72Þ
L þ lS T=ð1 TÞ
For typical values of transmission for single dopants or point defects, the ratio of
lS T=ð1 TÞ will be of the order of the mean free path and if L
lMFP , the total
transmission of a series of scattering sites each with transmission T can be taken in a
first approximation as
lMFP lMFP
TN ¼ ≈ : ð6:73Þ
L þ lMFP L
The contact resistance per channel is RC ¼ h=2q2 and defining the scattering resis-
tance in a single channel with N scattering sites per channel as RS ¼ hð1 TN Þ=2q2 TN ,
the resistance Eq. (6.66) is written as
1
R¼ ðRC þ RS Þ: ð6:74Þ
NC
This form emphasizes that the contact and scattering resistance for a single channel add
as series resistances but that the resistances of the NC channels are to be taken in parallel.
Equation (6.73) enables the ensemble resistance for identical scatterers to be related to
the transmission of a single scattering site and the elastic mean free path of the charge
carriers. For long conductors, the relationship becomes
1 h L
R≈ RC þ 2 ; ð6:75Þ
NC 2q NC lMFP
exhibiting the linear increase in resistance with increasing length characteristic of

Ohmic conductors. Recalling that the result is arrived at assuming L
lMFP implies
that many scattering events are required before Ohmic behavior emerges. This approach
Table 6.1 Estimates of the number of silicon atoms, length along the long axis in number of silicon
atoms, and number of dopant atoms for an approximate doping of 5 ×1019 cm−3
NW dimensions/nm3 Atoms/nanowire volume Atoms/nanowire length Dopant atoms/nanowire
60 × 20 × 20 1 200 000 222 1200

30 × 10 × 10 150 000 111 150
15 × 5 × 5 18 750 55 ~20
6×2×2 1 200 22 ~1
has been taken in predicting scattering resistances in nanowires with random distribu-
tions of scattering sites based on knowledge of a single scatterer [32,33].
If only a few dopants or point defects are present in a nanowire, the charge transport is in
an intermediate regime between ballistic and diffusive, or “quasi-ballistic.” In Table 6.1,
the number of dopant atoms compared to the total number of atoms present in a rectangular
nanowire of dimension 3a a a with a ¼ 20; 10; 5; and 2 nm and for the assumption
of a relatively high doping concentration level of 5 1019 dopants/cm3 is given. The
resulting analysis is straightforward to scale. If the dopant concentration is increased by
a factor of 10, the number of dopants within the nanowire will increase by a factor of 10,
and vice versa for a reduction in doping concentration by one order of magnitude.
This simple estimate of the number of atoms and dopant atoms in a silicon nanowire
channel is representative of transistors being considered in modern nanoelectronic
technologies, and also reveals that the channel dimensions are of the same order or
smaller than typical mean free paths in bulk silicon. Typically for ionized dopant
scattering the mean free path is roughly of the same order as the distance between
dopant atoms which can range from several 100 nm for low doping to less than 10 nm at
extremely high doping levels. In nanowires, scattering lengths for surface and electron–
phonon scattering can be significantly shorter than in bulk silicon and values of the order
of tens of nanometers have been reported in various cases [25,34]. However, as transistor
critical dimensions reduce to below 10 nm, it becomes clear that the use of macroscopic
quantities such as electron and hole mobility and drift velocity are no longer strictly
applicable as transistor dimensions become of the same length scale as the distance
between scattering events. For transistor cross-sections of a few nanometers and for gate
lengths less than 10 nm, e–ph and ionized impurity scattering effects are less likely to
significantly impede current flow as only a few scattering events can occur within a
channel region, although the influence of these scattering mechanisms can still be non-
negligible. Conversely as the surface-to-volume ratio in small cross-section nanowires
increases with shrinking transistor dimensions, surface scattering effects become
increasingly dominant. For ultra-scaled nanoelectronic transistors, fewer scattering
events within the active device region imply a greater correlation between a transistor’s
specific atomic structure and geometry in relation to current–voltage characteristics. As
a “statistical averaging” over many scattering events within a single device structure is
absent, the use of smaller transistor geometries leads to larger device to device variations
due to dopant fluctuations, surface morphology, and isolated electron–phonon scattering
events.
6.7 Quasi-ballistic transport in nanowire transistors
At critical dimensions of a few nanometers, quasi-ballistic or weak scattering transport

describes many of the essential features of charge transport in nanowire transistors.
Although device operation in terms of terminal currents appears similar in many respects
between macroscale and nanometer-scale field-effect transistors, the underlying physics
can be quite different between the two. In the following some features of transistor
operation highlighting device physics that emerge on the nanometer-scale are presented
for a simple model of a nanowire transistor. The model is assumed to be strictly one-
dimensional with a single-electron band in the drain and source electrodes. The potential
in the channel is assumed to be piece-wise linear. The model is an oversimplification of
realistic transistor structures; however, it is useful for demonstrating some of the features
for understanding nanowire transistor operation at small cross-sections (< 36 nm2) and
for gate lengths below 10 nm.
For an n-channel MOSFET in the OFF state, an idealized conduction band profile is
represented in Fig. 6.18(a). A gate voltage is applied to generate the potential barrier
along the channel impeding the flow of electrons from the source to drain. That current
flow is zero is reflected schematically in Fig. 6.18(a) as parabolic energy bands in the
source and drain are occupied by electrons up to the Fermi energy but with energies
lower than the electrostatic potential barrier in the channel and from the fact there is no
drain–source voltage bias. At normal operating temperatures, the source and drain
electrons will be occupied according to the Fermi–Dirac distribution function as in
Fig. 6.2, but for simplicity the electrons are shown as being occupied up to only the
source and drain Fermi levels. Only the portion of the dispersion with electron momenta
directed into the channel is shown to emphasize that it is only the incoming electrons that
need to be considered for charge transport. With Fig. 6.18(b), the same nanowire
transistor is shown but now with a drain–source voltage difference VDS that is lower
than the OFF state barrier created by the gate voltage VG . Although there is now a
potential voltage difference between the source and drain electrodes, charge carriers are
impeded to flow into the channel from the drain as these electrons are blocked by an
increase in the electrostatic barrier relative to their energies. Tunneling from the drain is
suppressed as there are no available states within the source electrode. The source
electrons have an increased energy relative to the drain electrons, but the electrostatic
potential in the channel is still sufficient to prevent significant charge flow from source to
drain. However, the possibility exists to tunnel from the source to drain as the source
electrons are shifted higher in energy with respect to the drain electrons, and there are
empty states in which to tunnel. The tunnel probability is largely determined by the gate
length, barrier height, effective masses of the charge carriers, and energy of the charge
carriers incident on the potential barrier.
This simplified nanowire transistor model may be considered as the limit of the top-
of-the-barrier model introduced in Chapter 1 for the case that the barrier maximum
defines the source which remains in equilibrium with the source electrode, and the
scattering resistance in the channel described in Section 6.6.2 is eliminated, i.e. transport
(a)
(b)
(c)
(d)
Figure 6.18 Idealized nanowire field-effect transistor electronic structure with a single band model in the drain
(left) and source (right) electrodes. (a) A gate voltage VG is applied at zero drain–source voltage
VDS ¼ 0 such that the electrostatic barrier within the channel region blocks charge carriers from source
and drain producing an OFF state for current flow. (b) The OFF state for the transistor is maintained but
at finite drain–source voltage VDS ≠ 0. (c) Maintaining the finite drain–source voltage, the gate voltage
is applied to lower the channel electrostatic barrier. Electrons above the electrostatic barrier can
“flyover,” whereas electrons near the maximum of the electrostatic barrier can tunnel through allowing
current flow signaling the onset of the ON state. (d) The gate voltage VG is applied to turn the device
fully “ON.” As the gate voltage is increased, more source electrons are able to flow across the
channel. Note that as jqjVDS becomes larger than EF the bottom of the source conduction band
rises above the filled levels in the drain and a current “saturation” is achieved.
in the channel is ballistic. Furthermore, an averaged injection velocity is not invoked and
the velocity of the injected carriers is directly determined by the Fermi distributions in
the source and drain regions.
In Fig. 6.18(c), the gate voltage is applied to lower the electrostatic barrier in the
channel to point to where current begins to flow and the transistor is in the “threshold”
region. If the gate voltage is applied to effectively eliminate the electrostatic barrier in
the channel while holding the drain–source voltage VDS constant, the drain–source
voltage across the channel results in a conduction band profile akin to that sketched in
Fig. 6.18(d). In this case and with the idealization that all electrons will be transmitted
Figure 6.19 A triangular potential barrier. Analysis of the tunneling through a triangular potential barrier
allows for a preliminary analysis of source–drain leakage currents in short-channel nanowire
transistors.
from source to drain with unity transmission, all electrons entering the channel will be
accelerated across the transistor by the force due to the channel electric field without
scattering. This is a highly idealized scenario as even in the case of a potential ramp,
electrons incident on the voltage ramp across the channel will be partially reflected,
although for more realistic, smoother voltage profiles this effect is not as pronounced
[35]. As a first crude approximation, the channel resistance will be given by the inverse
of the conductance quantum and number of “channels.” The conductance quantum is
independent of material parameters, and in the absence of scattering in an ultra-short
channel and without a tunnel barrier, the current will only depend on the transmission
(taken to be unity at each incoming electron energy in this example) and the number of
channels which is related to the DoS. Note that increasing VDS beyond the point
where the bottom of the source conduction band rises above the drain Fermi energy
will not result in increased current. Hence the transistor is in “saturation” although in a
very different sense from velocity saturation limited mobility occurring in macroscale
field-effect transistors.
Intermediate to the fully OFF state and the fully ON state, the gate and drain–source
voltages are applied to control current flow between these two limits. In Fig. 6.19(b),
the electrons from the source must be able to tunnel across the entire channel to
generate a current and for a well-designed transistor this process is suppressed.
However, as the gate voltage is applied to reduce the electrostatic barrier at fixed
VDS , electrons at higher energies in the source impinge on a potential profile that can be
approximated by a triangular barrier with a width that can become significantly shorter
than the lithographic channel length. Tunneling through a triangular barrier, or Fowler–
Nordheim tunneling, is invoked as a simple model for describing currents across gate
oxides, surface emission, and for analysis of scanning tunneling microscopy. Various
approximations exist describing tunneling through and for emission over (or “flyover”) a
triangular barrier [36]. A semi-classical method for estimating a solution for the
Schrödinger equation known as the Wentzel–Kramers–Brillouin (WKB) approximation
commonly applied to describe Fowler–Nordheim tunneling yields a transmission coef-
ficient as
pffiffiffiffiffiffiffiffiffiffiffi 3=2 !
4 2m qϕB
T ∝ exp : ð6:76Þ
3ℏΕ
Unlike the approximation to the fully ON model whereby electron transport is fully
ballistic and there is no tunneling, in the intermediate voltage bias ranges there is a
contribution to the current from tunneling which depends directly on the effective mass,
a material property, and the voltages and electric fields Ε that are to a large extent
governed by transistor design such as the gate induced potential barrier ϕB and the
electric field in the channel Ε due to the drain–source voltage. The gate voltage can be
applied to increase the potential barrier height and transmission across the channel is
rapidly suppressed as seen through Eq. (6.76). At a fixed barrier offset between the
channel and source, a larger drain–source voltage creates a larger electric field in the
channel which acts to narrow the width of the tunnel barrier resulting in increased
current flow. At low drain–source voltage, the slope of the potential barrier is lower
implying a wider tunnel barrier and a strongly suppressed tunnel current. In addition to
the voltages applied to the device, the effective mass of the charge carriers also
influences the behavior of the device in the tunneling regime. For low effective masses,
it is easier for electrons to tunnel through the triangular potential barrier and it becomes
easier to turn the transistor ON, but likewise more difficult to achieve a low OFF current.
The previous discussion can be summarized as stating that in a fully ballistic
regime, the DoS in the source region will determine the maximum current drive. As a
transistor is turned OFF, the gate potential and the channel electric field work against
each other in determining the current–voltage characteristics with a higher gate voltage
VG increasing the barrier height ϕB , while increasing drain–source voltage VDS increases
the channel electric field resulting in a narrower tunnel barrier. The above discussion
neglects the thermal distribution of the charge carriers in the drain and source resulting in
thermal emission of electrons over the potential barrier, and in ultra-scaled nanowire
transistors tunneling and thermionic emission currents can be of comparable
magnitudes.
The potential barrier across a nanowire channel is smoother than the piece-wise
linear model presented and Fig. 6.20 presents a more realistic channel voltage
profile. However, much of the analysis presented with minor modification remains
valid. Note the analysis presented assumes a single parabolic band in the source drain
regions, so implicitly this presentation is restricted to low voltages although exten-
sion of the model to include multiple energy bands is possible with the underlying
behavior and conclusions remaining applicable. Although very similar current–
voltage characteristics compared to field-effect transistors on the macro-scale are
observed, it should be highlighted that through barrier tunneling plays a much larger
role in ultra-scaled nanowire transistors. For quasi-ballistic transport, the saturation
in current is related to the energy width of the occupied source conduction band and
not to high electric fields causing velocity saturation that limits transistor operation
for longer length scales where diffusive transport dominates. To ensure high ON
currents, low effective masses and a large density of states in the source is desired.
U
x source
drain
Figure 6.20 The piece-wise linear model of Fig. 6.18 represents a highly idealized view of the channel
potential profile and a more realistic potential profile in one dimension is shown for reference.
However, the basic physical principles presented carry over to more realistic potential profiles and
for more realistic device structures.
However, to suppress tunneling in the OFF state requires large effective masses, and
large gate and low drain–source biases. Hence transistor design remains, as for
macro-scale transistor design, a strongly coupled trade-off against competing mate-
rial and geometry constraints but with new physical mechanisms underpinning
device operation on the nanometer-scale.
6.8 Green’s function treatment of quantum transport
Green’s functions are commonly used in engineering and science to understand the
influence of a “source” at one position and time on other positions and at other times.
Green’s functions are often invoked to describe the effect of an electron, hole or other
particle injected into a system and to follow the particle’s trajectory and interactions with
other potential fields or scattering with other particles. Green’s functions are applied to
study electron and hole transport in nanostructures with an advantage that the effects of
elastic and inelastic scattering can be included and that the method can be formulated for
open system boundary conditions [37, 38] that give rise to measured current–voltage
characteristics in nanostructures. Importantly, Green’s function techniques are relatively
straightforward to implement numerically. The use of Green’s functions have been
thoroughly introduced in the literature [39,40] and for more advanced textbooks on
this subject, the reader is referred to the Further reading listed at the end of this chapter.
In the following, a brief background to the use of the Green’s function approach in
quantum transport is presented.
6.8.1 Green’s function for Poisson’s equation

Before considering the use of Green’s function in transport, its use in the solution of
Poisson’s equation is considered to highlight the main mathematical ideas for the general
use of the method. Poisson’s equation in differential form is
q
∇2 V ð~
rÞ ¼ LV ð~
rÞ ¼ ρð~
rÞ; ð6:77Þ
ε0
where V ð~rÞ is the electrostatic potential arising from a charge distribution qρð~
rÞ, and ε0
is the permittivity of free space. The equation has been written in an intermediate form
with a linear operator defined to be L ¼ ∇2 . An integral solution for Eq. (6.77) is sought
of the form
ð
q 0 0 0
V ð~rÞ ¼ Gð~ r Þd 3 r :
r Þρð~
r;~ ð6:78Þ
ε0
Equations (6.67) and (6.68) imply that

0 0
∇2 Gð~ r Þ ¼ δð~
r;~ r ~
r Þ; ð6:79Þ
or in operator form the equation for the Green’s function can be expressed as
LL1 ¼ 1; ð6:80Þ
stating the Green’s function is the inverse of the linear operator relating charge to
potential in Poisson’s equation. The solution for the Green’s function is found from
the relation
1
∇2 0 ¼ 4πδð~r ~ r0Þ ð6:81Þ
j~
r ~rj
leading to
1 1
Gð~ r 0Þ ¼
r;~ 0 : ð6:82Þ
4π j~
r ~rj
The integral form of Poisson’s equation Eq. (6.78) is now written as

ð
q r0Þ 3 0
ρð~
V ð~
rÞ ¼ 0 d r ; ð6:83Þ
4πϵ 0 j~
r ~ rj
which is recognized as Coulomb’s law for a continuous charge distribution. The Green’s
r 0 to the electrostatic potential at position
function relates the charge located at position~
r, and the integration sums over all charges to yield the net electrostatic potential at a
~
given point.
6.8.2 Green’s function for the Schrödinger equation

Similarly, the Green’s function for the Schrödinger equation provides the probability
amplitude for a particle initially found at a point in space and time ðxi ; ti Þ to be found at a
final time at ðxf ; tf Þ. Unlike in Poisson’s equation where the sources are the electric
charges giving rise to the electrostatic potential, in the case of the time-dependent
Schrödinger equation the wave function in the past acts as a source for the future. The
Green’s function that describes the propagation of the probability amplitude into the
future from a point source is the retarded Green’s function, which is required to satisfy
the time-dependent Schrödinger equation
∂
iℏ GR ðxf ; xi ; tf ; ti Þ ¼ HGR ðxf ; xi ; tf ; ti Þ for tf > ti ; ð6:84Þ
∂t
with boundary condition

lim GR ðxf ; xi ; tf ; ti Þ ¼ iδðxf xi Þ: ð6:85Þ
tf →ti þ0
For a time-independent Hamiltonian H with eigenvalues En and eigenfunctions ψn ðxÞ,

it is straightforward to verify that
X
GR ðxf ; xi ; tf ; ti Þ ¼ i exp½iðtf ti ÞΕn =ℏψn ðxf Þψn ðxi Þ ð6:86Þ
n
is a solution to the time-dependent Schrödinger equation Eq. (6.83). Noting that a

complete set of eigenfunctions has the property that
X
ψn ðxf Þψn ðxi Þ ¼ δðxf xi Þ; ð6:87Þ
n
it is seen that this form of the retarded Green’s function satisfies the boundary
condition as tf ←ti þ0, which is a shorthand notation that ti approaches tf from
the “future” denoted by “+0.” The retarded Green’s function is taken to be GR ¼ 0 for
tf < ti : Similar relations hold for defining an advanced Green’s function if tf < ti ;
however, for the present discussion the focus is on the retarded Green’s function.
Knowledge of the Green’s function allows for construction of the wave function at
ðxf ; tf Þ to be constructed
ð
ψðxf ; tf Þ ¼ i dxi GR ðxf ; xi ; tf ; ti Þψðxi ; ti Þ: ð6:88Þ
Since the Hamiltonian has been assumed to be independent of time, the Green’s function
will only depend on the difference t ¼ tf ti ; and using the Fourier transform to express
the Green’s function in the conjugate energy variable Ε yields
ð Xð
iEt=ℏ R
R
G ðxf ; xi ; EÞ ¼ i dte G ðxf ; xi ; tÞ ¼ i dt exp ½itðE En Þ=ℏψn ðxf Þψn ðxi Þ:
n
ð6:89Þ
A direct Fourier transformation of the eigenfunction expansion of the Green’s func-

tion results in an ill-defined integral. Introducing a small, positive imaginary part to the
energy which is denoted as E→E þ iη leads to
X ψ ðxf Þψ ðxi Þ

n
GR ðxf ; xi ; E þ iηÞ ¼ n
: ð6:90Þ
n
E þ iη En
The þiη prescription makes the energy complex by adding a small imaginary term
with η > 0 and ensures that Fourier transform of the retarded Green’s function remains
mathematically well defined. This form enables the Green’s function to describe the
injection of an electron at a time in the past with energy E into a many-electron system. If
instead of a small positive energy component being added to the energy, a small negative
component iη is added, the advanced Green’s function is obtained as expressed in the
energy domain.
The Fourier transformed Green’s function that satisfies
ðE þ iη HÞGR ðxf ; xi ; E þ iηÞ ¼ δðxf xi Þ ð6:91Þ
is the operator inverse to the linear operator defining the time-dependent Schrödinger
equation with appropriate time domain boundary conditions imposed as
GR ðxf ; xi ; E þ iηÞ ¼ ðE þ iη HÞ1 : ð6:92Þ
The solution to the Green’s function for a free electron can be obtained by recalling
the expression for the plane wave eigenfunctions and eigenvalues and to assume a
continuum of states. This allows the sum over energy states to be replaced as an
integral over wave number. The result for the free electron retarded Green’s function
becomes
rffiffiffiffiffiffi
m ipffiffiffiffiffiffiffi
R
G ðxf ; xi ; EÞ ¼ i e 2mEjxf xi j : ð6:93Þ
2E
Analytical results using Green’s functions can be very insightful and powerful
theoretical tools; however, finding closed-form solutions can be challenging. For exam-
ple, even solution of the simple potential step problem studied earlier in the chapter is
relatively difficult to arrive at using analytical Green’s functions [41,42]. Hence in
modern nanowire studies the primary use of the Green’s function is for the development
of computer simulations, and relies on the fact that Green’s function formalisms may be
implemented relatively efficiently in terms of computational time and with numerical
stability.
6.8.3 Application of Green’s function to transport in nanowires

In transport simulations of nanowire transistors, it is common for source, channel
and drain regions to be treated quantum mechanically and the effect of the gate
voltage is coupled semi-classically to the quantum regime as an external electric
field. The effects for many-electrons within the channel region may be solved for
self-consistently in the presence of the gate generated electric field. If the
left lead device region right lead
HLL HDD HRR
hLLcell hLLcell hLLcell hLLcell HDD hRRcell hRRcell hRRcell hRRcell
hLLint hLLint hLLint hLLint hRRint hRRint hRRint hRRint
+ VDS –
Fig. 6.21 Typical simulation structure for nanowire transistor scattering for Green’s function simulations
partitioning the Hamiltonians for the left and right electrodes, and the device region. Note that the
device region incorporates portions of the electrode regions to enable a straightforward treatment
of the coupling between the three regions.
simulation is performed quantum mechanically using the LCAO approximation or

in a similar set of localized basis functions, the Hamiltonian can be spatially
partitioned as shown in Fig. 6.21. In the literature, the drain and source are often
referred to as left “L” and right “R” leads with their role as drain and source
determined by the polarity of the voltage applied across the channel region. The
active channel region is labeled as the device, “D.” Using these designations, it is
seen in Fig. 6.21 that the left- and right-hand electrodes are composed of units or
principal layers containing a number of atoms that are repeated periodically in the
directions away from the device. The electrodes are constructed such that atoms
contained within one repeat unit or principal layer can only interact with atoms in
neighboring principal layers. The central region consists of the channel or device
region. It is often the case that one principal layer from the construction of the
electrodes is included on either side of the device region to ensure that the device-lead
interactions are the same as between two lead cells within the electrode regions to
simplify the computations; however, this is not a fundamental constraint.
The Hamiltonian for the system is written
0 1
.. inty
B . hLL C
B int cell y C
B hLL hLL hint
LL 0 C
B inty
C
B
B hint
LL hcell
LL hLL
C
C
H¼B C
y
B hint
LL HDD hint
RR C ð6:94Þ
B y C
B hint
RR hcell
RR hint
RR C
B y C
B
@ 0 hint
RR hcell
RR
int C
hRR A
..
hcell
RR .
where the elements hcell cell int int

LL , hRR , hLL , hRR , and HDD are the left electrode principle layer,
right electrode principal layer, left electrode layer–layer interaction, right electrode
layer–layer interaction, and device Hamiltonian matrices, respectively. The dimensions
the matrices are given by the number of localized basis set functions used to describe the
different regions. Given this simulation configuration, the Hamiltonian for the device
can be conceptually written as
0 10 1 0 1
HLL HLD 0 ~cL ~
cL
@ HDL HDD HDR A@ ~ cD A ¼ @ ~ cD A : ð6:95Þ
0 HRD HRR ~cR ~
cR
It is assumed in Eq. (6.94) that the localized basis is orthogonal (which is not always
the case). The matrices HLL and HRR are in principle infinite as the principal layers
describing the electrodes are repeated indefinitely. The solution for the wave function on
the device region is given in terms of the coefficients in ~ c D that are consistent with the
boundary conditions applied to the leads including the drain–source bias voltage, the
interaction of the device region with the electrodes, and the external gate voltage.
Assuming the left and right leads are appropriately treated, the matrix eigenvalue
equation can be formally expressed as three equations
HLL~
c L þ HLD~ c L ; HDL~
c D ¼ E~ c L þ HDD~
c D þ HDR~
c R ¼ E~
cD;
HRD~
c D þ HRR~
c R ¼ E~
cR: ð6:96Þ
The first and last of these equations can be re-expressed as
c L ¼ ðE HLL Þ1 HLD~

~ c R ¼ ðE HRR Þ1 HRD~
cD; ~ cD; ð6:97Þ
and the inverse matrices are labeled as electrode Green’s functions

gL ¼ ðE HLL Þ1 ;
ð6:98Þ
gR ¼ ðE HRR Þ1 :
The boundary conditions for the electrode Green’s functions are to be chosen to
provide inward propagating electrons or holes from the electrodes into the channel, but
such that electrons or holes exiting the channel into the electrodes are not back reflected.
An effective Schrödinger equation on the device region can be expressed with the aid of
two self-energies Σ that describe the right and left electrodes
½HDD þ ΣL ðEÞ þ ΣR ðEÞ~

c D ¼ E~
cD;
ΣL ðEÞ ¼ HDL gL HLD ;
ΣR ðEÞ ¼ HDR gR HRD : ð6:99Þ
The steps leading to Eq. (6.98) treat the left and right electrode Hamiltonians as finite
matrices and the matrix algebra is not well defined as the boundary conditions on the
electrode self-energies are not explicitly presented. A formally correct treatment of the
electrodes described by self-energies relies on recursion relationships and explicitly
selecting the appropriate boundary conditions for the propagation of electrons within the
electrode regions which then allows for the manipulation of the electrode Hamiltonians
as finite matrices. Applying the recursion relations and the boundary conditions results
in electrode self-energies expressible in finite form through Green’s functions developed
for the description of the electronic structure of surfaces, which are named sensibly
“surface Green’s functions” [43]. As the electrodes act as the voltage sources to the
device region, both electrodes are assumed to be locally in equilibrium allowing the
electronic structure for the “left electrode” and “right electrode” to be determined in
the absence of voltage bias. Application of source–drain voltage can then be applied by
shifting the Fermi levels in the lead self-energies and solving for the Green’s function on
the device region self-consistently with the leads. In calculations with sufficiently small
applied voltages, self-consistency is not required [44]. For nanowire transistors a range
of voltages are applied across a device, iterating to self-consistency has a large effect on
current–voltage characteristics and properties such as sub threshold slope, with the self-
consistent solution resulting in prediction of improved performance [11]. Although not
explicitly stated, it is assumed that the gate voltage only acts on the device region. The
gate voltage as described can be accomplished in a first approximation as a constant
added to the diagonals of the device region Hamiltonian, or in general and more
correctly as a classical electrostatic potential added to the device region Hamiltonian.
Details for applying open system boundary conditions with Green’s function approaches
can be found in [44,45].
The spatial partitioning of the Hamiltonian operators requires their matrix representa-
tions to be expressed in terms of localized basis functions. Through the use of the
electrode self-energies, the effective Schrödinger equation reduces the infinite matrix
problem to a dimension of the number of basis functions required to describe the device
region. A Green’s function on the device region is defined,
GD ðEÞ ¼ ½E HDD ΣL ðEÞ ΣR ðEÞ1 ; ð6:100Þ
and solved for self-consistently over the energy range relevant for electrons or holes
injected from the electrodes. Relationships between the Green’s function and the density
matrix allow for the current to be directly computed, or more commonly the derivation
of the transmission as a function of the Green’s functions and electrode self-energies
allows for the transmission TðEÞ or equivalently the Landauer conductance spectrum in
units of 2q2 =h to be calculated from
6.9 Summary 217
TðEÞ ¼ Tr½ΓL ðEÞGD ðEÞ† ΓR ðEÞGD ðEÞ: ð6:101Þ
The functions ΓL;R ðEÞ ¼ i½ΣL;R ðEÞ ΣL;R † ðEÞ are spectral densities and in the pre-
sent context describe the coupling of electrode states to electronic states inside the
device region. A particularly attractive feature of treating electron transport with a one-
electron Green’s function is that additional self-energies can be defined to describe
scattering mechanisms on the device region including electron–phonon scattering and
electron–electron scattering.
6.9 Summary
The combination of voltage sources acting as charge carrier reservoirs in quasi-equili-

brium in combination with the properties of individual conducting channels leads to
conductance quantization. As scattering is introduced, conductance is reduced and, in
the macroscopic limit, charge carrier mobility and Ohmic resistances emerge. For
nanoelectronic devices fabricated on nanometer length scales, electrons travel across
lengths less than mean free paths for typical scattering implies that charge transport is
intermediate between the ballistic regime characterized by no scattering and the diffu-
sive regime which emerges after many scattering events. A method often applied in the
literature to describe this intermediate regime or quasi-ballistic transport is the Green’s
function method whereby ballistic transport and transport with scattering, and inter-
mediate regimes can be described.
Further reading
Quantum transport
S. Datta, Electronic Transport in Mesoscopic Systems, Cambridge: Cambridge
University Press, 1995.
D.K. Ferry and S.M. Goodnick, Transport in Nanostructures, Cambridge: Cambridge
University Press, 1997.
Green’s functions in physics

G.D. Mahan, Many-Particle Physics, New York: Kluwer Academic/Plenum Publishers,
2000.
E.N. Economou, Green’s Functions in Quantum Physics, Berlin: Springer Verlag, 2006.
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7 Nanowire transistor circuits
7.1 CMOS circuits
Nanowire FETs can be used in the same fashion as any other type of MOSFET to
construct the logic gates that are the building blocks for data processors and control
circuits, as well as memory cells of various types such as static random access memory
(SRAM), flash memory, and so on. The topology of nanowire transistors makes them
particularly suitable for making array-like circuits such as crossbar nanowire circuits
and nanoscale application-specific integrated circuits. Nanowire FETs can even be used
as photodetectors [1]. Last but not least, nanowire transistor-based sensors can also be
combined with CMOS electronics to deliver powerful chemical or biomedical analytical
devices.
Nanowire transistors can be used as single devices. They can also be used in serial or
parallel combinations. Figure 7.1 shows horizontal nanowire transistors in a parallel
configuration; using this architecture a high current drive with a small layout footprint
can be achieved [2]. Vertical nanowire transistors lend themselves quite naturally to the
formation of NAND-based architectures as shown in Fig. 7.2.
7.1.1 CMOS logic

Techniques for the design and optimization of nanowire circuits are still in their infancy.
Key performance indicators (KPIs) include ON/OFF currents, effective current and
effective gate capacitance, CV/I, integration density, and other performance measures
normally associated with CMOS transistors. Key process and layout parameters include
number of nanowires per transistor, footprint, nanowire diameter, and other process-
related parameters such as gate length, gate over-underlap length and source/drain (S/D)
region length. One particular study indicates that through design optimization, the total
capacitance and parasitic resistance of typical nanowire CMOS gates can be reduced by
over 80% compared to nanowire designs without optimized process parameters.
Significant improvements are achieved through the reduction of the source/drain exten-
sion length, gate overlap, and nanowire diameter. Optimization of the device parameters
can also achieve an improvement of over 90% reduction in delay and power consump-
tion at the circuit level [3].
With the decrease of both device dimensions and supply voltage, variability has
become an important issue in integrated circuit fabrication. Device parameters such as
G
(a) (c)
G
G
S D
S D
S D
(b) G
G
G
S D
S D
D
S
Figure 7.1 Horizontal nanowire transistors. (a) Single transistor. (b) Four transistors in parallel occupying the
footprint of a single transistor. (c) Twelve transistors in parallel occupying the footprint of four
transistors.
(b)
(a)
G4 G4
D
D G3
G3
G G
G2 G2
S
G1 G1
S
Figure 7.2 Vertical nanowire transistors. (a) Single transistor. (b) Four transistors in series forming a
NAND-type gate.
threshold voltage, drain-induced barrier lowering (DIBL), and ON and OFF currents
exhibit statistical variations. The origins of these variations are multiple and include gate
line edge roughness (LER), random doping fluctuations (RDF), nanowire diameter
variations, and/or nanowire surface roughness. LER basically introduces statistical
variations of gate length at the device level and from device to device. As a result of
the excellent control of short-channel effects such as DIBL, gate-all-around (GAA)
nanowire transistors show less LER variability than any other type of MOSFET. This
can be further improved using transistors with gate underlap. RDF is very low in GAA
nanowire transistors when using an undoped channel, but increases with doping concen-
tration. Control of nanowire diameter and roughness is very important and can be
optimized using processing techniques such as hydrogen anneal or nanowire oxidation.
Data from the literature indicate that the variability of GAA nanowire FETs can be
significantly lower than in bulk planar devices and might be comparable with, if not better
than, that for undoped fully depleted ultrathin-body SOI and FinFET devices [4,5].
Variability effects decrease as the diameter of a nanowire is decreased. As the
nanowire radius is reduced from 25 nm to 1 nm in vertical GAA FETs with an undoped
body and a gate length of 40 nm, the variation in threshold voltage decreases from 140 to
approximately 6 mV for nMOS transistors and from 130 to 11 mV for pMOS transistors,
both of which are indications of diminishing short-channel effects with reduced dia-
meter. Subthreshold slope is 62 mV/dec for this nMOS and 62.5 mV/dec for the pMOS
transistors at a drain voltage of 1 V. These characteristics are close to ideal and
significantly better than in double-gate SOI transistors [6,7]. In addition these vertical,
undoped GAA silicon nanowire transistors dissipate less power than bulk and SOI MOS
transistors while yielding comparable performance in terms of switching frequency.
The nanowire radius and effective channel length can both be varied until a common
body geometry can be determined for both nMOS and pMOS transistors to limit OFF
currents below 1 pA while producing highest ON currents. In [6], DC characteristics
of the optimum n- and p-channel transistors for threshold voltage roll-off, DIBL and
subthreshold slope were calculated and simple CMOS gates including an inverter, 2- and
3-input NAND, NOR, and XOR gates, and full adder were designed and simulated. The
layout of the resulting full adder is shown in Fig. 7.3 and the area measures 0.11 µm2,
which is 5.2 times smaller than a 6-transistor SRAM cell laid out using a 65 nm
technology node.
It is worth noting that vertical and horizontal GAA transistors are not necessarily
symmetrical, i.e. electrical characteristics may be different when source and drain are
swapped. This is due to processing, for example if the width of the nanowire is not
VDD
A
200 nm
B
C
A
B
C
carry
sum
GND
550 nm
Figure 7.3 Full adder layout using 40 nm effective channel length and 4 nm body radius nMOS and
pMOS nanowire transistors. A, B, and C are the two inputs of the full adder and the carry-in,
respectively. After [6].
constant resulting in the drain end of the channel being wider or narrower than the source
end can lead to the asymmetric behavior [8]. The asymmetry in the electrical character-
istics can also arise due to inhomogeneous doping concentration from source to drain
in the channel, or to a difference of resistance between the source and the drain
junction [9,10]. BSIM Spice models for nanowire transistors can be found in the
literature applied for the optimization of transistor designs [11].
The vertical gate-all-around nanowire transistor architecture is of particular interest
because it offers both integration density and speed/power performance increase with
respect to horizontal device integration. The comparison of vertical nanowire and
FinFET CMOS shows nearly 40% delay reduction in nanowires, highlighting the
excellent potential of vertical GAA CMOS for technology nodes below 15 nm [12].
The behavior of parasitic resistances and capacitances is markedly different in vertical
GAA transistors than in classical lateral devices due to structural asymmetry. The use of
a top metal electrode overlapping the nanowire reduces the resistance difference to
the bottom electrode. The parasitic capacitances can be modeled as parallel plate
capacitors with cylindrical fringing field components. Simulations show that the gate-
active/extensions are dominating contributors to parasitic capacitance. If the bottom
electrode is used as drain, the capacitance is further amplified due to the Miller effect and
circuits with device sources at the top have higher delay than devices with the source
located at the bottom of a vertical transistor structure. Gate delay can be increased by as
much as 65% when using the top electrode as the source. The combined parasitic
resistances and capacitances to a large degree determine the overall transistor perfor-
mance and circuit delay. Thus, the structural asymmetry places layout restrictions on
circuit designs implemented with vertical nanowire FET devices that do not generally
occur in horizontal FET layouts [13].
7.1.2 SRAM cells

A circuit cell that can greatly benefit from the reduced short-channel effects character-
istic of nanowire transistors is the static random-access-memory (SRAM) cell. The static
noise margin (SNM) of a 6-transistor (6T) SRAM cell represents its ability to retain a bit
of information if the supply voltage (VCC) fluctuates. It can be measured during a “hold”
cycle (i.e. when the access transistors connecting the memory inverter pair are turned
OFF), or during a read cycle (the access transistors are turned ON). Due to the additional
disturbance introduced when the access transistors are switched ON, the read SNM is
always smaller than the hold SNM and dictates the minimum operating supply voltage
for the memory cell. The SNM is obtained graphically by drawing and mirroring the
inverter input–output characteristics of half a cell (i.e. an inverter plus access transistor)
and finding the largest square that can be inserted between the two curves. A graph
containing the two mirrored curves is commonly referred to as a “butterfly curve.” The
SNM of an SRAM cell represents the minimum DC voltage disturbance necessary to
upset the cell state, and can be quantified by the length of the side of the maximum
square that can fit inside the butterfly curves formed by the cross coupled inverters. The
SNM of a cell is a function of the DIBL of both the pull-up and pull-down transistors
500
Planar MOSFET
400 W-gate nanowire
Margin, SNM (mV)
GAA nanowire
Signal-to-Noise
300
Hold
200 Read
100
0
0.0 0.2 0.4 0.6 0.8 1.0
VDD (V)
Figure 7.4 Simulated read and hold SNM versus supply voltage VDD for 6T SRAM cells made with either
planar MOSFETs, omega-gate nanowire FETs, or GAA nanowire FETs. Gate length is 20 nm.
used in the cell’s inverters. Any increase of DIBL degrades both read and hold SNMs.
Thus, devices with low DIBL should offer optimum SNM results [14].
A comparative analysis of the stability of 6T SRAM cells made using different FET
architectures was published in 2006 [15]. The simulation study was made by using a
mixed-mode device-circuit coupled simulation taking quantum mechanical effects into
account. Three different types of devices were considered: planar MOSFETs, omega-
gate nanowire transistors, and GAA nanowire transistors. The devices were simulated
with a gate length of 20 nm. The static noise margins (SNM) of 6T SRAM cells
made using the different devices were compared. It was found that the SRAM with
GAA-nanowire-based design provides an improvement in stability under the modes of
read and hold compared with the two other simulated circuits, and that the omega-gate
design is itself better than the single-gate planar design. Compared with conventional
planar MOSFETs, more than 35% improvement of read SNM is observed for the GAA
design over a large range of supply voltages as plotted in Fig. 7.4, while there is a 10%
improvement for the hold SNM. The same study also shows that GAA-nanowire-based
SRAM cells have much more stable SNM against temperature variations than bulk FET
cells. Another set of simulations comparing SRAM cells made using SOI FinFETs and
GAA nanowires shows similar results and reaches similar conclusions [16].
These simulation results have been qualitatively corroborated by experimental results
obtained from SRAM arrays with GAA nanowire transistors with a width, height, and
channel length of 5 nm, 15 nm, and 40 nm, respectively. The nanowire SRAM cells
achieve a read SNM of 325 mV at a supply voltage of 1 V, while the corresponding cell
made with planar transistors achieves an SNM of only 160 mV. A comparison between
the two circuits is shown in Fig. 7.5 [17].
The SNM can be further improved by introducing additional reduction in DIBL using
a gate underlap architecture [18]. Junctionless nanowire transistors have an inherent
underlap architecture because the source and drain doping is the same as the channel
doping. This allows one to reach higher SNM values when compared to using
400
M
Margin, SNM (mV)
RA
ar S
Signal-to-Noise
n
Pla
300
200 ire SRAM

GAA Nanow
100
0.6 0.8 1.0 1.2
VDD (V)
Figure 7.5 Measured read signal-to-noise margin (SNM) versus supply voltage VDD for 6T SRAM cells
made using either planar MOSFETs or GAA nanowire FETs. Gate length is 40 nm.
300
Inversion-mode GAA
Junctionless GAA
Read SNM (mV)
200
100
2 3 4 5 6 7 8
Figure 7.6 Simulated read SNM of 6T SRAM cells vs. GAA nanowire diameter for both inversion mode
and junctionless operation. The gate length is 10 nm and the supply voltage is 800 mV.
inversion-mode devices. Simulations predict a read SNM of 180 mV for a gate length of
20 nm and a supply voltage of 900 mV. This is considerably higher than benchmark
inversion-mode FinFETs or trigate SRAM cells as reported in the literature for gate
lengths ranging between 22 and 40 nm and featuring read SNM values between 140 and
160 mV [19].
In a similar way, the read SNM of GAA nanowire SRAMs increases when the
nanowire diameter is decreased. The read SNM of 6T SRAM cells has been simulated
as a function of nanowire diameter for both inversion mode and junctionless transistors.
The gate length was 10 nm and the supply voltage was 800 mV. Figure 7.6 shows the
simulation results. As can be expected, DIBL decreases as the nanowire diameter is
decreased and, in turn, the SNM increases. Furthermore, junctionless transistors have a
smaller DIBL than the inversion mode transistors, except perhaps in the case where
the diameter is relatively large (>8 nm). In such a case, short-channel effects can
be worse for junctionless or accumulation mode transistors compared to inversion mode

transistors because of some loss of gate control over the buried channel [20]. Based on
the measurement of CMOS inverter characteristics, GAA nanowire technology has
been shown capable of producing SRAM cells with a hold SNM of 90 mV, 270 mV,
and 450 mV at supply voltages of 200 mV, 600 mV, and 1.2 V, respectively [21].
SRAM cell stability and SNM are affected by any variation of the transistor
characteristics. All sources of variability such as random doping fluctuations (RDF),
line-edge roughness (LER), or nanowire diameter fluctuations increase the variability
of the cell characteristics and reduce the SNM. These variability effects are minimized
when GAA transistors are used, such that the minimum cell operating voltage, VCCmin,
can be reduced by 100 mV at the 10 nm node when compared to FinFET SRAM cells
[22]. Furthermore, using multiple nanowire devices in parallel greatly suppresses the
impact of the fabrication parameters on variability of the SNM due to a statistical
averaging effect within each individual memory cell [23].
A 16 × 16 SRAM core consisting of 16 identical columns, each of which includes 16
rows of six transistor (6T) memory using vertical gate-all-around CMOS nanowire
transistors, can be found in the literature [24]. The GAA nanowires are used for bit
storage cells, pre-charging circuits, sense amplifiers for read operation, write circuits,
and for output latch/buffers.
SNM can be further improved using stacked vertical GAA transistors with two
transistors per stack. In this way, “disturb-free” 10-transistor (10T) SRAM cells can
be designed. These cells have a footprint that is only 67% that of an 8T cell made with
planar transistors. The footprint of an 8T vertical GAA SRAM cell without stacked
transistors is 64% that of a planar layout [25].
7.1.3 Non-volatile memory devices

Nanowire transistors are commonly used to fabricate three-dimensional NAND flash
memories with ultra-high density data storage with low cost per bit. These transistors
have a polycrystalline silicon channel and are used to make ultra-high density, low bit
cost memories. Among several approaches, the Bit Cost Scalable (BiCS) flash technol-
ogy has been demonstrated by several groups. The BiCS cell array consists of multiple
control gates placed in series around polysilicon “nano-pipes” or “nano-pillars” as
represented graphically in Fig. 7.7. Typically, the control gate electrodes are made by
etching holes in stacked conductive plates. These are subsequently coated with a gate
dielectric stack and filled with the polysilicon gate material. In some instances the
polysilicon does not completely fill the holes but rather coats their inside wall, thereby
forming a “macaroni-shaped” semiconductor layer, the inside of which is subsequently
filled with a dielectric material. Each intersection of a control gate plate and a polysilicon
“nanowire” forms a flash memory cell. The gate dielectric is usually silicon oxide/
nitride/oxide (ONO). Electrons from the channel can tunnel though the bottom oxide
layer and be trapped in the nitride, thereby changing the threshold voltage of the
transistor and thereby storing information. The resulting transistor is called a silicon-
oxide-nitride-oxide-silicon (SONOS) device. A string of such transistors forms a NAND
(a) (b) BL SL
Bit Line (BL) SGD SGS

Source Line (SL) SL SL
Select Gates (SG) CG31 CG00
nanowire with gate oxide

Vertical ‘’NAND” polysilicon
CG30 CG01
Control Gates (CG)
CG29 CG02
CG17 CG14
CG16 CG15
Pipe Gate
Pipe
Pipe Gate
Figure 7.7 Example of BiCS NAND flash memory structure. (a) Cross-section of the device showing
multiple control gates (32 in series). The pipe gate allows 32 transistors to be placed in series using
only 16 control gate layers. (b) Equivalent circuit [25].
flash memory structure. At one end of the string is a source side select gate (SGS) and at
the other end a drain select gate (SGD). The SGD is itself connected to a bit line
[26,27,28].
BiCS transistors are made out of polycrystalline silicon and have no heavily doped
source/drain regions between successive control gates. As a result they are slow
compared to standard silicon devices and present a high resistivity in the ON state.
The use of polysilicon as channel material increases pass disturbs and reduces the
worst case string current. For every doubling in density, the worst case string current is
divided by a factor of two. As a result of the channel being low-mobility polysilicon
and the source/drain regions not being heavily doped, the worst case string current,
occurring when all cells in a string have high threshold voltage, quickly tends to
unacceptably low current values as density increases. To mitigate these problems,
single-crystal nanowire BiCS processes have been proposed. Horizontal GAA
MOSFETs with a nanowire diameter of 7 nm were used to make SONOS NAND
strings. The single-crystal nature of the devices enabled large programming threshold
voltage shifts and fast program/erase operation speed. Both the threshold voltage shift
window and programming speed improved as the nanowire diameter and tunnel oxide
thickness were decreased. A threshold voltage window of 4 V was maintained after 104
program/erase cycles and the cells showed an extrapolated retention time of 10 years at
room temperature [29].
If the low current drive problem of BiCS can be solved by using single-crystal
nanowires, it still remains difficult, at least in vertical devices, to make source and
drain diffusions aligned to the gate. This issue can be avoided by using junctionless
devices. Junctionless devices realized on vertical silicon nanowire GAA structures

with channel length down to 20 nm have been shown to have comparable electrical
characteristics to those of junction-based nanowire SONOS devices (SS < 70mV/
decade, leakage current < 10−12 A and a memory window of 3.2 V with 1 ms pro-
gram/erase time). Being free of junctions, the process complexity is significantly
reduced and this device becomes a suitable platform for vertically stacked ultra-high
density memory applications [30].
Planar NAND flash memory cells have an intrinsic cell area of 4F2 per bit, where F is
the minimum feature size, assuming a pitch of 2F for each printed level. Density can be
pushed beyond that limit by using three-dimensional configurations through vertical
stacking of cells. A two-level stacked junctionless GAA SONOS memory fabricated
using a vertical, single-crystal silicon nanowire platform was reported in 2011. These
SONOS devices have a footprint of 3F2 per bit and a memory string built based on this
technology has been demonstrated. Each vertical nanowire comprises two GAA gates
stacked on top of one another like two rings on a finger pointing upwards. The top and
bottom cells exhibit similar programming speeds and a 3.4 V threshold shift window. A
program/erase time of 10 ms was used at +15 V and –18 V program/erase operations,
respectively. The memory is able to store 2 bits per vertical nanowire using the four
states 0 0, 0 1, 1 0, and 1 1, i.e. two states per gate, one bit being stored at the source
side of the channel (bottom bit or Bbit) and one at the drain side (top bit or Tbit). It is
found that the memory window can be well maintained after 105 s at 25°C for both fresh
and cycled cells. Endurance testing reveals that 85% of the memory window can be
maintained after 10 years at 125°C [31].
It is also possible to store multiple bits in the gate dielectric of a single-gate device.
Operation of a junctionless vertical silicon nanowire GAA SONOS memory
(JL-SONOS) with two physical storage nodes per cell was first reported in 2011 [32].
In this device, charges are separately stored in the nitride layer near the top/bottom region
of the vertical wire channel, i.e. either near the source or near the drain as shown in
Fig. 7.8. Measurements of the program/erase speed, endurance and retention reveal
that robust 2-bit-per cell storage was achieved. This structure and the vertical nature of
the transistor relaxes traditional channel length limitations and integration density limita-
tions associated with traditional horizontal devices. In addition, the absence of junctions
makes this device highly manufacturable with low cost and relatively low thermal
budget. The junctionless SONOS devices have an n-type doping concentration of
1019 cm−3 and their electrical characteristics are comparable to those of junction-based
SONOS devices. The reported subthreshold slope is below 70 mV/decade and
off-currents are below 1 pA. This is attributed to the small wire diameter and the excellent
gate control provided by the GAA architecture. The retention characteristics of the
devices have been tested for 104 program/erase cycles. The programming window
corresponding to the threshold voltage shift is larger than 3 V for both the top bit (drain
side of the channel) and the bottom bit (source side). This window can be well maintained
after 105 s at 85°C for fresh and cycled cells. The stable subthreshold slope after program/
erase cycling indicates minimal damage or build-up of charges in the ONO layer. The
programming window and retention characteristics of the device are shown in Fig. 7.9.
Gate Drain Source
Tbit Tbit
N+ nanowire
Metal gate
O
N
O
Bbit Bbit
N+
P-substrate
Figure 7.8 Schematics of a vertical silicon nanowire GAA junctionless SONOS flash memory device. The
charges can be separately stored in the ONO (oxide-nitride-oxide) gate dielectric stack above the
top (Tbit, drain side) and bottom (Bbit, source side) regions of the vertical-wire channel. The wire
diameter for the fabricated device is 20 nm, and the gate length is 120 nm. Tunnel oxide, nitride,
and top oxide of the ONO structure have a thickness of 5, 7, and 7 nm, respectively [31].
5
Threshold voltage (V)
4 Bbit high + Tbit high

Bbit low + Tbit high
3 Bbit high + Tbit low
Bbit low + Tbit low
10–1 100 101 102 103 104 105 106

Retention time (s)
Figure 7.9 Programming window (threshold voltage) and retention characteristics of the vertical silicon
nanowire GAA junctionless SONOS flash memory device shown Fig. 7.8. “Bbit high” means the
bottom of the channel is in a high threshold state, “Tbit low” means the top of the channel is in a
low threshold state, etc.
GAA junctionless SONOS devices have been demonstrated using vertical nanowires
as well. Such devices have been demonstrated by making homogeneously n+-doped
silicon GAA nanowire transistors on a bulk substrate with a diameter and a gate length of
4 nm and 20 nm, respectively. The junctionless GAA SONOS device shows a high read
current (> 10 µA), a large threshold voltage programming window margin (> 6.5 V), a
narrow distribution of the erased VTH, and excellent cycle endurance (105 cycles) [33].
For completeness, one should mention that other types of non-volatile memory cells
can be made using nanowire transistors, beside SONOS. Resistive RAM (RRAM)
operation has been demonstrated using a 1T–1R (one transistor, one resistor)
architecture built on vertical GAA nano-pillar transistors using either junctionless or
junction-based dopings. The transistors were fabricated using fully CMOS compatible
technology and RRAM cells were stacked onto the tip of the nano-pillars with smallest
diameters of 37 nm achieving a compact 4F2 footprint. It was found that these cells show
excellent switching properties, including ultralow switching current/power, multi-level
storing ability, good endurance (over 105 program/erase cycles), 10 year retention at
85°C, and fast switching time below 50 ns [34]. To explore this topic further, the
excellent book by B. Prince on vertical 3D memory technologies is recommended [35].
7.2 Analog and RF transistors
The benefits of the GAA nanowire architecture for analog applications and the impact of
excellent control of short-channel effects on analog performance can be understood using
the example of a single transistor amplifier. Consider a MOSFET used as an amplifier in
the basic common-source configuration. Two important performance indicators of the
amplifier/transistor are the open-loop gain (intrinsic gain) Av0 and transition unit-gain
frequency, fT. These are mathematically defined by the following expressions [36]:
Av0 ¼ gm =gD and fT ¼ gm =ð2πCL Þ; ð7:1Þ
where CL is the load capacitance. Define the Early voltage, VEa, and the “normalized”
current of a transistor Is as
VEa ¼ ID =gD IS ¼ ID =ðW =LÞ: ð7:2Þ
The intrinsic gain and transition frequency can be rewritten in the following way:
gm gm W=L
Av0 ¼ Vea and fT ¼ IS : ð7:3Þ
ID ID 2πCL
The two latter expressions highlight the parameter gm/ID, labeled the “transconduc-
tance-current ratio.” It is an important performance indicator of a device since it
represents the ratio of the amplification and speed (gm) to the power dissipated to achieve
this amplification and speed (ID). In weak inversion the transconductance-current ratio is
intimately related to the subthreshold slope SS since

gm dID 1 d lnðID Þ d log10 ðID Þ lnð10Þ
¼ ¼ ¼ lnð10Þ ¼ : ð7:4Þ
ID dVG ID dVG dVG SS
The subthreshold slope is itself linked to the body factor n (or body effect coefficient),
which represents the efficiency of channel control by the gate through the following
relationship:
kT
SS ¼ n lnð10Þ: ð7:5Þ
q
A minimum subthreshold slope (60 mV/dec at room temperature) is achieved

when the control of the channel potential by the gate is perfect, in which case
n = 1. Imperfect coupling leads to values of n larger than unity. In strong inversion
gm/ID is given [37] by
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
gm 2μCox W =L
¼ : ð7:6Þ
ID nID
Here again, the low value for n found in GAA devices ensures optimum gm/ID
performance. The benefits provided by the GAA architecture for analog circuits are
thus: high values of gm/ID (related to low values of SS) due to the excellent gate control,
and large Early voltage (related to low output conductance).
In order to achieve high analog/RF performance, GAA nanowire devices must be
optimized and their parasitics must be reduced to a minimum. A multi-dimensional
design optimization method with awareness of process variations and transistor para-
sitics such as source and drain resistance was developed by Liu et al. [38]. Analog/RF
performance indicators such as the cutoff frequency, fT, the transconductance-current
ratio, gm/ID, the intrinsic gain, gm/gD, and other figures of merit were optimized using the
proposed method. Through design optimization, GAA nanowire FETs were shown to
deliver higher fT than planar FETs. Some of the critical parameters for analog perfor-
mance, such as source/drain resistance/capacitance, are highly process dependent. Their
values can be extracted from the S-parameter analysis of 3D simulations of nanowire
transistors [39]. The highest frequency performance ever measured for an MOS tran-
sistor was obtained using omega-gate In0.63Ga0.37As nanowire transistors. The nano-
wires have a hexagonal section and a minimum width and height of 11 and 25 nm,
respectively. Such devices with a gate length of 32 nm have been reported to reach an fT
of 280 GHz and an fmax of 312 GHz at VDD = 0.5 V [40].
Because of their low DIBL and low body effect coefficient, GAA nanowire transistors
offer a high degree of linearity. Linearity can be improved by using junctionless
nanowire devices, which exhibit lower output conductance than inversion mode devices
because in the junctionless transistor the saturation channel length is virtually indepen-
dent of drain voltage [41]. Increasing channel doping concentration to degenerate levels
(1020 cm−3) further improves linearity. Using a heavily doped channel increases drain
saturation velocity to values up to 5 × 107 cm/s in silicon [42]; this high velocity reduces
the pinch-off effect, further reducing drain conductance and improving linearity. As a
result, performance of junctionless nanowire transistors appears to be much better than
that of short-channel planar MOSFET in terms of RF linearity [43].
VDD
VDD
Vbias2
Vbias2 Q5 Q5a Q5b
Q1a Q2a
Source contact
Vin Vbias1 Nanowire
Q1 Q2
Vbias1
Vin
Q2b
Vout Q1b
Vout Gate
Q3 Q4 Q3 Drain contact
Q4
GND
(a) (b) (c)
Figure 7.10 Schematics (a) and layout (b) of simple single-state CMOS amplifier made with vertical GAA
nanowire transistors; (c) layout of an individual vertical nanowire transistor [44].
An example of performance estimation for an amplifier made with vertical gate-

all-around nanowire transistors can be found in [44]. That paper presented the
SPICE modeling of nMOS and pMOS vertical GAA FETs with 10 nm channel
length and 4 nm channel diameter. The fully depleted BSIMSOI parameters were
extracted from input and output I–V characteristics obtained from 3D numerical
simulations. The distributed RC parasitic of the nMOS and pMOS transistors were
calculated and added to the SPICE models as subcircuits. The low-frequency, high-
frequency, small-signal, and large-signal characteristics of the individual nMOS and
pMOS GAA FETs were extracted from the numerical simulations. When biased at
VDS = 0.5 V and VGS = 0.5 V, the nMOS and pMOS GAA FETs delivered 2 and 0.7
μA drain current, 14 and 8 μA/V transconductance, 36 and 25 THz unity-current-
gain cutoff frequency (fT), and 120 and 100 THz maximum frequency of oscillation
(fmax), respectively. A simple single-stage amplifier (inverter) made with these
transistors and dissipating 1.64 μW power was shown to have a 500 GHz bandwidth
with a 6.5-fold gain and −24 dBm third-order intermodulation distortion tones for a
two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The
large-signal operation of the amplifier with 1 V output swing exhibited 2.2 ps delay,
5.4 ps rise time, and 4.7 ps fall time, while oscillating at 30 GHz. A differential pair
amplifier was designed using the same devices (L = 10 nm, channel diameter =
2 nm) with the circuit and layout shown in Fig. 7.10. The amplifier dissipates 5 μW
power and provides 5 THz bandwidth with a voltage gain of 16 and total harmonic
distortion better than 3%. The layout area of the differential pair amplifier is x =
136 nm and y = 190 nm. All these parameters indicate that vertical nanowire GAA
FETs are promising candidates for realizing next generation high-speed analog
integrated circuits [45].
7.3 Crossbar nanowire circuits
Doped semiconductor nanowires organized in a row and column arrangement can be

used to create a matrix-like array of nanodevices. The nanowire crossings can be turned
into devices such as pn diodes, bipolar junction transistors, and MOSFETs. Using
classical boron and phosphorous doping impurities, silicon nanowires have successfully
been used as building blocks to assemble different types of semiconductor nanodevices
and to create logic gates. Passive diode structures can be made by crossing p- and n-type
nanowires. These structures exhibit rectifying transport similar to planar pn junctions.
Active bipolar transistors consisting of heavily and lightly n-doped nanowires crossing a
common p-type wire base have been made with common base and emitter current gains
as large as 0.94 and 16, respectively. In addition, p- and n-type nanowires have been used
to assemble complementary inverter-like structures [46].
Crossed nanowire pn junctions and junction arrays can be used to create integrated
nanoscale MOS transistor arrays where the semiconductor nanowires can be used either
as conducting channels or as gate electrodes. Such nanowire arrays have been configured
as OR, AND, and NOR logic-gate structures with substantial gain. These logic gates
have then been used to implement basic computation functions such as a binary half
adder [47].
Logic gates and circuits using crossed nanowire FETs have been proposed to
fabricate “nanoscale application specific integrated circuits” (NASICs). Such cir-
cuits consist of an array of crossed nanowires placed in two superimposed layers,
one with horizontal nanowires and one with vertical nanowires. The nanowires are
used to form both gate and channel material of the FETs. Enhancement-mode
n-channel devices can be made using a p-type channel, and an n+ gate, source,
and drain. Junctionless nanowire FETS can also be used and are easier to fabricate
since they are composed of a uniformly doped n+ nanowire for source, channel, and
drain, and a p+ nanowire for the gate. Using such an arrangement one can obtain
positive threshold voltages and reasonable ON/OFF current ratios. Portions of the
nanowires can be transformed from transistors to simple conductors using localized
silicidation. This localized “defunctionalization” of the FETs can also be used to
create desired logic functions as shown schematically in Fig. 7.11 in a manner
similar to programmable logic arrays [48,49,50].
Design methodologies specific for nanowire array-based circuits have been devel-
oped. Starting from a functional description of the circuit and using technological data,
the physical design of the described function can be generated by placing nanowires,
FETs, and connections in a nanoarray arrangement. Each circuit sub-block can be
simulated considering resistances, capacitances, and FET currents using a simulator
such as SPICE. The example of such a methodology applied to the design of a 2-bit full
adder with horizontal nanowire transistors can be found in the literature [51]. The
crossbar architecture can also be used with vertical GAA transistors. Crossbar layout
can be applied to vertical GAA nanowire transistors. Crossbar layout offers the simpli-
city in interconnect routing at the penalty of larger area compared to custom design with,
7.3 Crossbar nanowire circuits 235
INPUTS GND
(a) (b) (c) (d) veva
heva
VDD
GND
hpre
OUTPUTS
vpre
VDD
Figure 7.11 NASIC manufacturing pathway with junctionless crossbar FETs and “grid-first” assembly. (a)
Formation of a nanowire array with n-type horizontal nanowires and p-type vertical nanowires.
(b) Lithography mask to protect regions of vertical nanowires from silicide formation. (c)
Silicidation of portions of the top nanowires to avoid the formation of transistors at certain cross
points (the grey portions of the vertical nanowires are now transformed into silicide). (d)
Junctionless NASIC 1-bit full adder circuit with contacts “heva,” “veva,” “hpre,” and “vpre,”
which stand for horizontal evaluation gate, vertical evaluation gate, horizontal pre-charge gate,
and vertical pre-charge gate, respectively. The transistors whose channels are made using the
horizontal nanowires are n-channel devices and those made in the vertical nanowires are p-channel
devices [47].
for example, a 45% larger area in the example of a full adder but with similar speed/
power performance [52].
Logic gates can also be achieved with crossbar arrays of junctionless nanowire FETs.
This approach has been demonstrated by the fabrication of NAND gates and NOR gates
as well as 2 × 2 and 4 × 6 decoders using heavily doped silicon nanowires as both
conductors and transistors. Nanowires with a cross-section of 23 nm (width) × 18 nm
(thickness) were used to demonstrate the functionality of such a crossbar array. The
nanowires are locally thinned down to a thickness of 7 nm and gates are placed to form
junctionless transistor channels. This thinning process is needed to make it possible to
turn the transistors to an OFF state. The controlled formation of nanoscale constrictions
in junctionless nanowires allows for the formation of high-quality field-effect transistors
that efficiently modulate the flow of the current in the nanowire. The constrictions act
as potential barriers and the height of the barriers can be selectively tuned by gates,
making the device concept compatible with the crossbar geometry in order to create
logic circuits [53].
Nanowire transistors with specific gate dielectric stacks can be programmed by charge
injection and trapping in the gate dielectric. This programming technique, similar to that
used in SONOS flash memory cells can be used to modify the threshold voltage of
transistors in a non-volatile manner. Each nanowire FET (NWFET) node in an array can
thus be programmed to be placed in an active or an inactive state, and by mapping
different active-node patterns into the array, combinational and sequential logic func-
tions can be achieved. As a demonstration of this concept, Ge/Si core/shell nanowires
coupled with an Al2O3–ZrO2–Al2O3 dielectric stack have been used to fabricate
non-volatile nanowire field-effect transistors with programmable threshold voltages

and with the capability to drive cascaded elements. The devices were integrated to
define a logic tile consisting of two interconnected arrays with 496 functional configur-
able FET nodes. The logic tile was programmed and operated first as a full adder with a
maximal voltage gain of ten and input–output voltage matching. Afterwards the same
logic tile was reprogrammed and used to demonstrate full-subtractor, multiplexer,
demultiplexer, and clocked D-latch functions. This programmability feature opens the
door to promising new circuit architectures for low-power application-specific nanoe-
lectronic processors [54].
In 2014, a rudimentary nanocomputer built from an array of 15 nanometer-wide core-
shell germanium-silicon nanowire was reported in the press [55]. This nanocomputer is
a nanoelectronic finite-state machine built through modular design using a multi-tile
architecture. Each tile/module consists of two interconnected crossbar nanowire arrays
with each crossing-point consisting of a programmable nanowire transistor node. The
nanoelectronic finite-state machine integrates 180 programmable nanowire transistor
nodes in three tiles or six total crossbar arrays and incorporates both sequential and
arithmetic logic, with extensive inter-tile and intra-tile communication that exhibits
rigorous input/output matching. The system realizes the complete 2-bit logic flow and
clocked control over state registration that are required for a finite-state machine or
computer. The flexibility of the technology was exemplified by reprogramming the
circuit to a functionally distinct 2-bit full adder with 32-set matched and complete
logic output. This constitutes the most advanced crossbar nanowire circuit to date
[56]. At the design level, computer tools are being developed to predict logic behavior,
defect-induced output error rate assessment, switching activity, power, and timing
performance, as well as to improve fault tolerance [57,58].
Programmability of nanowire transistors and circuits can be further improved using
the approach described by de Marchi et al. in 2012 [59,60] in which the polarity, i.e.
either n-channel or p-channel behavior, of a GAA nanowire FET can be changed at
will. This ambipolar silicon nanowire (SiNW) FET features two independent gate-all-
around electrodes and vertically stacked SiNW channels. One gate electrode, identi-
fied as the “polarity gate” enables dynamic configuration of the device polarity
between n- or p-type, while the other gate labeled the “control gate” acts as a regular
MOSFET gate and is used to switch the device ON and OFF. Measurement results on
silicon show an ION/IOFF ratio larger than 106 and a subthreshold slope of 64 mV/dec
(70 mV/dec) for p (n)-type operation within the same device. Furthermore, the
exclusive or (XOR) operation is embedded in the device characteristics, which allows
one to make an XOR gate with only two transistors. In this device the silicon nanowire
is basically undoped. The “polarity gate” (PG) is located on both sides of the control
gate in close proximity to source and drain Schottky junctions. If a negative voltage is
applied to the PG, those parts of the nanowire covered by the PG are filled with holes
and become field-induced p-type source and drain. Conversely, applying a positive
bias to the PG accumulates electrons near the Schottky contacts and creates field-
induced n-type source and drain. The control gate is then used as in a regular MOSFET
to establish a channel between the field-induced source and drain or to turn it ON or
7.4 Input/output protection devices 237
(a) Control Gate (b) S PG CG PG D

VPG = High N-channel
VCG = Low Turned off
VPG = High N-channel
VCG = High Turned on
S D N-channel
VPG = Low
VCG = High Turned off
VPG = Low N-channel

VCG = Low Turned on
Polarity Gates
Figure 7.12 (a) Ambipolar silicon nanowire (SiNW) FET featuring a control gate and two polarity gates.
(b) Conceptual band diagrams for the device. Four cases are shown, describing the four
combinations of high/low bias for the polarity gate and control gate of the device.
OFF. The basic structure and device operation are shown in Fig. 7.12. The range of
applied voltage ranges for the PG and CG are comparable. Digital circuits using these
transistors can therefore exploit both gates as logic inputs, enabling the design of
compact cells that implement XOR more efficiently than in CMOS. The ability of a
single double-gate nanowire FET with in-field polarity control to implement the XOR
function enables several applications and advantages in logic circuit design. As an
alternative, the substrate of an SOI wafer can be used as back gate to act as polarity
electrode [61]. It is also possible to select the polarity of a nanowire transistor by using
a single polarity gate at the source side of the channel [62,63,64].
7.4 Input/output protection devices
The input/output (I/O) transistors of an integrated circuit are exposed to the outside
world and can experience electrostatic discharges that would normally “kill” a regular
transistor. For example, a person touching the I/O pin of an integrated circuit could
deliver a spike of electrostatic electricity. The amplitude of the voltage spike might reach
several thousand volts for a short period of time. The Human Body Model (HBM)
represents the electrostatic discharge delivered by someone touching an I/O pin by a
100 pF capacitor holding the electrostatic voltage. The electrostatic discharge is deliv-
ered to the I/O transistors through a 1.5 kΩ resistor representing the average resistance of
a person handling an integrated circuit.
To prevent electrostatic discharge (ESD) induced damages from occurring in inte-
grated circuits, it is essential to develop and implement ESD protection structures. An
effective way to protect the electronics system against an ESD event is to incorporate
an ESD protection structure on the microchip to increase the survivability of the core
circuit when an ESD event occurs. These protections are usually made out of diodes or
thyristor-like devices that clamp the input/output voltage to values within the GND–VDD
voltage bracket. In a diode-based ESD protection, negative voltage spikes are shorted
to GND by a diode and positive voltage spikes are clamped to VDD by a second diode.
These ESD protection devices need to be in a high-impedance state during the normal
system operation and must be turned on quickly when the ESD event takes place so that
the current generated can be conducted by the protection devices and discharged to the
ground or supply rail. It is also important that the ESD protection devices not be
damaged by the ESD stress and return to a high-impedance state after the ESD event
has occurred [65].
There is, to date, very little published literature on ESD testing of nanowire
devices although there is a publication appearing in 2009 by Liu et al. reporting
the results of ESD testing of polysilicon nanowire FETs [66]. The transistors were
tested in the diode configuration (drain tied to gate) using a transmission line
pulsing technique. It was found that ESD robustness of these devices depends on
the nanowire dimension, number of nanowires in parallel, and layout topology: a
higher ESD robustness can be obtained by decreasing the channel length and
increasing the number of nanowires placed in parallel. For devices having a fixed
number of parallel nanowires, improved ESD robustness and smaller area consump-
tion can be achieved using a multiple drain/source layout. GAA nanowire transistors
with diameter of 10 nanometers and a gate oxide thickness of 5 nm exhibit an HBM
ESD tolerance of only 435 V, a level much lower than that of typical bulk
MOSFETs and that of the industry ESD standards for commercial applications.
SEM/TEM failure analysis proves that the poor heat conduction properties of the
SOI structure and the very small section of the nanowire channels are the probable
causes of vulnerability to ESD stress. On the other hand, the nanowire devices
present several favorable features: the floating body enables no-snapback I–V
characteristic and low holding voltages, and the use of multi-finger (drain and
source) and multi-nanowire layouts improves area efficiency. Furthermore, the
ESD robustness of GAA nanowire FETs is superior to that of FinFETs in terms
of the failure current and trigger voltage [67].
7.5 Chemical and biochemical sensors
In some applications, frequently called “More than Moore” applications, it is suitable to

combine pure microelectronic circuitry with a layer of devices such as sensors or
actuators to create compact monolithic systems with high levels of functionality. For
example, it can be contemplated making intelligent, implantable medical biosensors that
can be remotely accessed to monitor outpatients at home instead of them having to
remain in a hospital environment. Nanowire-based biosensors are actively being devel-
oped to detect early warning signs of a variety of medical conditions such as heart
disease or cancer therapy [68], for real time monitoring of blood sugars for diabetes,
amongst others.
Semiconductor nanowires and nanowire transistors are particularly well adapted to
the fabrication of chemical or biochemical sensors for several reasons:
Target species
Linker
Dielectric
Semiconductor
Figure 7.13 Functionalization of a nanowire using a linker.
1. Nanowires have an extremely high surface-to-volume ratio, which is ideal for

sensing minute quantities of a chemical compound [69].
2. The liquid–solid interface of a nanowire transistor has a strong influence on the
electronic properties of the nanowire and the presence of electrically charged
molecules can easily be detected through changes in nanowire resistivity.
3. It is possible to create dense arrays of nanowire sensors and interconnect them to
readout electronics.
4. Nanowire sensors can be re-usable [70].
5. Silicon nanowire sensor devices are compatible with CMOS processing and can,
therefore, offer biomedical and biochemical “system-on-chip” (SoC) solutions
[71,72,73,74,75,76].
Furthermore, the use of top-down silicon fabrication techniques can insure wafer-
scale device integration and repeatable device fabrication based on reliable process
techniques established over the years by the semiconductor industry.
The general principle behind the operation of nanowire transistor detection of a
chemical species is the creation of electric charges at the surface of the nanowire.
These charges modulate the conductivity of the wire in such a way that a variation of
current can be measured. Calibration techniques are used to establish a correlation
between the variation of current and the concentration of the chemical species to be
measured. The channel of the nanowire transistor can be covered by a gate dielectric
or/and by “functionalizing molecules,” or “linkers” that are synthesized to selectively
link to molecules of the species to be detected as shown in Fig 7.13 [77].
Since the detection takes place in the channel region, the nanowire cannot be fully
surrounded by a gate stack, in order to allow a portion of the sensitive channel region to
be exposed to the ambient. This is usually done using one of the following methods:
1. Back gating technique: One can use a back gate such as the silicon substrate under-
neath the buried oxide in the case of an SOI nanowire to modulate the current in the
device while most of the channel surface area is exposed to the ambient [78]. Using
this approach a circuit consisting of 36 clusters of five individually addressable
nanowires each and an integrated silicon nanowire array biosensor has been demon-
strated. The device is capable of sensing 1 fg/ml of human cardiac troponin-T (a key
protein biomarker that is present in elevated concentrations in the bloodstream of
patients suffering from acute myocardial infarction, or “heart attack”) in an assay
buffer solution, as well as 30 fg/mL in an undiluted serum environment. The
conductance changes of the individual nanowires are obtained through direct elec-
trical measurement. This array chip can detect ultralow concentrations of biomarkers
in human serum solutions, where the total protein concentration exceeds the mini-
mum detectable concentration of the target biomolecule by approximately 12 orders
of magnitude, demonstrating the high sensitivity and rapid response of silicon
nanowire technology for biomedical applications [79].
2. Liquid gating technique: Gating can be achieved through use of a liquid electrolyte in
which the species to detect is dissolved or suspended. An example of this detection
technique can be found in [80] where complementary silicon nanowire pH sensors
were made on a 150 mm silicon-on-insulator wafer using a conventional wafer-level
top-down process. One nanowire has an n-type channel and the other has a p-type
channel and they are mounted in a standard CMOS inverter configuration. The
measured output quantity is the output voltage of the inverter. The nanowire surfaces
were functionalized using 3-aminopropyl-triethoxysilane in order to obtain an amine
(-NH2) surface that can selectively respond to the presence of hydrogen ions. The
liquid gate reference electrode consists of a 0.1 M potassium phosphate buffer
solution with pH values ranging from 5 to 9 and connected to an Ag/AgCl reference
electrode. The resulting sensors exhibit an output voltage variation of 162 mV/pH for
a supply voltage VDD = 1 V. Many nanowires can be vertically stacked to increase
sensitivity and performance [81].
3. Vacuum-gap gate technique: In this case the gate can be all-around, but there is no
solid-state gate dielectric – the “dielectric” is a vacuum or air gap between the
nanowire and the gate electrode. Molecules entering the gap region can be detected
through a change of permittivity of the ambient in the gap, and thus a change of
electrical characteristics of the transistor [82].
4. Floating gate technique: One can use a functionalized floating gate electrode located
next to a control electrode, which can also be functionalized to simplify the fabrica-
tion process. When the target molecules bind to the linkers on the gate electrodes, the
overall dielectric constant of the material in the spacing between the control gate and
the floating gate is modified, and the current in the nanowire transistor shows
measurable variations. A protein sensor based on this floating gate sensing technique
integrated into a nano-interdigitated array was first demonstrated in 2009 [83]. The
sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus
immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml and
exhibits a high selectivity and reproducible specific detection. The sensor detection
limit can be improved by optimizing the geometrical parameters of array such as
nanowire width and height, inter-wire distance, as well as the gate oxide thickness.
This type of nanobiosensor, with real-time and label-free capabilities, can easily be
used for the detection of other proteins, DNA, virus and cancer markers. Moreover,
1.E-05
pH 7 pH 10
pH 10
1.E-06
pH 7
Drain current (A)
1.E-07
1.E-08
1.E-09
1.E-10 pH 4 pH 4
pH 4 pH 4
1.E-11
0 500 1000 1500 2000 2500 3000
Time (s)
Figure 7.14 Drain current variation with pH level at VDD = 1 V, VBG = 0 V, for a back-gated silicon
nanowire transistor of 20 nm width and 1 μm length. After [84].
on-chip associated electronics nearby the sensor can be integrated since its fabrica-
tion is compatible with complementary metal oxide semiconductor (CMOS)
technology.
As a general rule, the sensitivity of a nanowire sensor increases when reduced
doping, at smaller diameters and shorter channel lengths, is used. For maximum
sensitivity, the sensors should be operated in the depletion mode; that is, the doping
of the sensor and the molecule should have the same polarity [84]. It is, however, worth
pointing out that nanowire transistors with high doping concentration can achieve high
sensitivity, provided they are operated in the subthreshold region (i.e. in depletion);
backgated junctionless nanowire transistors have demonstrated very high sensitivity to
sensing pH levels. When such a device operates in the subthreshold region, it exhibits
3 orders of magnitude difference in current, responding to pH values changing from
4 to 7 to 10 as shown in Fig. 7.14 [85]. Nanowire sensors can also be made sensitive to
ionic concentrations on pH-neutral solutions such as that obtained by diluting phtha-
late in buffered Fisher pH 7 solution described in [86] with the detection of the
different pH levels shown in Fig. 7.15.
Detection sensitivity can be improved by increasing the number of sensing nanowires.
The most sensitive nanowire sensor reported so far consists of a 3D array of vertically
stacked horizontal silicon nanowire field-effect transistors. The array contains 140 fully
depleted and ultra-thin (15 to 30 nm) suspended channels. The channels are covered by a
thin gate dielectric. The nanowire conductivity can be controlled by either a reference
electrode or by three local gates: a back gate (an SOI wafer was used in this experiment)
and two symmetrical metal side-gates, which offers unique sensitivity tuning opportu-
nities. The nanowires were functionalized using (3-Aminopropyl)-triethoxysilane
(APTES) and were biotynilated for pH and streptavidin (protein) sensing, respectively.
These nanowire arrays are able to measure a streptavidin concentration of 17 aM
(attomoles), which is the lowest reported in literature to date. When operated in the
1.E-07
Relative buffer concentration
1.E-08 125 125 125
25
Drain current (A)
5
1.E-09
1
1.E-10
1.E-11
Dry Dry Dry Dry Dry
1.E-12
0 1000 2000 3000 4000 5000
Time (s)
Figure 7.15 Time dependence of the drain current ID demonstrating the sensitivity of back-gated nanowire
transistors to phthalate diluted at different concentrations in buffered Fisher pH 7 solutions.
After [85].
subthreshold regime, the devices functionalized with APTES show an extremely high
sensitivity (ΔID/pH) of ~0.70 decade/pH [87].
7.6 Summary
This chapter presents a survey of the application of nanowires in circuit and sensor
applications. The use of nanowires in novel circuit configurations and the performance
of nanowire transistors in logic, analog, and RF circuit has been highlighted for select
applications as well as SRAM and flash memory cells. The use of nanowire devices is
particularly well suited to new circuit architectures such as crossbar circuits and
“nanoscale application specific integrated circuits” (NASICs). The large surface area-
to-volume ratio of nanowires provides many advantages for sensing minute amounts of
chemicals and biochemicals. Applications of nanowires with detection sensitivity as low
as a few tens of attomoles are reported in the literature. “Nanowire transistors” in the
form of FinFETs are already in production at the most advanced nanoelectronics
fabrication sites, and as gate-all-around configurations and new device architectures
become available, most advanced circuitry will become based on these novel structures.
Their ability to act as switches, logic gates, memory cells, and sensors based on
configuration and processing, enables new circuit architectures and systems that can
be readily integrated together for new and not yet thought of applications.
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Preface

one-dimensional (1D) quantum conﬁnement effects become observable. The formation

Chapter 6: Charge transport in quasi-1D nanostructures investigates how charge

2 Multigate and nanowire transistors 18

2.5.1 Junctionless transistor 44

3 Synthesis and fabrication of semiconductor nanowires 54

4 Quantum mechanics in one dimension 81

5 Nanowire electronic structure 107

6 Charge transport in quasi-1D nanostructures 167

6.5.4 Alloy scattering 194

7 Nanowire transistor circuits 221

1.1 Moore’s law

10,000,000 IBM CPU

1.2 The MOS transistor

Figure 1.4 Schematic view of a classical bulk MOSFET.

material is silicon, although other semiconductors such as germanium (Ge), silicon

Drain Current, ID (logarithmic scale)

Drain Current, ID (linear scale)

where kB is Boltzmann’s constant, T is the temperature, q is the charge of an

Parameter Equation Unit Scaling factor

Physical dimensions: L, W, Xj, Xdepl m γ1

1.3 Classical scaling laws

1.4 Short-channel effects

(Amperes, logarithmic scale)

1.5 Technology boosters

1.5.1 New materials

1.5.3 Electrostatic control of the channel

1.6 Ballistic transport in nanotransistors

1.6.1 Top-of-the-barrier model

where T is the temperature in degrees Kelvin, kB is Boltzmann’s constant and m* is the

ID ¼ WCox ðVG VTH Þvinj ; ð1:5Þ

Rc is a “reﬂection” or backscattering coefﬁcient that represents the degree of ballisticity.

1.6.2 Ballistic scaling laws

Parameter Equation Unit Scaling factor

Physical dimensions: L, W, Xj, Xdepl m γ1

miniaturization of transistors is outlined. A summary of some of the challenges to the

[16] S. Salahuddin, S. Datta,“Can the subthreshold swing in a classical FET be lowered

As presented in Chapter 1, the use of a multigate architecture is a technology booster that

2.2 The multigate architecture

(a) (b) (c)

2.3 Reduction of short-channel effects using multigate architectures

The potential distribution in the channel of a fully depleted, inversion-mode n-channel

d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ qNa

dEx ðx; y; zÞ dEy ðx; y; zÞ dEz ðx; y; zÞ

2.3.1 Single-gate MOSFET

d 2 Φðx; y; zÞ d 2 Φðx; y; zÞ qNa

Φðx; zÞ ¼ c0 ðxÞ þ c1 ðxÞz þ c2 ðxÞz2 : ð2:5Þ

εox Φf ðxÞ ΦG 1 εox Φf ðxÞ ΦG 2

d 2 Φf ðxÞ εox Φf ðxÞ ΦG qNa

which permits Eq. (2.7) to be rewritten as

2.3.2 Double-gate MOSFET

Φðx; zÞ ¼ c0 ðxÞ þ c1 ðxÞz þ c2 ðxÞz2 : ð2:11Þ

1. assuming the device is inﬁnitely wide in the y direction leads to dΦ=dy ¼ 0;

εox Φs ðxÞ ΦE 1 εox Φs ðxÞ ΦG 2

Expressing Φðx; zÞ as a function of Φc ðxÞ results in

d 2 Φc ðxÞ ΦG Φc ðxÞ qNa

2.3.3 Triple- and quadruple-gate MOSFETs

2.3.4 Cylindrical gate-all-around MOSFET

Φðx; rÞ ¼ co ðxÞ þ c1 ðxÞ r þ c2 ðxÞ r2 : ð2:21Þ

The boundary conditions to Poisson’s equation for the case represented by

d 2 Φc ðxÞ ΦG Φc ðxÞ qNa

is the natural length for a cylindrical channel in a gate-all-around (GAA)

200 Subthreshold slope 100

where ny ¼ 1; 2; 3; …; nz ¼ 1; 2; 3; …, and where mi is the effective mass of electrons in