CHAPTER 1

INTRODUCTION TO VLSI DOMAIN

1.1 VLSI Design

The complexity of VLSI is being designed and used today makes the manual
approach to design impractical. Design automation is the order of the day. With the rapid
technological developments in the last two decades, the status of VLSI technology is
characterized by the following.

A steady increase in the size and hence the functionality of the ICs:

• A steady reduction in feature size and hence increase in the speed of operation as well as
gate or transistor density.

• A steady improvement in the predictability of circuit behavior.

• A steady increase in the variety and size of software tools for VLSI design.

The above developments have resulted in a proliferation of approaches to VLSI design.

1.2 History of VLSI

VLSI began in the 1970s when complex semiconductor and communication

technologies were being developed. The microprocessor is a VLSI device. The term is no
longer as common as it once was, as chips have increased in complexity into the hundreds
of millions of transistors.

This is the field which involves packing more and more logic devices into smaller
and smaller areas. VLSI circuits can now be put into a small space few millimeters across.
VLSI circuits are everywhere. Our computer, our car, our brand new state-of-the-art digital
camera, the cell-phones, and what we have.

1.3 Various integrations

Over time, millions, and today billions of transistors could be placed on one chip,
and to make a good design became a task to be planned thoroughly.

In the early days of integrated circuits, only a few transistors could be placed on a
chip as the scale used was large because of the contemporary technology, and
manufacturing yields were low by today's standards. As the degree of integration was small,

1
the design was done easily. Over time, millions, and today billions of transistors could be
placed on one chip, and to make a good design became a task to be planned thoroughly.

1.3.1 SSI technology

The first integrated circuits contained only a few transistors called "small-scale
integration" (SSI), digital circuits containing transistors numbering in the tens provided a
few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips
TAA320 had as few as two transistors. The term Large Scale Integration was first used by
IBM scientist Rolf Landauer when describing the theoretical concept from there came the
terms for SSI, MSI, VLSI, and ULSI.

1.3.2 MSI technology

The next step in the development of integrated circuits, taken in the late 1960s,
introduced devices which contained hundreds of transistors on each chip, called "medium-
scale integration" (MSI).

They were attractive economically because while they cost little more to produce
than SSI devices, they allowed more complex systems to be produced using smaller circuit
boards, less assembly work (because of fewer separate components), and a number of other
advantages.
1.3.3 LSI technology

Further development, driven by the same economic factors, led to "Large Scale
Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip.
Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors,
that began to be manufactured in moderate quantities in the early 1970s, had under 4000
transistors. True LSI circuits, approaching 10,000 transistors, began to be produced around
1974, for computer main memories and second-generation microprocessors.

1.3.4 VLSI technology

Final step in the development process, starting in the 1980s and continuing through
the present, was in the early 1980s, and continues beyond several billion transistors as of
2009.In 1986 the first one megabit RAM chips were introduced, which contained more than
one million transistors. Microprocessor chips passed the million transistor mark in 1989 and
the billion transistor mark in 2005.The trend continues largely unabated, with chips
introduced in 2007 containing tens of billions of memory transistors.

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1.4 VLSI Design Flow

Start

Design Entity

Logic Synthesis
Pre layout Simulation

System Partitioning

Floor Planning Pre layout Simulation

Placement

Finish Routing Circuit Extraction

Fig 1.1 VLSI design flow

3
 CHAPTER 2

LITERATURE SURVEY
2.1 Brief study about adders

With the advancements in VLSI technology, the circuit designs are getting miniature
in size, consuming lesser power for performing their intended operation and becoming
faster in operation. We all know that area, power and speed are the major constraints in
VLSI design, and the designers are taking enormous efforts to improve their designs
relative to these constraints, but all of these cannot be improved simultaneously.

In this modern era of technological advancements, everything is becoming fast-

paced and heading towards completely digital processes. Hence, there is an immense
need of developing faster processors which would operate on digital signals, but as we
head towards improving any one of the design parameter, the other parameters are also
affected, and so with the improvement in speed of operation of any circuit, its area
occupancy also increases.

In circuits like digital signal processor (DSP), microprocessor, or arithmetic and logic
unit (ALU) of any processor, the unit performing arithmetic operations is very important
when considered with respect to the design constraints mentioned above. Most arithmetic
circuits consist of adder, subtractor, multiplier, divider, etc.; the adder unit being the most
basic unit among all the other units.

In this paper, we are comparing various adders in terms of their delay and area, as the
adder is used in the construction of other arithmetic circuits and the performance of the
adder is decisive of the performance of other circuits employing the use of adders.

2.1.1 Single-bit Adders

2.1.1.1 Half adder

Half adder is a combinational arithmetic circuit that adds two numbers and produces a
sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is
the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is
clear that a half adder circuit can be easily constructed using one X-OR gate and one AND
gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage.

4
The half adder can add only two input bits (A and B) and has nothing to do with the carry
if there is any in the input. So if the input to a half adder have a carry, then it will be
neglected it and adds only the A and B bits. That means the binary addition process is not
complete and that’s why it is called a half adder. The truth table, schematic representation
and XOR,AND realization of a half adder are shown in the figure below.

Table 2.1 Truth table Fig. 2.1 Schematic and realization of half adder
NAND gates or NOR gates can be used for realizing the half adder in universal logic and
the relevant circuit diagrams are shown in the figure below.

Fig. 2.2 Half adder using NAND & NOR logic

2.1.1.2 Full Adder

The full adder is a little more difficult to implement than a half adder. The main
difference between a half adder and a full adder is that the full adder has three inputs and
two outputs. The two inputs are A and B, and the third input is a carry input C IN. The
output carry is designated as COUT , and the normal output is designated as S.

5
 Table 2.2 Truth table of Full Adder

The output S is an EX – OR between the input A and the half adder SUM output
B. The COUT will be true only if any of the two inputs out of the three are HIGH or at
logic1.
Thus, a full adder circuit can be implemented with the help of two half adder
circuits. The first half adder circuit will be used to add A and B to produce a partial sum.
The second half adder logic can be used to add CIN to the sum produced by the first half
adder circuit. Finally, the output S is obtained. If any of the half adder logic produces a
carry, there will be an output carry. Thus, COUT will be an OR function of the half adder
CARRY outputs.

.Fig. 2.3 Full Adder

6
 Figure 2.4 Schematic representation of a single bit Full Adder
With the help of this type of symbol, one can add two bits together,
taking a carry from the next lower order of magnitude and sending a
carry to the next higher order of magnitude.
NAND gates or NOR gates can be used for realizing the full adder in universal logic
and the relevant circuit diagrams are shown in the figure below.

Figure 2.5 Full Adder using NAND Logic

7
 Figure 2.6 Full adder using NOR logic
2.1.2 Multi-bit Adders
The half-adder and the full-adder are the simplest addition elements which are limited
to single-bit addition. For performing multi-bit addition, we need to cascade multiple full-
adder (FA) units.

The design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder
(CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLA), Carry Save
Adder (CSA), Carry Select Adder (CSlA) and Carry Bypass Adder (CBA) are discussed
below. The each and every adder is named based on the propagation of carry between the
stages.

2.2.1 Ripple Carry Adder

Arithmetic operations like addition, subtraction, multiplication, division are basic

operations to be implemented in digital computers using basic gates like AND, OR, NOR,
NAND etc. Among all the arithmetic operations if we can implement addition then it is easy
to perform multiplication (by repeated addition), subtraction (by negating one operand) or
division (repeated subtraction). Half Adders can be used to add two one bit binary numbers
and Full adders to add two three bit numbers. The block diagram of 4-bit Ripple Carry Adder
is shown here below in Figure 2.1. It is possible to create a logical circuit using multiple full
adders to add N-bit numbers. Each full adder inputs a C in, which is the Cout of the previous
adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the
next full adder. Note that the first (and only the first) full adder may be replaced by a half
adder (under the assumption that Cin = 0). The block diagram of 4-bit Ripple Carry Adder is
shown here below –

8
 Fig 2.7 A 4 bit Ripple Carry Adder

The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple carry adder is relatively slow when number of stages get increased,
since each full adder must wait for the carry bit to be calculated from the previous full
adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each
full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full
adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31
* 2 (for carry propagation in later adders) = 65 gate delays.

The disadvantage of the ripple-carry adder is that it can get very slow when one needs to add
many bits.

2.2.2 Carry Look Ahead Adder

A carry-look ahead adder (CLA) is a type of adder used in digital logic. A carry-look
ahead adder improves speed by reducing the amount of time required to determine carry
bits. It can be contrasted with the simpler, but usually slower ripple carry adder for which
the carry bit is calculated alongside the sum bit, and each bit must wait until the previous
carry has been calculated to begin calculating its own result and carry bits (see adder for
detail on ripple carry adders). The carry-look ahead adder calculates one or more carry
bits before the sum, which reduces the wait time to calculate the result of the larger value
bits. The kogge- stone adder and brent- kung adder are examples of adder.

9
 Fig 2.8 A 4 bit Carry Look Ahead Adder
Carry look ahead logic uses the concepts of generating and propagating carries.
Although in the context of a carry look ahead adder, it is most natural to think of
generating and propagating in the context of binary addition, the concepts can be used
more generally than this. In the descriptions below, the word digit can be replaced
by bit when referring to binary addition of 2.
The addition of two 1-digit inputs A and B is said to generate if the addition will
always carry, regardless of whether there is an input carry (equivalently, regardless of
whether any less significant digits in the sum carry). For example, in the decimal addition
52 + 67, the addition of the tens digits 5 and 6 generates because the result carries to the
hundreds digit regardless of whether the ones digit carries (in the example, the ones digit
does not carry (2+7=9)).
In the case of binary addition, A + B generates if and only if both A and B are 1. If
we write G(A, B) to represent the binary predicate that is true if and only if A+B
generates, we have:
G(A,B) = A+B
The addition of two 1-digit inputs A and B is said to propagate if the addition will
carry whenever there is an input carry (equivalently, when the next less significant digit in
the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens
digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones
were to carry (which in this example, it does not). Note that propagate and generate are
10
defined with respect to a single digit of addition and do not depend on any other digits in
the sum.
In the case of binary addition, A +B propagates if and only if at least one
of A or B is 1. If we write P(A, B) to represent the binary predicate that is true if and only
if A+B propagates, we have
P(A,B) = A+B
Sometimes a slightly different definition of propagate is used. By this definition A
+ B is said to propagate if the addition will carry whenever there is an input carry, but
will not carry if there is no input carry. Fortunately, due to the way generate and propagate
bits are used by the carry look ahead logic, it doesn't matter which definition is used. In
the case of binary addition, this definition is expressed by:
Pi= Ai⊕Bi

For binary arithmetic, or is faster than xor and takes fewer transistors to
implement. However, for a multiple-level carry look ahead adder, it is simpler to use
’
P (A,B).
Given these concepts of generate and propagate, when will a digit of addition
carry? It will carry precisely when either the addition generates or the next less significant
bit carries and the addition propagates. Written in Boolean algebra, with Ci the carry bit
of digit i, and Pi and Gi the propagate and generate bits of digit i
respectively, Ci+1 = Gi + (Pi·Ci).
Implementation details
For each bit in a binary sequence to be added, the Carry Look Ahead Logic will
determine whether that bit pair will generate a carry or propagate a carry. This allows the
circuit to "pre-process" the two numbers being added to determine the carry ahead of time.
Then, when the actual addition is performed, there is no delay from waiting for the ripple
carry effect (or time it takes for the carry from the first Full Adder to be passed down to
the last Full Adder). Below is a simple 4-bit generalized Carry Look Ahead circuit that
combines with the 4-bit Ripple Carry Adder we used above with some slight adjustments:
For the example provided, the logic for the generate (g) and propagate (p) values
are given below. Note that the numeric value determines the signal from the circuit above,
starting from 0 on the far left to 3 on the far right:
C1 = G0 +P0·C0

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 C 2= G1 + P1·C1
C3 = G2 + P2·C2
C4= G3 + P3·C3
Substituting C1 into C2, then C2 into C3, then C3 into C4 yields the expanded
equations:
C1 = G0 +P0·C0
C 2= G1 + G0·P1 + C0·P0·P1
C3 = G2+ G1·P2 + G0·P1·P2 + C0·P0·P1·P2
C4 = G3 + G2·P3 + G1·P2·P3 + G0·P1·P2·P3 + C0·P0·P1·P2·P3
To determine whether a bit pair will generate a carry, the following logic works:
G i = A i · Bi
To determine whether a bit pair will propagate a carry, either of the following logic
statements work:
Pi= Ai ⊕Bi

The reason why this works is based on evaluation of C1 = G0 +P0·C0. The

only difference in the truth tables between (Pi= A⊕B) and (A+B) is when
both A and B are 1. However, if both A and B are 1, then the G0 term is 1 (since its
equation is A·B) and the P0· C0 term becomes irrelevant. The XOR is used normally
within a basic full adder circuit; the OR is an alternate option (for a carry look ahead
only) which is far simpler in transistor-count terms.
The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit
by having each CLA Logic circuit produce a propagate and generate signal to a higher-
level CLA Logic circuit. The group propagate (PG) and group generate (GG) for a 4-bit
CLA are:
PG = P0·P1·P2·P3
GG = G3 + G2·P3 + G1·P2·P3 + G0·P1·P2·P3
Putting 4 4-bit CLAs together yields four group propagates and four group
generates. A Look ahead Carry Unit (LCU) takes these 8 values and uses identical logic to
calculate Ciin the CLAs. The LCU then generates the carry input for each of the 4 CLAs
and a fifth equal to C16.
The calculation of the gate delay of a 16-bit adder (using 4 CLAs and 1 LCU) is not as
straight forward as the ripple carry adder. Starting at time of zero:

 calculation of Pi and Gi is done at time 1

12
  calculation of Ci is done at time 3
 calculation of the PG is done at time 2
 calculation of the GG is done at time 3
 calculation of the inputs for the CLAs from the LCU are done at
 time 0 for the first CLA
 time 5 for the second, third & fourth CLA
 calculation of the are done at
 time 4 for the first CLA
 time 8 for the second, third & fourth CLA
 calculation of the final carry bit (C16) is done at time 5
 The maximum time is 8 gate delays (for S8-15). A standard 16-bit ripple carry adder
would take 31 gate delays.

2.3 Multiplexer
A Multiplexer is a device that allows one of several analog or digital input signals
which are to be selected and transmits the input that is selected into a single medium.
Multiplexer is also known as Data Selector. A multiplexer of 2n inputs has n select lines
that will be used to select input line to send to the output. Multiplexer is abbreviated as
Mux. MUX sends digital or analog signals at higher speed on a single line in one shared
device. It recovers the separate signals at the receiving end. The Multiplexer boosts or
amplifies the information that later transferred over network within a particular bandwidth
and time.

13
 Fig 2.9 A n:1 Mux

A two–to–one multiplexer is a combinational circuit that uses one control switch

(S) to connect one of two input data lines (A or B) to a single output (Z). Only one of the
input data lines can be aligned to the output of the multiplexer at any given time.

Fig 2.10 A Schematic diagram Table 2.3 A 2x1 mux truth table

14
Fig 2.11 Realization of 2:1 MUX

15
 CHAPTER 3
PROPOSED PROJECT
3.1 Introduction

Binary addition is the single most important operation that a processor performs. Most
of the adders have been designed for synchronous circuits even though there is a strong
interest in clockless/asynchronous processors/circuits. Asynchronous circuits do not
assume any quantization of time. Therefore, they hold great potential for logic design as
they are free from several problems of clocked(synchronous) circuits. In principle, logic
flow in asynchronous circuits is controlled by a request-acknowledgment hand shaking
protocol to establish a pipeline in the absence of clocks. Explicit handshaking blocks for
small elements, such as bit adders, are expensive. Therefore, it is implicitly and efficiently
managed using dual-rail carry propagation in adders. A valid dual-rail carry output also
provides acknowledgment from a single-bit adder block. Thus, asynchronous adders are
either based on full dual-rail encoding of all signals (more formally using null convention
logic that uses symbolically correct logic instead of Boolean logic) or pipelined operation
using single-rail data encoding and dual-rail carry representation for acknowledgments.
While these constructs add robustness to circuit designs, they also introduce significant
overhead to the average case performance benefits of asynchronous adders. Therefore, a
more efficient alternative approach is worthy of consideration that can address these
problems.

This brief presents an asynchronous parallel self-timed adder(PASTA) using the

algorithm originally proposed. The design of PASTA is regular and uses half-adders (HAs)
along with multiplexers requiring minimal interconnections. Thus, it is suitable for VLSI
implementation. The design works in a parallel manner for independent carry chain
blocks. The implementation in this brief is unique as it employs feedback through XOR
logic gates to constitute a single-rail cyclic asynchronous sequential adder. Cyclic circuits
can be more resource efficient than their acyclic counterparts.

On the other hand, wave pipelining (or maximal rate pipelining) is a technique that
can apply pipelined inputs before the outputs are stabilized. The proposed circuit manages
automatic single-rail pipelining of the carry inputs separated by propagation and inertial
delays of the gates in the circuit path.

16
 Thus, it is effectively a single-rail wave-pipelined approach and quite different from
conventional pipelined adders using dual-rail encoding to implicitly represent the
pipelining of carry signals.

3.2 Background

There are a myriad designs of binary adders and we focus hereon asynchronous self-
timed adders. Self-timed refers to logic circuits that depend on and/or engineer timing
assumptions for the correct operation. Self-timed adders have the potential to run faster
averaged for dynamic data, as early completion sensing can avoid the need for the worst
case bundled delay mechanism of synchronous circuits. They can be further classified as
follows.

3.3 Design of PASTA

In this section, the architecture and theory behind PASTA is presented. The adder first
accepts two input operands to perform half additions for each bit. Subsequently, it iterates
using earlier generated carry and sums to perform half-additions repeatedly until all carry
bits are consumed and settled at zero level.

Fig 3.1. GENERAL BLOCK DIAGRAM OF PASTA

Fig. 3.2. State diagrams for pasta. (a) initial phase. (b) iterative phase

17
3.3.1 Architecture of PASTA

The general architecture of the adder is shown in Fig. 1.8Theselection input for
two-input multiplexers corresponds to the Req handshake signal and will be a single 0 to
1 transition denoted by SEL. It will initially select the actual operands during SEL = 0 and
will switch to feedback/carry paths for subsequent iterations using SEL = 1. The feedback
path from the HAs enables the multiple iterations to continue until the completion when
all carry signals will assume zero values.

3.3.2 State Diagrams

In Fig.3.2 two state diagrams are drawn for the initial phase and the iterative phase
of the proposed architecture. Each state is represented by (Ci+1 Si) pair where Ci+1, Si
represents carry out and sum values, respectively, from the ith bit adder block. During the
initial phase, the circuit merely works as a combinational HA operating in fundamental
mode. It is apparent that due to the use of HAs instead of FAs, state (11) cannot appear.
During the iterative phase (SEL = 1), the feedback path through multiplexer block is
activated. The carry transitions (Ci) are allowed as many times as needed to complete the
recursion.

From the definition of fundamental mode circuits, the present design cannot be
considered as a fundamental mode circuit as the input–outputs will go through several
transitions before producing the final output. It is not a Muller circuit working outside the
fundamental mode either as internally, several transitions will take place, as shown in the
state diagram. This is analogous to cyclic sequential circuits where gate delays are utilized
to separate individual states.

3.3.3 Recursive Formula for Binary Addition

Let and denote the sum and carry, respectively, for ith bit at the jth iteration. +1

The j th iteration for the recursive addition is formulated by

18
 th
The recursion is terminated at k iteration when the following condition is met:

Now, the correctness of the recursive formulation is inductively proved as

follows.

Theorem 1: The recursive formulation of (1)–(4) will produce correct sum for any
number of bits and will terminate within a finite time.

Proof: We prove the correctness of the algorithm by induction on the required number of
iterations for completing the addition (meeting the terminating condition).
Basis: Consider the operand choices for which no carry propagation is required, i.e 0= 0 for ∀i,

i∈ [0..n]. The proposed formulation will produce the correct result by a single-bit computation time and terminate instantly as (4) is met.
Induction: Assume that +1≠0for some ith bit at kth iteration.

th
Let l be such a bit for which +1= 1. We show that it will be successfully transmitted to next higher bit in the (k + 1) iteration.
As shown in the state diagram, the kth iteration of lth bit state( +1, ) and (l + 1)th bit state ( +2, +1 ) could be in any of (0, 0), (0, 1), or (1, 0) states. As +1=
1, it implies that = 0. Hence, from (3), +1 +1= 0 for any input condition between0 to l bits.

th th
We now consider the (l + 1) bit state ( +2, +1 )for k iteration. It could also be in any of (0, 0), (0, 1),
th th
or (1, 0) states. In (k+1) iteration, the (0, 0) and (1, 0) states from the k iteration will correctly produce output
of (0, 1) following (2) and (3). For (0, 1) state, the carry successfully propagates through this bit level following
(3).

Thus, all the single-bit adders will successfully kill or propagate the carries until
all carries are zero fulfilling the terminating condition.

19
 The mathematical form presented above is valid under the condition that the
iterations progress synchronously for all bit levels and the required input and outputs
for a specific iteration will also be in synchrony with the progress of one iteration. In
the next section, we present an implementation of the proposed architecture which is
subsequently verified using simulations.

20
  NGO project, skip to step 8. If you are
creating an HDL or schematic project,
 Click Next, and optionally, add existing source files to your project in the Add
Existing Sources page.
 Click Next to display the Project Summary page.
 Click Finish to create the project.

5.4.2 What to expect

Project Navigator creates the project file, project_name.ise, in the directory you
specified. All source files related to the project appear in the Project Navigator Sources
tab. Project Navigator manages your project based on the project properties (top-level
module type, device type, synthesis tool, and language) you selected when you created the
project. It organizes all the parts of your design and keeps track of the processes necessary
to move the design from design entry through implementation to programming the
targeted Xilinx device.

5.4.3 What to do next

You can perform any of the following:

 Create and add source files to your project.

 Add existing source files to your project.

 Run processes on your source files.

5.5 Using ISE example projects

To help familiarize you with the ISE™ software and with FPGA and CPLD
designs, a set of example designs is provided with Project Navigator. The examples show
different design techniques and source types, such as VHDL, Verilog, ABEL, schematic,
or EDIF, and include different constraints and stimulus files.

5.5.1 To open an example

1. Select File > Open Example.

2. In the Open Example Project dialog box, select the Sample Project Name that you
want to use.

35
 To help you choose an example project, the Project Description field describes each
project. In addition, you can scroll to the right to see additional fields, which provide
details about the project.

3. In the Destination Directory field, enter a directory name or browse to the

directory.

4. Click OK.

5.5.2 What to expect

The example project is placed in the directory you specified in the Destination
Directory field and is automatically opened in Project Navigator. You can then run
processes on the example project and save any changes.

5.5.3 Creating a source file

A source file is any file that contains information about a design. Project
Navigator provides a wizard to help you create new source files for your project.

5.5.4 What to do first

Open a project in Project Navigator.

5.5.5 To create a source file

1. Select Project > New Source.

2. In the New Source Wizard, select the type of source you want to create.

Different source types are available depending on your project properties (top-level
module type, device type, synthesis tool, and language). Some source types launch
additional tools to help you create the file, as described in Source File Types.

3. Enter a name for the new source file in the File Name field. Follow the naming
conventions described in File Naming Conventions.

4. In the Location field, enter the directory name or browse to the directory.

5. Select Add to Project to automatically add this source to the project.

6. Click Next.

7. If you are creating a source file that needs to be associated with an existing source
file, select the appropriate source file, and click Next. If this does not apply, skip to the
next step.

36
 8. In the New Source Wizard - Summary window, verify the information for the new
source, and click Finish.

5.5.6 What to expect

After you click Finish, the New Source wizard closes. In some cases, a related tool
is launched in which you can finish creating your file. After the source file is created, it
appears in the Project Navigator Sources tab. If you selected Add to Project when creating
the source file, the file is automatically added to the project.

5.5.7 Adding a source file to a project

Project Navigator allows you to add an existing source file to a project. The source
file can reside in the project directory or in a remote directory. If you generated your
source file using the New Source wizard and selected Add to Project, you do not need to
add the source file to your project; it is automatically part of your project.

5.5.8 What to do first

Open a project in Project Navigator.

5.5.9 To add a source file to a project

1. Select Project>Add Source.

2. In the Add Existing Sources dialog box, browse to the source file and select it.

3. Click Open.

5. In the Adding Source Files dialog box, select the Design View in which you want
the source file to appear.

6. Click OK.

37
 b = 32'b00100110000101010100000000000010;

#20 sel=1'b1;

end

always #5 clk=~clk;

endmodule

GDI Techniques:

2.1 GATE DIFFUSION INPUT (GDI) The performance of a digital circuit is judged by its speed in producing output
when an input is given to it. The most common technology for designing digital circuits is the CMOS technology.
After the development of CMOS logic, there was increasing need to optimize circuit in terms of speed. One
technique thought of was by using Pass Transistor Technology (PTL) which makes use of lesser number of gates
to realize an operation. The Transmission Gate (TG) is one of them which are typically a combination of NMOS
and PMOS transistors connected in parallel. The GDI cell represents another form of pass transistor technology
which looks similar to CMOS but differs in the supply provided to the input terminals. The main advantages of
PTL over conventional CMOS design are as follows- 1) lesser number of transistors results in low power
dissipation and lesser delay. 2) Lesser number of transistors so smaller area and lesser interconnect effects.
However, PTL technologies also suffer from two main problems such as reduced circuit speed at low power
operations and greater static power dissipation. GDI technique that can be used to design fast, low power
circuits using only a few transistors. The GDI cell is similar to a CMOS inverter structure. In a CMOS inverter the
source of the PMOS is connected to VDD and the source of NMOS is grounded. But in a GDI cell this might not
necessarily occur. There are some important differences between the two. The three inputs in GDI are
namely1) G- common inputs to the gate of NMOS and PMOS 2) N- input to the source/drain of NMOS 3) P-
input to the source/drain of PMOS Bulks of both NMOS and PMOS are connected to N or P (respectively), that
is it can be arbitrarily biased unlike in CMOS inverter. Moreover, the most important difference between CMOS
and GDI is that in GDI N, P and G terminals could be given a supply ‘VDD’ or can be grounded or can be
supplied with input signal depending upon the circuit to be designed and hence effectively minimizing the
number of transistors used in case of most logic circuits (eg. 12 AND, OR, XOR, MUX, etc). As the allotment of
supply and ground to PMOS and NMOS is not fixed in case of GDI, therefore, problem of low voltage swing
arises in case of GDI which is a drawback and hence finds difficulty in case of implementation of analog circuits.
2.2 OPERATIONAL ANALYSIS The most common problem with PTL technique is its low voltage swing. An extra
buffer circuitry may be used additionally to eliminate the problem of low swing and improve drivability. The
problem of low swing can be understood with the help of a random function shown in figure and table.
Functionality Of any Random Function using GDI A B Functionality Logic A B Y 0 0 pMOS Trans Gate Vtp 0 1
CMOS Inverter 1 1 0 nMOS Trans Gate 0 1 1 CMOS Inverter 0 Table 2.1 GDI truth table for inverter The problem
of low swing occurs only when A=0 and B=0 where the voltage level is VTP instead of 0.This occurs due to the
poor high to low transition characteristics of PMOS. In the rest of the cases it provides full swing. 2.3 GDI CELL
USING SHANNON EXPANSION Shannon’s Expansion Theorem: The Shannon’s expansion theorem is used
iteratively to build any BDD for a given Boolean function. Shannon’s expansion theorem states that “Any
switching function of n variables can be expressed as a sum of products of n literals, one for each variable’. 13
Let us assume that f (x1, x2, ..., xn) is a switching function of n variables. According to Shannon , one way of
expressing this function is f(x1, x2, ..., xn) = x1f(1, x2, ..., xn) + x1'f(0, x2, ..., xn) On the right side, the function is
the sum of two terms, one of them relevant when x1 is equal to 1 and the other when x1 is equal to 0 . The first
term is x1 times what remains of f when x1 is equal to the value 1 and the second term is x1' times what
remains of f when x1 is equal to 0. Shannon’s expansion theorem in the general case is f = a0 x1'x2' ... xn' +
a1x1'x2' ... xn–1'xn + a2x1'x2' ... xn–1 xn' + ...+ a2n–2 x1x2... xn' + a2n–1 x1x2... xn Each ai is a constant in which
the subscript is the decimal equivalent of the multiplier of ai viewed as a binary number. Thus, for three
variables, a5 (binary 101) is the coefficient of x1x2'x3. In a similar way it can be stated as “any switching
function of n variables can be expressed as a product of sums of n literals, one for each variable “. The concept
of Shannon theorem could be applied with ease to design a basic GDI cell. In Shannon expansion theorem, any
function F can be written as: F(x1…xn) = x1H(x2….xn) + (not x1)G(x2…xn) = x1F(1,x2…xn)+(notx1)F(0,x2….xn) (1)
That is a larger function can be broken down into smaller function as shown above in equation (1). Then, the
smaller functions could be further broken down if possible till the time it is not further reducible. The output
function of a basic GDI cell (where A, B, and C are inputs to G, P, and N, respectively) is given by: Out=AC +
(notA) B (2) Therefore, comparing equations (1) and (2) it is seen that a standard GDI cell can be used to
implement any logic function based on Shannon expansion theorem as shown below taking an example. If
A=x1, C=F(1,x1….xn), B=F(0,x1…..xn) then Out=F(x1…xn)=x1F(1,x2…xn) +( not x1) F(0,x2…xn). 2.4 BASIC T FLIP
FLOP: T flip flop with clock pulse is shown in Fig. 2.1. This particular configuration is the basis for many CMOS T
flip flops, but it does suffer from a similar limitation as the SR flip flop. The characteristic table for toggle or T
flip flop is described in Table I. This is equivalent with, if T is "0", the state will not change and if T is "1" then flip
flop will change state or toggle. 14 Figure 2.1: a T flip flop based on cross-coupled NOR gates. TABLE 2.2: THE
CHARACTERISTIC TABLE FOR A TOGGLE OR 2.5 BASIC GDICELL The GDI method is based on the simple cell
shown in Fig.2.2. A basic GDI cell contains four terminals - G (the common gate input of the nMOS and pMOS
transistors), P (the outer diffusion node of the pMOS transistor), N (the outer diffusion node of the nMOS
transistor) and the D node (the common diffusion of both transistors). P, N and D may be used as either input
or output ports, depending on the circuit structure. Table 2.3 shows how various configuration changes of the
inputs P, N and G in t 15 N P G D Function '0' B A HB F1 B '1' A H + B F2 '1' B A A + B OR B '0' A AB AND C B A
HB+AC MUX '0' '1' A H NOT TABLE 2.3: SOME LOGIC FUNCTIONS THAT CAN BE IMPLENTED WITH A SINGLE GDI
CELL. 2.6 DESIGN OF LOW-POWER, HIGH-SPEED GDIT FLIP FLOP A novel implementation of a GDI TFF is shown
in Fig.2.3. It is based on the MasterSlave connection of two GDI Latches and some gates. Each latch consists of
four basic GDI cells, resulting in a simple eight-transistor structure and gates consists six transistors in order
that related with latch. The components of the latch circuit can be divided into two main categories; GDI gate
and inverter. GDI gate uses two transistors and controlled by the Clk signal. Clk signals fed to the gate of
transistors and create two alternative states: one state is when the Clk is low and the signals are propagating
through PMOS transistors and create transient state and other one is when the Clk is high and the prior values
are maintained due to conduction of the outputs. In this state, GDI gates holding state of the latch. Other gates
for main T flip flop are inverter gates. They are responsible for maintaining the complementary values of the
internal signals and the circuit outputs. Note that the size of the p-channel transistor is wider than that of the
n-channel transistor. This width difference is not needed for functionally correct operation. Rather, it somewhat
compensates for the difference in the motilities of n-channel and p-channel transistors. The effective mobility
of n-channel transistors is between two and four times that of p-channel transistors. These inverters has
important role for swing restoration and improved driving abilities of the outputs, it's buffering of the internal
signals and create suitable output current for driving of load.

Software details:

CHAPTER-6

SOFTWARE TOOL

6.1. 180 NM Process:

The 180 nm process refers to the level of CMOS process
technology that was reached in the 2002–2003 timeframe, by most leading
semiconductor companies, like Intel, AMD, Infineon, Texas Instruments,
IBM, and TSMC.
The origin of the 180 nm value is historical, as it reflects a
trend of 70% scaling every 2–3 years. The naming is formally determined by
the International Technology Roadmap for Semiconductors (ITRS).
The 180 nm wavelength was introduced by many (but not
all) companies for lithography of critical layers mainly during the 180 nm
node. Yield issues associated with this transition (due to the use of new
photo resists) were reflected in the high costs associated with this transition.
Even more significantly, the 300 mm wafer size became main stream at the
90 nm node. The previous wafer size was 200 mm diameter.
As of 2009, 45 nm technologies is largely replacing 90 nm and
65 nm technology in leading-edge chip products. However, some products,
notably chipsets, have moved from older 130 nm technology to the 90 nm
process.

6.2. Tanner Software:

 Today’s semiconductors and electronic systems are complex that
designing them would be impossible without electronic design automation
(EDA). This primer provides a comprehensive overview of the electronic
design process, and then describes how design teams use Cadence tools to
create the best possible design in the least amount of the time.

Design Specification:

This step involved stating in definite terms the performance of the chip. Like
if we are making a processor, data size, processor speed, special functions,
power etc. is clearly stated at this point. Also somewhat it is decided, the
way to implement the design. So, it deals with architectural part of the
design at highest level possible.

HDL:

Hardware Description Language is used to run the simulations. It is very

expensive to build the entire chip and then verify the performance of the
architecture. Imagine if after designing a chip for a whole year, the chip
fabricated, does not come even closer to the stated specifications. Hardware
description languages provide a way to implement a design without going
into much architecture, simulate and verify the design output and
functionality.For eg. rather than building a mux design in hardware, we can
write Verilog code and verify the output at higher level of abstraction.
Examples of HDL: VHDL, Verilog HDL

Tanner EDA Design Tools:

 S-edit - a schematic capture tool

 T-SPICE - the SPICE simulation engine integrated with S-edit

 W-edit - waveform formatting

Tanner Tools:

 Tanner EDA is a suite of tools for the design of integrated circuits.

  Tanner EDA is mainly used to analyze circuits at switch level & gate
level.

 These are tool used to ;

 enter schematics

 perform SPICE simulations

 do physical design (i.e., chip layout)

 perform design rule checks (DRC) and layout versus schematic (LVS)
checks.

S-EDIT:

 S-Edit is a powerful design capture & entry tool that can generate
netlists directly usable in T-Spice simulations.
 Provides an integrated environment for editing circuits, setting up and
running simulations and probing the results.
 It also provides the ability to perform SPICE simulations of the circuit
 These circuits that can be driven forward into a physical layout.

T-SPICE:

 It is a complete design capture and simulation solution that provides

accuracy.

 The role of T-Spice is to help design and verify a circuit’s operation.

 T-Spice simulation results allow circuit designers to verify and fine-

tune designs before submitting them for fabrication.

 Performs fast, accurate simulations for analog and mixed-signal IC

designs and fully supports foundry models for reliable and accurate
simulations.

T-SPICE vs SPICE:

 T-Spice uses an extended version of the SPICE, compatible with all

industry-standard SPICE simulation programs.
  Speed: T-Spice provides highly optimized code for evaluating device.

 It also provides the option of table-base transistor model evaluation

which yields dramatic increase simulation speed.

MEASUREMENT PROCEDURE

The test chip in fabricated in a standard six metal 130-nm CMOS process
occupying an area of 790-by- 470 μm. The chip was packaged in a surface
mount case and soldered on a printed circuit board, which provides all DC
and RF connections. The VCO is buffered by on-chip open drain amplifiers,
which are not included in the total current consumption. Power supply on
the PCB is bypassed with surface mounted tantalum and ceramic
capacitors. All phase noise values are measured with HP4352S signal source
analyzer through a divide-by-2 circuit. Phase noise improvement of 6 dB due
to frequency division is removed from the measurement results. Operating
voltage VDD is set to 2.8 V with the regulator dropping it to between 2.3 and
2.45 V at VCORE depending on oscillation frequency. Measured current
consumption across the entire coarse tuning range is between 7.3 and 10.6
mA, shows the output frequency across the entire coarse tuning range. The
tuning range is from 3015 to 5298 MHz. The measured voltage at VCORE
and the current consumption versus oscillation frequency are shown in Fig.
10. The measured phase noise results at 1- and 3-MHz offsets for the entire
tuning range or better phase noise performance at all oscillation frequencies
at 1-MHz offset. The performance is comparabl S-EDIT

Creating an Inverter Using S-Edit

To launch S-Edit in one of the LAB PCs, go to

Start > Electrical> Tanner EDA > Tanner Tools v15.2 > S-Edit v15.2 64-
bit.

Now we will create an inverter schematic and symbol. Start with creating a
new design by going to

File > New > New Design.

Specify the folder you want to create your design in and the name of your
design. Suppose you name it “ENGN1600_tutorial”. It will show up in the
Libraries navigator on the left.

On public machines, the Libraries might not immediately be loaded. To add

library to your design, download the Tanner Libraries folder here (use the
password given in class). Now, click on “Add…” button on
the Libraries window in S-EDIT, or go to File > Open > Add Library and
browse the download folder to point to Libraries\All\All.tannerfile. After
loading the library, several sub-libraries will show up in the Libraries
window, such as IO_Pads and Devices.

Once the library is loaded you will see the following libraries loaded in the
Libraries window:
 Creating the schematic

To load a schematic cell, go to Cell > New View… You will see the following
screen:

Write the name of the cell you want to create the schematic of and then click
OK. A new cell view will open up.

A CMOS inverter needs an NMOS, a PMOS, Vdd, Gnd and In/Out ports.On
the left in the Libraries window,click on the Devices library, its symbol
objects will be listed in the window 12
You might have to move your parts around to make the schematic look the
way you want it. When you click on a particular part on the schematic, the
function of the THREE-BUTTON MOUSE is shown somewhere on the toolbar
like this:

So to Move a part around the schematic, select the part with

either LEFT or RIGHT mouse button and use the MIDDLE button to
move.Alternatively, you can click on the part, hold down ALTkey and drag
the part to somewhere else on the screen. To Zoom In and Out, either use
the View menu or the mouse Scroll wheel or use the + sign to zoom in and –
sign to zoom out.

Once we have the main parts in place, it is time to add I/O ports and wire
the parts together. Select and place an Input port and an Output port on the
schematic and give the ports a unique name.
Now using the wiring tool make appropriate connections. After clicking
on the wiring tool, a SINGLE MOUSE CLICK starts the wiring. If you want to
end wiring at a particular location, DOUBLE CLICK.Your completed inverter

schematic should look like this. is the input port and is the output
port.

So we have made the connections. Now it is time to go change the length

and width of the MOS devices as per the specifications.

Inverter Symbol

To create a symbol, first create a View — create a new cell with a new
symbol view, or create a new symbol view of an existing cell using Cell >
New View. Give the symbol a View name, and select the interface it is to be
associatedwith. Then, using the polygon and drawing tools

, draw the usual symbol for an inverter. Add the

input and output ports. Make sure to give the ports the same name that you
used in the schematic i.e. in and out. Now using lines (not wires) connect
the ports to the inverter symbol. You should have something that looks like:
The creation of the symbol might be helpful when you do hierarchical
design.

CREATING SPICE NETLIST FROM THE SCHEMATIC

Go to File > Export> Export Spice.

Specify the Ouput filename. Check Exclude .endinOptions (Without

the .end, the generated SPICE file can be included in other SPICE files.)
Say Export.

The SPICE file is saved in the same directory as the schematic. The file
contains the following information:

MNMOS_1 Out In GndGnd NMOS_VTG W=150n L=50n AS=135f PS=2.1u

AD=135f PD=2.1u MPMOS_1 Out In VddVdd PMOS_VTG W=300n L=50n
AS=270f PS=2.4u AD=270f PD=2.4u

This generated SPICE file is NOT complete. This is just a description of the
circuit structure that you drew in the schematic. In order to simulate the
inverter, we still need to add some MOS models, simulation type (DC,
transient, AC, Monte Carlo etc.) and give an Input Stimulus.

The T-Spice Pro Circuit Simulation System

The design cycle for the development of electronic circuits includes an

important pre-fabrication verification phase. Because of the expense and
time pressures associated with the fabrication step, accurate verification is
crucial to efficient design. The role of T-Spice is to help design and verify a
circuit’s operation by numerically solving the differential equations
describing the circuit. T-Spice simulation results allow circuit designers to
verify and fine-tune designs before submitting them for fabrication.

T-Spice Pro is a complete circuit design and analysis system that includes:

 Dx Designer schematic editor. DxDesigner is a powerful design

capture and analysis package that can generate net lists directly
usable in T-Spice simulations.

 T-Spice circuit simulator. T-Spice performs fast and accurate

simulation of analog and mixed analog/digital circuits. The simulator
includes the latest and best device models available, as well as
coupled line models and support for user-defined device models via
tables or C functions.

 W-Edit waveform viewer. W-Edit displays T-Spice simulation output

waveforms as they are being generated during simulation. T-Spice
uses an extended version of the SPICE input language that is
compatible with all industry standard SPICE simulation programs. All
of SPICE’s device models are incorporated, as well as resistors,
capacitors, inductors, mutual inductors, single and coupled
transmission lines, current sources, voltage sources, controlled
sources, and a full complement of the latest advanced semiconductor
device models from Berkeley and Philips Labs.

T-Spice also incorporates numerous innovations and improvements not

found in other SPICE and SPICE-compatible simulators:

 Speed. T-Spice provides highly optimized code for evaluating device

models, formulating the systems of linear equations, and solving those
systems. In addition to the standard direct model evaluation, T-Spice
also provides the option of table-base transistor model evaluation, in
which the results of device model evaluations are stored in tables and
reused. Because evaluation of device models can be computationally
expensive, this technique can yield dramatic simulation speed
increases.
  Convergence. T-Spice uses advanced mathematical methods to
achieve superior numerical stability. Large circuits and feedback
circuits, impossible to analyze with other SPICE products, can be
simulated in T-Spice.

 Accuracy. T-Spice uses very accurate numerical methods and charge

conservation to achieve superior simulation accuracy.

 Macro modeling. T-Spice simulates circuits containing “black box”

macrodevices. A macro device can directly use experimental data as
its device model. Macrodevices can also represent complex devices,
such as logic gates, for which only the overall transfer characteristics,
are of interest.

 Input language extensions. The T-Spice input language is an

enriched version of the standard SPICE language. It contains many
enhancements, including parameters, algebraic expressions, and a
powerful bit and bus input wave specification syntax.

 External model interface. You can develop custom device models

using C or C++.

 Runtime waveform viewing. The W-Edit waveform viewer displays

graphical results during simulation. T-Spice analysis results for
voltages, currents, charges, and power can be written to single or
multiple files.

Simulation and Analysis Examples

This collection of examples provides a hands-on introduction to the

integrated components of the T-Spice Pro circuit analysis suite. The most
common types of analysis and simulation features are demonstrated,
including DC operating point computations, DC transfer sweeps, transient
analysis, AC and noise analysis, and direct versus table-based model
evaluation.

SPICE Simulation Setup in S-Edit

Prior to running the T-Spice simulation, the analysis commands and all
processing options need to be established. This is accomplished using the
Setup SPICE Simulation dialog in DxDesigner.
 Ensure that you are viewing the top level schematic. For this example,
the top level cell is named inverter_TestBenchOperatingPoint.
Right-click on inverter_TestBenchin the Libraries window and use
 Open View to select the schematic OperatingPoint.
 Use Setup > SPICE Simulation to launch the Setup SPICE
Simulation dialog. The proper simulation settings for the
Inverter_TestBenchexample have already been entered for you. Note
that the DC Operating Point Analysis box is checked. Also note the
settings in the General options for File Search Path and Include
Files.

Export the Netlist to T-Spice

 In the inverter_Testbench Operating Point schematic, use Tools >

Design Checks to execute the Design Checker.
 The Design Checker will display any violation or errors in the
Command window. There should not be any errors in the file
inverter_Testbench Operating Point.
  Press the T-Spice icon ( ) to export a T-Spice netlist file named
inverterOP.sp.
 DxDesigner will launch T-Spice with the inverterOP.sp netlist open.

DC Operating Point Analysis

DC operating point analysis finds a circuit’s steady-state condition, obtained
(in principle) after the input voltages have been applied for an infinite
amount of time.
Schematic

Each of the components visible in the schematic has properties associated

with it. Properties are textual elements, created in DxDesigner, that are
attached to an object and provide key information about its design and
simulation commands in T-Spice.
If you "push in" to open a specific instance, you can see that the physical
dimensions of the component N1 in the inverter are defined by the
properties:
M=1
W = 2.5u
L = 0.25u
N1 is an instance of the symbol NMOS, which represents an n-channel
MOSFET transistor. Properties that describe the operation of a generic n-
channel MOSFET are defined at the symbol level. Properties specific to
component N1, such as length and width, are defined when N1 is created.
Property values defined at the component level take precedence over default
(symbol) values.

T-Spice Input
********* Simulation Settings - General section *********
.option search="C:\src\TannerToolsShippingFiles\Libraries\Models"
.lib "Generic_025.lib" TT
*-------- Devices: SPICE.ORDER < 0 --------
* Design: AnalysisExamples / Cell: Inverter_TestBench / View:
OperatingPoint
/ Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Operating point analysis testbench of an inverter
* Date: 06/15/2007 2:56:17 PM
* Revision: 0
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 06/15/2007 2:56:17 PM
* Revision: 0
*-------- Devices: SPICE.ORDER == 0 --------
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u
AD=3.125p PD=7.5u
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
.param Vpwr = 3.3v
*-------- Devices: SPICE.ORDER == 0 --------
VVin N_2 Gnd DC 1
XX1 N_2 N_1 Gnd Vdd INV
VVpower Vdd Gnd DC Vpwr
CC1 N_1 Gnd 1p
********* Simulation Settings - Analysis section *********
.op
********* Simulation Settings - Additional SPICE commands *********
.end
Two transistors, MP1 and MN1, are defined in inverterOP.sp. These are
MOSFETs, as indicated by the key letter M that begins their names.
Following each transistor name are the names of its terminals in the
required order: drain–gate–source–bulk. Then the model name (PMOS or
NMOS in this example) and physical characteristics, such as length and
width, are specified. A capacitor CC1 (signified by the key letter C) connects
nodes N 1 and GND with a capacitance of 1p.
Two DC voltage sources are defined: VVin, which sets node N2 to 1.0 volt
relative to ground and VVpower, which sets node Vdd to 3.3 volts as defined
by the variable Vpwr.

 Notice that the simulation settings which were entered in the SPICE
Simulation Setup dialog resulted in .option, .lib, and .op commands
being written to the T-Spice input file. The .lib command causes T-
Spice to read the contents of the Generic_025.lib library file for the
evaluation of transistors MP1 and MN1, and the search option
identifies the path to the library files. In this case, the library file
contains two device .model commands, describing MOSFET models
PMOS and NMOS, as shown below for PMOS:

Run the Simulation In T-Spice

 With inverterOP.sp open in T-Spice, use File > Save to save the file.
 Click the Run Simulation button in the T-Spice simulation toolbar.
 In the Run Simulation dialog, click Start Simulation.
 T-Spice will open a new window displaying the simulation log.

Output
 The output file lists the DC operating point information for the circuit.
You can read this file in T-Spice or any text editor.

Open the Output File

 If if not already displayed, select View > Simulation Manager from
the T-Spice menu to open the

Simulation Manager:
Select the InverterOP.out display line in the window, then click the Show
Output button to open the output file InverterOP.out in a new T-Spice
window.
If you prefer to view the output in a text editor, simply open InverterOP.out
as a text file. The output file contains the following DC operating point
information (in addition to comments of various kinds, not shown here.
DC ANALYSIS - temperature=25.0
v(N_1) = 3.0633e+000
v(N_2) = 1.0000e+000
v(Vdd) = 3.3000e+000
i1(VVin) = 0.0000e+000
i2(VVin) = 0.0000e+000
i1(VVpower) = -3.1508e-004
i2(VVpower) = 3.1508e-004
Transient Analysis—Inverter
Transient analysis provides information on how circuit elements vary
with time. The basic T-Spice command for transient analysis has three
modes. In the op mode (default), the DC operating point is computed, and T-
Spice uses this as the starting point for the transient simulation. Example 3
illustrates this option.
Schematic

T-Spice Input
********* Simulation Settings - General section *********
.option search="...\Tanner EDA\Tanner Tools v12.6\Libraries\Models"
.probe
.option probev
.option probei
.lib "Generic_025.lib" TT
*-------- Devices: SPICE.ORDER < 0 --------

* Design: AnalysisExamples / Cell: Inverter_TestBench / View:

TransientAnalysis / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Transient analysis testbench of an inverter
* Date: 12/18/2005 7:28:14 PM
* Revision: 5
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 12/18/2005 7:28:14 PM
* Revision: 5
*-------- Devices: SPICE.ORDER == 0 --------
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u
AD=3.125p PD=7.5u
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
.param Vpwr = 3.3v
*-------- Devices: SPICE.ORDER == 0 --------
VVin In GndPULSE(0 Vpwr 0 1n 1n 49n 100n)
XX1 In Out Gnd Vdd INV
VVpower Vdd Gnd DC Vpwr
CC1 Out Gnd 1p
*-------- Devices: SPICE.ORDER > 0 --------
.PRINT TRAN V(Out)
.PRINT TRAN V(In)
.MEASURE TRAN RiseDelay_MeasureDelay_1 TRIG v(In) VAL='(Vpwr-
0)*50/100+0'
TD='0' RISE=1 TARG v(Out) VAL='(Vpwr-0)*50/100+0' TD='0' FALL=1 OFF
.MEASURE TRAN FallDelay_MeasureDelay_1 TRIG v(In) VAL='(Vpwr-
0)*50/100+0'
TD='0' FALL=1 TARG v(Out) VAL='(Vpwr-0)*50/100+0' TD='0' RISE=1 OFF
.MEASURE TRAN AvgDelay
PARAM='(RiseDelay_MeasureDelay_1+FallDelay_MeasureDelay_1)/2.0' ON
.MEASURE TRAN FallTime TRIG v(Out) VAL='(Vpwr-0)*90/100+0' TD=0
Fall=1 TARG
v(Out) VAL='(Vpwr-0)*10/100+0' TD=0 FALL=1 ON
.MEASURE TRAN RiseTime TRIG v(Out) VAL='(Vpwr-0)*10/100+0' TD=0
RISE=1 TARG
v(Out) VAL='(Vpwr-0)*90/100+0' TD=0 RISE=1 ON

********* Simulation Settings - Analysis section *********

.tran 250p 300n
********* Simulation Settings - Additional SPICE commands *********
.end
 This circuit is similar to that of Inverter, except that voltage source
VVinhere generates a pulse (indicated by the keyword pulse) to In, rather
than setting a constant value. The times and voltages that define the “legs”
of the waveform are specified in the arguments to pulse. The initial current
is zero amperes and the peak current is Vpwr, with an initial delay of zero
seconds. The rise and fall times are one nanosecond, with a pulse width of
49 nanoseconds and a pulse period of 100 nanoseconds. The .trancommand
specifies the characteristices of the transient analysis to be performed; in
this example the maximum time step allowed is 250 pico with a total
duration of 300 nanoseconds.
Output:

6.2 Summary:

In this chapter we study about the software tool i.e Tanner tool v13.0 and
various Design Tools in Tanner EDA likeS-edit,a schematic capture tool, T-
SPICE,the SPICE simulation engine integrated with S-edit and W-edit,
waveform formatting.
 CHAPTER 7
SIMULATION AND RESULTS
7.1 Simulation and results

SIMULATION
RESULTS

CHAPTER-8
CONCLUSION

Sub threshold leakage power consumption is a great challenge in Nano-meter scale (CMOS)
technology, although previous techniques are effective in some ways, no perfect solution for
reducing leakage power consumption is yet known. Therefore, based upon technology &
design criteria the designers can choose the techniques. In this paper, we provide novel circuit
structure in terms of static & dynamic powers named as “sleep method” it’s a new remedy for
designers. This technique shows the least speed power product among all techniques. The
Proposed technique achieving ultra-low leakage power consumption with much less speed,
especially it shows nearly 20-40% of power than the existing. So, it can be used for future
IC'S for area & power Efficiency
50