Professional Documents
Culture Documents
7 July 2008 1
Agenda
7 July 2008
14 March 2
System Verification Challenges
Test I/F
ARM Boot ROM Controller
ARM Core
Boot Config
High Speed
Pheripheral
PLL
External Bus
Interface
TIMER
ARM Interconnect
I2C
GPIO
Low Speed
Pheri pheral
7 July 2008
14 March 4
ARM SoC DV Methodology
Formal Verification
FPGA Prototyping
7 July 2008
14 March 5
Formal Verification
7 July 2008
14 March 6
Formal Verification
ARM Core
ARM Interconnect(PL301)
IP IP
7 July 2008
14 March 7
Formal Verification
Model
ARM Interconnect(PL301)
Score
Checking
engine Board
IP
7 July 2008
14 March 8
Formal Verification
7 July 2008
14 March 9
Formal Verification
Property Check
• Develop a formal specification of the AXI protocol.
Various kinds of components
>1 Masters
Slave(s)
Example:-
property (@(posedge ACLK) disable iff (!ARESETn)
(ARVALID) |=>##n ( RVALID);
End property;
7 July 2008
14 March 10
Formal Verification
7 July 2008
14 March 11
Formal Verification
Limitations of Formal
Size limit
7 July 2008
14 March 12
Hardware Software Co Verification
7 July 2008
14 March 13
Hardware Software Co-Verification Flow
SW Tools
(Compiler, Linker,
Debugger) HDL Simulation
Tools
Executable Object
file DUT
Memory Model
7 July 2008
14 March 14
FPGA Prototyping
7 July 2008
14 March 15
FPGA Prototyping
Inter-Processor
Communication
(socket) Logic Simulation
BFM
Microprocessor
With Hardware
evaluation board
Design
Bus Transaction
read/write
7 July 2008
14 March 16
FPGA Prototyping Limitations
•Only synthesizable modules can be mapped into an FPGA and run for
debugging.
7 July 2008
14 March 17
ARM SoC Test Bench Construction
Emulation Pins
TB
ARM
ARM
ARM TB
Core
Core configuration
Core other Pins
Active
ActiveBFM
ActiveBFM
BFM
Resets
DUT
Active
ActiveBFM
BFM
clocks Passive BFM
7 July 2008
14 March 18
Active component
An active component can be synthesizable or behavioral,
typically modeling functionalities required for supporting
the DUT. Active component can interact with DUT and
influences behavior of DUT.
Passive component
Passive components are observers in Test bench which
does not influence DUT behavior. Passive component are
usually behavioral model, extracting information and
validating the correctness of design behavior.
7 July 2008
14 March 19
Conclusion
7 July 2008
14 March 20
Q&A
Q&A
7 July 2008
14 March 21