A new ruler on the storage market :
3D-NAND flash for high-density memory
And its technology evolutions and challenges on the future
Invited Paper
Jaeduk Lee, Jaehoon Jang, Junhee Lim, Yu Gyun Shin, Kyupil Lee, and Eunseung Jung
Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea, email: jaeduklee@samsung.com
Abstract— Scaling limitations in planar-NAND cell are
discussed, including the depletion of floating gate and
anomalous programming behavior. It is inevitable to have a
paradigm shift to 3D-NAND due to numerous scaling
limitations of planar NAND. However, the process
complexity also increases in 3D-NAND as the mold height
goes up in an exponential trend. Thus, scaling down of mold
pitch is required, which degrades the cell characteristics. COP
(Cell over Peripheral) 3D-NAND architecture has been
developed as an area-scaling technology. CSL (Common-
Source Line) junction leakage and p+ junction leakage at
peripheral transistors have been improved by increasing the
grain size and the thickness of barrier metal, respectively.
I. INTRODUCTION
The main origin of scaling limitations of planar-NAND
ascribe to the limited scaling of the thickness of tunnel oxide
and IPD. The thickness of tunnel oxide and IPD has
maintained their minimum thickness to guarantee the retention
of the stored charges. Figure 1 shows scaling limitations of
planar-NAND cell. The numbers in Fig. 1 indicate the order of
significance to overcome the scaling issues. More detailed
discussions on the floating gate depletion and instability of
programming at the active corner are discussed in this paper.
3D-NAND is rapidly replacing the storage market from
planar-NAND because the planar-NAND has reached to the
physical limitations, such as cell-to-cell interference [1],
patterning, the physical dimension of the IPD, and the channel
coupling [2]. 3D-NAND is able to release these limitations by
stacking up in vertical direction. However, 3D-NAND also
has different technical barriers mostly from the increase of the
mold height, although a part of them are similar issues as the
planar-NAND. In this paper, advantages of 3D-NAND
comparing with planar-NAND are discussed and technical
barriers to extend the 3D-NAND are further discussed. To
minimize the increase of mold height in 3D-NAND, COP
architecture has been developed and technical issues that have
been resolved are shown.
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11.2.1
II. SCALING LIMITATIONS OF PLANAR NAND
Figure 2 shows abnormal programming phenomenon in p-
type FG(floating gate) cell. The programming is retarded at
the start of programming, however there is abrupt
programming after a critical threshold voltage [3]. Figure 3
shows the physical model of the abnormal programming.
Insufficient dopant at the floating gate induces significant
deep depletion in the floating gate. After some specific time,
enough inversion charges are generated at the top of the
floating gate, then the deep depletion diminishes, which leads
to abrupt programming. Dependency of operating temperature,
doping concentration in Fig. 2 shows the generation
mechanism of inversion charges is BTBT (band-to-band
tunneling). The weak dependency on the temperature and the
different bending point of Vth for higher and lower doping
cell show the thermal generation and the electron injection
through tunnel oxide are not dominant mechanism to recover
the inversion layer.
Figure 4(a) shows anomalous ISPP (Incremental-Step
Pulse Programming) phenomenon of a planar NAND cell. The
measured cell has a configuration of type-A as in Fig. 4(b) and
the simulated current profile in Fig. 4(c) shows current
crowding at the active corner. To explain this phenomenon,
we suggested a Monte Carlo model as in Fig. 4(d). The key of
the model is the distribution of BFN parameter separated by
normal cells and anomalous cells. Figure 4(e) shows the
simulation exactly regenerates the experimental results. The
tail bits in ISPP of Fig. 4(a) are formed by anomalous
programming, which are caused by the localized charge
trapping at the extremely-narrow FN current path, thereby
disturbs FN current path unstably as is manifest by Fig. 4(f).
III. TECHNOLOGY BARRIERS TO EXTEND THE 3D-
NAND FOR FUTURE STORAGE DEVICE
Figure 5 shows the scaling trend of planar-NAND
saturates at mid-10nm. However, rapid increase of the number
of tiers in 3D-NAND is evident. Each new generation of 3D-
NAND shown in Fig. 6 evolves by stacking up more layers in
vertical direction [4]. Due to its one-dimensional nature for
extending to the next generation, the height of the mold
increases in an exponential manner as shown in Fig. 7. To
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 suppress the exponential growth of the mold height, it is is eliminated by doping the GSL transistor with an offset
required to scaling down the height of unit mold. However, it implantation at the bottom corner of GSL transistor.
faces similar issues when area scaling is done in planar-
Figure 13(c) shows degraded CSL junction characteristics
NAND flash cells. The sheet resistance of WLs and the cell-
of COP structure by the effect of grain boundary traps. The
to-cell interference between the cells increase abruptly as
trap sites provide SRH trapping center at the junction, thus the
shown in Fig. 8. The increase of sheet resistance of WLs
generation current increases with the traps. The junction
severely degrades the performance of NAND chip and the
leakage has been improved by increasing the grain size of the
increase of cell-to-cell interference reduces reliability
poly-Si sub-plate that results in the reduction of traps.
robustness due to narrower valley to valley space in VT.
Another big change in the COP architecture is the
The cell-to-cell interference between BLs is superior in
sequence of metallization. In the reference 3D-NAND, cell
3D-NAND comparing with planar-NAND due to the
stack formation is followed by the metallization, however in
surrounding-gate structure as shown in Fig. 9, however the
the COP process sub-layer interconnection is done before the
behaviors are different as in Fig. 10. Charges in the floating
formation of cell stack and final interconnection is followed.
gate cell are distributed on the surface of the floating gate,
Hence, the sub-layer interconnection in the COP suffers from
while charges can be spread between the WL space as shown
a significant amount of heat budget during the formation of
in Fig. 10(c) as well as confined just beside the WLs as in Fig.
cell. It results in the degradation of junction breakdown
10(b). Thus, the cell-to-cell interference between WLs
voltage of peripheral transistors. It has been improved by
degrades abruptly in 3D-NAND as a function of WL pitch
adjustment of barrier metal thickness as in Fig. 12(d).
because charges can be spread on the space between WLs
depending on the geometry and programming bias conditions. The cell characteristics of COP 3D-NAND with the cells
built on the poly-Si sub-plate show the same distribution as
Mechanical failures are initiated as the mold height
the reference 3D-NAND as shown in Fig. 12(e) after the
increases, such as excessive wafer warpage, mechanical
improvement of grain size.
fracture, or crack generation. The warpage level is higher for
the chips with higher area ratio of cell, because the mold itself
contains high-stress refractory metal. Loss in productivity due
to the low throughput for thicker mold should be overcome by V. CONCLUSIONS
the development of new equipment. The paradigm shift from planar NAND to 3D-NAND is
inevitable because the planar NAND has faced several
The P/E cycling characteristics of CTF-based 3D-NAND physical limitations that hardly be overcome, however the 3D-
cell is superior to FG-based planar NAND cell as in Fig. 11(a). NAND itself also has numerous issues for the extension of the
The better cycling characteristic of CTF-based NAND NAND generations. The main obstacle is attributed to the
originates from the incorporation of holes for the erase exponential growth of the number of cell stack layers unless
operation. The holes compensate for the electron trapping in area scaling of 3D-NAND would be applied, thus scaling of
the gate dielectrics, hence charge trapping can be minimized unit mold is being adopted and COP architecture has been
as shown in Fig. 11(b). developed.
The cell current decreases as the mold height increases,
which degrades sensing speed and noise immunity.
Furthermore, the current decreases at cold temperature as REFERENCES
shown in Fig. 12, opposite comparing with the planar-NAND [1] Jae-Duk Lee, Sung-Hoi Hur, and Jung-Dal Choi, “Effects of floating-gate
cell, because the channel material is poly-Si in the 3D-NAND. interference on NAND flash memory cell operation”, IEEE Electron
The poly-Si has a grain boundary barrier as in Fig. 12(b) that Device Letters, Vol. 23, no. 5, pp. 264 – 266, 2002.
lowers the mobility and it becomes much severe at low [2] Youngwoo Park, Jaeduk Lee, Seong Soon Cho, Gyoyoung Jin, and
EunSeung Jung, “Scaling and reliability of NAND flash devices”, IEEE
temperature due to lower thermal velocity of electrons [5]. International Reliability Physics Symposium, 2014, pp. 2E.1.1 - 2E.1.4.
[3] Alessio Spessot, Christian Monzio Compagnoni, Fabrizio Farina,
Alessandro Calderoni, Alessandro S. Spinelli, and Paolo Fantini,
"Effect of Floating-Gate Polysilicon Depletion on the Erase Efficiency
IV. COP 3D-NAND ARCHITECTURE of nand Flash Memories," IEEE Electron Device Lett., vol. 31, no. 7,
COP-based VNAND architecture has been introduced [6] pp. 647-649, Jul. 2010.
with the unique feature of 3D-NAND adopting poly-Si as the [4] Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, “Vertical
cell array using TCAT(Terabit Cell Array Transistor) technology for
channel material and the upper space above the peripheral ultra-high density NAND flash memory”, Symposium on VLSI
circuits is empty. Figure 12(a) shows a typical COP 3D- Technology, 2009, pp. 192 – 193.
NAND architecture. The cell array should be fabricated on the [5] S. D. S. Malhi, H. Shichijo, S. K. Banerjee, R. Sundaresan, M., Elahy, G.
poly-Si sub-plate, thus GSL (Ground Select Line) transistor P. Pollack, W. F. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P.
K. Chatterjee, and H. W. Lam, “Characteristics and three-dimensional
and the CSL junction have degraded characteristics due to the integration of MOSFET’s in small-grain LPCVD polycrystalline
grain boundary traps. silicon,” IEEE Trans. Electron Devices, vol. ED-32, p.258, 1985.
[6] Krishna Parat, Chuck Dennison, “A floating gate based 3D NAND
Double peak in GSL transistor of Fig.13(b) is attributed to technology with CMOS under array”, IEEE International Electron
the dopant segregation at the grain boundaries. The sub-peak Devices Meeting (IEDM), 2015, pp. 48-51.

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11.2.2
 (1) Cell-to-cell interference
(6) FG depletion CG 7
(7) WL resistance 1 6
(8) Hot-carrier disturbance (GIDL/DIBL) 3
(9) Active corner instability FG 4
10
9
(5) Channel boosting potential 5 2
(10) Reliability window, Number of Electrons 8

Increasing Process Complexity

(2) Patterning (Gate etch, Active Photo)
(3) IPD thickness limitation
(4) CG filling
* In the order of significance Substrate
Design Rule
Fig. 1. Scaling limitations in planar-NAND flash cell.

* Boron Doping Concentration: A << B

Boron Doping: A Boron Doping: B
8 8
6
Abrupt 6
programming
4 4
Vth [V]

Vth [V]
Vth [V]

2
Vth [V]

2
0 0
-2 25C -2 25C
55C 55C
Slower 85C 85C
-4 -4
programming 115C 115C
-6 -6
No. of ISPP pulses [A.U.] No. of ISPP pulses [A.U.]

Fig. 2. Deep-depletion phenomenon in p-FG cell. Fig. 3. Deep-depletion modeling.

Fig. 4. Monte Carlo simulation modeling of anomalous programming at the active corner.

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11.2.3
 200 100
180 90
160 80

Tiers of 3D-NAND
Planar D/R [nm]

Mold Height [A.U.]

140 70
120 60
100 50
80 40
60 30
40 20
20 10
0 0
01 03 05 07 09 11 13 15
Year
3D-NAND technology nodes
Fig. 5. Technology trends of planar-NAND Fig. 6. Schematic diagram of 3D-NAND Fig. 7. Mold height increase trend in 3D-
and 3D-NAND structure. NAND technology nodes.

Trap
layer
Cell-to-cell interference [A.U.]

tPROG [A.U.] X1/2

WL

Trapped
charges
WL
WL Rs [A.U.]

FG

Planar NAND 3D-NAND (a) (b) (c)

Mold Pitch Mold Pitch

Fig. 8. Mold scaling issues in 3D-NAND. Fig. 9. Comparison of programming time Fig. 10. Dependency of cell-to-cell interference on the
(tPROG) between planar vs. 3D-NAND. location of stored charges. (a) Floating gate, (b) 3D-
NAND localized charges, (c) 3D-NAND spread charges.
Vth shift by P/E cycling [A.U.]

100%
Cell current [A.U.]
Log(Id) [A.U.]

D (grain diameter)
FG FG 80C Vb e-
(Dotted line) Barrier
33% height boundary
-20C boundary
3D-NAND
3D-NAND (Dashed line)

Vg Mold Height
(a) P/E Cycling (b) Id/Vg Curves (a) Cell current (b) A conduction model of Poly-Si
Fig. 11. (a) Comparison of P/E cycling characteristics, (b) Id- Fig. 12. (a) Cell current as a function of mold height. (b)
Vg curves before (solid), after (dash) cycling. Conduction mechanism of electrons in poly-Si channel.

1E+07 1E+07
CSL Junction Leakage [A.U.]

1E+06 Reference doping

1E+06
(Dashed)
P+ Junction BV [A.U.]

1E+05 1E+05
Thicker
# of GSL [ea]

# of Cells

1E+04 Barrier metal 1E+04

1E+03 1E+03
1E+02 1E+02
Larger grain size Reference 3D-NAND
1E+01 Offset doping 1E+01 COP 3D-NAND
(Solid)
1E+00 1E+00
GSL Vth [A.U.] CSL Voltage [A.U.] Cell Vth [A.U.]
(a) COP structure (b) GSL Vth (c) CSL Junction Leakage (d) Peri transistor junction (e) COP TLC-distribution
Fig. 13. COP 3D-NAND architecture. (a) Schematic diagram of COP structure, (b) GSL Vth distribution, (c) improvement of CSL junction
leakage, (d) improvement of p+ junction breakdown voltage, (e) fabricated COP-cell Vth distribution.

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