EE141

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  Phase 2 announced. Launched in the next 24

hours.
  Hw 6 due on Fr.

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  Last lecture
  Ratioed Logic
  Dynamic Logic
  Today’s lecture
  Domino Logic
  Registers
  Reading (Ch 6, Ch 7)

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Goals: - Design bit-node so that clock frequency is minimized

- Layout bit and check nodes
Due Date: Wednesday April 13

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off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

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  Noise sensitivity and small noise margins

  Leakage
  Charge sharing
  Clock feedthrough

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Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.

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Clock feedthrough
Clk
Out
In1
In2
Voltage

In3 In &
Clk
In4 Out
Clk
Time, ns
Clock feedthrough

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Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

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Out1
Voltage

Clk

In Out2

Time, ns

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  Capacitive coupling
  Substrate coupling
  Minority charge injection
  Supply noise (ground bounce)

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Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

ΔV
Out2

Only 0 → 1 transitions allowed at inputs!

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Clk Mp Clk Mp Mkp

1→1 Out1 Out2
1→0
0→0
In1 0→1
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

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  Only non-inverting logic can be implemented

  Very high speed
  static inverter can be skewed, only L-H transition
critical
  Input capacitance reduced – smaller logical effort

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Designing with Domino Logic

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Output = f(In) Output = f(In, Previous In)

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Two key (related) reasons that we need

sequencing:
(1) Want to know when an input has a “new”
value

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Two key (related) reasons that we need

sequencing:
(2) Need to slow down signals that are too fast
  In order to keep them aligned with slower ones

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  Latch: level-sensitive   Register: edge-triggered

clock is low - hold mode stores data when
clock is high - transparent clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

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tD → Q

D Q D Q

Clk Clk

tC → Q tC → Q

Register Latch

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CLK
t Register
tsu thold D Q

D DATA CLK
STABLE t
tc → q

Q DATA
STABLE t

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Static Dynamic

CLK

D Q

CLK

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Gain should be larger than 1 in the transition region

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Use the clock as a decoupling signal,

that distinguishes between the transparent and opaque states

CLK

D D

CLK

Forcing the state

Converting into a MUX
(can implement as NMOS-only)

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CLK

D D

CLK

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Negative latch Positive latch

(transparent when CLK= 0) (transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK
CLK

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NMOS only Non-overlapping clocks

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  N latch is transparent   P latch is transparent

when Φ = 0 when Φ = 1

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Two opposite latches trigger on edge

Also called master-slave latch pair

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Multiplexer-based latch pair

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2.5
CLK

1.5 tclk-q(LH)
D tclk-q(HL)

Volts Q
0.5

2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)

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