Microelectronics Reliability 54 (2014) 2410–2416

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Microelectronics Reliability
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Electrical Overstress of Integrated Circuits

K.T. Kaschani a,⇑, R. Gärtner b,1
a
Texas Instruments, Haggertystr. 1, 85356 Freising, Germany
b
Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany

a r t i c l e i n f o a b s t r a c t

Article history: Common misconceptions regarding electrical overstress (EOS) and the failure characteristics of
Received 11 March 2013 integrated circuits (ICs) are summarized, analyzed and clarified. In order to avoid EOS fails right from
Received in revised form 7 April 2014 the beginning of the IC design process, a methodology is proposed that accounts for the special
Accepted 9 April 2014
characteristics of ICs and their applications in order to deal with EOS in the design, handling and
Available online 10 May 2014
application of ICs.
Ó 2014 Elsevier Ltd. All rights reserved.
Keywords:
Electrical overstress
EOS
Robustness
Integrated circuit
Linearity

1. Introduction electrical stress requirements though needed are often neglected

There is a trend driven by system manufacturers to integrate
more and more ‘‘EOS protection’’ on-chip due to cost, overall form
factor and performance reasons [1]. Unfortunately, many users of
ICs often do not distinguish between the different causes of EOS
[2,3]. E.g. users expect the integrated component-level ESD (CL-
ESD) protection of ICs not only to withstand any CL-ESD event
but also to protect ICs from system-level ESD (SL-ESD) and other
kinds of electrical stress. This lack of distinction has unintention-
ally been encouraged over many years by IC manufacturers, who
classified field returns, which were caused by specific types of
EOS, simply as ‘‘EOS/ESD’’ [3]. Moreover, despite the remarkable
advances in ESD control, many users of ICs still cling to meanwhile
out-dated ESD requirements, e.g. 2 kV human-body-model (HBM)
[4], or misinterpreted models, e.g. the so-called ‘‘machine-model’’
(MM) [5]. At the same time, IC manufacturers are required to sup-
ply ‘‘EOS robust’’ ICs to their customers without knowing the final
application and its electrical stress requirements [1].
These inconsistencies cause several replacement processes and
result typically in a trial-and-error development process to design
‘‘EOS robust’’ ICs (cf. Fig. 1). Unfortunately, only a few electrical
stress requirements (e.g. CL-ESD and latch-up (LU) requirements)
are generally specified by system manufacturers (1). Other
⇑ Corresponding author. Tel.: +49 8161 80 4348; fax: +49 8161 80 3322.
E-mail addresses: kt-kaschani@ti.com (K.T. Kaschani), reinhold.gaertner
@infineon.com (R. Gärtner).
1
Tel.: +49 89 234 23754; fax: +49 89 234 9552117.
and are therefore shaded in grey in Fig. 1. Hence, IC manufacturers
have to get by with the knowledge that they have learned from
previous designs and analyses of competitor ICs (2) in order to
design ‘‘robust’’ ICs (3). Since on the other hand system manufac-
turers are not aware of the failure characteristics of ICs and of
the electrical stress they are exposed to in their manufacturing
and application environments, system manufacturers often com-
pare compatible ICs of competitors to select the most ‘‘robust’’
one (4). Unfortunately, this trial-and-error process causes often
unpleasant surprises, e.g. when an IC with an excellent CL-ESD
immunity fails for another kind of electrical stress. In this case, sys-
tem manufacturers often request failure analysis reports and
detailed information on the failing IC from the IC manufacturer
(5). Unfortunately, they generally do not provide much informa-
tion on the conditions that caused the failure. As a result, IC man-
ufacturers typically run failure analyses in order to find the root
cause of the failure and try to fix it by a re-design of the IC (6). If
the root cause of the failure cannot be found and ICs still fail, some
system manufacturers respond to the assumed lack of ‘‘EOS robust-
ness’’ by increasing their CL-ESD and LU requirements or by asking
for robustness validation of ICs (7). Finally, they rate IC manufac-
turers based on the ‘‘EOS robustness’’ of their ICs.
The aforementioned inconsistencies and the problems they
cause are often due to common misconceptions regarding ICs
and EOS. These misconceptions and the desire for simple EOS solu-
tions are often encouraged by today’s tight time-to-market and
cost requirements [6]. Therefore, it is important to understand
and accept that physics does not respond to time-to-market and

http://dx.doi.org/10.1016/j.microrel.2014.04.007
0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
Fig. 1. Typical trial-and-error development process to design ‘‘EOS robust’’ ICs. (The chronological sequence is indicated by the digits 1–7).
cost requirements. Only by taking into account the characteristics
of ICs, their application systems and the different kinds of electrical
stress that they may experience, it is possible to protect them from
EOS.
Given these facts, it is the purpose of this paper to clarify the
failure characteristics of ICs, to present typical causes of EOS and
to propose a methodology that accounts for the special character-
istics of ICs and their applications in order to deal with EOS in the
design, handling and application of ICs.
2. Failure characteristics of ICs
The expectation of on-chip ESD protection to protect ICs not
only from CL-ESD events but also from other kinds of electrical
stress is often based on one or the other of the following
assumptions:
(a) The current path within an IC is assumed to be the same for
different kinds of electrical stress.
(b) The same part of an IC is assumed to be damaged regardless
of the kind of electrical stress.
(c) Specific parts of an IC are assumed to respond equally to dif-
ferent kinds of electrical stress.
(d) The response of an IC to electrical stress is assumed to be
independent of its mode of operation.
(e) The response of an IC to electrical stress is assumed to be
proportional to the level of the given electrical stress.
(f) It is assumed that the responses of an IC to single kinds of
electrical stress can be superimposed to give the response
of the IC to superimposed electrical stresses.
As explained in [2], all these assumptions refer to characteris-
tics of linear systems. Hence, the expectation of on-chip ESD
protection to protect ICs not only from CL-ESD events but also from
other kinds of electrical stress is typically based on the assumption
that ICs are linear systems. Unfortunately, this assumption is
generally wrong as will be explained in the following sections.
2.1. Semiconductor devices and ICs
As shown in [2], active devices (diodes, transistors and SCRs) are
non-linear devices. This is the reason, why their electro-thermal
characteristics are not analytically solved but are numerically
2411
simulated [7]. The non-linear characteristics of active devices
become especially clear, by taking saturation, breakdown, snap-
back, hysteresis and memory effects into account. Especially ESD
protection elements are typically driven deeply into breakdown,
in order to clamp the voltage while conducting large currents. As
explained in [8], their breakdown does not necessarily occur
instantaneously as soon as a certain threshold voltage is exceeded
but may be significantly delayed. The non-linearity of ESD protec-
tion devices is also confirmed by the lack of a common correlation
between their HBM robustness and their SL-ESD robustness as
reported in [1]. In fact, different ESD protection elements were
found to have significantly different correlation factors, which
makes it very difficult (if not impossible) to predict their response
to other kinds of electrical stress.
Even passive devices like resistors, capacitors and inductors are
known to show non-linear characteristics, if these devices are
operated beyond their safe operating area, which may occur for
any EOS [9,10]. Taking into account that almost all ICs employ both
active and passive devices, it has to be concluded that ICs are gen-
erally non-linear systems.
2.2. Failure mechanisms
The failures caused by EOS can generally be divided into revers-
ible (soft) and irreversible (hard) failures. A reversible failure can
be removed by a functional reset (e.g. a power restart or a logic
reset) or it can be healed by self-healing or physical treatment
(e.g. annealing). Reversible failures are caused by electrical stress
exceeding the trigger threshold of a functional failure mechanism
(a switching operation, i.e. a non-linear mechanism) or by
approaching the failure threshold (e.g. breakdown, another non-
linear mechanism) of an IC component. Hence, the failure mecha-
nisms causing reversible failures are non-linear.
Irreversible failures are permanent. They are either caused by
electrical stress exceeding the trigger threshold of a physical fail-
ure mechanism (immediate failure) or by accelerated aging
(delayed failure). The major failure mechanisms leading to irre-
versible failures caused by EOS are thermal overload due to dissi-
pated energy and dielectric breakdown due to an electric field or
voltage stress imposed for a certain amount of time [11]. As
explained in [2,12], the relation between the thermal overload
threshold of semiconductor devices and the stress time on the
one hand and the relation between the time-to-failure and the
2412 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
electrical field (or voltage) across gate oxides on the other hand is
always non-linear. Hence, also the major failure mechanisms caus-
ing irreversible failures of ICs are non-linear.
2.3. Failure signatures
According to [2,13] different kinds of EOS typically cause differ-
ent types of failure signatures. E.g. while charged-device-model
(CDM) type overstress events generally cause dielectric breakdown
due to their large peak currents, which in turn lead to high overvol-
tages within ICs, HBM-type overstress events cause melt-filaments
due to the dissipated energy. In contrast, high energy EOS events
often result in large molten areas or even blown bond wires [16]
owing to a tremendous power dissipated over a long period of
time. This shows that there is generally no correlation between
the failure signatures of different EOS events. Hence, this lack of
correlation confirms again that ICs are non-linear systems.
Note, since the major failure mechanisms in ICs depend on the
time duration that voltages and/or currents are applied [2], failure
signatures can generally not be clearly attributed to specific volt-
age and/or current waveforms. In fact, many different voltage
and/or current waveforms can lead to the same failure signature.
By means of the type and the size of the different failure signatures,
only some fundamental characteristics of voltage and current
waveforms that caused the failure can be inferred. Hence, the met-
aphor of a ‘‘fingerprint’’ that is often used to describe failure signa-
tures is misleading. Failure signatures are not that unique.
2.4. Failure location
As already indicated in the previous section, different EOS
waveforms may lead to different failure locations within ICs. As
explained in [2], the failure location can vary for different ESD
events that are imposed on the same pin of an IC because different
stress waveforms can trigger different current paths in ICs. The
more complex the on-chip circuitry is that is connected to a pin,
the more different current paths may be triggered by different
stress waveforms that are imposed on that pin. This proves that
the same part of an IC is not necessarily damaged regardless of
the kind of EOS. Furthermore, since SL-ESD is often regarded as
superposition of HBM and CDM and although a successful superpo-
sition has been reported in a couple of individual cases, the exam-
ple given in [2] also proves that the responses of an IC to single
kinds of EOS can generally not be superimposed to give the
response of the IC to superimposed EOS. Again, such a behavior
is a characteristic of a non-linear system.
2.5. Window effects
A PASS–FAIL–PASS–FAIL sequence that is obtained as the stress
imposed on an IC is increased is called window effect [2,9]. It is
characterized by failing stress levels that are framed by lower
and higher stress levels, which are passed. Window effects are
well-known and often caused by competition between protection
elements and devices to be protected. They prove that the response
of an IC to an electrical stress is not necessarily proportional to the
level of the given electrical stress. Therefore, window effects are an
indication for the non-linear nature of ICs.
2.6. Mode of operation
According to [17] the SL-ESD immunity of an audio amplifier IC
was found to vary depending on the applied supply voltage of the
IC. When unbiased, the SL-ESD immunity of the IC was found to be
7 kV. However, when the IC was biased, the SL-ESD immunity
turned out to be only 1 kV. This proves that the response of an IC
to an electrical stress is not necessarily independent of its mode
of operation, which in turn confirms the non-linearity of ICs.
2.7. Application circuit
Also application circuits can have a strong effect on the immu-
nity of ICs to electrical stress. E.g. the effects of external capacitors
connected to the pins of ICs are explained in [2,18]. Depending on
the kind of the ESD protection devices that are integrated with an
IC, external capacitors can be both beneficial or detrimental to the
electrical stress immunity of that IC. If non-snapback devices are
employed, external capacitors can mitigate the electrical stress
imposed on ESD protection devices by buffering detrimental peak
currents. However, if snapback devices are involved, external
capacitors may lead to immediate destruction of an ESD protection
device, as soon as its trigger voltage is exceeded. This shows that
the electrical stress immunity of an IC is not necessarily indepen-
dent of its application system and that ICs have to be regarded as
non-linear systems.
All of the aforementioned aspects prove the non-linear failure
characteristics of ICs. These non-linear characteristics have a
strong impact on the design of any electrical stress protection both
on component-level and on system-level. E.g. the quasi-static IV
characteristics of protection elements and the breakdown voltages
of devices to be protected are not constant, but have to be adjusted
to each type of electrical stress. As a result, on-chip CL-ESD protec-
tion cannot be expected to protect ICs from any other kind of elec-
trical stress.
3. EOS root causes
One of the reasons, why EOS of ICs is so difficult to address, is
the lack of a clear and consistent definition of EOS. Traditionally,
many IC and system manufacturers are used to classify failures as
‘‘EOS failures’’ based on the size of the physical failure signature
and hence based on the dissipated energy. While small failure
signatures (small dissipated energies) are attributed to ‘‘ESD’’,
large failure signatures (large dissipated energies) are attributed
to ‘‘EOS’’. Unfortunately, this ‘‘definition’’ is not clear as medium
dissipated energies and medium sized failure signatures are con-
cerned. Furthermore, it does not account for failures caused by
electromagnetic interference (EMI) and by misapplication. Given
the traditional failure classification, any low-energy electrical
stress that exceeds the absolute maximum ratings (AMR) of an
IC and causes it to fail is likely to be attributed to the cause
‘‘ESD’’ rather than to the cause ‘‘EOS’’. It is no surprise, that cus-
tomers of ICs request ever-increasing CL-ESD immunities, if the
root causes of IC failures are only determined based on the effects
of electrical overstress. Therefore, EOS is defined in this paper as
follows:
Fig. 2. EOS in relation to AMR for a given electrical stress type and failure
probability distribution of an IC.
 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
Definition. Electrical overstress (EOS) is any electrical stress that
exceeds any of the absolute maximum ratings (AMR) of an IC and
causes it to fail, reversibly or irreversibly, immediately or delayed.
This definition and its implications are illustrated in Fig. 2. In
this figure, the rate of immediate failures indicated by the solid
bold line is plotted over the stress level of a given electrical stress
type. The stress level range that covers the increase of the failure
rate from 0% to 100% is denoted as typical failure thresholds
(tFT) of all healthy ICs of the same type that experience the same
electrical stress. Since failure thresholds are subject to process
spread they are given by a band rather than a sharp line. Above
the tFT, all healthy ICs will immediately fail. Below the tFT, all
healthy ICs are robust against immediate failures; they may
become subject to accelerated aging and delayed failures though.
Within the tFT band, immediate failures or accelerated aging of
ICs may occur depending on the individual failure thresholds of
the given ICs and the electrical stress they experience. AMR sepa-
rate the area of safe handling and application from EOS. The uncer-
tainty introduced by unknown electrical stress and unknown
application conditions and the impact of accelerated aging on the
useful life of an IC have to be taken into account when AMR are
specified. The guard band between the AMR and the tFT accounts
for these factors. Note, in some cases noticeable accelerated aging
may already occur when the recommended operating conditions
(ROC) are exceeded for more than just an instant. Such cases are
usually indicated in the datasheets of corresponding ICs. They
require that the recommended operating conditions are in total
not exceeded for too long.
Fig. 3. Cause–effect diagram with typical causes of EOS to ICs (cf. [3]).
2413
tFT are not constant but depend on the given electrical stress
type. E.g. the power-to-failure of an integrated diode for constant
electrical stress is much lower than the power-to-failure of the
same diode for a 1 ns electrical stress pulse [2,9,10]. Therefore,
AMR cannot be constant either and have to be adjusted for the
electrical stress that an IC is supposed to withstand. Hence, in
the EOS definition given above AMR are not restricted to constant
voltages, but comprise all constant and time-dependent physical
limits that are specified by IC manufacturers in order to ensure ser-
viceability and avoid reversible and irreversible, immediate and
delayed failures of ICs. This understanding of AMR matches quite
well the AMR definition given in IEC 60134 [14]. Following the
EOS definition given above, EOS is a specification violation that
results in IC failures. In this connection, the term ‘‘EOS robust’’ is
of course a contradiction in terms, for no product can be expected
to withstand a violation of its own specification.
In order to develop effective measures to deal with EOS, it is
necessary to understand its typical root causes rather than to con-
centrate on its effects. Some of these root causes are shown in the
cause-effect diagram of Fig. 3. According to this diagram, EOS
causes can generally be divided into ESD, EMI and misapplication.
The category ESD includes both causes of charging and of uncon-
trolled discharges. The category EMI is divided into slow voltage
transients (e.g. uncontrolled power supplies), surge currents, fast
voltage transients, noise and EMI due to RF and electromagnetic
pulses (EMP). Finally, the category Misapplication is divided into
causes due to assembly, testing, (application) system design, mis-
insertion and specification violations. Note, although [15] suggests
that latch-up (LU) can cause EOS failures, LU is not included with
2414 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
the EOS cause-effect diagram, because LU is not a cause but a failure
mechanism. Quite the contrary, given the EOS definition of this
paper, EOS, i.e. electrical stress that exceeds the corresponding
AMR, may trigger a LU of an IC. Given the number of typical causes
per EOS type, Fig. 3 nicely agrees with a recent report that attri-
butes only 6% of customer complaints to ESD but 94% to other
EOS [16]. This clearly shows the need to concentrate on EOS rather
than on ESD.
4. 5-Steps EOS methodology
In order to minimize IC failures due to EOS the 5-steps EOS
methodology shown in Fig. 4 is proposed [3]. It comprises the
following steps:
(S1) EOS Minimization covers the minimization of EOS sources in
the design, handling and application wherever possible.
(S2) EOS Risk Assessment denotes the risk assessment of possible
and potentially harmful electrical stress in the design, han-
dling and application of ICs.
(S3) Electrical Stress Specification addresses the specification of
the electrical characteristics of inevitable and potentially
harmful electrical stress.
(S4) EOS Mitigation describes the mitigation of the impact of
inevitable electrical stress.
(S5) EOS Root Cause Analysis covers the failure analysis and root
cause identification of fails due to unforeseen EOS.
4.1. EOS minimization (S1)
Every EOS that does not occur, does not need to be risk assessed,
specified, mitigated and root cause analyzed. Hence, minimization
of EOS sources is the most powerful measure to avoid fails due to
EOS [3]. Minimization can be achieved by paying attention to the
causes of EOS shown in Fig. 3.
EOS related to handling can be minimized e.g. by ESD control,
hot plug control and optimized working procedures. EOS related
to applications can be minimized e.g. by hot plug control, connec-
tor design and AMR compliance. EOS related to cross-coupling can
be minimized e.g. by noise and EMI control. Standards can help to
minimize EOS sources that are related to routine tasks and proce-
dures, such as the handling of ICs, the design of connectors and the
control of noise and EMI.
4.2. EOS risk assessment (S2)
The purpose of risk assessments is to discover and anticipate
risks, to identify their root causes, to quantify their impact and to
Fig. 4. 5-steps EOS methodology.
define precautions in order to minimize unacceptable risks [3]. In
this way, risk assessments also help to avoid over- or under-engi-
neering of systems. To consider all relevant risks both intuitive and
systematic risk assessments should be carried out.
Intuitive methods (e.g. brainstormings) should be applied
first to avoid biasing other people’s mind. For the same reason,
individual intuitive methods should be applied prior to joint
intuitive methods. Afterwards, systematic methods should be
deployed.
Systematic methods can be divided into failure-driven risk
assessments and risk assessments of peculiarities. Failure-driven
risk assessments focus on possible failures. ‘‘Bottom-up’’ methods
(e.g. failure mode and effects analysis) start with possible failures
on component-level and assess their impact on system-level and
application-level. In contrast, ‘‘top-down’’ methods (e.g. fault tree
analysis) start with failures on application-level and trace back
all failures on system-level and component-level that may cause
the given failures on application-level. In order to cover as many
risks as possible, it is recommended to use at least one ‘‘bottom-
up’’ method and one ‘‘top-down’’ method [19]. Special attention
should also be paid to peculiarities because they often introduce
special risks [3]. Special requirements or features should be taken
into account (e.g. those related to functionality, reliability, time-to-
market or cost). Risks are also introduced by changes (e.g. of
human resources, materials, supplies, tools, machines, techniques
and procedures) or by special environmental conditions (e.g. espe-
cially low/high temperature, humidity, pressure, radiation, noise).
Finally, also possible and (assumed) ‘‘impossible’’ user action
(misuse) should be considered [19].
For any unacceptable risk that is identified in the course of the
EOS risk assessment, it has to be evaluated, if the given risk can be
addressed by EOS minimization (S1) or if it needs to be addressed
by EOS mitigation (S4). Given the power of EOS minimization as
explained in the previous section, it is recommended to address
as many EOS risks as possible by means of EOS minimization
(S1). Only those EOS risks that cannot be minimized should be
addressed by EOS mitigation (S4). Note, EOS risks can of course
be generally minimized by best practice design techniques (e.g.
EMC design techniques) as well as fail-safe design techniques
(e.g. provision of redundant systems) [19]. Specific EOS risks, how-
ever, need to be carefully specified and addressed in order to be
effectively mitigated [3].
4.3. Electrical stress specification (S3)
Due to the non-linear failure characteristics of ICs, different
parts of an IC may be damaged depending on the time depen-
dent waveform of an electrical stress [2]. Hence, a necessary
prerequisite for the mitigation of the impact of inevitable
electrical stress is a complete and detailed specification of its
electrical properties in terms of time-dependent current and
voltage waveforms and repetition rates [3]. Only with such a
specification, system and component designers are able to
develop effective mitigation strategies. Measurements and com-
puter simulations can help to characterize and specify inevitable
electrical stress [20].
Note, the specification of electrical stress requires a fundamen-
tal understanding of the given system: its manufacturing condi-
tions, its components, its application and its environmental
conditions [3]. Often, such a specification cannot be ruled by a
standard. Also, a comparative specification, which only refers to a
related system or component and is often made for lack of time,
is not sufficient because it bears the risk of ignoring serious threats
on the one hand and of driving unreasonable and ineffective over-
engineerings on the other hand.
 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
4.4. EOS mitigation (S4)
Typically, EOS involves both the application system and its
components. Taking into account the non-linearity of ICs and of
other components, the resulting system affected by EOS can
become very complex [3].
As already mentioned, EOS can generally be mitigated by best
practice design techniques as well as fail-safe design techniques
[19]. However, this is often not sufficient, if specific types of elec-
trical stress represent a special risk to the given system. In such
a case, it is beneficial to decouple as many components as possible
in terms of the given electrical stress from the remaining system.
This can be achieved e.g. in case of ESD by shielding and in case
of EMI by low pass filters. Such decoupling measures should be
introduced as close as possible to the given electrical stress source
in order to be most effective. If a component is effectively decou-
pled from the remaining system, an electrical stress created or
fed into the system will not reach this component. Hence, compo-
nents that are decoupled from the system can be designed inde-
pendent of system-level electrical stress. As a result, electrical
stress decoupling maximizes the freedom of system designers to
design components into their systems. The electrical stress protec-
tion of the remaining system and its components has to be co-
designed, which generally will lead to a more special and hence
less flexible design of both the component and the system. As a
result, co-designing will limit the freedom of system designers to
apply co-designed components to different systems. However,
electrical stress decoupling and co-designing do not rule out each
other. While parts of a system can be decoupled, other parts can
be co-designed.
Co-designing of IC pins implies that the interfacing IC cir-
cuitry has to be designed to partly or completely withstand a
given electrical stress. This imposes additional requirements
on the design of such circuitries, which in turn may impair
the functionality of the given IC pin. E.g. co-designing a high
speed input pin for SL-ESD would add a significant capacitive
load and/or series resistance to this pin, which in turn could
distort the input signal. A corresponding co-designing of a sup-
ply pin could increase the leakage current of this pin so much
that it may become critical for battery applications. As a result,
decoupling is the preferred mitigation strategy for IC pins that
may be functionally impaired by co-designing. These pins are
typically supply pins, high speed or RF input pins and low
impedance, high speed, RF or high voltage output pins. In addi-
tion, pins that are connected to local PCB networks in order to
support basic IC functions are naturally decoupled and usually
do not need to be co-designed. Basic IC functions are supported
e.g. by decoupling capacitors and charge-pump capacitors for
internal voltage supplies, grounded resistors, passive feedback
networks and crystals for internal oscillators. As a general rule,
pins connected to complex IC circuitries and pins, the function
of which is likely to be impaired by co-designing, should be
decoupled.
4.5. EOS root cause analysis (S5)
Even with all the aforementioned steps (S1) to (S4) meticu-
lously followed, there may be fails due to unforeseen EOS. Due
to the complexity of the entire system and the manufacturing
process, it is of utmost importance to identify the root cause
of each fail in the first step before the most effective corrective
action on manufacturing-level, system-level or component-level
can be determined in the second step [3]. Unfortunately, this
simple truth is often ignored for ‘‘lack of time’’. Instead, to fix
the unsolicited fail without loss of time often ‘‘short cuts’’ are
taken, which eventually take much more time to fix the problem
2415
than a careful root cause analysis and correction process. Need-
less to say, problems that are delayed by such ‘‘short cuts’’ do
not vanish but get bigger.
Example: During the ramp-up of a new IC an increased number
of field returns was observed by OEM 1. The failure analysis of the
IC manufacturer revealed a large carbonized area (burn mark)
above one of the power transistors that are used to drive a motor
and a smaller carbonized area above the ESD protection element
of the corresponding pin. The system manufacturer and the IC
manufacturer assumed a weakness of the wafer process to be the
root cause of the field returns. To verify this assumption, it was
decided to analyze the final test data-logs and the process-control
monitoring data of the affected lots and to run an ESD re-qualifica-
tion with increased sample size on all affected lots. The analysis of
the final test data-logs, the process-control monitoring data and
the ESD re-qualification did not give any results that could support
the assumption of a weakness of the wafer process. A possible
weakness of the PCB was a priori ruled out by the system manufac-
turer. For lack of time, it was finally decided to introduce a leakage
current screening test into the final test of the IC in order to screen
for weak devices as a containment action. At the same time, OEM 2
and OEM 3 completed the qualification of products based on sim-
ilar PCBs of the same system manufacturer. Half a year later, the
number of field returns increased strongly. After three time-con-
suming troubleshooting processes with three different OEMs, it
finally turned out that the field returns were caused by an insuffi-
cient free-wheeling diode that was used on the PCBs of the system
manufacturer as a replacement of a costly Schottky diode. This
free-wheeling diode caused repetitive inductive voltage transients
that were driving the ESD protection element connected to the
same IC pin repeatedly into breakdown until it finally failed. This
failure caused a short-circuit condition for one of the power tran-
sistors, which was damaged because it was turned-off too late by
the overtemperature detection circuit of the IC.
An effective root cause analysis requires [3]:
(1) Detailed specification of the failure conditions (When was
the damaged part last known to be fully functional? When
was it first known to fail? Which processes has it experi-
enced in between?)
(2) Localization of the damaged structure (Which system, com-
ponent and structure is damaged?)
(3) Identification of the failure signature (How is the failure
mechanically, optically and electrically characterized?)
(4) Narrowing down of possible failure mechanisms (Which
failure mechanisms can explain the given failure conditions,
location and signature? This should be done by engineers,
who are familiar with the damaged structure and its failure
mechanisms.)
(5) Identification of likely root causes that meet all of the afore-
mentioned criteria (What is the probability of the experi-
enced processes to cause the given failure? Which
processes have the highest probability to cause the given
damage? Computer simulations may help to narrow down
the likely root cause, because in contrast to measurements
they do not affect the signal integrity [21].)
Given today’s tight time-to-market requirements, trouble-
shootings have to be both efficient and effective [3]. To meet
these requirements they need to be supported by templates
that guide engineers quickly through the troubleshooting pro-
cess. Also a co-troubleshooting by system and component
designers may be needed to reach this goal. Finally, given the
likely root cause steps (S1) to (S4) of the 5-step EOS methodol-
ogy should be repeated in order to determine effective correc-
tive actions.
2416 K.T. Kaschani, R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416
5. Summary and conclusions
Common misconceptions concerning ICs and EOS that facilitate
IC failures have been summarized, analyzed and clarified. It was
pointed out that ICs have in general non-linear failure characteris-
tics, which have a strong impact on the design of any electrical
stress protection both on component-level and on system-level.
In order to develop effective measures to deal with EOS, typical
causes of EOS have been presented. Based on a recent investigation
of ESD and EOS failures the need to concentrate on EOS rather than
on ESD was explained.
In order to avoid EOS fails right from the beginning of the design
process, a 5-steps methodology was introduced to deal with EOS in
the design, handling and application of ICs. Based on the typical
causes of EOS this methodology addresses (S1) the minimization
of EOS sources, (S2) the risk assessment of possible EOS, (S3) the
specification of inevitable electrical stress, (S4) the mitigation of
EOS and (S5) the root cause analysis of EOS failures. Special atten-
tion was paid to EOS minimization strategies, EOS risk assess-
ments, the concepts of electrical stress decoupling and co-
designing, typical mitigation strategies and to the measures for
efficient and effective troubleshootings.
Standards that are often called for can only help to solve fre-
quent problems related to regular electrical stress. However, they
are not suitable and may be even detrimental for problems that
are rare or related to irregular electrical stress. Needless to say,
standards cannot improve the robustness of ICs against unknown
electrical stresses and standards cannot protect ICs from specifica-
tion violations. Therefore, both system designers and component
designers are asked to pay attention to the special characteristics
of ICs and EOS and to collaborate in order to solve the EOS prob-
lems in the design, handling and application of ICs.
Acknowledgments
The authors would like to thank the members of the ESD Forum
e.V., Charvaka Duvvury and Hans Kunz from Texas Instruments,
Michael Mayerhofer from Infineon Technologies, Christoph Thienel
from Bosch and Jean-Luc Lefebvre from Presto Engineering for
many inspiring and fruitful discussions on EOS.
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