Finite State Machine with Datapath

FSMD (finite state machine with data path)

 An FSMD combines an FSM and regular sequential
circuits.
 The FSM
 examines the external commands and status
 generates control signals to specify operation of the regular
sequential circuits,
 That is collectively known as a data path.
 The FSMD is used to implement systems described by
RT(register transfer) methodology.
 The operations are specified as
 data manipulation
 transfer among a collection of registers.
Single RT operation
 An RT operation specifies data manipulation and transfer for a
single destination register.
 Represented by
rdest  f (rsrc1, rsrc2, … rsrcn)
 where
 rdest is the destination register,
 rsrc1, rsrc2, … rsrcn are the source registers,
 f (rsrc1, rsrc2, … rsrcn) specifies the operation to be performed.
 The notation indicates that
 contents of the source registers are fed to the f (.) function
( realized by a combinational circuit )
 result is passed to the input of the destination register
 Result in the destination register is stored at the next rising edge of
the clock.
RT operations
Commands Operation
r1 0 constant 0 is stored in the r1 register.
rl  rl The content of the rl register is written back to itself
r2  r2 >> 3 The r2 register is shifted right three positions and then
written back to itself
r2  rl The content of the rl register is transferred to the r2 register
ii+1 The content of the i register is incremented by 1 and the
result is written back to itself
d  sl + s2 + s3. The summation of the sl, s2, and s3 registers is written to the
d register
y  a*a The a squared is written to the y register
RT operation implementaion
 A single RT operation can be implemented by
 constructing a combinational circuit for the f (.) function
 connecting the input and output of the registers.
 _reg and _next suffixes represent the input and output of a register.
 Result from the f (.) function is stored to the destination register on the next
rising edge of the clock.
Example: a  a-b+1
ASMD chart
 RT based circuit specifies which RT
operations should be executed in each
step.
 Operation done on a clock-by-clock basis,
 similar to a state transition of an FSM.
 Use FSM to specify the sequencing of an
RT algorithm.
 RT operations are incorporated to the
ASM chart and call it an ASMD (ASM
with data path) chart.
 The RT operations can be placed where
the output signals are used.
ASMD chart
RT operation with conditional box

All operations are done in parallel inside an ASMD block

Decision box with a register
 RT operation is controlled by
an embedded clock signal
 destination register is updated
when the FSMD exits the current
ASMD block
 not within the block.
 The r + r-1 operation actually
means that:
 r_next = r_reg - 1;
 r_reg <= r_next
 at the rising edge of the clock
(i.e., when the FSMD exits the
current block).
 “delayed store ” might
introduce some error.
Block diagram of an FSMD
Block diagram of an FSMD

 The data path performs the required RT operations. It consists of

 Data registers: store the intermediate computation results
 Functional units: perform the functions specified by the RT operations
 Routing network: routes data between the storage registers and the
functional units
 The data path follows the control signal to perform the desired RT
operations and generates the internal status signal
Block diagram of an FSMD

 The control path is a regular FSM, it contains

 state register, next-state logic, and output logic.
 It uses the external command signal and the data path's status
signal as the input and generates the control signal to control
the data path operation.
 The FSM also generates the external status signal to indicate
the status of the FSMD operation.
CODE DEVELOPMENT OF AN FSMD
 The debouncing circuit example seen previously uses an
FSM and a timer
 the two units are running independently
 the FSM has no control over the timer.
 The 10-ms enable tick can be asserted at any time
 the FSM does not know the time elapsed when the first tick is
detected in the waitl_l or wait0_l state.
 Thus, the waiting period is between 20 and 30 ms
 This deficiency can be overcome by applying the RT
methodology.
Debouncing circuit based on RT
methodology
Code with explicit data path components
 The FSMD code can be developed by
 Separating the control FSM and the key data path components.
 From an ASMD chart identify
 Key data path components
 Associated control signals and
 Describe these components in individual code segments.
Code with explicit data path components
 The key data path component of the debouncing circuit
ASMD chart is a custom 21-bit decrement counter that
can:
 Be initialized with a specific value
 Count downward or pause
 Assert a status signal when the counter reaches 0
 We can use a binary counter with
 q-load signal to load the initial value
 q-dec signal to enable the counting.

 generates a q-zero status signal, when the counter reaches

zero.
Code with explicit data path components
 The control path consists of an FSM, which takes at input
 the sw input
 the q-zero status
 Asserts the control signals,
 q-load
 q-dec
Code with explicit data path components
 modul e debounce-explicit
(
input wire clk, reset, input wire sw,
output reg db-level , db-tick
);

 // s y m b o l i c s t a t e d e c l a r a t i o n
local param [I : 01
zero = 2'b00, wait0 = 2'b01,
one = 2'b10, wait1 = 2'bll;

 // number of counter bits ( 2 - N * 20ns = 40ms)

localparam N = 21 ;

 // s i g n a l d e c l a r a t i o n
reg [I: 0] state_reg , state_next ;
reg [N-1:0] q_reg;
wire [N-1: 01 q_next ;
wire q_zero;
reg q_load, q_dec;
Code with explicit data path components
 // fsmd state & data registers
always @ ( posedge clk , posedge reset )
i f ( reset )
begin
s tate_reg <= zero ;
q_ reg <= 0 ;
end
e1se
begin
state_reg <= state_next ;
q_reg <= q_next ;
end

 // FSMD data path ( counter ) next - state logic

assign q-next = ( q_load ) ? ( N ( l’b1 ) ) : // load 1 . . 1
( q_dec ) ? q_ reg - 1 : // decrement
q _ reg ;

 // status signal
assign q_zero = ( q_next ==0) ;
Code with explicit data path components
 // FSMD control path next - state logic
always @*
begin
state_ next = state_reg ; // default state :
the same
q_ load = l ' b0 ; // default output : 0
q_dec = 1 'b0; // default output : 0
db_ tick = l ' b0 ; // default output : 0

 case ( state_ reg )

zero :
begin
db_ level = l ' b0 ;
if (SW)
begin
state - next = waitl ;
q - load = l ' b l ;
end
end
Code with explicit data path components
 waitl :
begin
db - level = l ' b0 ;
i f (sw)
begin
q-dec = l ' b l ;
i f ( q- zero )
begin
state - next = one ;
db - tick = l ' b l ;
end
end
else // sw==0
state - next = zero ;
end
Code with explicit data path components
 one :
begin
db - level = l ' bl ;
if (~sw)
begin
state - next = wait0 ;
q - load = l ' bl ;
end
end
Code with explicit data path components
 wait0 :
begin
db - level = 1 ' b l ;
if (~sw)
begin
q-dec = 1 ' b l ;
if ( q-zero )
state - next = zero ;
end
else // sw==I
state - next = one ;
end
default : state - next = zero ;
endcase
end
endmodule
Code with implicit data path components
 module debounce
(
input wire clk , reset ,
input wire sw,
output reg db_level , db_tick );

 // symbolic state declaration

localparam [ I : 0]
zero = 2 ' b00 ,
wait0 = 2 ' b01,
one = 2 ' b10 ,
wait1 = 2 ' bll ;

 // number of counter bits ( 2^N * 2Ons = 40ms)

localparam N=21;

 // signal declaration
reg [N-1:0] q_ reg , q_ next ;
reg [ I : 0] state _reg , state _next ;
Code with implicit data path components
 // body
// fsmd state & data registers
always @ (posedge clk, posedge reset )
 i f ( reset )
begin
state_reg <= zero ;
q_reg <= 0 ;
end
else
begin
state_reg <= state_next ;
q_reg <= q_next ;
end
Code with implicit data path components
 // next - state logic & data path functional units /
routing
always @ *
begin
state_next = state_reg ;
// default state: the same
q-next = q_reg ; // default q: unchnaged
db_tick = l' b0 ; // default output : 0
case ( state_reg )
zero :
begin
db - level = l ' b0 ;
if ( SW )
begin
state_next = wait l ;
q-next = {N{l'bl});
// load I ...1
end
end
Code with explicit data path components
 wait1 :
begin
db_level = l ' b0 ;
if (SW)
begin
q-next = q_ reg - 1 ;
i f (q_next==0)
begin
state_next = one ;
db _tick = 1' bl ;
end
end
else // sw==0
state_next = zero ;
end
Code with explicit data path components
 one :
begin
db-level = l’bl;
if (~SW)
begin
state-next = wait 0 ;
q-next = {N{l'bl));
// load I . . I
end
end
Code with explicit data path components
 wait 0 :
begin
db-level = l’bl ;
if (~sw)
begin
q-next = q-reg
if ( q-next ==0)
state-next = zero;
end
else // sw==1
state-next = one ;
end

 default : state-next = zero ;

 end case
 End
 endmodule