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Datasheet
Order Numbers:
LAN8710Ai-EZK for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710Ai-EZK-TR for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710A-EZC for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
LAN8710A-EZC-TR for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
Datasheet
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Datasheet
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 32-QFN Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3.2 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.7 LED1/REGOFF Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.8 LED2/nINTSEL Polarity Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.9 Near-end Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.10 Far Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.11 Connector Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.12 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source) . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.4 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 5.5 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5.6 RMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 5.7 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 6.1 32-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 6.2 Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.3 Taping Dimensions and Part Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.4 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 6.5 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Datasheet
List of Tables
Table 2.1 MII/RMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.3 Serial Management Interface (SMI) Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.4 Ethernet Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.5 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.6 Analog Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.7 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.8 32-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.9 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3.2 MII/RMII Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.3 Interrupt Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3.4 Alternative Interrupt System Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 3.5 Pin Names for Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3.6 MODE[2:0] Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3.7 Pin Names for Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4.1 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 4.2 SMI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.1 Device Only Current Consumption and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 5.2 Non-Variable I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5.3 Variable I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.4 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.5 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 5.6 Power Sequence Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5.7 Power-On nRST & Configuration Strap Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 5.8 MII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5.9 MII Transmit Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 5.10 RMII Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 5.11 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.12 SMI Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.13 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 6.1 32-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Datasheet
Chapter 1 Introduction
BYTE 8-bits
FIFO First In First Out buffer; often used for elasticity buffer
The LAN8710A/LAN8710Ai supports communication with an Ethernet MAC via a standard MII (IEEE
802.3u)/RMII interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports
10Mbps (10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8710A/LAN8710Ai implements
auto-negotiation to automatically determine the best possible speed and duplex mode of operation. HP
Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
The LAN8710A/LAN8710Ai supports both IEEE 802.3-2005 compliant and vendor-specific register
functions. However, no register access is required for operation. The initial configuration may be
selected via the configuration pins as described in Section 3.7, "Configuration Straps," on page 36.
Register-selectable configuration options may be used to further define the functionality of the
transceiver.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be
configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The
linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for
lower system power dissipation.
The LAN8710A/LAN8710Ai is available in both extended commercial and industrial temperature range
versions. A typical system application is shown in Figure 1.1.
Datasheet
10/100 MII/
LAN8710A/
RMII MDI
Ethernet Transformer RJ45
LAN8710Ai
MAC
Mode LED
Crystal or
Clock
Oscillator
MODE[0:2]
Mode Control HP Auto-MDIX
Auto- 100M TX 100M TXP/TXN
nRST Negotiation Logic Transmitter
Reset Control
RXP/RXN
RMIISEL Transmitter
TXD[0:3] 10M TX 10M
SMI Management
Logic Transmitter MDIX
TXEN Control
Control
TXER
XTAL1/CLKIN
TXCLK
PLL XTAL2
RXD[0:3]
RMII/MII Logic
Datasheet
nINT/TXER/TXD4
TXCLK
TXEN
nRST
TXD2
TXD1
TXD0
MDC
24
23
22
21
20
19
18
17
TXD3 25 16 MDIO
RXN 30 11 RXD0/MODE0
RXP 31 10 RXD1/MODE1
RBIAS 32 9 RXD2/RMIISEL
1
8
RXCLK/PHYAD1
RXD3/PHYAD2
VDD2A
XTAL2
LED1/REGOFF
XTAL1/CLKIN
VDDCR
LED2/nINTSEL
Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal
is active low. For example, nRST indicates that the reset signal is active low.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the
buffer types is provided in Section 2.2.
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Transmit TXD0 VIS The MAC transmits data to the transceiver using
1 this signal in all modes.
Data 0
Transmit TXD1 VIS The MAC transmits data to the transceiver using
1 this signal in all modes.
Data 1
Transmit TXD2 VIS The MAC transmits data to the transceiver using
Data 2 this signal in MII Mode.
1 (MII Mode) Note: This signal must be grounded in RMII
Mode.
Transmit TXD3 VIS The MAC transmits data to the transceiver using
Data 3 this signal in MII Mode.
1 (MII Mode) Note: This signal must be grounded in RMII
Mode.
Transmit TXER VIS When driven high, the 4B/5B encode process
Error (PU) substitutes the Transmit Error code-group (/H/)
(MII Mode) for the encoded data word. This input is ignored
in the 10BASE-T mode of operation.
Transmit TXCLK VO8 Used to latch data from the MAC into the
Clock transceiver.
(MII Mode) MII (100BASE-TX): 25MHz
1
MII (10BASE-T): 2.5MHz
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Receive RXD0 VO8 Bit 0 of the 4 (2 in RMII Mode) data bits that are
Data 0 sent by the transceiver on the receive path.
Receive RXD1 VO8 Bit 1 of the 4 (2 in RMII Mode) data bits that are
Data 1 sent by the transceiver on the receive path.
Receive RXD2 VO8 Bit 2 of the 4 (in MII Mode) data bits that are sent
Data 2 by the transceiver on the receive path.
(MII Mode) Note: This signal is not used in RMII Mode.
MII/RMII RMIISEL VIS This configuration strap selects the MII or RMII
Mode Select (PD) mode of operation. When strapped low to VSS,
Configuration MII Mode is selected. When strapped high to
1 VDDIO RMII Mode is selected.
Strap
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on
page 37 for additional details.
Receive RXD3 VO8 Bit 3 of the 4 (in MII Mode) data bits that are sent
Data 3 by the transceiver on the receive path.
(MII Mode) Note: This signal is not used in RMII Mode.
PHY Address PHYAD2 VIS Combined with PHYAD0 and PHYAD1, this
2 (PD) configuration strap sets the transceiver’s SMI
1 Configuration address.
Strap
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Receive Error RXER VO8 This signal is asserted to indicate that an error
was detected somewhere in the frame presently
being transferred from the transceiver.
Note: This signal is optional in RMII Mode.
PHY Address PHYAD0 VIS Combined with PHYAD1 and PHYAD2, this
0 (PD) configuration strap sets the transceiver’s SMI
Configuration address.
Strap
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Receive RXCLK VO8 In MII mode, this pin is the receive clock output.
Clock MII (100BASE-TX): 25MHz
(MII Mode) MII (10BASE-T): 2.5MHz
PHY Address PHYAD1 VIS Combined with PHYAD0 and PHYAD2, this
1 (PD) configuration strap sets the transceiver’s SMI
1 address.
Configuration
Strap
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Receive Data RXDV VO8 Indicates that recovered and decoded data is
1 available on the RXD pins.
Valid
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Carrier Sense CRS_DV VO8 This signal is asserted to indicate the receive
/ Receive medium is non-idle in RMII Mode. When a
Data Valid 10BASE-T packet is received, CRS_DV is
(RMII Mode) asserted, but RXD[1:0] is held low until the SFD
byte (10101011) is received.
Note: Per the RMII standard, transmitted data
is not looped back onto the receive data
pins in 10BASE-T half-duplex mode.
Carrier Sense CRS VO8 This signal indicates detection of a carrier in MII
1 Mode.
(MII Mode) (PD)
Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
LED 1 LED1 O12 Link activity LED Indication. This pin is driven
active when a valid link is detected and blinks
when activity is detected.
Note: Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
LED 2 LED2 O12 Link Speed LED Indication. This pin is driven
active when the operating speed is 100Mbps. It
is inactive when the operating speed is 10Mbps
or during line isolation.
Note: Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Datasheet
BUFFER
NUM PINS NAME SYMBOL TYPE DESCRIPTION
Datasheet
1 VDD2A 17 MDC
2 LED2/nINTSEL 18 nINT/TXER/TXD4
3 LED1/REGOFF 19 nRST
4 XTAL2 20 TXCLK
5 XTAL1/CLKIN 21 TXEN
6 VDDCR 22 TXD0
7 RXCLK/PHYAD1 23 TXD1
8 RXD3/PHYAD2 24 TXD2
9 RXD2/RMIISEL 25 TXD3
10 RXD1/MODE1 26 RXDV
11 RXD0/MODE0 27 VDD1A
12 VDDIO 28 TXN
13 RXER/RXD4/PHYAD0 29 TXP
14 CRS 30 RXN
15 COL/CRS_DV/MODE2 31 RXP
16 MDIO 32 RBIAS
Datasheet
IS Schmitt-triggered input
VO8 Variable voltage output with 8mA sink and 8mA source
PU 50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AI Analog input
P Power pin
Note: The digital signals are not 5V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*," on
page 66 for additional buffer information.
Note 2.3 Sink and source capabilities are dependant on the VDDIO voltage. Refer to Section 5.1,
"Absolute Maximum Ratings*," on page 66 for additional information.
Datasheet
This chapter provides functional descriptions of the various device features. These features have been
categorized into the following sections:
Transceiver
Auto-negotiation
HP Auto-MDIX Support
MAC Interface
Serial Management Interface (SMI)
Interrupt Management
Configuration Straps
Miscellaneous Functions
Application Diagrams
3.1 Transceiver
TX_CLK
(for MII only) PLL
NRZI MLT-3 Tx
125 Mbps Serial NRZI MLT-3
Converter Converter Driver
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data
is in the form of 4-bit wide 25MHz data.
Datasheet
For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The
data is in the form of 2-bit wide 50MHz data.
The transmit data passes from the MII/RMII block to the 4B/5B encoder. This block encodes the data
from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 3.1. Each 4-bit data-
nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used
for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
11000 J First nibble of SSD, translated to “0101” Sent for rising TXEN
following IDLE, else RXER
01101 T First nibble of ESD, causes de-assertion Sent for falling TXEN
of CRS if followed by /R/, else assertion
of RXER
Datasheet
3.1.1.3 Scrambling
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC
regulations to prevent excessive EMI from being radiated by the physical wiring.
The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in
multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own
scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on
outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-
T and 100BASE-TX signals pass through the same transformer so that common “magnetics” can be
used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination
and impedance matching require external components.
Datasheet
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100BASE-TX transmitter.
RX_CLK
(for MII only)
PLL
NRZI
DSP: Timing
NRZI MLT-3 MLT-3
recovery, Equalizer
Converter Converter
and BLW Correction
6 bit Data
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.
Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
3.1.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
Datasheet
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
3.1.2.4 Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs
the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to
descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for
IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size
of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-
symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts
the synchronization process.
3.1.2.5 Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream
Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored
and utilized until the next start of frame.
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The
translated data is presented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101”
as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the transceiver to assert the
receive data valid signal, indicating that valid data is available on the RXD bus. Successive valid code-
groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting
of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert the carrier sense
and receive data valid signals.
The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/
delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either
the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media
Independent Interface (MII mode).
Datasheet
RX_CLK
RX_DV
Figure 3.3 Relationship Between Received Data and Specific MII Signals
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the
DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER
signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected
during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and
the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted
when the bad SSD error occurs.
In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the
controller at a rate of 25MHz. The controller samples the data on the rising edge of RXCLK. To ensure
that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the
falling edge of RXCLK. RXCLK is the 25MHz output clock for the MII bus. It is recovered from the
received data to clock the RXD bus. If there is no received signal, it is derived from the system
reference clock (XTAL1/CLKIN).
When tracking the received data, RXCLK has a maximum jitter of 0.8ns (provided that the jitter of the
input clock, XTAL1/CLKIN, is below 100ps).
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the
controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN
(REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of
the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).
The MAC controller drives the transmit data onto the TXD bus. For MII, when the controller has driven
TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK.
The data is in the form of 4-bit wide 2.5MHz data. For RMII, TXD[1:0] shall transition synchronously
with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the
device. TXD[1:0] shall be “00” to indicate idle when TXEN is deasserted. Values of TXD[1:0] other than
“00” when TXEN is deasserted are reserved for out-of-band signalling (to be defined). Values other
Revision 1.4 (08-23-12) 24 SMSC LAN8710A/LAN8710Ai
DATASHEET
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by the device.TXD[1:0] shall provide
valid data for each REF_CLK period while TXEN is asserted.
In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops
back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the
COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat) signal.
See Section 3.8.7, "Collision Detect," on page 42, for more details.
The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI
data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz
clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted
(TXEN is low), the 10M TX block outputs Normal Link Pulses (NLPs) to maintain communications with
the remote link partner.
The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before
being driven out as a differential signal across the TXP and TXN outputs.
The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio
magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH
circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential
voltage levels below 300mV and detect and recognize differential voltages above 585mV.
The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded
data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to
RXN of the remote partner and vice versa), the condition is identified and corrected. The reversed
condition is indicated by the XPOL bit of the Special Control/Status Indications Register. The 10M PLL
is locked onto the received Manchester signal, from which the 20MHz cock is generated. Using this
clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is
then converted from serial to 4-bit wide parallel data.
The 10M RX block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain
the link.
Datasheet
For MII, the 4-bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on
the rising edge of the 2.5 MHz RXCLK.
For RMII, the 2-bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid
on the rising edge of the RMII REF_CLK.
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, which results in holding the TXEN input for
a long period. Special logic is used to detect the jabber state and abort the transmission to the line
within 45ms. Once TXEN is deasserted, the logic resets the jabber condition.
As shown in Section 4.2.2, "Basic Status Register," on page 53, the Jabber Detect bit indicates that a
jabber condition was detected.
3.2 Auto-negotiation
The purpose of the auto-negotiation function is to automatically configure the transceiver to the
optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism
for exchanging configuration information between two link-partners and automatically selecting the
highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in
clause 28 of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Indication bits of the PHY Special Control/Status Register, as well as in the Auto
Negotiation Link Partner Ability Register. The auto-negotiation protocol is a purely physical layer
activity and proceeds independently of the MAC controller.
The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement
Register. The default advertised by the transceiver is determined by user-defined on-chip signal
options.
When enabled, auto-negotiation is started by the occurrence of one of the following events:
Hardware reset
Software reset
Power-down reset
Link status down
Setting the Restart Auto-Negotiate bit of the Basic Control Register
On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of
Fast Link Pulses (FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as
Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst
Datasheet
consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP
burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being
transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the transceiver advertises 802.3 compliance in its selector field (the first
5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the Auto
Negotiation Advertisement Register.
There are 4 possible matches of the technology abilities. In the order of priority these are:
100M Full Duplex (Highest Priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (Lowest Priority)
If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is
capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If
the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as
the highest performance operation.
Once a capability match has been determined, the link code words are repeated with the acknowledge
bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation
to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.
The capabilities advertised during auto-negotiation by the transceiver are initially determined by the
logic levels latched on the MODE[2:0] configuration straps after reset completes. These configuration
straps can also be used to disable auto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for additional information.
Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of
the capabilities advertised by the transceiver. Writing the Auto Negotiation Advertisement Register
does not automatically re-start auto-negotiation. The Restart Auto-Negotiate bit of the Basic Control
Register must be set before the new abilities will be advertised. Auto-negotiation can also be disabled
via software by clearing the Auto-Negotiation Enable bit of the Basic Control Register.
Auto Negotiation Link Partner Ability Register is used to store the link partner ability information, which
is coded in the received FLPs. If the link partner is not auto-negotiation capable, then the Auto
Negotiation Link Partner Ability Register is updated after completion of parallel detection to reflect the
speed capability of the link partner.
Datasheet
signal transmitted by the link partner. Auto-negotiation resumes in an attempt to determine the new
link configuration.
If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the
Basic Control Register, the LAN8710A/LAN8710Ai will respond by stopping all transmission/receiving
operations. Once the break_link_timer is completed in the Auto-negotiation state-machine
(approximately 1200ms), auto-negotiation will re-start. In this case, the link partner will have also
dropped the link due to lack of a received signal, so it too will resume auto-negotiation.
In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode,
CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection
is disabled.
Datasheet
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status
Indications Register.
Datasheet
The device must be configured in MII or RMII mode. This is done by specific pin strapping
configurations. Refer to Section 3.4.3, "MII vs. RMII Configuration," on page 31 for information on pin
strapping and how the pins are mapped differently.
3.4.1 MII
The MII includes 16 interface signals:
transmit data - TXD[3:0]
transmit strobe - TXEN
transmit clock - TXCLK
transmit error - TXER/TXD4
receive data - RXD[3:0]
receive strobe - RXDV
receive clock - RXCLK
receive error - RXER/RXD4/PHYAD0
collision indication - COL
carrier sense - CRS
In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller.
The controller synchronizes the transmit data to the rising edge of TXCLK. The controller drives TXEN
high to indicate valid transmit data. The controller drives TXER high when a transmit error is detected.
On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal.
The controller clocks in the receive data on the rising edge of RXCLK when the transceiver drives
RXDV high. The transceiver drives RXER high when a receive error is detected.
3.4.2 RMII
The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use
between Ethernet transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for
data and control is defined. In devices incorporating many MACs or transceiver interfaces such as
switches, the number of pins can add significant cost as the port counts increase. RMII reduces this
pin count while retaining a management interface (MDIO/MDC) that is identical to MII.
Datasheet
The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted
asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE-
T mode when squelch is passed, or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are
detected, the carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the device has additional bits to be presented on RXD[1:0] following the initial
deassertion of CRS_DV, then the device shall assert CRS_DV on cycles of REF_CLK which present
the second di-bit of each nibble and de-assert CRS_DV on cycles of REF_CLK which present the first
di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25 MHz in 100Mbps
mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (i.e. the FIFO still has bits to
transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0],
TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering
is required on the transmit data path. However, on the receive data path, the receiver recovers the
clock from the incoming data stream, and the device uses elasticity buffering to accommodate for
differences between the recovered clock and the local REF_CLK.
Most of the MII and RMII pins are multiplexed. Table 3.2, "MII/RMII Signal Mapping" describes the
relationship of the related device pins to the MII and RMII mode signal names.
Datasheet
nINT/TXER/TXD4 TXER/
TXD4
CRS CRS
RXDV RXDV
RXD2/RMIISEL RXD2
RXD3/PHYAD2 RXD3
TXCLK TXCLK
RXCLK/PHYAD1 RXCLK
Note 3.2 The RXER signal is optional on the RMII bus. This signal is required by the transceiver,
but it is optional for the MAC. The MAC can choose to ignore or not use this signal.
Datasheet
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock
provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output
signal that receives serial data (commands) from the controller SMC and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges. The minimum cycle time (time between two consecutive rising or two consecutive
falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by
the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 3.5 and Figure 3.6. The timing relationships of the MDIO signals are
further described in Section 5.5.6, "SMI Timing," on page 76.
Read Cycle
MDC ...
MDIO 32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 ... D1 D0
Start of OP Turn
Preamble PHY Address Register Address Data
Frame Code Around
Write Cycle
MDC ...
MDIO 32 1's 0 1 0 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 ... D1 D0
Start of OP Turn
Preamble PHY Address Register Address Data
Frame Code Around
Data To Phy
Datasheet
The device’s interrupt system provides two modes, a Primary Interrupt mode and an Alternative
interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set.
These modes differ only in how they de-assert the nINT interrupt output. These modes are detailed in
the following subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The
Alternative interrupt mode requires setup after a power-up or hard reset.
30.5 29.5 Remote Fault 1.4 Remote Fault Rising 1.4 Falling 1.4, or
Detected Reading register 1 or
Reading register 29
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 Reading register 1 or
Reading register 29
30.2 29.2 Parallel Detection 6.4 Parallel Rising 6.4 Falling 6.4 or
Fault Detection Fault Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
30.1 29.1 Auto-Negotiation 6.1 Page Received Rising 6.1 Falling of 6.1 or
Page Received Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
Note 3.3 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,
nINT will assert for 256 ms, approximately one second after ENERGYON goes low when
the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON
interrupt mask should always be cleared as part of the ENERGYON interrupt service
routine.
Datasheet
Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt.
After a cable is plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and
nINT will be asserted low. To de-assert the nINT interrupt output, either clear the ENERGYON bit in
the Mode Control/Status Register by removing the cable and then writing a ‘1’ to the INT7 bit in the
Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt Mask Register).
CONDITION BIT TO
INTERRUPT SOURCE EVENT TO TO CLEAR
MASK FLAG INTERRUPT SOURCE ASSERT nINT DE-ASSERT nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.7
30.6 29.6 Auto-Negotiation 1.5 Auto-Negotiate Rising 1.5 1.5 low 29.6
complete Complete
30.5 29.5 Remote Fault 1.4 Remote Fault Rising 1.4 1.4 low 29.5
Detected
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.4
30.3 29.3 Auto-Negotiation 5.14 Acknowledge Rising 5.14 5.14 low 29.3
LP Acknowledge
30.2 29.2 Parallel 6.4 Parallel Detection Rising 6.4 6.4 low 29.2
Detection Fault Fault
30.1 29.1 Auto-Negotiation 6.1 Page Received Rising 6.1 6.1 low 29.1
Page Received
Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
Datasheet
Note: The system designer must guarantee that configuration strap pins meet the timing
requirements specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on
page 72. If configuration strap pins are not at the correct voltage level prior to being latched,
the device may capture incorrect strap values.
Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except
for REGOFF and nINTSEL which should be tied to VDD2A.
The device’s SMI address may be configured using hardware configuration to any value between 0
and 7. The user can configure the PHY address using Software Configuration if an address greater
than 7 is required. The PHY address can be written (after SMI communication at some address is
established) using the PHYAD bits of the Special Modes Register. The PHYAD[2:0] configuration straps
are multiplexed with other signals as shown in Table 3.5.
PHYAD[0] RXER/RXD4/PHYAD0
PHYAD[1] RXCLK/PHYAD1
PHYAD[2] RXD3/PHYAD2
The device’s mode may be configured using the hardware configuration straps as summarized in
Table 3.6. The user may configure the transceiver mode by writing the SMI registers.
Datasheet
[13,12,10,8] [8,7,6,5]
110 Power Down mode. In this mode the transceiver will N/A N/A
wake-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in
Register 18.7:5(see Section 4.2.9, "Special Modes
Register," on page 60) must be configured to some
other value and a soft reset must be issued.
The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3.7.
MODE[0] RXD0/MODE0
MODE[1] RXD1/MODE1
MODE[2] COL/CRS_DV/MODE2
When the nRST pin is deasserted, the MIIMODE bit of the Special Modes Register is loaded according
to the RMIISEL configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes
Register.
Refer to Section 3.4, "MAC Interface," on page 30 for additional information on MII and RMII modes.
Datasheet
Note: Because the REGOFF configuration strap shares functionality with the LED1 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.1, "REGOFF and
LED1 Polarity Selection," on page 39 for additional information on the relation between
REGOFF and the LED1 polarity.
To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the
REGOFF configuration strap to VDD2A. At power-on, after both VDDIO and VDD2A are within
specification, the transceiver will sample REGOFF to determine whether the internal regulator should
turn on. If the pin is sampled at a voltage greater than VIH, then the internal regulator is disabled and
the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must be at least 80% of the
operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when
operating at 3.3V) before voltage is applied to VDDCR. As described in Section 3.7.4.2, when
REGOFF is left floating or connected to VSS, the internal regulator is enabled and the system is not
required to supply +1.2V to the VDDCR pin.
The +1.2V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the
regulator off mode using the REGOFF configuration strap as described in Section 3.7.4.1. By default,
the internal +1.2V regulator is enabled when REGOFF is floating (due to the internal pull-down
resistor). During power-on, if REGOFF is sampled below VIL, then the internal +1.2V regulator will turn
on and operate with power from the VDD2A pin.
Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 39 for additional information on the relation between
nINTSEL and the LED2 polarity.
Datasheet
3.8.1 LEDs
Two LED signals are provided as a convenient means to determine the transceiver's mode of
operation. All LED signals are either active high or active low as described in Section 3.8.1.2,
"nINTSEL and LED2 Polarity Selection" and Section 3.8.1.1, "REGOFF and LED1 Polarity Selection,"
on page 39.
The LED1 output is driven active whenever the device detects a valid link, and blinks when CRS is
active (high) indicating activity.
The LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive
when the operating speed is 10Mbps or during line isolation.
Note: When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO.
The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically
change polarity based on the presence of an external pull-up resistor. If the LED1 pin is pulled high to
VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED1 output will
be active low. If the LED1 pin is pulled low by the internal pull-down resistor to select a logical low for
REGOFF, the LED1 output will then be an active high output. Figure 3.7 details the LED1 polarity for
each REGOFF configuration.
10K
~270 ohms ~270 ohms
LED1/REGOFF
Note: Refer to Section 3.7.4, "REGOFF: Internal +1.2V Regulator Configuration," on page 38 for
additional information on the REGOFF configuration strap.
The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically
change polarity based on the presence of an external pull-down resistor. If the LED2 pin is pulled high
to VDD2A to select a logical high for nINTSEL, then the LED2 output will be active low. If the LED2
Datasheet
pin is pulled low by an external pull-down resistor to select a logical low for nINTSEL, the LED2 output
will then be an active high output. Figure 3.8 details the LED2 polarity for each nINTSEL configuration.
nINTSEL = 1 nINTSEL = 0
LED output = Active Low LED output = Active High
VDD2A
LED2/nINTSEL
10K
LED2/nINTSEL
Note: Refer to Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration," on page 38 for additional
information on the nINTSEL configuration strap.
Note: Input signals must not be driven high before power is applied to the device.
This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this
mode, the entire transceiver (except the management interface) is powered-down and remains in this
mode as long as the Power Down bit is “1”. When the Power Down bit is cleared, the transceiver
powers up and is automatically reset.
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status
Register. In this mode, when no energy is present on the line the transceiver is powered down (except
for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation
signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is
powered-down and nothing is transmitted. When energy is received via link pulses or packets, the
ENERGYON bit goes high and the transceiver powers-up. The device automatically resets into the
Datasheet
state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is
disabled.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
3.8.5 Resets
The device provides two forms of reset: Hardware and Software. The device registers are reset by
both Hardware and Software resets. Select register bits, indicated as “NASR” in the register definitions,
are not cleared by a Software reset. The registers are not reset by the power-down modes described
in Section 3.8.3.
Note: For the first 16us after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this
time, it will switch to 25 MHz if auto-negotiation is enabled.
A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing,"
on page 72 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3,
"Power-On nRST & Configuration Strap Timing," on page 72 for additional information.
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset
process will be completed within 0.5s from the setting of this bit.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It
activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier
sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter
pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter
pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If
/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by
some non-IDLE symbol.
Datasheet
The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This
enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-
asserted within 4 bit times of TXEN falling.
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID
signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for
an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the
Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time
DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T
receiver logic.
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing
purposes, as indicated by the blue arrows in Figure 3.9. The near-end loopback mode is enabled by
setting the Loopback bit of the Basic Control Register to “1”. A large percentage of the digital circuitry
is operational in near-end loopback mode because data is routed through the PCS and PMA layers
into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless
Datasheet
Collision Test is enabled in the Basic Control Register. The transmitters are powered down regardless
of the state of TXEN.
TXD TX
10/100 X CAT-5
Ethernet XFMR
RXD RX
MAC X
Digital Analog
SMSC
Ethernet Transceiver
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in
Figure 3.11. The far loopback mode is enabled by setting the FARLOOPBACK bit of the Mode
Control/Status Register to “1”. In this mode, data that is received from the link partner on the MDI is
looped back out to the link partner. The digital interface signals on the local MAC interface are isolated.
Note: This special test mode is only available when operating in RMII mode.
Far-end system
TXD TX
10/100 X CAT-5 Link
Ethernet XFMR
MAC
RXD
X
RX Partner
Digital Analog
SMSC
Ethernet Transceiver
The device maintains reliable transmission over very short cables, and can be tested in a connector
loopback as shown in Figure 3.11. An RJ45 loopback cable can be used to route the transmit signals
Datasheet
an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and
100.
1
TXD TX 2
10/100 3
4
Ethernet XFMR 5
RXD RX
MAC 6
7
Digital Analog 8
Datasheet
LAN8710A/LAN8710Ai
10/100 PHY
32-QFN
MII MII
MDIO
MDC
nINT
Mag RJ45
TXD[3:0] TXP
4 TXN
TXCLK
TXER RXP
TXEN
RXN
RXD[3:0]
4
RXCLK
RXDV
XTAL1/CLKIN
25MHz
LED[2:1]
XTAL2
2
nRST
Interface
Datasheet
LAN8710A/LAN8710Ai
32-QFN Power
Supply
3.3V
Ch.2 3.3V
Core Logic
Circuitry
VDDDIO VDD1A
VDDIO Ch.1 3.3V
Supply
Circuitry
1.8 - 3.3V CBYPASS
CF CBYPASS
RBIAS
LED1/
REGOFF VSS 12.1k
~270 Ohm
Datasheet
LAN8710A/LAN8710Ai
32-QFN Power
Supply
3.3V
Ch.2 3.3V
Core Logic
Circuitry
VDDDIO VDD1A
VDDIO Ch.1 3.3V
Supply
Circuitry
1.8 - 3.3V CBYPASS
CF CBYPASS
RBIAS
LED1/
REGOFF VSS 12.1k
~270 Ohm
10k
Datasheet
Ferrite
LAN8710A/LAN8710Ai bead
Power 49.9 Ohm Resistors
32-QFN Supply
3.3V
VDD2A
CBYPASS
VDD1A
CBYPASS Magnetics
RJ45
TXP 1
2
75 3
4
5
6
TXN 7
8
RXP
75
RXN
1000 pF
3 kV
CBYPASS
Datasheet
VDD2A
CBYPASS
VDD1A
CBYPASS Magnetics
RJ45
TXP 1
2
75 3
4
5
6
TXN 7
8
RXP
75
RXN
1000 pF
3 kV
CBYPASS
Datasheet
This chapter describes the various control and status registers (CSR’s). All registers follow the IEEE
802.3 (clause 22.2.4) management register set. All functionality and bit definitions comply with these
standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition,
allowing for addressing of these registers via the Serial Management Interface (SMI) protocol.
WO Write only: If a register or bit is write-only, reads will return unspecified data.
WC Write One to Clear: writing a one clears the value. Writing a zero has no effect
RC Read to Clear: Contents is cleared after the read. Writes have no effect.
SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After
it is read, the bit will either remain high if the high condition remains, or will go low if
the high condition has been removed. If the bit has not been read, the bit will remain
high regardless of a change to the high condition. This mode is used in some Ethernet
PHY registers.
NASR Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED Reserved Field: Reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combined. Some examples of this are shown below:
R/W: Can be written. Will return current setting on a read.
R/WAC: Will return current setting on a read. Writing anything clears the bit.
Datasheet
REGISTER INDEX
(DECIMAL) REGISTER NAME GROUP
Datasheet
14 Loopback R/W 0b
0 = normal operation
1 = loopback mode
10 Isolate R/W 0b
0 = normal operation
1 = electrical isolation of PHY from the MII/RMII
6:0 RESERVED RO -
Note 4.1 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Datasheet
15 100BASE-T4 RO 0b
0 = no T4 ability
1 = T4 able
8 Extended Status RO 0b
0 = no extended status information in register 15
1 = extended status information in register 15
7:6 RESERVED RO -
5 Auto-Negotiate Complete RO 0b
0 = auto-negotiate process not completed
1 = auto-negotiate process completed
3 Auto-Negotiate Ability RO 1b
0 = unable to perform auto-negotiation function
1 = able to perform auto-negotiation function
0 Extended Capabilities RO 1b
0 = does not support extended capabilities registers
1 = supports extended capabilities registers
Datasheet
Datasheet
Note 4.2 The default value of this field will vary dependant on the silicon revision number.
Datasheet
15:14 RESERVED RO -
12 RESERVED RO -
9 RESERVED RO -
7 100BASE-TX R/W 1b
0 = no TX ability
1 = TX able
Note 4.3 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Datasheet
15 Next Page RO 0b
0 = no next page ability
1 = next page capable
Note: This device does not support next page ability.
14 Acknowledge RO 0b
0 = link code word not yet received
1 = link code word received from partner
13 Remote Fault RO 0b
0 = no remote fault
1 = remote fault detected
12:11 RESERVED RO -
10 Pause Operation RO 0b
0 = No PAUSE supported by partner station
1 = PAUSE supported by partner station
9 100BASE-T4 RO 0b
0 = no T4 ability
1 = T4 able
Note: This device does not support T4 ability.
7 100BASE-TX RO 0b
0 = no TX ability
1 = TX able
5 10BASE-T RO 0b
0 = no 10Mbps ability
1 = 10Mbps able
Datasheet
15:5 RESERVED RO -
Datasheet
15:14 RESERVED RO -
13 EDPWRDOWN R/W 0b
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
12:10 RESERVED RO -
9 FARLOOPBACK R/W 0b
Enables far loopback mode (i.e., all the received packets are sent back
simultaneously (in 100BASE-TX only)). This bit is only active in RMII mode.
This mode works even if the Isolate bit (0.10) is set.
0 = Far loopback mode is disabled
1 = Far loopback mode is enabled
Refer to Section 3.8.9.2, "Far Loopback," on page 43 for additional
information.
8:7 RESERVED RO -
6 ALTINT R/W 0b
Alternate Interrupt Mode:
0 = Primary interrupt system enabled (Default)
1 = Alternate interrupt system enabled
Refer to Section 3.6, "Interrupt Management," on page 34 for additional
information.
5:2 RESERVED RO -
1 ENERGYON RO 1b
Indicates whether energy is detected. This bit transitions to “0” if no valid
energy is detected within 256ms. It is reset to “1” by a hardware reset and
is unaffected by a software reset. Refer to Section 3.8.3.2, "Energy Detect
Power-Down," on page 40 for additional information.
0 RESERVED R/W 0b
Datasheet
15 RESERVED RO -
13:8 RESERVED RO -
Note 4.4 The default value of this field is determined by the RMIISEL configuration strap. Refer to
Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 37 for additional
information.
Note 4.5 The default value of this field is determined by the MODE[2:0] configuration straps. Refer
to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Note 4.6 The default value of this field is determined by the PHYAD[2:0] configuration straps. Refer
to Section 3.7.1, "PHYAD[2:0]: PHY Address Configuration," on page 36 for additional
information.
Datasheet
Datasheet
15 AMDIXCTRL R/W 0b
HP Auto-MDIX control:
0 = Enable Auto-MDIX
1 = Disable Auto-MDIX (use 27.13 to control channel)
14 RESERVED RO -
13 CH_SELECT R/W 0b
Manual channel select:
0 = MDI (TX transmits, RX receives)
1 = MDIX (TX receives, RX transmits)
12 RESERVED RO -
11 SQEOFF R/W 0b
Disable the SQE test (Heartbeat): NASR
0 = SQE test is enabled
1 = SQE test is disabled
10:5 RESERVED RO -
4 XPOL RO 0b
Polarity state of the 10BASE-T:
0 = Normal polarity
1 = Reversed polarity
3:0 RESERVED RO -
Datasheet
15:8 RESERVED RO -
7 INT7 RO/LH 0b
0 = not source of interrupt
1 = ENERGYON generated
6 INT6 RO/LH 0b
0 = not source of interrupt
1 = Auto-Negotiation complete
5 INT5 RO/LH 0b
0 = not source of interrupt
1 = Remote Fault Detected
4 INT4 RO/LH 0b
0 = not source of interrupt
1 = Link Down (link status negated)
3 INT3 RO/LH 0b
0 = not source of interrupt
1 = Auto-Negotiation LP Acknowledge
2 INT2 RO/LH 0b
0 = not source of interrupt
1 = Parallel Detection Fault
1 INT1 RO/LH 0b
0 = not source of interrupt
1 = Auto-Negotiation Page Received
0 RESERVED RO 0b
Datasheet
15:8 RESERVED RO -
0 RESERVED RO -
Datasheet
15:13 RESERVED RO -
12 Autodone RO 0b
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not active)
1 = Auto-negotiation is done
5 RESERVED RO -
1:0 RESERVED RO -
Datasheet
Positive voltage on signal pins, with respect to ground (Note 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Negative voltage on signal pins, with respect to ground (Note 5.3) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V
Note 5.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested that a clamp circuit be used.
Note 5.2 This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.
Note 5.3 This rating does not apply to the following pins: RBIAS.
Note 5.4 0oC to +85oC for extended commercial version, -40oC to +85oC for industrial version.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 5.2, "Operating Conditions**", Section 5.1, "Absolute Maximum Ratings*", or any other
applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant
unless specified otherwise.
Datasheet
**Proper operation of the device is guaranteed only within the ranges specified in this section. After
the device has completed power-up, VDDIO and the magnetics power supply must maintain their
voltage level with +/-10%. Varying the voltage greater than +/-10% after the device has completed
power-up can cause errors in device operation.
Note: Do not drive input signals without power supplied to the device.
Note: The current at VDDCR is either supplied by the internal regulator from current entering at
VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
Datasheet
Note: Current measurements do not include power applied to the magnetics or the optional external
LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in
10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
Note 5.6 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.
5.4 DC Specifications
Table 5.2 details the non-variable I/O buffer characteristics. These buffer types do not support variable
voltage operation. Table 5.3 details the variable voltage I/O buffer characteristics. Typical values are
provided for 1.8V, 2.5V, and 3.3V VDDIO cases.
Note 5.7 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Note 5.8 XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.
Datasheet
Note 5.9 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 5.10
Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 5.10
Signal Rise and Fall Time TRF 3.0 - 5.0 nS Note 5.10
Note 5.10 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor.
Note 5.11 Offset from 16nS pulse width at 50% of pulse peak.
Datasheet
Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 5.13
Note 5.13 Min/max voltages guaranteed as measured with 100Ω resistive load.
5.5 AC Specifications
This section details the various AC timing specifications of the device.
Note: The MII/SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3
specification for additional timing information.
Note: The RMII timing adheres to the RMII Consortium RMII Specification R1.2.
OUTPUT
25 pF
Datasheet
tpon tpoff
VDDIO
Magnetics
Power
VDD1A,
VDD2A
Figure 5.2 Power Sequence Timing
Note: When the internal regulator is disabled, a power-up sequencing relationship exists between
VDDCR and the 3.3V power supply. For additional information refer to Section 3.7.4,
"REGOFF: Internal +1.2V Regulator Configuration," on page 38.
Datasheet
tcss tcsh
Configuration Strap
Pins Input
totaa todad
Configuration Strap
Pins Output Drive
Figure 5.3 Power-On nRST & Configuration Strap Timing
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,
"Configuration Straps," on page 36 for details. Configuration straps must only be pulled high or
low and must not be driven as inputs.
Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.
Datasheet
tclkp
tclkh tclkl
RXCLK
tval tval thold
RXD[3:0]
thold
tval
RXDV
Figure 5.4 MII Receive Timing
tval RXD[3:0], RXDV output valid from rising edge of 28.0 ns Note 5.16
RXCLK
thold RXD[3:0], RXDV output hold from rising edge of 10.0 ns Note 5.16
RXCLK
Note 5.15 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.16 Timing was designed for system load between 10 pf and 25 pf.
Datasheet
tclkp
tclkh tclkl
TXCLK
tsu thold tsu thold thold
TXD[3:0]
thold tsu
TXEN
Figure 5.5 MII Transmit Timing
tsu TXD[3:0], TXEN setup time to rising edge of 12.0 ns Note 5.18
TXCLK
thold TXD[3:0], TXEN hold time after rising edge of 0 ns Note 5.18
TXCLK
Note 5.17 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.18 Timing was designed for system load between 10 pf and 25 pf.
Datasheet
tclkp
tclkh tclkl
CLKIN
(REF_CLK)
toval toval tohold
RXD[1:0],
RXER
tohold toval
CRS_DV
tsu tihold tsu tihold tihold
TXD[1:0]
tihold tsu
TXEN
Figure 5.6 RMII Timing
toval RXD[1:0], RXER, CRS_DV output valid from 14.0 ns Note 5.19
rising edge of CLKIN
tohold RXD[1:0], RXER, CRS_DV output hold from 3.0 ns Note 5.19
rising edge of CLKIN
tsu TXD[1:0], TXEN setup time to rising edge of 4.0 ns Note 5.19
CLKIN
tihold TXD[1:0], TXEN input hold time after rising edge 1.5 ns Note 5.19
of CLKIN
Note 5.19 Timing was designed for system load between 10 pf and 25 pf.
Datasheet
tclkp
tclkh tclkl
MDC
tval tohold
tohold
MDIO
(Data-Out)
tsu tihold
MDIO
(Data-In)
tval MDIO (read from PHY) output valid from rising 300 ns
edge of MDC
Datasheet
Note 5.20 The maximum allowable values for Frequency Tolerance and Frequency Stability are
application dependant. Since any particular application must meet the IEEE ±50 PPM Total
PPM Budget, the combination of these two values must be approximately ±45 PPM
(allowing for aging).
Note 5.22 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
±100 PPM.
Note 5.23 0oC for extended commercial version, -40oC for industrial version.
Note 5.24 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are
required to accurately calculate the value of the two external load capacitors. The total load
capacitance must be equivalent to what the crystal expects to see in the circuit so that the
crystal oscillator will operate at 25.000 MHz.
Datasheet
Datasheet
Datasheet
Datasheet
Rev. 1.4 Section 4.2.2, "Basic Status Updated definitions of bits 10:8.
(08-23-12) Register," on page 53
Rev. 1.3 Company disclaimer on Removed company address and phone numbers.
(03-12-12) page 2
Table 2.7, “Power Pins,” on Updated VDDCR pin note to include requirement
page 16 of 1uF and 470pF decoupling capacitors in parallel
to ground on the VDDCR pin.
Figure 3.13 Power Supply Updated diagrams to include 1uF and 470pF
Diagram (1.2V Supplied by decoupling capacitors on the VDDCR pin.
Internal Regulator) on
page 46 and Figure 3.13
Power Supply Diagram
(1.2V Supplied by Internal
Regulator) on page 46
Table 4.2.9, “Special Modes Updated MIIMODE bit description and added note:
Register,” on page 60 “When writing to this register the default value of
this bit must always be written back.”
Rev. 1.2 (11-10-10) Section 5.5.5, "RMII Updated diagrams and tables to include RXER.
Interface Timing," on
page 75
Datasheet
Section 5.5.4, "MII Interface Corrected signal names on MII timing diagrams
Timing," on page 73 and tables. Updated Table 5.8 tval max to 28.0 ns.
Updated Table 5.9 tsu and thold values to 12.0 ns
and 0 ns, respectively.
Table 5.7, “Power-On nRST Updated todad description: “Output drive after
& Configuration Strap nRST deassertion”
Timing Values,” on page 72
Rev. 1.1 (04-09-10) Section 5.1, "Absolute Modified “HBM ESD Performance by adding “per
Maximum Ratings*" JEDEC JESD22-A114” and changed “+/-5kV” to
“Class 3A”
Table 5.2, “Non-Variable I/O Corrected O12 VOH minimum value to “VDD2A -
Buffer Characteristics,” on 0.4”
page 68 Corrected ICLK VILI maximum value to “0.35”
Corrected ICLK VIHI maximum value to “VDD2A +
0.4”
Section 5.2, "Operating Added note: “Do not drive input signals without
Conditions**," on page 67 power supplied to the device.”
Table 5.9, “MII Transmit Corrected tsu and thold minimum values to 10 ns.
Timing Values,” on page 74
Rev. 1.0 (12-09-09) Document reworked for clarity and consistency with other SMSC documentation.