Uninterruptible Power Supply Reference Design With A PIC-Www - Circuitdiagram

M PICREF-1
Uninterruptible Power Supply Reference Design
INTRODUCTION PICREF-1 OVERVIEW

At times, power from a wall socket is neither clean nor The Microchip Technology PICREF-1 UPS Reference
uninterruptible. Many abnormalities such as blackouts, Design offers a ready-made uninterruptible power sup-
brownouts, spikes, surges, and noise can occur. Under ply solution with the flexibility of a microcontroller.
the best conditions, power interruptions can be an The PIC17C43 microcontroller handles all the control
inconvenience. At their worst, they can cause loss of of the UPS system. The PIC17C43 is unique because
data in computer systems or damage to electronic it provides a high performance and low cost solution not
equipment. found in other microcontrollers.
It is the function of an Uninterruptible Power Supply The PIC17C43 PWM controls an inverter whose out-
(UPS) to act as a buffer and provide clean, reliable put, when filtered, results in a sinusoidal AC output
power to vulnerable electronic equipment. The basic waveform. Fault signaling can be initiated internal or
concept of a UPS is to store energy during normal external to the PIC17C43 depending on the type of
operation (through battery charging) and release fault. A fault will disable the entire inverter. The output
energy (through DC to AC conversion) during a power voltage and current will be monitored by the PIC17C43
failure. to make adjustments “real-time” to correct for DC offset
UPS systems are traditionally designed using analog and load changes.
components. Today these systems can integrate a The PIC17C43 controls all module synchronization as
microcontroller with AC sine wave generation, offering well as inverter control and feedback. The PIC17C43
the many benefits listed below. uses zero crossing for synchronization of input voltage/
PIC17C43 Microcontroller Benefits phase to output voltage/phase. All internal module syn-
chronization is handled by the PIC17C43.
• High Quality Sine Wave - High throughput allows
for high quality output The control algorithms and software are written in C for
• Flexibility - core control features and operations maintainability and transportability.
can be changed with software modifications only PICREF-1 Key Features
• Transportability of Design • True UPS Topology
• Variable Loop Response • True Sinusoidal Output
• Digital Filtering • Point-to-Point Output Correction
• Parts and Complexity Reduction • 1400 VA Rating
• Peripheral Integration • 120/240 V Input
• Ease of Interfacing
• Testability
• Time to Market
Information contained in this publication is intended through suggestion only and may be superseded by updates. No
representation or warranty is given and no liability is assumed by Microchip Technology Inc. with respect to the accu-
racy or use of such information, or infringement of patents arising from such use or otherwise. It is the responsibility
of each user to ensure that each UPS is adequately designed, safe, and compatible with all conditions encountered
during its use. “Typical” parameters can and do vary in different applications. All operating parameters, including
“Typicals”, must be validated for each customer application by the customer's technical experts. Use of Microchip's
products as critical components in life support systems is not authorized except with express written approval by
Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
 1997 Microchip Technology Inc. DS30450C-page 1

PICREF-1
TABLE OF CONTENTS
System Overview .......................................................................................................................................3
Hardware Overview ...................................................................................................................................6
Software Overview .....................................................................................................................................9
Test Results .............................................................................................................................................13
Design Background .................................................................................................................................15
Design Modifications ...............................................................................................................................17
Appendix A: System Specifications .......................................................................................................19
Appendix B: Schematics..........................................................................................................................19
Appendix C: Software Listing..................................................................................................................37
Appendix D: PCB Layout & Fab Drawing ...............................................................................................41
Appendix E: Bill Of Materials (BOM).......................................................................................................45
Appendix F: UPS Demo Unit....................................................................................................................53
ACKNOWLEDGMENTS
Project Lead Engineer:
Robert Schreiber, Microchip Technology
Reference Design Documentation:
Beth McLoughlin, Microchip Technology
System and Code Development:
Airborne Power (Consultants)
Guy Gazia (guyg@airbornepower.com),
David Karipides (davek@airbornepower.com),
Terry Allinder
DS30450C-page 2  1997 Microchip Technology Inc.

PICREF-1
SYSTEM OVERVIEW The OR’d DC bus voltage is fed into the free running
chopper which both isolates the DC bus from the
The power flow for the PICREF-1 system is shown in H-Bridge inverter and doubles the DC voltage for the
Figure 1. The Uninterruptible Power Supply (UPS) is inverter to operate at 120 or 240 volts. The output of the
either supplying power based on the input power, if the chopper is filtered to remove switching noise and then
unit is plugged in, or based on the batteries. fed into the H-Bridge.
Power Flow The PIC17C43 microcontroller controls the inverter by
When available, the input power is filtered for common driving the H-bridge through Hardware Protection cir-
mode noise and is protected from surges/spikes by cuitry and Insulated Gated Bipolar Transistor (IGBT)
input power protection circuitry. The power then goes drivers. The output of the H-bridge is filtered and drives
into the power factor correction (PFC) module which the load with an AC sine wave that is synchronized to
forces the input current to be sinusoidal so that power the input AC voltage.
utilization is more efficient. The PFC module also recti- An A/D converter provides feedback to the PIC17C43
fies the input AC power to produce voltage-regulated for output monitoring.
DC power which is used by the rest of the functional All module synchronization, control, and fault detection
modules. are handled through the PIC17C43.
This rectified AC power is OR’d through diodes with the
DC voltage generated from the battery boost circuit.
The battery boost voltage is set slightly lower than the
rectified AC input voltage so that, under normal condi-
tions, the rectified AC input power provides power to
the load. Once the voltage from the rectified AC input
source drops below the battery boost DC voltage, the
power is drawn from the battery boost module. In this
mode the battery charger is turned off so as not to
cause an additional load on the battery (i.e., so the bat-
tery is not charging itself).
FIGURE 1: PICREF-1 UNINTERRUPTIBLE POWER SUPPLY (UPS) BLOCK DIAGRAM

Power Flow
Current Sense
Charge Control A/D
Voltage Sense
BBC
Sync
Battery & Battery
Battery Boost Enable
Charger Circuit
PWM Hardware
PIC17C43
Pos_Neg Protection
Fault
Zero Inverter
Crossing Fault
Inverter
PFC Control
Sync IGBT
Input Power Drivers
120/240 V Output Power
50/60 Hz Chopper 120/240 V
Sync 50/60 Hz
Input Power
Factor Free H-Bridge Output
Power Running (Inverter) Filtering
Protection Correction &
Rectification Chopper

PICREF-1
Inverter Operation As long as none of the out-of-saturation signals
(Q9/Q10/Q11/Q12 OC Alarm) are LOW, the power
The H-bridge circuit works by generating the separate
stage can be enabled. When the PIC17C43 is first pow-
positive and negative cycles needed for sine wave gen-
ered up, the ENABLE line (PORTC, bit0) will be in a
eration. The PIC17C43 controls all signals to the hard-
high impedance state. A pull-down resistor keeps the
ware protection circuitry and IGBT drivers and thus
ENABLE line held LOW so that any spurious signals
controls the generation of the sine wave (Figure 2).
which may be generated while the system is initializing
Software Fault / No Enable will not drive the H-Bridge. If any of the out-of-satura-
Driving the FAULT HIGH will disable the inverter’s tion signals go LOW, the FAULT signal goes HIGH,
power stage. reporting to the PIC17C43 that an external fault
occurred. This will disable the H-Bridge.
Hardware Fault
The inverter may be re-enabled by cycling the ENABLE
The hardware protection logic automatically disables line LOW and then HIGH to reset the flip-flop and allow
the inverter’s power stage in the event any of the IGBT’s the PIC17C43 to drive the H-Bridge again.
have gone out of saturation, i.e., an external short was
placed on the H-Bridge which was so severe that an The PIC17C43 microcontroller and hardware protec-
appreciable voltage was developed across one of the tion circuits are found on the PICREF-1 Inverter Control
switches that was on. This feature prevents a short Card. IGBT driver circuits are found on the Inverter
from immediately destroying the switching devices. Drive Card. Schematics for these cards can be found in
Appendix B.
FIGURE 2: INVERTER OPERATION
Q9 Drive Q9_G
Q10 Drive Q10_G
ENABLE
Q11 Drive Q11_G
PWM
PIC17C43 Hardware Q12 Drive IGBT Q12_G
POS_NEG Protection Drivers
Q9 OC Alarm Q9_C
FAULT
Q10 OC Alarm Q10_C
Q11 OC Alarm Q11_C
Q12 OC Alarm Q12_C
DCBus
Simplified
Q9_C Q10_C H-Bridge
(Inverter)
Q9_G Q9 Q10_G Q10 AC Output
L1
AC HI
Output
Filtering
L2 AC LO
Q11_C Q12_C
Q11_G Q11 Q12_G Q12

PICREF-1
Normal Operation The transistor drive signals are fed into the IGBT Drive
circuits (Inverter Drive Card) to determine the state (ON
In normal operation (FAULT is LOW and ENABLE is
or OFF) of each transistor. A drive signal of ‘1’ corre-
HIGH), the states of Q9, Q10, Q11 and Q12 are deter-
sponds to an IGBT being OFF, and a drive signal of ‘0’
mined by POS_NEG and PWM signals. These signals
corresponds to an IGBT being ON.
pass through steering logic which produce transistor
(QX) drive signals (see Inverter Control Card schemat- From Table 1, when the POS_NEG signal is 0, Q10 is
ics in Appendix B). held ON, Q12 is held OFF, and Q9,Q11 are modulated
in a complementary fashion with the PWM signal. Sim-
The steering logic causes the IGBT pairs Q9,Q11 and
ilarly, when POS_NEG is 1, Q9 is held ON, Q11 is held
Q10,Q12 to be held in the OFF state for one microsec-
OFF, and Q10,Q12 are modulated in a complementary
ond before allowing them to switch ON. This prevents
fashion with the PWM signal. Therefore, the differential
shoot-through from occurring during changes of states
output signal from the H-Bridge has an average value
from the PWM. This is necessary because of the rela-
proportional to the duty cycle of the PWM signal and a
tively slow turn off times for the IGBTs. This prevents
polarity set by the POS_NEG signal. The output filter
complementary pairs from being ON at the same time.
smooths this pulse train and all that remains is the aver-
Table 1 describes the drive values for different input val- age value of the PWM signal (Figure 3).
ues of POS_NEG and PWM.
To understand how the PIC17C43 determines the mod-
TABLE 1 INVERTER CONTROL SIGNALS ulation for the H-Bridge transistors, please see the sec-
Q9 Q10 Q11 Q12
tion Software Overview.
POS_NEG PWM
Drive Drive Drive Drive
0 0 0 0 1 1
0 1 1 0 0 1
1 0 0 0 1 1
1 1 0 1 1 0
QX Drive = 1 -> transistor QX is OFF
QX Drive = 0 -> transistor QX is ON
FIGURE 3: INVERTER WAVEFORMS
AC Output
AC HI/LO
POS_NEG
PWM

PICREF-1
HARDWARE OVERVIEW Use of the PIC17C43 means the availability of variable
loop response, or software that can adjust to different
This section describes the PICREF-1 hardware and loads. Digital filtering is another microcontroller benefit
how it functions in the UPS system. Hardware detail as it reduces components that would be necessary for
(schematics) may be found in Appendix B. analog filtering.
Microcontroller Also, the high level of peripheral integration (from the
A typical analog UPS solution is shown in Figure 5. By PIC17C43’s USART and PWM modules) further
using a microcontroller, this design can be greatly sim- reduces the complexity of the design. This reduces the
plified. That is, the functions of the DC offset amp, error development time and the components needed.
amp and PWM drive can be implemented in software. Converting from analog to digital also enhances the
Therefore, modifications to the design are made repeatability, manufacturability, and flexibility of the
through code changes, not component changes. design. Product test is made easier as well, and
In addition, there is no need to generate an external time-to-market is reduced.
sine wave reference; this is embedded in the microcon-
troller. FIGURE 4: PIC17C43 PINOUT
The PIC17C43 is the heart of PICREF-1 (Figure 4). PDIP, CERDIP, Windowed CERDIP
The high performance of the Harvard architecture gives
the user the throughput needed for high quality sine VDD 1 40 RD0/AD8
RC0/AD0 2 39 RD1/AD9
wave generation. The single-cycle multiply means RC1/AD1 3 38 RD2/AD10
faster program execution and response to waveform RC2/AD2 4 37 RD3/AD11
RC3/AD3 5 36 RD4/AD12
changes. Only 8 bits of the 10-bit PWM is needed to RC4/AD4 6 35 RD5/AD13
RC5/AD5 7 34 RD6/AD14
resolve a high quality output waveform.
PIC17C4X
RC6/AD6 8 33 RD7/AD15
RC7/AD7 9 32 MCLR/VPP
In addition, using a PIC17C43 microcontroller enables VSS 10 31 VSS
RB0/CAP1 11 30 RE0/ALE
the customer to use the same core control for multiple RB1/CAP2 12 29 RE1/OE
products (transportability) and add further enhance- RB2/PWM1 13 28 RE2/WR
RB3/PWM2 14 27 TEST
ments through software changes (flexibility). RB4/TCLK12 15 26 RA0/INT
RB5/TCLK3 16 25 RA1/T0CKI
RB6 17 24 RA2
RB7 18 23 RA3
OSC1/CLKIN 19 22 RA4/RX/DT
OSC2/CLKOUT 20 21 RA5/TX/CK
FIGURE 5: TYPICAL ANALOG SOLUTION

H-BRIDGE
+200Vdc
Q1 Q2
DRIVE A DRIVE B
DC DC-DC AC
Bus Converter Out
Q3 Q4
DRIVE B DRIVE A
DIFF
DC OFFSET AMP
CORRECTION
+ +V
+
-
-
+Vcc ERROR AMP -V
+
DRIVE A
PWM -
DRIVE
DRIVE B
-Vcc
SINE WAVE REFERENCE

PICREF-1
Input Power Monitoring By their nature, switched mode power supplies have a
reduced power factor. This is due to the fact that the
The input power is monitored to determine the value of
current is delivered in narrow pulses at the peak of the
the output waveform. So, if 120V is input, 120V will be
voltage sine wave. This increases the RMS value of
output, and if 240V is input, 240V will be output.
current, which limits the current that can be drawn from
The 120V/240V relay (power switch) shown in the a typical wall socket. Therefore, with power factor cor-
schematics (Appendix B) has not been implemented as rection, available power increases and distortion
this would have been part of the software “housekeep- decreases.
ing” functions.
The example below shows how PFC can increase the
Input Power Protection ability to drive loads from a typical outlet.
The input filtering circuit provides input protection for
the UPS and isolation from the power source. The main EXAMPLE 1: POWER FACTOR
components of the circuit are the MOV, which sup- CORRECTION USAGE
presses surges/spikes, and the input power line filter. The power source is 120 V ± - 10% at 20 Amps with
The common mode filter prevents UPS switching noise a 20% derating.
from getting back onto the main power lines.
The input to the UPS PFC’d to 0.95.
FIGURE 6: INPUT FILTERING CIRCUIT The efficiency of the UPS is 70%.
The load is a workstation which is rated at 900
Watts with a PF of 0.65.
Power Metal
from Oxide Common Input Power Can the load be driven with a 1400 VA rated UPS and
power Varister mode 120/240 V
line filter a standard outlet (20A)?
(MOV)
Load Power:
PF = (Pout Watts / Pout VA)
EMI/RFI filtering and spike/surge protection are very
0.65 = 900 W / Pout VA
important in a robust UPS design. Input filtering is
heavily dependent upon design specifics (shielding, Pout VA = 1384 VA
grounding, layout, etc.), so following sound design prin- Input Power:
ciples and testing is the only way to verify actual perfor-
mance. Pin Watts = Pout Watts / Efficiency
Pin Watts = 900 Watts / 0.70
Power Factor Correction & Rectification
Pin Watts = 1286 Watts
This portion of the PICREF-1 has not been imple-
mented. However, the theory of how power factor cor-
rection circuitry would function in a UPS is discussed Pin Watts = Vin (Min) * Iin * PFC
here, and a general PFC schematic is given in
Appendix B. 1286 Watts = 108 V * Iin * 0.95
The output from the input filtering circuit feeds into the Iin = 12.5 Amps
power factor correction (PFC) circuit. The PFC circuit Available Current:
produces a regulated DC bus by means of a full wave 20 Amps x 80% = 16 Amps
rectifier which feeds a boost converter. The PFC con-
trol system consists of two feedback loops. A current (VA rating is volts * amps. Power drain is watts. PF
loop forces the input current to match the waveshape is Watts/VA and is typically 0.6-0.7 for computers.)
and phase of the input voltage, thus producing a high From the output power perspective, the load power for
power factor. The secondary outer loop adjusts the the workstation is below 1400 VA, so the device can be
magnitude of the input current so that the output DC driven. From the input power perspective, the power
voltage is regulated. This circuit also detects the mag- need is 1286 watts, which translates into 12.5 Amps of
nitude of the input voltage. This is used to set the output current at the minimum input voltage. The derating of
voltage magnitude. the outlet is 16 Amps, so the outlet is capable of provid-
Synchronization of the PFC is derived from the micro- ing the current needed to supply the UPS. However, if
controller. the PF at the input would have been 0.65 instead of
0.95, the current required would have been 18.3 Amps
PFC comes into play when designing for high power which would violate the derating conditions.
requirement applications. In discussing power require-
ments for a system, care must be taken in defining
terms. In a DC system, the DC source supplies real
current to the real load. The power for this system is
defined in watts (volts x amps).

PICREF-1
Battery, Battery Charger and yields either 120V or 240V AC output levels. The output
Battery Boost Circuit is rectified to form a square wave with a duty cycle of
90-92%. This is done to minimize the ripple and stress
This portion of the PICREF-1 has not been imple-
on components. A snubber circuit is in place to bleed
mented. However, the theory of how a battery back-up
current from the parasitic capacitance of the inductor
circuit (battery, battery charger and battery boost)
and voltage spikes which occur during the off period of
would function in a UPS is given here.
the duty cycle.
The battery is charged from input power once the bus
Synchronization of the chopper circuitry is handled
voltage exceeds 40V DC. The input power turns off
through the PIC17C43. In the event of a loss of the syn-
when the bus voltage drops below 40V DC. The battery
chronization signal, the chopper has an internal syn-
charger circuit turns off when the battery power is
chronization source.
enabled.
Inverter and Output Filtering
The 48V DC battery bus is stepped up to 360V through
the battery boost (push-pull) circuit. The battery boost The input to the inverter is the free running chopper
voltage is slightly less than the battery charger bus volt- rectified square wave. After appropriate DC Bus filter-
age created from the input power source. This is done ing, this waveform is fed into the H-bridge circuit
so that the power source under normal operation is the (Figure 2). The H-Bridge is under the control of a
input power. A UC3825 PWM controller is used as part PIC17C43 running at 25MHz.
of the battery boost control circuitry due to its inte- The output of the H-Bridge (differentially) consists of a
grated drive protection and low cost. waveform of rectangular pulses with a constant fre-
The UC3825 is optimized for high frequency switched quency of 25kHz and a duty cycle that varies to corre-
mode power supply applications. Particular care was spond with the absolute value of the desired output sine
given to minimizing propagation delays through the wave. Output filtering produces the smooth sine wave.
comparators and logic circuitry while maximizing band- There are snubber circuits on Q9 and Q10 of the
width and slew rate of the error amplifier. This controller H-Bridge which discharge spikes back onto the DC bus
is designed for use in either current mode or voltage to minimize component stress.
mode systems with the capability for input voltage
feed-forward. The inductors L1 and L2 suppress ripple and additional
inductors, capacitors and discretes provide further fil-
Protection circuitry includes a current limit comparator tering of the output voltage.
with a 1V threshold, a TTL compatible shutdown port,
and a soft start pin which will double as maximum duty Hardware Protection and IGBT Drivers
cycle clamp. The logic is fully latched to provide jitter The PIC17C43 controls the inverter through the hard-
free operation and prohibit multiple pulses at an output. ware protection circuitry and the drivers for the
An under-voltage lockout section with 800mV of hyster- H-Bridge. Insulated Gate Bipolar Transistors (IGBTs)
esis assures low start up current. During under voltage are used for the H-Bridge rather than MOSFETs due to
lockout, the outputs are high impedance. their lower ON resistance. Although IGBTs have a
This device features totem pole outputs designed to slower turn on time than MOSFETs, the relatively low
source and sink high peak currents from capacitive frequency of operation (PWM frequency = 25kHz)
loads, such as the gate of a power MOSFET. The ON makes this property irrelevant.
state is designed as a high level. Inverter control signals connect the PIC17C43 and the
DC Bus inverter through the hardware protection circuit and the
IGBT drivers. These control signals are: ENABLE,
The 380V DC bus is generated either from the primary FAULT, POS_NEG and PWM. See System Overview -
power source, under normal operating conditions, or Inverter Operation for a detailed discussion of how
the battery boost circuit, under “no power” conditions. PIC17C43 signals control the H-Bridge inverter.
The DC bus is filtered for noise and spikes at the input
to the free running chopper. ENABLE will enable or disable all drive capability to the
H-bridge. This is a local enable.
Free Running Chopper
A FAULT will override the ENABLE, but can be reset in
The free running chopper generates a square wave at the software so that a hardware retry may be
twice the magnitude of the DC bus. The frequency of attempted.
the chopper is 100kHz and the duty cycle of the square
A FAULT can also be generated by the H-bridge cir-
wave is approximately 45%. A current transformer is
cuitry directly in order to shut done the IGBTs as
used for sensing the current. A UC3825 PWM control-
quickly as possible (Hardware, or HW, FAULT). In the
ler is used due to its high PWM frequency and low cost.
event of a catastrophic failure, H-bridge hardware can
The output of the free running chopper is fed into a respond faster than the PIC17C43 software. This will
transformer which generates the output voltage based prevent damage to the IGBTs.
on the magnitude of the source voltage. A relay selects
the secondaries of a center-tapped transformer which

PICREF-1
The POS_NEG signal controls the H-Bridge modula- The flow diagram for the software is shown in Figure 7.
tion for either positive or negative wave generation. The main software function looks for the zero crossing
The modulation scheme (using PWM) is inherent in the point and calculates the input frequency. Based on the
hardware protection circuitry. The hardware protection calculation, the appropriate look-up table is indexed.
also allows for a dead time on the IGBTs during state The SW checks for violation of maximum conditions
transitions. and sets the appropriate flags. The loop continues
indefinitely based on the zero crossing detect.
Output Monitoring Using A/D Converter
Information on how the look-up table is generated is
Feedback of the output AC sine wave is accomplished provided in the first subsection.
through the use of an external 8-bit A/D converter. An
The interrupt is set up to occur periodically based on
8-bit A/D is considered adequate based on the speed
the output frequency of the wave. The interrupt period
of operation of the PIC17C43 and the resolution
is initialized so that 32 interrupts occur within the
needed for 120V.
half-wave period. During the interrupt, there must be
Both the output current and output voltage are moni- sufficient margin to perform two A/D conversions (cur-
tored through the A/D converter. The voltage is sensed rent and voltage), calculate offsets and errors, and
at the output stage and is fed to the A/D through an op adjust the output duty cycle. The interrupt flow diagram
amp circuit. The voltage is attenuated to the A/D input is shown in Figure 8.
range. An op amp is used so that any DC offset compo-
Adjusting the AC output waveform requires adjusting
nents remain with the signal and can be measured. The
the PWM that controls the inverter circuitry (H-Bridge).
current is monitored through a current transformer.
To do this, compensator coefficients need to be deter-
The current and voltage inputs are used to correct for mined. That is, in pseudocode:
any errors in the magnitude of the output wave. The
X = (Output_V) - Vref;
output voltage is sampled 32 times per half-wave which Y = c * Yold + d(X + Xold);
results in an output wave with 1.5% distortion (resistive Yold = Y;
load with feedback) while running the PIC17C43 at 25 Xold = X;
MHz. Where Y = output; X = error.
Power factor correction also makes use of the feedback How to calculate the coefficients c and d for a sin-
signals, as well as zero crossing. Information about the gle-pole compensator is shown in the second subsec-
output wave is compared with zero crossing information.
tion about the input wave to provide input/output syn-
A listing of all UPS PIC17C43 software is shown in
chronization. The zero crossing detect signal comes
Appendix C.
directly from the input wave and is used to indicate if a
zero crossing point has been detected. The PIC17C43
then measures from point-to-point on the zero crossing
to calculate the frequency of the input wave. This data
is used to generate a sine wave of the same frequency
through internal look-up tables.
Note: Power factor correction has not been
implemented in PICREF1.
SOFTWARE OVERVIEW
The PIC17C43 embedded software controls the opera-
tion of the AC sine wave generation. It is imperative that
the loop response be fast enough to minimize distortion
on the output wave. Therefore, the throughput of the
microcontroller is a critical parameter.
The architecture of the PIC17C43 provides enough
throughput to execute the control algorithm with a min-
imum of distortion. The architecture is efficient enough
to support the device running at 33 MHz (121 ns
instruction cycle), so can easily support 25 MHz (160
ns instruction cycle) to meet the distortion requirement.
The system described in this paper has a measured
total distortion of 3% (resistive load) without feedback
and 1.5% THD with feedback. The load regulation with
feedback was measured to be 0.8%.

PICREF-1
FIGURE 7: MAIN PROGRAM FLOW
Zero Crossing N
Detected?
Calculate Input Power

Frequency
50Hz or 60Hz?
Set pointer to 50Hz Set pointer to 60Hz

Table Table
N I > Imax or
V > Vmax?
N
Inverter Enabled?
Disable Y
PWM
Zero Crossing N
Disable Detected?
Inits
Y
Set Flags Set Flags Set Flags
Shaded objects indicate provisional sections.

Power factor correction not implemented.

PICREF-1
FIGURE 8: INTERRUPT HANDLER FLOW Look-Up Table
The sinusoidal reference table for the DSP-based
inverter is generated as follows:
Preset Timer for Sampling Rate
1. Choose Vp such that this number corresponds
with the desired output voltage of the inverter.
Example: If the desired output voltage is 120V
and the A/D converter used to sample the output
voltage has a gain of 1.5 counts per output volt,
Read Voltage
then:
Vp = 1.5(120 2)
and Vp would be equal to 254.6, or 255 rounded to
Read Current the nearest integer.
The external circuitry interfacing the A/D converter
to the output of the inverter should scale the input
voltage to the A/D such that the peak of the desired
output voltage should correspond to almost a full
Calculate DC Offset count on the A/D.
2. The table is generated from the following equa-
tion with k = 0.... N/2 - 1 and N = the number of
samples per cycle.
Calculate DC Error
2π k
Vref = Vp sin ----------
N
Example: For the Vp of the previous example and
N = 64 samples per cycle, this yields the following
Calculate Duty Cycle based on table entries. Note that only 32 entries are gener-
DCold, Error, Errorold ated as the negative-going halfwave may be gen-
erated from the negative of the first 32.
Vref = 0, 25, 50, 74, 98, 120, 142, 162, 180, 197,
212, 225, 235, 244, 250, 254, 255, 254, 250, 244,
235, 225, 212, 197, 180, 162, 142, 120, 98, 74, 50,
Return
25.

PICREF-1
Calculating the Compensator Coefficients DC Offset Correction
A convenient way of determining the coefficients for an DC Offset is corrected for by taking the DC offset from
IIR (Infinite Impulse Response) compensator from an a single cycle. This offset is integrated over time and
analog transfer function in the Laplace (s) domain is the used to correct the output wave. The DC offset is added
Bilinear z-transform. The following example illustrates to the sine wave to determine the point-to-point magni-
the technique for a compensator with a single pole. tude. This is then compared to the reference sine wave
to determine DC offset correction.
EXAMPLE 1: SINGLE-POLE
COMPENSATOR
An inverter is designed that requires a compensator
of the form:
a
H ( s ) = ------------- (1)
s+b
The first step is to normalize H(s) and make note of

the cutoff frequency (cutoff frequency = b):
(a ⁄ b )b
H ' ( s ) = ------------------- (2)
s+1
Choose a sampling frequency at least 32 times the

desired output frequency (i.e., 1.92kHz for a 60 Hz
inverter). If the desired gain crossover frequency of
the loop response is more than 1/4 of the chosen
sampling rate, a higher rate equal to at least 4 times
the gain crossover frequency should be used.
Make the following substitution in (1):
z–1
s = α ------------- (3)
z +1
Where α = cot(b * T/2).
Thus,
a(z + 1)
H (z ) = ----------------------------------------------------------- (4)
αb ( z ( α + 1 ) – ( α – 1 ) )
The last step is to determine the difference equation
that will yield the transfer function of (4).
y (z ) = H ( z ) • x ( z )
y (z ) [ αb ( z ( α + 1 ) – ( α – 1 ) ) ] = a ( z + 1 ) x (z ) (5)
Multiplying both sides by (1/z) and using the fact that;
Z [ y [ k – n ] ] = z ( –n ) Z [ y [ k ] ] (6)
yields the desired difference equation.
α–1 a
y [ k ] = -------------y [ k – 1 ] + ------------------------------ ( x [ k ] + x [ k – 1 ] )
α+1 2(α + 1)(b )
(7)

PICREF-1
TEST RESULTS The example output waveform is a stepped-down ver-
sions of the actual output waveform, available for oscil-
No Load Conditions loscope display by placing a probe on the UPS “Load
Figure 9 is an example output waveform under no-load, Monitor” BNC connector.
no feedback conditions.
FIGURE 9: AC OUTPUT - NO LOAD, NO FEEDBACK
Load Conditions
Figure 10 is an example output waveform under load, Figure 11 is an example output waveform under load,
no feedback. The load used was resistive, drawing 8.6 with feedback. The load used was resistive and induc-
Amps. tive, drawing 4 Amps.
This example output waveform is a stepped-down ver- This example output waveform is the actual UPS output
sion of the actual output waveform, available for oscillo- waveform.
scope display by placing a probe on the UPS “Load
Monitor” BNC connector.
FIGURE 10: AC OUTPUT - RESISTIVE LOAD, NO FEEDBACK

PICREF-1
FIGURE 11: AC OUTPUT - RESISTIVE AND INDUCTIVE LOAD WITH FEEDBACK

PICREF-1
DESIGN BACKGROUND For instance, most appliances are always on, thus the
power used by the appliance is the RMS value of the
An example of how to implement a UPS system using sine wave, which is approximately 120 volts. However,
a microcontroller has been described in the previous equipment such as computers use peak voltage val-
sections. However, if a customer wishes to change part ues, which are approximately 170 volts.
or all of this reference design, then understanding the
When a square wave output is used to supply power to
reasons why the design was developed as it was must
computer equipment, the RMS and peak values are
be understood.
equivalent, thus stressing some loads and under-sup-
When designing a UPS system, there are three items plying others. So the best output to provide electrical
that must be considered: cost vs. performance, output equipment is the output that they are designed to oper-
waveform and topology. ate with - a sine wave.
Cost vs. Performance The speed of the PIC17C43 allows this reference
A UPS system has to be reliable. Money saved on fea- design to produce a sinusoidal output AC waveform.
tures or performance can be overshadowed by the cost This causes less stress on all electrical equipment.
associated with data loss or component failure. So it is Actual output waveform graphics are provided in the
important to develop a cost effective solution which sat- section Test Results.
isfies both end user price sensitivity and design robust- Topology
ness.
To an end user, the function of a UPS system is much
By incorporating a PIC17C43 microcontroller into the more important than form. Despite the many variations
UPS design, the number of necessary components is of UPS systems on the market, they can be boiled
reduced, thus reducing cost. Also, PIC17C43 peripher- down into two major topologies: Off-line and On-line
als and speed enhance the performance of the UPS UPS.
system. Software control of the PIC17C43, and thus
Off-Line UPS
the UPS, allows for ease of modification and addition of
special features. So in terms of cost vs. performance, The first topology is known as off-line or standby, mean-
the PIC17C43 offers a win-win solution. ing that the inverter is normally off-line. A block diagram
of an off-line UPS is shown in Figure 12. (The solid line
Other components of this reference design were cho-
represents the primary power path and the dashed line
sen considering cost and performance. However, there
represents the secondary or back-up power path.)
are other design options which are discussed in the
section Design Modifications. In normal operation, the output power comes from the
input power source. This implies that there is a transfer
Output Waveform
time in switching the inverter on-line during a power
Some UPS designs use a square wave output instead interruption. If this transfer time is too great, there will
of a sine wave. This makes the system cheaper to probe a less than smooth transition for the load on the
duce. But is this type of waveform really acceptable? UPS. This could lead to the same problems that the
Electrical equipment uses power delivered in the form UPS was designed to avoid.
of a sine wave from local utility companies. When con- The advantage of this topology lies in the fact that the
sidering alternative waveforms, how differing loads rely stress on the inverter is decreased due to the inverter
on different parts of the standard power company being turned off during normal operation. However,
waveform must be examined. since the inverter only runs during power interruptions,
this feature lends itself to latent failures when back-up
power is needed the most.
FIGURE 12: OFF-LINE UPS
Battery Inverter
Charger Battery (DC to AC)
AC Output
Transfer
Switch
AC Input

PICREF-1
On-Line UPS
The other major topology is the on-line or true UPS. As switched back to primary power through the bypass
the name implies, the inverter is always on-line. A block switch. This allows for the failed condition to be cor-
diagram of the on-line UPS is shown in Figure 13. rected while AC input power is still good.
At start-up the UPS is in bypass mode until the inverter The one drawback to the on-line topology is that the
is running and synchronized with the input power inverter is always on-line. This would imply that the “life”
source. Control is then transferred to the inverter. The of this topology would be shorter than an off-line UPS.
inverter remains on-line during normal operation and However, the life of a UPS in practice has more to do
during power failure operation until the battery is with the robustness of the design than the topology
exhausted. During an inverter failure, the power is used.
The topology used for this reference design is the true
(on-line) UPS.
FIGURE 13: ON-LINE UPS
Battery
Charger Battery
Inverter
AC Input (DC to AC)
AC Output
Rectifier
(AC to DC) Bypass
Switch

PICREF-1
DESIGN MODIFICATIONS FIGURE 14: PIC16C72 PINOUT
This reference design is for guidance only, and it is PDIP, SOIC, SSOP
anticipated that customers will modify parts of it. With MCLR/VPP 1 28 RB7
this in mind, this section suggests modifications that RA0/AN0 2 27 RB6
the customer may wish to make to the design. RA1/AN1 3 26 RB5
RA2/AN2 4 25 RB4
• The PIC16/17 family of microcontrollers offers a RA3/AN3/VREF 5
PIC16C72
24 RB3
wide variety of options for a UPS design from the RA4/T0CKI 6 23 RB2
PIC16C72 to the PIC17C756. The PIC16C72, RA5/AN4/SS 7 22 RB1
PIC16C73A, PIC16C74A, PIC17C43, and VSS 8 21 RB0/INT
OSC1/CLKIN 9 20 VDD
PIC17C756 all have the processing throughput to
OSC2/CLKOUT 10 19 VSS
generate the sine wave described in this docu- RC0/T1OSO/T1CKI 11 18 RC7
mentation. RC1/T1OSI 12 17 RC6
For this design (PIC17C43), the frame rate for 64 RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
point sampling of a 60Hz sinewave is 260 usec.
The feedback code is approximately 200 instruc-
tions, which yields a frame usage of 30 usec of
the 260 usec. This leaves a margin of 230 usec FIGURE 15: PIC16C73A PINOUT
for additional housekeeping features (serial com-
munications, battery management, error detec- PDIP, SOIC, SSOP
tion, fault reporting, etc.) that the user may
MCLR/VPP 1 28 RB7
implement. RA0/AN0 2 27 RB6
In converting the design to a PIC17C756, the user RA1/AN1 3 26 RB5
would integrate the A/D functionality. This would RA2/AN2 4 25 RB4
PIC16C73A
RA3/AN3/VREF 5 24 RB3
add additional time to the frame for the A/D con-
RA4/T0CKI 6 23 RB2
version. For instance, if the user wanted to moni- RA5/AN4/SS 7 22 RB1
tor Line Voltage, Line Current, Battery Voltage, VSS 8 21 RB0/INT
Battery Current, this would add approximately 120 OSC1/CLKIN 9 20 VDD
usec to the frame. The overall frame usage would OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
increase from 30 usec to 150 usec out of 260
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
usec, but the external A/D and associated over- RC2/CCP1 13 16 RC5/SDO
head would be eliminated. Additionally, house- RC3/SCK/SCL 14 15 RC4/SDI/SDA
keeping features such as battery management,
fault detection, and serial communications could
be added easily within the remaining frame time.
FIGURE 16: PIC16C74A PINOUT
In converting the design to a PIC16C72,
PIC16C73A, or PIC16C74A, the processor fre- PDIP
quency would be decreased and the math
required for the sine wave generation would be MCLR/VPP 1 40 RB7
performed in firmware. This would increase the RA0/AN0 2 39 RB6
frame usage by approximately 60-100 usec RA1/AN1 3 38 RB5
RA2/AN2 4 37 RB4
depending on the desired resolution. Also, the
RA3/AN3/VREF 5 36 RB3
user would integrate the A/D functionality. As RA4/T0CKI 6 35 RB2
described above, Line Voltage, Line Current, Bat- RA5/AN4/SS 7 34 RB1
PIC16C74A
tery Voltage, and Battery Current monitoring RE0/RD/AN5 8 33 RB0/INT

would add approximately 120 usec to the frame. RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
The overall frame usage would increase to
VDD 11 30 RD7/PSP7
approximately 210-250 usec out of 260 usec. This VSS 12 29 RD6/PSP6
would allow minimal housekeeping functionality to OSC1/CLKIN 13 28 RD5/PSP5
be integrated. If serial communications was OSC2/CLKOUT 14 27 RD4/PSP4
desired, the PIC16C73A hardware USART would RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
minimize the software overhead required. The
RC2/CCP1 17 24 RC5/SDO
PIC16C74A incorporates this feature as well as RC3/SCK/SCL 18 23 RC4/SDI/SDA
additional I/O lines if more I/O is needed. RD0/PSP0 19 22 RD3/PSP3
RD1/PSP1 20 21 RD2/PSP2

PICREF-1
FIGURE 17: PIC17C756 PINOUT • A different A/D converter for output waveform
feedback. An 8-bit A/D is acceptable for 120V, but
Shrink PDIP (750 mil) a 10-bit A/D would yield better resolution for 240V.
VDD 1 64 VSS • A PAL to replace discrete digital components. Use
RC0/AD0 2 63 RC1/AD1
RD7/AD15 3 62 RC2/AD2 of external fault detection can also reduce the
RD6/AD14 4 61 RC3/AD3 number of components used.
RD5/AD13 5 60 RC4/AD4
RD4/AD12 6 59 RC5/AD5
RC6/AD6
• MOSFETs are also suitable switching elements
RD3/AD11 7 58
RD2/AD10 8 57 RC7/AD7 for an inverter. They are much faster switches
RD1/AD9 9 56 RA0/INT
RB0/CAP1 than IGBTs and, in many lower power cases, are
RD0/AD8 10
PIC17C756 55
RE0/ALE 11 54 RB1/CAP2
RB3/PWM2
less expensive than IGBTs. The faster switching
RE1/OE 12 53
RE2/WR 13 52 RB4/TCLK12 times allow for a higher frequency PWM signal,
RE3/CAP4 14 51 RB5/TCLK3
MCLR/VPP 15 50 RB2/PWM1 which would thus require a smaller size/cost out-
TEST 16 49 VSS put filter to remove the switching frequency from
VSS 17 48 OSC2/CLKOUT
VDD 18 47 OSC1/CLKIN the output. Also, driving MOSFETs may be easier
RF7/AN11 19 46 VDD
RF6/AN10 20 45 RB7/SDO than driving IGBTs.
RF5/AN9 21 44 RB6/SCK
RF4/AN8 22 43 RA3/SDI/SDA The disadvantage of MOSFETs is that their “on”
RF3/AN7 23 42 RA2/SS/SCL state resistance RDS(on) is large enough to cause
RF2/AN6 24 41 RA1/T0CKI
RF1/AN5 25 40 RA4/RX1/DT1 dissipation problems for high power inverters and
RF0/AN4 26 39 RA5/TX1/CK1
AVdd 27 38 RG6/RX2/DT2 their saturation voltage is less stable over temper-
AVSS 28 37 RG7/TX2/CK2 ature. In addition, as the voltage rating of MOS-
RG3/AN0/VREF+ 29 36 RG5/PWM3
RG2/AN1/VREF- 30 35 RG4/CAP3 FETs is increased, their conduction loss
RG1/AN2 31 34 VDD
RG0/AN3 32 33 VSS increases.
IGBTs have the benefit that their saturation volt-
age is a relatively constant 3 volts even when
many tens to hundreds of amperes are flowing
through the device. This makes for an inverter
which has high efficiency at high output currents.
As for the gate drivers, it is not necessary to use
the special IGBT drivers that IGBT manufacturers
produce for their product. IGBTs, like MOSFETs,
do not draw any continuous gate current, but do
have significant amounts for gate capacitance.
This requires a circuit that can move the required
charge in and out of the gate in short periods of
time. Also, the gate drive circuit must have a provi-
sion to isolate the high voltage of the IGBT bridge
from the logic level voltages on the inverter control
PCB. Generally, the hybrid IGBT drivers include
some form of out-of-saturation protection circuitry
which may or may not be needed based on the
application.

PICREF-1
APPENDIX A: SYSTEM The Inverter is driven by the Inverter Drive circuitry,
which in turn is controlled by the Inverter Control cir-
SPECIFICATIONS cuitry containing the microcontroller.
The following is a list of specifications for the UPS unit:
UPS circuit board (PCB) power flow is shown in
AC Input: 120/240 VAC ± 10%, 50/60 Hz ± 3Hz Figure B-1.
UPS Output: 120/240 VAC ± 10%, 50/60 Hz ± 3Hz
B.1 UPS System Overview
(User-Selectable), Sinusoidal
Rating: 1400 VA In the Battery Boost circuit, the transistor pairs are con-
Input Filtering: EMI/RFI Filtering nected in parallel for the purpose of handling high cur-
rents. The current transformer T2 is connected as
Metal Oxide Varistor (MOV) shown to sense each pair’s current with just one trans-
for Spike/Surge Protection former, i.e., to prevent it from saturating.
APPENDIX B: SCHEMATICS The control for the 120V/240V relay (power switch) was
not implemented. Wherever input power monitoring
The UPS schematics shown in this section may be
would take place, monitoring for 120 or 240V would
obtained electronically on the Microchip BBS and
also occur and switch the relay. These functions would
WWW site (HPGL format; recommend 0.3 pen).
be placed before the PFC circuit.
The UPS may be split into 4 main circuits: Input Power
Factor Correction, Battery Boost, Free-Running Chop- B.2 Power Factor Correction
per, and Inverter. The UPS is an on-line device which
normally will have the Power Factor Correction circuit The Power Factor Correction circuit is provisional, so
feeding the Chopper, which then feeds the Inverter. If the parts listed are generic parts.
the input power should be lost, the Power Factor Cor-
rection circuit falls out of the power flow and the Battery
Boost circuit automatically provides power to the
Chopper.
FIGURE B-1: PCB POWER FLOW
Inverter Control Card

From Battery Boost PCB
Battery
PIC17C43,
Hardware
Protection Inverter Drive Card
IGBT Drivers
From Power Factor H-Bridge To

Input Free-Running
Correction PCB Chopper PCB (Inverter) Output
Filter Filter
Power Flow PCB
Other
Control Circuitry

Battery Boost Circuit
D1 L1 D3
T1 DESI 30-12A 500uH DESI 30-12A
ZZ3449
FIGURE B-2:
DS30450C-page 20
BATTERY(+)BUS
C1
PICREF-1
1uF
600V
Q1 D2
Q2
IRFP264 DESI 30-12A
IRFP264
Q1_DRIVE Transistor Pair A

Push-Pull Battery 380Vdc Bus
Boost Circuit +DC_BUSS
Q2_DRIVE I_GND
R4
C5 100k
6100uF 2W
Q3 350V
Q4
IRFP264 C4
IRFP264
1uF
600V
Q3_DRIVE Transistor Pair B
Push-Pull Battery
Q4_DRIVE Boost Circuit
C6 R5
6100uF 100k
UPS SYSTEM OVERVIEW - PAGE 1 OF 3
350V 2W
BB_I_FDBK1
T2
ZZ3450
BB_I_FDBK2 I_GND
B_GND
B_GND
LEGEND
External to Board
AC_IN_HI PWR_AC_IN_HI DC_BUS_OUT(+)
Input Filter / Power Factor
Protection Correction Internal to Board
AC_IN_LO PWR_AC_IN_LO DC_BUS_OUT(-)
I_GND
 1997 Microchip Technology Inc.

FIGURE B-2:
240Vac or 120Vac
Power Switch
Free-Running Chopper Circuit
+DC_BUSS
T6

CH_I_FDBK1 CH_I_FDBK2 ZZ3455
X1 Rectifier Circuit
T4 T5
ZZ9454 ZZ9454
CH_GND CH_GND RYL1

X2
D9 L4
DESI 60-12A 725uH
Q5 Q6
2N6770 2N6770 RECT_WAV
Q5_DRIVE Q6_DRIVE
C10 R6
Q5_DRIVE_RET Q6_DRIVE_RET 250uF 100k
350V 2W
C9
1uF
600V
O_GND
C11
RYL2 250uF R7
Q7 Q8 100k
350V
2N6770 2N6770 2W
Q7_DRIVE Q8_DRIVE
D10
Q7_DRIVE_RET Q8_DRIVE_RET DESI 60-12A
120_OR_240
O_GND
I_GND
I_GND
DS30450C-page 21
PICREF-1
FIGURE B-2:
DS30450C-page 22
IGBT H-Bridge
RECT_WAV
PICREF-1
Q9_C Q10_C
Output Filtering
Q9 Q10 L5 L7 T7
Q9_G Q10_G 300uH 50uH ZZ3459
AC_OUT_HI
C12 C13
Q9_E 0.58uF Q10_E 0.58uF
R8
5.6 OUT_IFDBK1
C14 C15 C17
10uF 10uF 10uF
600V 600V 600V
OUT_IFDBK2
Q11_C C16
Q12_C
10uF
L6 600V
300uH
AC_OUT_LO
Q11 Q12
Q11_G Q12_G
Q11_E Q12_E
O_GND

D5
DESI60-06A
FIGURE B-3:
DC BUS OUT(+) (To page 2)
D6
DESI60-06A
L1
500µH
L1 OUT (To page 2)

I SENSE (To page 2)
R1
375k
Vcc
D1 D2
MDA4008 MDA4008 C2 C3
PWR_AC_IN_HI
1µF 0.47µF
PWR_AC_IN_LO
R2 C5 C6
375k 0.47µF 1µF
D3 D4
MDA4008 MDA4008
P_GND
13 R9
C4 4.7k
Vcc 1µF
P_GND 1 3
I(SENSE) EA 0
2 4 INV VREF
MULT INV
(To page 2) (To page 2)
8 U1 5 R8
R(T) OVP OVP 12k
6 UC3854 12 (To page 2) Q5
I(SIN) Unitrode OUT 2N2222A
7 14
RAMPC VREF
16 10
C(T) SHUT R10
POWER FACTOR CORRECTION (PFC) – PAGE 1 OF 2
R3 R4 R5 15 9 10k
C1 SIG_G CLK
25.98k 5.1k 29.3k
0.01µF PWR_G
R6 R7
11 10k 1k
P_GND
P_GND
LEGEND
External to Board
Internal to Board
DS30450C-page 23
PICREF-1
L1 OUT
(From page 1)
Vcc
FIGURE B-3:
DC BUS OUT(+)
(From page 1)
DS30450C-page 24
C7 C8 DC_BUS_OUT(+)
1µF 0.47µF
PICREF-1
Q1 Q2 Q3 Q4
P_GND R19 R20 C9 R23

180k 180k 6100µF 100k
R13 R14 R15 R16
VDD VDD
24 24 24 24
OUT
C11
IN
VREF 1µF
(From page 1) OUT
PFC – PAGE 2 OF 2
U2
TSC429CPA R18 R21 C10 R24
180k 180k 6100µF 100k
GND GND
P_GND
INV
D7 (From page 1)
R11 1N4150-1
20k
I SENSE OVP
(From page 1)
(From page 1) T1
R12
100 R17 R22
4.87k 4.56k
500:1
P_GND DC_BUS_OUT(-)
P_GND
LEGEND
External to Board
Internal to Board

Vcc
R3 R2
37.5k 37.5k
FEEDBACK C5 C6
1µF 0.47µF
B_GND
FIGURE B-4:
R1 R8 VREF
C7 R25 R26
523 10k 470pF 2.49k 2.49k
C18 15 13 16 2
B_GND B_GND
1µF
Vcc Vc VREF NL

R9 1 U4a
B_GND INV 4049
2.67k
3 11 3 2
E/A OUT OUT A Out A (To page 2)
C8 5
2700pF Rt U5
6 UC3825AN 14 5 4
BB_SYN1 Ct OUT B Out B (To page 2)
7 U4b
RAMP
4 12 4049
CLK/LEB PGND
R10 R11
24 6.8k SS I Lim GND
8 9 10
C19 C10
C9 100pF 100pF R12
B_GND 510
0.01µF
B_GND
R24
C11 C12
1.5k
470pF 680pF
R13
B_GND 1k
Vcc
C15
R21 R20
0.1µF 10k 100
BATTERY BOOST (BB) CONTROL CARD – PAGE 1 OF 3
D15 D16
R23 1N4150-1 1N4150-1
LOW_BAT
69.8k B_GND 2 4 R14 BB_I_FDBK1
BATTERY(+)BUS -
1 Q1 6.2 BB_I_FDBK2
3 2N2222A 1/4W
VREF + U6a
11 LM139 D17 D18
LEGEND
1N4150-1 1N4150-1
C17 R22 C16
10nF 10k 10nF
External to Board
B_GND
B_GND
Internal to Board B_GND
DS30450C-page 25
PICREF-1
Vcc
FIGURE B-4:
DS30450C-page 26
C3 C4
Portion of Battery Boost Circuit
1µF 0.47µF
PICREF-1
B_GND
1 8
VDD VDD R6
R4 5.6
2k OUT 7 Q1_DRIVE
2 IN Transistor Pair A
OUT A
OUT 6 Q2_DRIVE Push-Pull Battery
(From page 1)
BB – PAGE 2 OF 3
R7
R5 U2
5.6
1k TSC429CPA Q2_DRIVE
GND GND
4 5
B_GND
B_GND
Vcc Transistor Pair B

Push-Pull Battery
C13 C14 Q4_DRIVE

1µF 0.47µF
B_GND
1 8
VDD VDD R17
R15 5.6
2k OUT 7 Q3_DRIVE
2 IN
OUT B
OUT 6 Q4_DRIVE
(From page 1)
LEGEND
R18
R16 U3
5.6
1k TSC429CPA
B_GND
External to Board
GND GND
4 5
B_GND
Internal to Board
B_GND

FIGURE B-4:
R19 Q1_DRIVE
47 Vcc 1
1/2w U1 Q2_DRIVE
1 2
I 7815 O 3
T1

X1 R 3 B_GND
ZZ3448 2
D1 D2 4
1N5615 1N5615
C1 C2 5 Q3_DRIVE
33µF 100µF
BB – PAGE 3 OF 3
35V 25V 6 Q4_DRIVE
D3 D4 7 B_GND
1N5615 1N5615
8
X2
9 BB_I_FDBK1
B_GND 10
11 BB_I_FDBK2
12
13
LEGEND 14
1 X1 15 FEEDBACK
External to Board 2 X2 16
3 BB_SYN1 CN2
4 B_GND
Internal to Board
CN1 BATTERY(+)BUS
1
2 B_GND
3 LOW_BAT
4 B_GND
CN3
DS30450C-page 27
PICREF-1
C3
Vcc 1µF
C4
0.47µF
FIGURE B-5:
CH_GND
15 13 16 2
DS30450C-page 28
Vcc Vc VREF NL
R3 1 U5a
CH_GND INV
1.5k 4049
PICREF-1
3 11 3 2
E/A OUT OUT A 100kHz Out A
C7 5 (To page 2)
4700pF Rt U2
6 UC3825AN 14 5 4
FRC_SYN1 Ct OUT B 100kHz Out B
7 U5b (To page 2)
RAMP
4 12 4049
CLK/LEB PGND
R1
24 C10 SS I Lim GND
100pF
8 9 10
CH_GND CH_GND
CH_GND
C10 C11
Vcc
470pF 680pF
R6 R7
1k 510
D7 R19 R18 R4 CH_GND
1N985B 100k 4.7k 100 D8
1N4150-1
D6
1N985B Q2 CH_I_FDBK1
2N2222A
D5
1N985B Q2 CH_I_FDBK2
2N2222A
D9
R5 R7 1N4150-1
10k 20.0
+DC_BUSS
CH_GND
CH_GND CH_GND
CH_GND
FREE-RUNNING CHOPPER (FRC) CONTROL CARD – PAGE 1 OF 3
LEGEND
External to Board
Internal to Board

Vcc
Portion of Free-Running Chopper Circuit

FIGURE B-5:
C5 C6
1µF 0.47µF
+DC_BUSS
CH_GND
1 8
VDD VDD
R8 CH_I_FDBK1 CH_I_FDBK2

2.2k OUT 7
100kHz 2 IN
Out A
(From page 1) OUT 6
R9 U3
TSC429CPA T2 CH_GND CH_GND
1k
FRC – PAGE 2 OF 3
Q5_DRIVE
GND GND
R12
4 5
12
Q5_DRIVE_RET
CH_GND Q8_DRIVE Q5_DRIVE Q6_DRIVE

R13
12
Q8_DRIVE_RET Q5_DRIVE_RET Q6_DRIVE_RET
Vcc Q7_DRIVE
R14
12
Q7_DRIVE_RET
C12 C13
1µF 0.47µF Q6_DRIVE
Q7_DRIVE Q8_DRIVE
R15
12
CH_GND Q6_DRIVE_RET Q7_DRIVE_RET Q8_DRIVE_RET

1 8
VDD VDD
R10
100kHz 2.2k OUT 7
2 IN
Out B
(From page 1) OUT 6
R11 U4
1k TSC429CPA
LEGEND
GND GND
4 5
External to Board
CH_GND
Internal to Board
DS30450C-page 29
PICREF-1
FIGURE B-5:
DS30450C-page 30
R17
PICREF-1
47 Vcc
1/2 W U1
1 Q5_DRIVE
I 7815 O 3 1
X1 T1 R
2 Q5_DRIVE_RET
ZZ3448 2
D1 D2
1N5615 1N5615 3
C1 C2 4 Q6_DRIVE
33µF 100µF
FRC – PAGE 3 OF 3
35V 25V Q6_DRIVE_RET

5
D3 D4 6
1N5615 1N5615
7 Q7_DRIVE
X2
8 Q7_DRIVE_RET
CH_GND 9
10 Q8_DRIVE
11 Q8_DRIVE_RET
12
LEGEND 13
X1 14 CH_I_FDBK1
1
External to Board 2 X2 15 CH_GND
FRC_SYN1 16 CH_I_FDBK2
3
Internal to Board 4 CH_GND 17 CH_GND
J1 18
19
20 +DC_BUSS
J2

+5V
R28
U21 U19 1k
FLT+ 4N35 ENABLE+ 4N35
FIGURE B-6:
l l
U5
FLT- ENABLE- ADC10154CIN
R27 D7 13 4 CH0 (From page 2)
DB7 CH0
1k U1 D6 14 5
+5V PIC17C43 DB6 CH1 CH1 (From page 2)
D5 15 6

DB5 CH2
D4 16 7 -5V +5V
21 RA5/TX/CK RD7/AD16 33 D7 DB4 CH3
R29 D3 17 1
U20 1k 22 RA4/RX/DT RD6/AD14 34 D6 DB3 AV+
ZC+ 4N35 D2 18 9
23 RA3 RD5/AD13 35 D5 DB2 Vr+
l D1 19 10
24 RA2 RD4/AD12 36 D4 DB1 Vr-
D0 20 11
25 RA1/T0CKI RD3/AD11 37 D3 DB0 V-
RD’ 3 8
26 RA0/INT RD2/AD10 38 D2 RD Vrout
WR’ 23 C13 C14
ZC- 18 RB7 RD1/AD9 39 D1 WR C23 0.1µF 0.1µF
INT’ 21 330µF
17 RB6 RD0/AD8 40 D0 INT
+5V CS’ 2 10v
U4 16 RB5/TCLK3 RC7/AD7 9 RD’ +5V CS
CTX171 22 CLK
14 15 RB4/TCLK12 RC6/AD6 8 WR’
25MHz 24 -5V
VDD 14 7 CS’ C6 DV+ C31 C32
C5 RB3/PWM2 RC5/AD5 12
0.1µF DGND 0.1µF 0.1µF
PWM 13 RB2/PWM1 RC4/AD4 6 INT’
0.1µF
Gnd Out (To page 3) 12 RB1/CAP2 RC3/AD3 5 ALARM
7 8 11 RB0/CAP1 RC2/AD2 4 POS_NEG
27 TEST RC1/AD1 3 FAULT R36
R26
19 2 +5V 100
OSC1/CLKIN RC0/AD0 ENABLE 4.75k
+5V 20 28 (To/from R37
OSC2/CLKOUT RE2/WR 100
1 29 page 3) R25
VDD RE1/OE 4.75k R23
31 VSS RE0/ALE 30 D10 6 4.75k
C4 R30 -
10 32 47k 1N4150-1 7
0.1µF VSS MCLR/VPP -5V 5
+ U16b
R31 LM158
11 C26 4.75k
Clr
10 4.7µF
INVERTER CONTROL (INV CRTL) CARD – PAGE 1 OF 4
Clk R32
10V 4.75k
9 R24
U9 Q1
7 4.75k
74HC4040 Q2
6 3.125MHz
Q3 3.125MHz
5 (To page 2) +12V
LEGEND Q4
+5V 3 2 8
Q5 -
2 1
Q6 3
External to Board C7 4 195kHz + U16a
0.1µF Q7 195kHz 4
13 (To page 2) LM158
Q8
12 -12V
Q9
Internal to Board 14
Q10
15
Q11
1
Q12
DS30450C-page 31
PICREF-1
FIGURE B-6:
R2
931
DS30450C-page 32
R8
+5V +5V 82k
D6 +12V R5 R7 D8 R9
PICREF-1
R11 100k 100k R12 1k

8 2 6
2.2k - OSENSE_1 2.2k - CSENSE_1
1 7
CH0 CH1
(To page 1) 3 (To page 1) 5
U6a + OSENSE_2 U6b +
LT1013CN8 4 LT1013CN8
D5 R4 R6 D7 R10
-12V 100k 100k 49.9
-5V -5V
R3 C10 C11
931 47pF 47pF
INV CRTL - PAGE 2 OF 4
+5V T2
R21 BB_SYNC1
220
10
U18c 8
9 7400 BB_SYNC2
3.125MHz
(From page 1)
C21 FRC_SYNC1
0.1µF
10 1
U15c 8 U15a 3
9 74AC00 2 74AC00 FRC_SYNC2
R20 PFC_SYNC1
R22 1k
1k 13 U15d 4 U15b Q1
195kHz 74AC00 11 74AC00 6 2N2222A
12 5 PFC_SYNC2
(From page 1)
C22 +5V
22pF
C24 LEGEND
0.1µF
External to Board
Internal to Board

U2 +12V U7
1 2
T1 I 7812 O 3 I 7905 O 3
FIGURE B-6:
HF_BIAS1 C3 C9
C1 R R
2.2µF 2.2µF
D3 D4 47µF 2 25V 1
25V 25V -5V
1N5615 1N5615 L1
U3 +5V U8
1 2
I 7805 O 3 I 7912 O 3
D1 D2 C8 C2 C12
R R

1N5615 1N5615 47µF 2.2µF 2.2µF
25V 2 25V 1
25V -12V
HF_BIAS2
+5V
D9
INV CRTL – PAGE 3 OF 4
1N4150-1
R1
4.75k +5V
Out of 1
Saturation U13a 3
2 74AC00 FAULT 1
(From page 4) C29 U18a 3 4
0.1µF 2 7400 U14b 6
5 74AC00 Q10_DRIVE
1
4 U13b 10 13 U14a 3
U13c 8 U13d 11 1 13 2 74AC00 Q12_DRIVE
ENABLE 74AC00 6
5 9 74AC00 12 74AC00 U11a 3 U18d 11 10 1
2 74AC00 12 7400 U11c 8 U17a 3 4
9 74AC00 2 7486 U17b 6
5 7486
PWM
R19 +5V R33 +5V
4.75k 1k C27
1nF
4
C25 U11b 6 R35
0.1µF POS_NEG 5 74AC00 1k
L_HI
4
U18b 6 13
5 7400 U14d 11
12 74AC00 Q9_DRIVE
LEGEND
10
U14c 8
9 74AC00 Q11_DRIVE
External to Board 13 10
U11d 11 U17c 8 13
12 74AC00 9 7486 U17d 11
12 7486 +5V
Internal to Board R34
1k C28
1nF C30
0.1µF
L_HI
DS30450C-page 33
PICREF-1
FIGURE B-6:
DS30450C-page 34
R13
1k
1 Q9_OC_ALARM
PICREF-1
1 HF_BIAS1 1 OSENSE_1
2 C15
1nF 2 2 OSENSE_2
3 Q9_DRIVE
3 3 CSENSE_1
4 R14
1k 4 HF_BIAS2 4
5 Q10_OC_ALARM
CN2 CN5
6 C16
5
1nF 4 1 Out of
Q10_DRIVE U10a
7 Saturation ZC+ BB_SYNC1
3 4082 1 1
(To page 3)
8 R15 2 BB_SYNC2
ZC-
INV CRTL – PAGE 4 OF 4
1k 2 2
9 Q11_OC_ALARM CHP_SYNC1
3 FLT+ 3
10 C17 4 FLT- 4 CHP_SYNC2
1nF
11 Q11_DRIVE
CN3 CN6
12 R16
1k
13 Q12_OC_ALARM 1 ENABLE+ 1 PFC_SYNC1
14 C18 12 2 ENABLE- 2 PFC_SYNC2

1nF 11 U10b 13
15 Q12_DRIVE 3 3
10 4082
9
16 4 4
+5V
17 C20 CN4 CN7
18 0.1µF
+12V
19 C19 LEGEND
20 0.1µF
CN1 External to Board
Internal to Board

FIGURE B-7:
+12Vdc
R1, R5,
R9, R13 U9, U10
INVERTER DRIVE (INV DRV) CARD – PAGE 1 OF 2

1.5k R3, R7, U11, U12
R11, R15 7818
1.5k
3 1
O I
R
T1, T2, T3, T4
C3, C7, 2 D5, D9, D7, D11, ZZ3448
C4, C8, D13, D17 D15, D19
U5, U6, U7, U8 C11, C15 C12, C16 X1
Q#_OC_ALARM H11L1 100µF 33µF 1N5615 1N5615
25V 35V
To Inverter
Control Board
D6, D10, D8, D12,

O_GND Q#_GND X2
D14, D18 D16, D20
1N5615 1N5615
C17, C18, D1, D2,
C19, C20 D3, D4
330pF ERA34-10
+5Vdc Q#_GND
5 4 6
R2, R6, Q#_C

R10, R14 OVP 2
1.5k
C1, C5, R4, R8,
15 C9, C13
33µF R12, R16
35V 33
3
AMP Q#_G
14 1 C2, C6,
Q#_DRIVE
C10, C14
From Inverter 33µF
Control Board U1, U2, U3, U4 35V
EXB840
9 Q#_E
Q#_GND
Q# of
Inverter
H-Bridge
LEGEND
PICREF-1
External to Board
Note: The Inverter Drive Card has four (4) circuits as shown
DS30450C-page 35
Internal to Board
to drive each of the four Inverter H-Bridge transistors
(# = 9, 10, 11, 12).
1 Q9_OC_ALARM 1 X1 1 Q9_C
FIGURE B-7:
2 2 X2 2
DS30450C-page 36
3 Q9_DRIVE 3 3 Q9_G
4 4 4 Q9_E
PICREF-1
5 Q10_OC_ALARM CN2 CN3

6
Q10_DRIVE 1 Q10_C
7
8 2
Q11_OC_ALARM 3 Q10_G
9
4 Q10_E
10
11 Q11_DRIVE CN4
INV DRV – PAGE 2 OF 2
12
1 Q11_C
13 Q12_OC_ALARM
2
14
3 Q11_G
15 Q12_DRIVE
4 Q11_E
16 +5Vdc
CN5
17
18
+12Vdc Q12_C
1
19
2
20
3 Q12_G
CN1 Q12_E
O_GND 4
CN6
LEGEND
External to Board
Internal to Board

PICREF-1
APPENDIX C: SOFTWARE LISTING Housekeeping software should provide an overview
control of the UPS power stream as well as the neces-
The main purpose of the microcontroller software is to sary communication and test functions to the outside
provide an inverter fast feedback loop response, such world (i.e., on-board LCD display and host computer
that the transient response and output distortion are software interface).
that of a high performance design.
The PICREF-1 software source code, as it existed at
In addition, the inverter software may be used to pro- the time this document was published, is listed below.
vide the necessary communication to any “housekeep- The most current version of PICREF-1 software may be
ing” code as well as synchronization of the output obtained electronically on the Microchip BBS and
voltage to the input voltage waveform. The housekeep- WWW site.
ing software was not developed for this reference
design; however, the inverter software has “hooks” in
place for such interfacing.
/*****************************************************************************
* Filename: MAIN.C
******************************************************************************
*
* Author: Dave Karipides
* Company: APS, Inc.
* Date: 3-3-97
* Compiled Using MPLAB-C Rev 1.21
*
******************************************************************************
*
* Include Files:
*
******************************************************************************
*
* Description: The main routine calls all the functions for generating
* an OPEN_LOOP or FEEDBACK sine wave of either 50 or 60 Hz.
*
******************************************************************************
*
* Revisions:
* 3/3/97 Added FEEDBACK LOOP
*
*
******************************************************************************/
/*****************************************************************************
* main()
*
* Description: The main routine initializes the registers and loops
* forever. All control is handled in the TMR0 INT
* routine.
*
*
* Input Variables: NONE
*
* Output Variables: NONE
*
*
******************************************************************************/
//#define OPEN_LOOP
#define FEEDBACK
//#define 50Hz
#define 60Hz
#pragma option v
#include <17c43.h>
#include <math.h>
#include <delay16.h>
#ifdef OPEN_LOOP

PICREF-1
// This table yields Full VRMS input
unsigned char const pwmtab[32]={0,25,50,74,98,120,142,162,180,197,212,
225,235,244,250,254,255,254,250,244,235,
225,212,197,180,162,142,120,98,74,50,25};
#endif
#ifdef FEEDBACK
// This table yields slightly less than Full VRMS input
unsigned char const pwmtab[32]={0,20,40,60,79,97,114,131,145,159,171,
181,189,197,202,205,206,205,202,197,189,
181,171,159,145,131,114,97,79,60,40,20};
#endif
long read_ad(unsigned char); // Prototype for A/D converter function
unsigned char index; // Index into the sinewave reference table

unsigned char sign; // Flag used to unfold sinewave reference table
long reference; // Value of the sinewave refrence after unfolding
unsigned char reference_lo @ reference; // V1.21 of Compiler does not type cast unsigned
// char to long so we will write to low byte separately
long out_volt; // Magnitude of the output voltage;
long y; // Variables used in compensation routine
long yold;
long x;
long xold;
long ad_value; // A/D Converter Value
void main(void)
{
CLRWDT();
PORTC = 0; // Zero out portc latches
DDRC = 0x22; // Set up Data direction register for C
DDRB = 0; // Set up Data direction register for B
PR1 = 0xFF; // Setup PR1 register (24.4Khz @ 25Mhz clk)
PW1DCL = 0; // Set low bits of PWM to 0
PW1DCH = 0; // Init PWM duty cycle to 0
T0STA = 0x20; // Configure Timer0 prescaler

INTSTA.T0IE = 1; // Enable Timer 0 interrupt
TCON1.TMR1CS = 0;
TCON1.T16 = 0;
TCON2.TMR1ON = 1; // Start timer 1 (PWM timer)
TCON2.PWM1ON = 1; // Turn on the PWM
CPUSTA.GLINTD = 0; // Unmask the interrupts
index = 0; // Initialize variables

sign = 0;
y = 0;
yold = 0;
x = 0;
xold = 0;
PORTC.0 = 1; // Enable the Inverter
while(1); // Loop forever, execute in INT Routine
}
#ifdef FEEDBACK
__TMR0() // Timer interrupt
{
T0STA.T0CS = 0; // Stop timer
PORTB.7=1;
#ifdef 60Hz
TMR0L=0xA5;
TMR0H=0xF9; // Make Timer0 interrupt at 3.84KHz for 60Hz output
#endif
#ifdef 50Hz
TMR0L=0x5F; // Make Timer0 interrupt at 3.20KHz for 50Hz output
TMR0H=0xF8;

PICREF-1
#endif
T0STA.T0CS = 1; // Start timer
CLRWDT();
reference = 0; // Clear Reference Value

reference_lo = pwmtab[index]; // Lookup the value of the sinewave reference
if (!index) // Toggle Sign Every Cycle Through table

sign = ~sign;
++index; // Increment index
if (index == 32) // If end of table, reset counter
index = 0;
if (sign) // If negative going wave
{
reference = ~reference; // V1.21 of Compiler negate (-ref) doesn’t work for
reference = reference + 1; // ref<=0
}
ad_value = read_ad(0);
out_volt = ad_value - 512; // Read output voltage (512 counts=0 volts out)
// Form the expression y = yold + (0.09261 * (x + xold))

// Where yold, xold is the value of y, x from the previous sample
// x is the <error signal>, formed by the difference between the output
// of the inverter and the reference signal.
x = out_volt - reference;
y = ((x + xold) * 24);
y = y / 256;
y = y + yold;
if (y >= 0)
{
PORTC.2 = 0; // Set positive going cycle
} else
{
PORTC.2 = 1; // Set negative going cycle
y = ~y;
y = y + 1;
}
if (y > 255)
y = 255; // Limit y
PW1DCH = y; // Update duty cycle
xold = x; // Store previous sample’s state
yold = y;
PORTB.7=0;
}
#endif
#ifdef OPEN_LOOP
// The inverter runs in an open loop mode with OPEN_LOOP defined.
__TMR0() // Timer interrupt
{
T0STA.T0CS = 0; // Stop timer
#ifdef 60Hz
TMR0L=0xA5;
TMR0H=0xF9; //Make Timer0 interrupt at 3.84KHz for 60Hz output
#endif
#ifdef 50Hz
TMR0L=0x5F; //Make Timer0 interrupt at 3.20KHz for 50Hz output
TMR0H=0xF8;
#endif
T0STA.T0CS=1; //Start timer
CLRWDT();
PW1DCH = pwmtab[index];
if (!index)
{
PORTC.0 = 0; // Gate Drive off

PICREF-1
PORTC.2 = ~PORTC.2; // Flip Pos/Neg bit
PORTC.0 = 1; // Gate Drive on
}
++index;
if (index == 32)
index = 0;
PORTC.3 = ~PORTC.3; // Toggle bit to test freq.
}
#endif
long read_ad(unsigned char channel)

{
long result;
PORTC.6 = 1; // Write bit high

PORTC.7 = 1; // Read bit high
PORTC.4 = 1; // Chip select high
DDRD = 0; // Make PORTD an output
PORTD = 0x04; // Single ended mode signed 10 bit chan 0 Right justified
PORTC.4 = 0; // Select chip
PORTC.6 = 0; // latch command word int A/D
PORTC.6 = 1; // Start conversion
PORTC.4 = 1; // Deselect chip
while (PORTC.5); // Wait for conversion to complete
DDRD = 0xFF; // Make PORTD an input
PORTC.4 = 0; // Select chip
PORTC.7 = 0; // Read high byte
*( ((unsigned char*)&result) + 1) = PORTD;
PORTC.7 = 1;
PORTC.4 = 1;
PORTC.4 = 0;
PORTC.7 = 0; // Read low byte
*( ((unsigned char*)&result) ) = PORTD;
PORTC.7 = 1;
PORTC.4 = 1; // Reset chip select lines
return (result); // Return data
}

PICREF-1
APPENDIX D: PCB LAYOUT & FAB DRAWING
Top silk screen drawings for the UPS control cards are These drawings, and additional layout and fab drawings
shown in the following sections. The board dimensions (top and bottom copper, top and bottom solder masks,
listed are, with respect to the orientation of this page; drill drawings, report drawings and board drawings),
(horizontal dimension x vertical dimension). may be obtained electronically on the Microchip BBS or
The boards shown are: WWW site.
• Battery Boost PCB

• Free Running Chopper PCB
• Inverter Drive Card
• Inverter Control Card.
The Power Factor Correction circuit was not built up
onto a board.
FIGURE D-1: BATTERY BOOST PCB
( 5” x 3.8” ) U6 R26
C6
U2 CN2
R25 R6 1
C5
C17
C7 R4
R8 R7
R22
R23
1 C18 R5
UC3825AN
U4 C3
C10
U5
R20 R9 R15 C4
R11 U3
C9 R17
C8
R16
Q1 R18
R10 C12 R24
R12
CN3 R14 C13
R13 C14
C2
C11 C19 D16
C16 R21 U1
CN1 D18
D3 D4
C15 D17
C1
R1
D15
D1
T1 R19
D2 R2
1
R3
T1-1 T1-4
T1-3
T1-2
© 1997 Microchip Technology Inc. Preliminary DS30450B-page 41

PICREF-1
FIGURE D-2: FREE RUNNING CHOPPER PCB
( 4” x 5” )
C6
C5 T2-3 R12 1 J2
U3
R9 T2-4
T2-1
R8
C2
T2
U4
R15
R11 T2-2 T2-5
R10
T2-6
U5 C12
C3
R14
C4 T2-7
C13 T2-8
U2
T2-9 R13
R2 C10
C9 T2-10
R3 C7
U1
C11
D8
C8
R6
D3
D4
C1
R7
R16
R1
D1 Q1 R5
D2 R4 D9
R17
T1-3
T1-4 R18
R19
T1 Q2 D5
T1-2 D7
T1-1
J1
D6
1
DS30450B-page 42 Preliminary © 1997 Microchip Technology Inc.

PICREF-1
FIGURE D-3: INVERTER DRIVE CARD
( 5” x 8” )
D7
T1-3 U9 C4
C3
D5
T1-4 D6
D8 C1
U1
D1 1
15 1
C2
C17
R4
R2
T1 R3 CN3
R1
T1-2 T1-1
U5
T2-2 T2-1 D11 U10 C8
T2 D9 C7
T2-3
T2-4 D10
U2 D12 C5
D2 1
15 1
C6
C18
R6 R8
CN1
R5 R7 CN4
CN2
U6
1
D15 U11 C12

D13 C11
T3-3
T3-4 D14
U3 D16 C9
D3 1
15 1
C10
C19
R10 R12
T3 R9 R11 CN5
T3-2 T3-1 U7
1
T4-2 T4-1 D19 U12 C16

T4 D17 C15
T4-3
T4-4 D18
U4 D20 C13
D4 1
15 1
C14
C20
R14 R16
R13 R15 CN6

U8
1
© 1997 Microchip Technology Inc. Preliminary DS30450B-page 43

PICREF-1
FIGURE D-4: INVERTER CONTROL CARD
U8 U7 U2 U3
D2
D4
D3
D1
1
L1-4
C12 C9 C3
C2
L1-1
L1-2
L1-3
T1-1
C8
T1-6
CN2
C1
T1-2
T1-4
R10
L1
R9
R8
R12
T1-5
T1
U6
LT1013CN8
C13 C6
T1-3
R2
D7
D5
D8
C24
D6
R11
ADC10154
R4 1
R5
1
U5
C11
R7 C23
C10
R6
U21 U19 U20
C31
C32
R31
R37
R36
R3 4N35 4N35 4N35

R25 CN3
R26 1
R29
R27
R28
CN5 R23
R24
U4
R32
CTX171
U16
LM158
U1 C5
C26 CN4
T2-7
R30
D10
1
R19
C4
PIC17C43
T2-5
T2
C29
U13 U11 U9
C25
C7
R21
C21
74AC00 74AC00 74HC4040

CN6
T2-4
T2-1
C14
T2-2
1
T2-3
U10 U18 U15

R22
C22
R20
4082 7400 74AC00

Q1
C19
C20
R1
R16
C18
R15
C17
R14
C16
R13
C15
C27
R33
R34
C28
R35
U17
D9
7486 CN7
C30
U14
74AC00
CN1
DS30450B-page 44 Preliminary © 1997 Microchip Technology Inc.

PICREF-1
APPENDIX E: BILL OF MATERIALS (BOM)
This appendix lists the Bill of Materials (BOM) for the
UPS system assembly and for each of the UPS boards
described in Appendix D.
E.1 UPS System Assembly
PART #, MANUFACTURER,
DESCRIPTION QTY DESIGNATORS
CONTACT #
Transistor 4 Q1 - Q4 IRFP264, International Rectifier,
(310) 322-3331
Transistor 4 Q5 - Q8 IRF450, International Rectifier,
(310) 322-3331; or Generic 2N6770
Transistors, 2 to a block, 75A 2 Q9 - Q12 2MBI75L-060, Fuji,
(408) 922-9000; or
CM75DY-12H, Powerex,
(412) 925-7272
(800) 451-1415 (USA only)
Transformer 1 T1 ZZ3449, Airborne Power
See Acknowledgments for email address
Transformer, current 1 T2 ZZ3450, Airborne Power
Transformer 2 T4, T5 ZZ9454, Airborne Power
Inductor, 500uH 1 L1 ZZ3451, Airborne Power
Inductor, 300uH 2 L5, L6 ZZ3457, Airborne Power
Switch 2 RLY1, RYL2
Diode 3 D1, D2, D3 DESI 30-12A
Diode 2 D9, D10 DESI 60-12A
Capacitor, 1uF, 600V 3 C1, C4, C9 Generic
Capacitor, Electrolytic, 6100uF, 350V 2 C5, C6 Generic
Capacitor, Electrolytic, 250uF, 350V 2 C10, C11 Generic
Capacitor, 0.58uF 2 C12, C13 Generic
Capacitor, 10uF, 600V 4 C14 - C17 Generic
Resistor, 100kΩ, 2W 4 R4 - R7 Generic
Resistor, 5.6Ω 1 R8 Generic

PICREF-1
E.2 Battery Boost PCB
CONTACT #
Cap, Ceramic 3 C9,16,17 ECU-S1J103KBA, Panasonic
0.01µF, Radial Lead (714) 373-7366
Cap, Ceramic 1 C15 ECU-S2A104KBA, Panasonic
0.1µF, Radial Lead (714) 373-7366
Cap, Ceramic 3 C4, 6, 14 ECU-S1J474KBB, Panasonic
.47µF, Radial Lead (714) 373-7366
Cap, Tantalum 4 C3, 5, 13, 18 ECS-F1EE155K, Panasonic
1.5µF, 25V, Radial Lead (Digikey: P2044-ND)
(714) 373-7366
Cap, Electrolytic 1 C1 ECE-A1VU330, Panasonic
33µF, 35V, Axial Lead (714) 373-7366
Cap, Electrolytic 1 C2 ECE-B1EU101Y, Panasonic
100µF, 25V, Axial Lead (714) 373-7366
Cap, Ceramic 1 C10, 19 ECU-S2A101JCA, Panasonic
100pF, Radial Lead (714) 373-7366
Cap, Ceramic 2 C7, 11 ECU-S2A471JCB, Panasonic
470pF, Radial Lead (714) 373-7366
Cap, Ceramic 1 C12 ECU-S2A681JCB, Panasonic
680pF, Radial Lead (714) 373-7366
2700pF, Radial Lead (714) 373-7366
Terminal Block, Wire-to-PCB Stackable, 12 CN1, 2, 3 ED120/2DS, On-Shore Technology
200mil (602) 921-3000
Diode, Small-signal, Axial Lead 4 D15,16,17,18 1N4150-1, Microsemi
(602) 244-6900
Diode, Fast-Recovery, 200V, 1A, 4 D1-4 1N5615, Microsemi
Axial Lead (602) 244-6900
Transistor, Small-signal, NPN, TO-18 1 Q1 2N2222A, National Semiconductor
(408) 712-5800
(800) 272-9959 (USA Only)
Resistor, 5.6Ω, 1/4 Watt, Axial Lead 4 R6, 7, 17,18 Generic
Resistor, 6.2Ω 1/4 Watt, Axial Lead 1 R14 Generic
Resistor, 24Ω, 1/4 Watt, Axial Lead 1 R10 Generic
Resistor, 1kΩ, 1/4 Watt, Axial Lead 3 R 5, 13, 16 Generic
Resistor, 2kΩ, 1/4 Watt, Axial Lead 2 R4, 15 Generic
Resistor, 2.67kΩ, 1/4 Watt, Axial Lead 1 R9 Generic
Resistor, 10.4kΩ, 1/4 Watt, Axial Lead 3 R8, 21, 22 Generic

PICREF-1
E.2 Battery Boost PCB (Continued)
CONTACT #
IC, Hex Inverter 1 U4 MC14049UBCL, Motorola
14-PIN DIP (602) 244-6900
IC,+15V Voltage Regulator 1 U1 MC7815CT, Motorola
TO-220 (602) 244-6900
IC, Quad Comparator 1 U6 LM339N, National Semiconductor
14-PIN DIP (408) 712-5800
(800) 272-9959 (USA Only)
IC, Driver, Line, 2 U2, 3 TSC429CPA, TelCom
8-PIN DIP (415) 968-9241
(800) 888-9966 (USA Only)
IC, PWM, 1 U5 UC3825AN, Unitrode
18-PIN DIP (603) 429-8610

PICREF-1
E.3 Free Running Chopper PCB
CONTACT #
Cap, Ceramic 3 C4, 6, 13 ECU-S1J474KBB, Panasonic
.47µF, Radial Lead (714) 373-7366
Cap, Tantalum 3 C3, 5, 12 ECS-F1EE155K, Panasonic
1.5µF, 25V, Radial Lead (714) 373-7366
Cap, Electrolytic 1 C1 ECE-A1VU330, Panasonic
33µF, 35V, Radial Lead (714) 373-7366
Cap, Electrolytic 1 C2 ECE-B1EU101Y, Panasonic
100µF, 25V, Axial Lead (714) 373-7366
Cap, Ceramic 1 C9 ECU-S2A101JCA, Panasonic
100pF, Radial Lead (714) 373-7366
470pF, Radial Lead (714) 373-7366
680pF, Radial Lead (714) 373-7366
2200pF, Radial Lead (714) 373-7366
Cap, Ceramic 1 C7 ECU-S1J472KBA, Panasonic
4700pF, Radial Lead (714) 373-7366
Terminal Block, Wire-to-PCB 12 CN1, 2 ED120/2DS, On-Shore Technology
Dual-Stackable, 200mm spacing (602) 921-3000
Diode, Small-signal 2 D8, 9 1N4150-1, Microsemi
Axial Lead (602) 244-6900
Diode, Fast Rectifier 4 D1-4 1N5615, Microsemi
200V, 1A, Axial Lead (602) 244-6900
Diode, Zener 3 D5-7 1N985B, Motorola
Axial Lead (602) 244-6900
Transistor, Small-signal 2 Q1,2 2N2222A, National Semiconductor
NPN, TO-18 (408) 712-5800
(800) 272-9959 (USA Only)
Resistor, 12Ω, 1/4 Watt, Axial Lead 4 R12-15 Generic
Resistor, 1kΩ, 1/4 Watt, Axial Lead 3 R6, 9, 11 Generic
Resistor, 2.2kΩ, 1/4 Watt, Axial Lead 2 R8, 10 Generic
Resistor, 10kΩ, 1/4 Watt, Axial Lead 1 R5 Generic
Resistor, 100kΩ, 1/4 Watt, Axial Lead 2 R19 Generic
Transformer 1 T1 TF5S03ZZ3448, Airborne Power
Bias Supply See Acknowledgments for email address
Transformer 1 T2 TF5S03ZZ3460, Airborne Power
Drive See Acknowledgments for email address
IC, Hex Inverter 1 U5 MC14049UBCL, Motorola
14-Pin DIP (602) 244-6900

PICREF-1
E.3 Free Running Chopper PCB (Continued)
CONTACT #
IC, +15V Voltage Regulator 4 U1 MC7815CT, Motorola
TO-220 (602) 244-6900
IC, Driver, Line 2 U3, 4 TSC429CPA, TelCom
8-Pin DIP (415) 968-9241
(800) 888-9966 (USA Only)
IC, PWM 1 U2 UC3825AN, Unitrode
18-Pin DIP (603) 429-8610

PICREF-1
E.4 Inverter Drive Card
CONTACT #
Cap, Electrolytic, 12 C1, 2, 4-6, 8- ECE-A1VU330, Panasonic
33µF, 35V, Axial Lead 10, 12-14, 16 (714) 373-7366
Cap, Film, 100µF, 25V, Axial Lead 4 C3, 7, 11, 15 ECE-B1EU101Y, Panasonic
(714) 373-7366
Connector, Ribbon Cable, 1 CN1 3428-6002, 3M Scotchflex
20-position (512) 984-1800
(800) 225-5373 (USA Only)
Terminal Block, Wire-to-PCB, 10 CN2-6 ED120/2DS, On-Shore Technology
2 Position Dual, 200mil spacing (602) 921-3000
Diode, Fast Recovery, 4 D1-4 ERA34-10, Fuji (Collmer)
600V, 1A, Axial Lead (214) 233-1589
Diode, Fast-Recovery, 16 D5-20 1N5615, Microsemi
200V, 1A, Axial Lead (602) 244-6900
Resistor, 1/2 Watt, 33Ω, 1%, Axial Lead 4 R4, 8, 12, 16 Generic
Resistor, 1/4 Watt, 1.5kΩ, 1%, Axial Lead 12 R1-3, 5-7, 9-11, Generic
13-15
Transformer, Toroid 4 T1-4 TF5S03ZZ3448, Airborne Power
100kHz, 24:27 (Core is XJ-41605-TC)
IC, Optocoupler, 6-Pin DIP 4 U5-8 H11L1QT, QT Optoelectronics
Schmitt Trigger Logic-Output (214) 447-1304
Voltage Regulator, TO-220 4 U9-12 MC7818CT, Motorola
18Vdc (602) 244-6900
Driver, IGBT. Hybrid Package 4 U1-4 EXB840, Fuji
(201) 712-0555
Retainer, Toroid 4 100-2, Delbert-Blinn
(909) 629-3900
Screw, 4-40x1/2 ”, Stainless Steel 4 Generic
Washer, 4-40”, Stainless Steel 4 Generic

PICREF-1
E.5 Inverter Control Card
CONTACT #
Cap, Ceramic, C0G 1 C22 ECU-S2A220JCA, Panasonic
22pF, 100V, Radial Lead (714) 373-7366
Cap, Ceramic, X7R 8 C10, 11, 15-18, ECU-S2A102KBA, Panasonic
0.001µF, 100V, Radial Lead 27, 28 (714) 373-7366
Cap, Ceramic, X7R 15 C4-7, 13, 14, ECU-S2A104KBA, Panasonic
0.1µF, 100V, Radial Lead 19-21, 24, 25, (714) 373-7366
29, 30, 31, 32
Cap, Tantalum, 4 C2, 3, 9, 12 ECS-F1EE225K, Panasonic
2.2µF, 25V, Axial Lead (714) 373-7366
Cap, Electrolytic, 1 C23 ECE-A1CU331, Panasonic
330µF, 16V, Radial Lead (714) 373-7366
Cap, Electrolytic, 2 C1, 8 ECE-B1EFS470, Panasonic
47µF, 25V, Axial Lead (714) 373-7366
Cap, Tantalum, 1 C26 ECS-F1AE475K, Panasonic
4.7µF, 10V, Axial Lead (714) 373-7366
Connector, Ribbon Cable, 1 CN1 3428-6002, 3M Scotchflex
20-position (512) 984-1800
(800) 225-5373 (USA Only)
Terminal Block, Wire-to-PCB, 12 CN2-7 ED120/2DS, On-Shore Technology
2 Position Dual-Stackable, 200mm spacing (602) 921-3000
Diode, Small-signal, 6 D5-10 1N4150-1, Motorola
Axial Lead (602) 244-6900
Diode, Fast Recovery, 4 D1-4 1N5615, Microsemi
200V, 1A, Axial Lead (602) 244-6900
Transistor, Small-signal, 1 Q1 2N2222A, National Semiconductor
NPN, TO-18 (408) 712-5800
(800) 272-9959 (USA Only)
Resistor, 1/4 Watt, 49.9Ω, 1%, Axial Lead 1 R10 Generic
Resistor, 1/4 Watt, 220Ω, 1%, Axial Lead 1 R21 Generic
Resistor, 1/4 Watt, 1kΩ, 1%, Axial Lead 13 R9, 13-16, 20, Generic
22, 27-29, 33-35
Resistor, 1/4 Watt, 2.2kΩ, 1%, Axial Lead 2 R11, 12 Generic
Resistor, 1/4 Watt, 4.75kΩ, 1%, Axial Lead 8 R1, 19, 23-26, Generic
31, 32
Resistor, 1/4 Watt, 932kΩ, 1%, Axial Lead 2 R2, 3 Generic
Resistor, 1/4 Watt, 82kΩ, 1%, Axial Lead 1 R8 Generic
Resistor, 1/4 Watt, 100kΩ, 1%, Axial Lead 4 R4-7 Generic
Inductor, Toroid 1 L1 TF5S04ZZ3461, Airborne Power
Transformer, Toroid 1 T1 TF5S03ZZ3462, Airborne Power
1P/2S CT’ed See Acknowledgments for email address
1P/1S See Acknowledgments for email address
IC, 18-bit Shift Register, 1 U9 MC14040BAP, Motorola
16-Pin DIP (602) 244-6900
TO-220 (602) 244-6900
IC, -5V Voltage Regulator 1 U7 MC7905CT, Motorola
TO-220 (602) 244-6900

PICREF-1
E.5 Inverter Control Card (Continued)
CONTACT #
TO-220 (602) 244-6900
IC, -12V Voltage Regulator 1 U8 MC7912CT, Motorola
TO-220 (602) 244-6900
IC, Optocoupler 3 U19-21 4N35QT, QT Optoelectronics
6-Pin DIP (214) 447-1304
IC, Quad NAND Gates 4 U11, 13-15, 18 74AC00PC, National Semiconductor
14-Pin DIP (408) 712-5800
(800) 272-9959 (USA Only)
IC, A-D Converter, 1 U5 ADC10154CIN, National Semiconductor
24-Pin DIP (408) 712-5800
(800) 272-9959 (USA Only)
Oscillator, Clock 1 U4 CTX171, CTS
25MHz, (14-Pin DIP compatible) (815) 786-8411
IC, Op Amps 1 U16 LM358AN, National Semiconductor
Low-Power, Dual, 8-Pin DIP (408) 712-5800
(800) 272-9959 (USA Only)
IC, Op Amp 1 U6 LT1013CN8, Linear Technology
Precision, Dual, 8-Pin DIP (408) 432-1900
IC, Microcontroller 1 U1 PIC17C43, Microchip Technology
40-Pin DIP (602) 786-7200
IC, Dual 4-input AND Gate 1 U10 CD4082BE, Harris
14-Pin DIP (407)724-7000
(800) 4 HARRIS (USA Only)
IC, Quad 2-input Exclusive-OR 1 U17 74AC86PC, National Semiconductor
Gate, 14-pin DIP (408) 712-5800
(800) 272-9959 (USA Only)

PICREF-1
APPENDIX F: UPS DEMO UNIT The circuit boards used on the demo unit are the
inverter drive PCB, the inverter control PCB and a bias
The Demo Unit is a subset of the UPS. This unit was supply board used to supply 15Vdc to the unit’s dis-
designed to showcase the inverter, featuring the crete components.
PIC17C43 microcontroller. Therefore, there is no bat-
tery back-up circuitry. F.1 Demo Specifications
AC power is filtered as it enters the UPS demo unit.
The UPS demo specifications are the same as for the
There is also an input fuse to protect against surges.
UPS system.
There is no power factor correction circuitry, and a rec-
tifier-bridge is used to feed the inverter, or H-Bridge
(i.e., no free-running chopper). There is output filtering
and feedback circuitry.
F.2 Demo Additional Schematics, PCB’s, BOMs
FIGURE F-1: BIAS SUPPLY CIRCUIT
+15Vdc
1 T1
C3 ZZ3464
2 C2
0.1µF 47µF
25v
CN1
Q1
GND NDP4050 1
Vcc Vc 2
Rt Vr
CN2
Ct Cmp
R(T)
Dt U1
UC3525BN R2
Syn
R1 C1 47 Q2
6.04k 1pF Osc A NDP4050
SS B
E- E+ Inh Gnd R3
47
GND

PICREF-1
FIGURE F-2: BIAS SUPPLY BOARD FIGURE F-3: RECTIFIER-BRIDGE CIRCUIT
(2.4” X 2.4”) +
AC HI 1 CN2
T1
AC AC
AC LO
-
Q2
Q1
CN1 R3
+15V 1
C2
C3 R2
+
R1
GND
C1
U1
TABLE F-1: BIAS SUPPLY BOM
CONTACT #
Cap, Electrolytic, 1 C3 ECE-A1EU470, Panasonic
47µF, 25V, Radial Lead (714) 373-7366
Cap, Ceramic, 1 C2 ECU-S1J104KBB, Panasonic
.1µF, 63V, Radial Lead (714) 373-7366
Cap, Ceramic, 1 C1 ECU-S1J102JCB, Panasonic
.001µF, 63V, Radial Lead (714) 373-7366
Terminal Block, Wire-to-PCB, 2 CN1,2 ED120/2DS, On-Shore Technology
2 Position Dual-Stackable, (602) 921-3000
200mil spacing
Resistor, 1/4 Watt, 47Ω, 1%, Axial Lead 2 R2,3 Generic
Resistor, 1/4 Watt, 6.04KΩ, 1%, Axial Lead 1 R1 Generic
100KHz (Core XJ-41605-TC)
IC, PWM, 16-Pin DIP 1 U1 UC3525BN, Unitrode
(603) 429-8610
Transistor, TO-220 2 Q1,2 NDP4050, National Semiconductor
N-Chan, MOSFET, 50V (408) 712-5800
(800) 272-9959 (USA Only)
PCB, 2.4” x 2.4” 1 Generic PCB
Bias Supply, 100KHz
Retainer, Toroid 1 100-2, Delbert-Blinn
(909) 629-3900
Screw, 4-40x1/2 ”, Stainless Steel 1 Generic
Washer, 4-40”, Stainless Steel 1 Generic

PICREF-1
TABLE F-2: OTHER BOM
CONTACT #
Rectifier-Bridge Circuit 1 M5060SB1200, CRYDOM
(818) 956-3900
Power Supply PCB 1 SW10-15PC, Toko America
(847) 297-0070
Audio Transformer 1 705-0862, Allied
(On-Board Isolation Transformer) (817) 595-3500
(800) 433-5700 (USA Only)

PICREF-1
F.2.1 DEMO UNIT ASSEMBLY A UPS Demo Unit is shown in different stages of
assembly, for top and side aspects, in the figures below.
DANGER
Electrocution Hazard
Do Not Disassemble Unit
FIGURE F-4: DEMO PARTIAL ASSEMBLY - TOP VIEW
input
rectifier filtering
output
power
input filter input

inductor power
input
heat
fuse
sink
IGBT’s
IGBT’s
bias output filter
board inductors
FIGURE F-5: DEMO FULL ASSEMBLY - TOP VIEW

“Electrical
Hazard”
on-board output
isolation output
filtering power
transformer
inverter control
card “Danger:
High Voltage”
DC Bus
inverter drive
card DC Bus
bias capacitor
board
H-Bridge
(IGBT’s)
power
supply “Danger:
High Voltage”

PICREF-1
FIGURE F-6: DEMO PARTIAL ASSEMBLY - FRONT VIEW
input
rectifier filtering output
power
input filter
heat inductor
input
sink power
fuse output filter
bias inductors
board IGBT’s IGBT’s
FIGURE F-7: DEMO FULL ASSEMBLY - FRONT VIEW

inverter drive card
(underneath inverter control card)
“Electrical
Hazard”
output
filtering output
inverter control power
card
DC Bus
“Danger:
High Voltage”
H-Bridge
(IGBT’s)
DC Bus
capacitor
bias
board
“Danger:
power High Voltage”
supply

PICREF-1
FIGURE F-8: DEMO PARTIAL ASSEMBLY - INVERTER CARDS DETAIL
inverter control
card
output
filtering
inverter drive
card
H-Bridge
(IGBT’s)
DC Bus
capacitor
bias
board
FIGURE F-9: DEMO FULL ASSEMBLY - DC BUS DETAIL

DC Bus
DANGER
DC Bus Electrocution Hazard
Do Not Touch DC Bus
DC Bus
capacitor
IGBT’s IGBT’s

PICREF-1
F.3 How to Demo the PICREF-1 Follow these steps to demo the UPS Demo Unit:
1. Plug the receptacle end of a power cord into the
DANGER UPS Demo Unit “AC Input”. Plug the pronged

end of the power cord into an AC wall socket.
Electrocution Hazard 2. Plug the load into the UPS Demo Unit “Load”
socket (Optional). Make sure load can be driven
Do Not Disassemble Unit by the UPS Demo.
3. Connect an oscilloscope probe to the UPS
The UPS Demo Unit was not designed for sustained
Demo Unit “Load Monitor” BNC connector.
use, but only for short-term demonstration. Disconnect
the unit when not in use. 4. Display (Stepped Down) AC Output waveform
on oscilloscope.
Note: An isolation transformer should be used
with the UPS Demo Unit to avoid improper
grounding.
FIGURE F-10: HOW TO SET UP DEMO UNIT - REAR VIEW
Load
AC Input
Load Monitor
Ratio 1:23

M
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Uninterruptible Power Supply Reference Design With A PIC-Www - Circuitdiagram

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Uninterruptible Power Supply Reference Design With A PIC-Www - Circuitdiagram

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M PICREF-1

Uninterruptible Power Supply Reference Design

INTRODUCTION PICREF-1 OVERVIEW

 1997 Microchip Technology Inc. DS30450C-page 1

DS30450C-page 2  1997 Microchip Technology Inc.

FIGURE 1: PICREF-1 UNINTERRUPTIBLE POWER SUPPLY (UPS) BLOCK DIAGRAM

 1997 Microchip Technology Inc. DS30450C-page 3

FIGURE 2: INVERTER OPERATION

Q11_G Q11 Q12_G Q12

DS30450C-page 4  1997 Microchip Technology Inc.

FIGURE 3: INVERTER WAVEFORMS

 1997 Microchip Technology Inc. DS30450C-page 5

FIGURE 5: TYPICAL ANALOG SOLUTION

DS30450C-page 6  1997 Microchip Technology Inc.

 1997 Microchip Technology Inc. DS30450C-page 7

DS30450C-page 8  1997 Microchip Technology Inc.

 1997 Microchip Technology Inc. DS30450C-page 9

Calculate Input Power

Set pointer to 50Hz Set pointer to 60Hz

Set Flags Set Flags Set Flags

Shaded objects indicate provisional sections.

DS30450C-page 10  1997 Microchip Technology Inc.

 1997 Microchip Technology Inc. DS30450C-page 11

The first step is to normalize H(s) and make note of

Choose a sampling frequency at least 32 times the

DS30450C-page 12  1997 Microchip Technology Inc.

FIGURE 9: AC OUTPUT - NO LOAD, NO FEEDBACK

FIGURE 10: AC OUTPUT - RESISTIVE LOAD, NO FEEDBACK

 1997 Microchip Technology Inc. DS30450C-page 13

DS30450C-page 14  1997 Microchip Technology Inc.

FIGURE 12: OFF-LINE UPS

 1997 Microchip Technology Inc. DS30450C-page 15

FIGURE 13: ON-LINE UPS

DS30450C-page 16  1997 Microchip Technology Inc.

tery Voltage, and Battery Current monitoring RE0/RD/AN5 8 33 RB0/INT

 1997 Microchip Technology Inc. DS30450C-page 17

DS30450C-page 18  1997 Microchip Technology Inc.

FIGURE B-1: PCB POWER FLOW

Inverter Control Card

From Power Factor H-Bridge To

Power Flow PCB

 1997 Microchip Technology Inc. DS30450C-page 19

Q1_DRIVE Transistor Pair A

 1997 Microchip Technology Inc.

 1997 Microchip Technology Inc.

CH_GND CH_GND RYL1

 1997 Microchip Technology Inc.

DC BUS OUT(+) (To page 2)

L1 OUT (To page 2)

 1997 Microchip Technology Inc.

P_GND R19 R20 C9 R23

 1997 Microchip Technology Inc.

 1997 Microchip Technology Inc.

Vcc Transistor Pair B

C13 C14 Q4_DRIVE

 1997 Microchip Technology Inc.

 1997 Microchip Technology Inc.

35V 25V 6 Q4_DRIVE

 1997 Microchip Technology Inc.

Portion of Free-Running Chopper Circuit

 1997 Microchip Technology Inc.

CH_GND Q8_DRIVE Q5_DRIVE Q6_DRIVE