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1- in vhdl sensetivity list contains only signals , but in verilog always @(events

not only signals) these events could be posedge or negedge only


and couldn't be level sensetive for any signal (The event depends on both edge and
nonedge expressions, which synthesis does not support)

2-in if condition if there are more than one condition || or && don't make each
condition on brackets alone

3-The statements in 'always' block are outside the scope of the synthesis policy ,
only an 'if' statement is allowed at the top level in this always block

> lazm ykon feh if statement wa7da fy koll always statement not more than 1 you can
separate them in two different always statements .

4- The expression in the reset condition of the 'if' statement in this 'always'
block can only be a simple identifier or its negation
>By reset condition he means the first condition you check for in the always
staetment , you should have in always statement only if and else statement
and under the else stat. you put the other if statements and so on

5- Glue logic
don't add any logic in the hierarchical level just connected instances .

6-warning: Design rule attributes from the driving cell will be set on the port
> this means the out load of the drive cell and other attributes , why should this
be important ?
DC-SG(multiple objects with the same name )

7-�Incomplete timing specification list�


this warning appers as you haven't listed all the inputs or rhs signals inside
always st. for ex. in the sensetivity list
to solve it use : always(*) 2001 verilog
nthesisi

8- variable assigned in more than one block� -after read command or analyze-
> edit your design to have only one assignment place for each signal

9- Improper Startup or primt 'can't'


this means you haven't handled all the cases and just typed default to make it easy
&& this resulted in propagating some 'x' values to an output

10- check_design to make sure all signals are connected correctly in a hierarchical
design and no z wires

11-net has no drivers


> it means that you are using floating signal to implement some logic ,
if you checked the warning for the very firststages of synthesis u may find
the problem : LOADED SIGNAL BUT NOT ASSIGNED/DRIVEN , the tool assumes
the signal is zero which may lead the tool to completely remove the logic

12- ******//////////to generate vcd file from modelsim *********//////////////


> vcd file a7md.vcd
vcd add -r/testbench_tb/*

13- you may have unconstrained path warning even if you use registered outputs ,
this may be resulted from having asynchronous path through the reg which doesn't
obey the clock

14- if you have in2out setup violations you may have 2 solutions ( adding reg from
RTL code , put register ob all inputs and all outputs on DC)

15-[verilog] you can't use both blocking and nonblocking assignment at the same
always block

16- [verilog] you can't put in the sensetivity list signal without determining its
edge posedge negedge

17- you cannot assign any signal 'net' from two different places which operate in
parallel

18- in submodule *** a pin isn't connected to any nets >> this floating pin is
going to be connected to logic'1' or logic '0' by DC to protect it use dont_touch
command :
set_dont_touch true [get_nets *]

19-

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