Professional Documents
Culture Documents
OBJECT:
After completing this experiment, you will be able to:
1- Use TTL logic to verify experimentally several of rules for Boolean
algebra.
2- Experimentally determine the truth table for circuits with two input
variables.
THEORY:
In analog circuits many different voltages may exist at the same
time, whereas in digital circuits there are only two. These two voltages are
referred to as logic 1 and logic 0 states, as true and false or by some other
similar name. Because of the use of only two states, digital logic is said
to be binary in nature.
In digital logic there are three basic elements: The AND gate, the
OR gate, and Inverter (NOT gate). What the do is very simple but it is
essential that you under stand them by inter connecting a number of these
gates into circuits, they can perform various increasingly complex
functions such as addition of two numbers, counting, multiplication or
division of any two numbers, keeping the time of day, and even running
a whole computer. To learn their characteristics and the simple short and
methods by which their functions can be described, the two gates and the
inverter will be studied separately.
1-1
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
on the left, marked A and B, and the output is on the right, marked C.
The truth table is shown in Table (1-1) and the logic equation is C = A.B.
A
B C
A B C
0 0 0
0 1 0
1 0 0
1 1 1
2-The OR Gate:
The OR gate is a device whose output is a logic 1 if either one or
both its inputs are logic 1. The OR gate is shown by symbol in Fig. (1-2)
with the two inputs A and B again on the left and the output C on the
right. The truth table for OR gate is shown in Table (1-2) and the logic
equation is C = A + B.
A C
B
1-2
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A B C
0 0 0
0 1 1
1 0 1
1 1 1
3- The Inverter:
The third and most simple element of digital logic is the inverter, it
is also known as the NOT function. The inverter is different from the AND
and OR gates, in that it has only a single input. The inverter simply
converts logic 1 at its input to logic 0 at its output and conversely, logic 0
to a 1. The inverter can be represented by either of the symbols shown in
Fig. (1-3).
A C
0 1
1 0
1-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A C
B
Fig. (`1-4) Logic Symbol for NAND gate
A B C
0 0 1
0 1 1
1 0 1
1 1 0
A C
B
1-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A B C
0 0 1
0 1 0
1 0 0
1 1 0
6- The EX - OR Gate:
There is one more gate that needs to be considered – The gate EX
– OR which has only two inputs, shown in Fig. (1-6). The EX - OR
gate has a logic high output when either of its inputs is high but not
when both are high or both are low. Notice that in the logic equation
we have introduced a new symbol called EX - OR. The EX - OR gate
is quite useful, since its output is high only when the inputs are different,
it's truth table shown in Table (6) the logic equation is :
C = AB + A B
C =A B
A
B
A
B
1-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A B C
0 0 0
0 1 1
1 0 1
1 1 0
A C
B
(a)
A
B
C
A
B
(b)
1-6
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A B C
0 0 1
0 1 0
1 0 0
1 1 1
TIMING DIAGRAMS:
When a logic gate is performing a useful function in a circuit, its
inputs can change and its output will react to these changes according to
the truth table for that gate. It is often quite useful to have a symbolic
representation for these logic states, as they change with time. A
convenient method for doing this is to draw a timing diagram. The main
purpose of a timing diagram is to show what the conditions in a logic
circuit are at any one particular time. By using timing lines, it is possible
to oversee all inputs and outputs simultaneously. If any input or output
line is displayed on an oscilloscope screen.
C
(a)
(b)
1-7
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
(c)
(d)
Fig. (1-8) Timing diagram for logic gates.
(a) Timing diagram for AND gate.
(b) Timing diagram for OR gate.
(c)Timing diagram for EX-OR gate.
(d) Timing diagram for EX-NOR gate.
1-8
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
u
and is read AND ". The dot is frequently eliminated when logical
multiplication is shown. Thus A.B is written AB. The basic rules of
Boolean algebra are shown in Table (1-8).
2 A+ 1 =1
3 A. 0 = 0
4 A. 1 = A
5 A+ A = A
6 A+ A =1
7 A. A = A
8 A. A = 0
9 A=A
10 A + AB = A
11 A+ AB = A+B
12 (A + B)(A + C) = A + BC
1-9
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
In this experiment you will use TTL logic to become familiar with this
important family. There are several subfamilies of CMOS which have
different specifications. The original CMOS family was the 4000
series. Other families include the 54C / 74C family, which is
functionally and pin - out - compatible with TTL 54 / 74 series, and the 54
HC / 74HC, which is functionally and pin - out - compatible with TTL
54LS / 74LS logic. The 54C / 74C series is faster and can sink 50% more
current that the 4000 series. One disadvantage of CMOS is that it is
damaged more easily than TTL. Because the TTL (Transistor - Transistor
Logic) is the most widely used logic family. Almost every major
manufacturer has a TTL product line and most common TTL integrated
circuits are produced by several companies.
APPARATUS:
1. Oscilloscope.
2. The software Electronic Work Bench
3. Function generator.
4. Logic INTIKIT unit
5. I C ‘s 7 4 0 4 , 7 4 3 2 , 7 4 0 8 , 7 4 8 6 , 7 4 0 , 7 4 0 2 , 74266.
PROCEDURE:
1-10
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
5- Repeat steps (2), (3) and (4) for Fig. (1-2), Fig. (1-3), Fig. (1-4),
Fig. (1-5), Fig (1-6), Fig (1-7) and draw the output waveforms for each
figure.
6- Prove rule 1 (see Table 8) with the circuit of Fig. (1-9). Use 5V for the
power supply, with 0V to 4V level on the output. Sketch the input signal,
Vin, and voltage on your sketches. To obtain the proper time relationship
between signals, look at both signals at one time on the scope while
triggering on one channel only.
Vin Vout
7-Change the circuit to that of Fig. (1-10). Sketch the input and output
signals.
Vin Vout
9- Design a circuit that illustrates rule 10, Use the signal generator for A
and a switch (or wire) for B. Sketch the A input and output signal.
1-11
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
1-12
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
DISCUSSION:
1- Design the logic circuit for the following conditions and draw the
output wave form, X is a 0 if any two of the three variables A, B, and
C are 1, X is a1 for all other conditions.
2- Implement the following function with only AND and NOT gates.
F=A B + A B + B C
W=X Y (X Z + X Y Z + Y Z) + X Z
3- TTL SSI comes mostly in 14 - pin packages. Two pins are reserved for
power supply and the other pins are used for input and output
terminals. How many gates are enclosed in one such package if it
contains the following types of gates:-
a) 2 - input exclusive - OR gates.
b) 3 - input AND gates.
c) 4 – input NAND gates.
d) 5-input NOR gates.
e) 8 - input NAND gates.
4- Use NAND gate, NOR gate, or combinations of both to
implement the following expression:-
a) X=A [B + C (D + E)]
b) X = B (CDE + E F G) (A B + C)
5 - a) What is the applications of AND gate and OR gate?
b) In OR gate why 1 + 1 = 1?
c) The Fig. (12 - a) shows the A & B inputs and the output is C, For
the OR gate using the A and B inputs of Fig. (12 - a) draw the C
output for each of the following:
• The AND gate.
• The NAND gate Fig. (12 – b).
• The NOR gate Fig. (12 – c).
• The negative AND gate Fig. (12 – d).
1-13
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A C A C
B B
(a) (b)
A A
C C
B B
(c) (d)
1-14
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
OBJECT:
The EX - OR is a widely used function because of special arithmetic
properties which will be discussed below and because of its wide
applications.
THEORY:
1- Parity Checker:
Errors can occur as digital codes are being transferred from one point
to another within a digital system or while codes are being transmitted from
one system to another. The errors take the form of undesired changes in the
bits that make up the coded information that is, a 1 can change to a 0 or a
0 to 1, due to component malfunctions or electrical noise. If we have four
bit word, to detect the occurrence of an odd number of errors in this word, a
single bit will be added to the word that makes the number of (ones) in the
word either even number (even parity) or odd number (odd parity), so, if an
odd number of errors occurred in the word, then, the total number of ones
will not remain the same, it will change from odd to even or from even to
odd. The EX - OR gate is the most suitable circuit to provide parity
checker. Fig. (2-1) shown the circuit of four bit even parity checker.
A
B
2-1
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
2- Control Inverter:
The EX - OR gate can be used as a (NOT) gate by connecting one of
the inputs to logic 1, for this reason it can be used to complement a word
by using one of the inputs as control line as shown in Fig. (2-2). When
the control signal is logic zero then X=A, Y= B, Z=C, and when control
signal is logic one then X= A, Y= B, Z= C
A B C
Control signal
x y z
Fig. (2-2) Control inverter logic circuit.
3- Binary to Gray / Gray to Binary Conversion:
U
2-2
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
4- Digital Comparator:
The basic function of comparator is to compare the magnitude of two
quantities in order to determine the relationship of those quantities. In its
simplest form, a comparator circuit determines if two numbers are equal.
The EX-OR gate is a basic comparator because its output is a 1 if its two
input bits are not equal and a 0 if the inputs are equal. If the comparison is
such that the states of one number with respect to the other is to be specified
one of the three conditions A > B, A< B, and A = B.
0 0 0 0 1
1 0 1 0 0
0 1 0 1 0
1 1 0 0 1
APPARATUS:
2-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
PROCEDURES:
2-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
DISCUSSION:
1- Is the Gray code arithmetic code? Why? Where this code used?
2 - What is the parity bit?
3 - Design five - bit odd parity checker?
4- a) What are the main applications of the comparator?
b) Design two – two bit comparator.
5- Convert five bit Gray to binary code, write truth table and draw the
circuit diagram.
2-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
THEORY:
An arithmetic element is any circuit that can add, subtract, multiply,
divide, or perform some other arithmetic function with binary numbers.
Arithmetic elements lie securely in the domain of computer technology
and the related technology of electronic calculators. With all of the
complexity of computer circuits, it is slightly reassuring to realize, that, the
basis of all the arithmetic operations that a computer performs is one simple
circuit that consist of only a few gates - the full adder. The full adder simply
adds two binary logic bits (and a carry), but as it turns out, the full adder can
be used to subtract, multiply, divide, extract square roots, and perform many
other mathematical functions.
1- Binary Addition:
To perform the addition of two numbers in binary form, the following
four fundamental rules of algorithms are used:
0+0=0, 1+0=1, 0+1=1, 1+1=0 and carry 1
These algorithms can be applied to any two positive binary numbers,
(integers) and are the only basic rules that must be observed in binary
addition. For example:
3-1
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
11 Carries 111
0110 6 Augend 0011 3
0011 + 3 Addend 0111 + 7
1001 9 Sum 1010 10
HALF ADDER:
One logic circuit that can be used to begin implement addition
according to the above algorithms is shown in Fig. (3 - 1). It accepts two
binary digits on its input and produces two binary digits on its output, a sum
bit and a carry bit.
C 0 =A B
S=A B
A
SUM
B
CARRY
FULL ADDER:
The full-adder accepts three inputs, and generates a sum output and a
carry output. It must sum the two input bits and the input carry bit, yielding
the equation for the input carry bit, yielding the equation for the sum output
of the full- adder.
S = (A B) Ci
The output carry is a 1 for the full-adder if both inputs to the first
exclusive –OR gate are 1s or if both inputs to the second exclusive –OR
gate are 1s.
3-2
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
C 0 = A B + (A B) Ci
This function is implemented and combined with the sum logic to perform a
complete full-adder circuit, as shown in Fig. (3-2). this circuit is used in
calculators, computers, and much other arithmetic circuit to perform not
only addition, but also multiplication, division, and Subtraction. All these
operations can be performed by utilizing special algorithms and the full adder
circuit.
HA
A carry
CARRY OUT
sum
carry
B
sum SUM
Carry in
HA
3-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
B3 A3 B2 A2 B1 A1 B0 A0
3-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
2-BINARY SUBTRACTION:
Binary subtraction can be done in several different ways. First, to
perform direct subtraction of one binary number from another, rules or
algorithms can be written that are similar to those written for addition:
0 – 0 = 0, 1 – 0 = 1, 1 – 1 = 0, 0 – 1 = 1 and borrow (1)
These algorithms permit the subtraction of any two binary numbers, as
long as the minuend is larger than the subtrahend. Such subtraction is shown
by the following two examples:
1001 9 Minuend 1100 12
0101 5 Subtrahend 0011 3
0100 4 Difference 1001 9
There, is, however, another more commonly used method of subtraction,
which is based on adding the complement of one number to another
number, instead of subtracting
9 1001 Minuend 1001
-3 0011 Subtrahend 1100 complement of subtrahend
6 0110 1 0101 add to the minuend
1 add end-around carry to LSB
0110 difference
3-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A
SUM
B
CARRY
A
B
Borrow out
=A B Bi
Difference out
Borrow in
= AB + (A B) Bi
APPARATUS:
1. Logic INTIKIT unit
2. I C’s: 7404, 7408, 7432, 7486
3. The software Electronic Work Bench (EWB).
3-6
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
PROCEDURE:
Part One: Practical connection.
1 - Connect the circuit shown in Fig. (3-1) and find its truth table.
2- Connect the circuit shown in Fig. (3 -2) and find its truth table, then find
function of its outputs.
3- Repeat step (1) for Fig. (3- 4) and, repeat step (2) for Fig. (3-5).
4- Design parallel 2 - bit adder logic circuit and find its results
Part Two: Simulation using Electronic Work Bench (EWB).
1- Connect the circuit shown in Fig. (3-1), (3-2), (3-4), (3-5) by using
logic gates.
2- Repeat step 1 using IC’s.
3- Repeat step 1 using half adder block.
4- Connect the circuits shown in Fig. (3-4), for each set of the following
binary numbers, determine the result of the following:
(a) A3 A2 A1 A0 = 0100 B3 B2 B1 B0 = 0100
(b) A3 A2 A1 A0 = 1100 B3 B2 B1 B0 = 1001
(c) A3 A2 A1 A0 = 1000 B3 B2 B1 B0 = 1011
The following window represents example of the (EWB) package.
3-7
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
DISCUSSION:
1 - Show that the output carry in a full adder circuit can be expressed as.
Ci +1 = Gi + Pi Ci = {Gi Pi + Gi Ci)
3-8
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
n n×m 2n n – to – m
Inputs decoder Line decoder
The decoders represented here are called n –to –m line decoders. The
decoder is also used in conjunction with some code converters such as a
BCD – to – seven segment decoder.
ENCODERS:
U
U BCD DECODER:
The BCD decoder converts each BCD code word (8421) into one of ten
possible decimal digit indications. It is typically referred to as a 1 – of – 10
or 4 – line – to 10 – line decoder.
The method of implementation is essentially the same as for the 1- of –
16 decoder, except that only ten decimal digits 0 through 9.
4-1
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
This type of decoder accepts the BCD code on its inputs provides outputs
to energize seven – segment display devices in order to produce a digital
readout. Fig (4 -1 ) shows a common display format composed of seven light
– emitting elements or segments. By lighting certain combinations of these
segments, each of the ten decimal digits can be produced.
a
f b
g
e c
d
APPARATUS:
U
4-2
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
PROCEDURE:
U
4-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
DISCUSSION:
U
4-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
X0
B X1
A X2
X3
B A X0 X1 X2 X3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
C B A 0 1 2 3 4 5 6 7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
4-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
A3R A2
R A1
R A0 R Y0
R Y1
R Y2
R Y3
R Y4
R Y5
R Y6
R Y7
R Y8
R Y9
R
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
INPUTS OUTPUTS
W3 R W2 R W1 R W0 R X1
R X0 R
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
W1 X0
W3
X1
W2
g h
f a
a
f b
g
e c
d
e c dp
GND
+5v (a)
a
1s a
BCD A b
b
2s c
INPUTS B c
Decoder
d
7447 d
4s e
C e
8s f
f
D g
GND g
4-7
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
OBJECT:
U
THEORY:
U
The multiplexer or data selector is a circuit that has several input lines
and a single output line. It also has control or selection inputs that permit
digital data on any one of the inputs to switched to the output line.
The circuit that performs the opposite function called demultiplexer or
decoder, which takes data from one line and distributes them to a given
number of output lines. These definitions are illustrated in Fig. (5–1). The
routing of the data is determined by additional logic signals called the select
(or address) inputs. In multiplexer IC may have an enable input to control
the operation of the unit when the enable input is in a given binary state, the
outputs are disabled, and when it is in the other state (the enable state), the
circuit function as a normal multiplexer. The enable input (sometimes called
strobe) can be used to expand two or more multiplex. Enable input digital
multiplexer with a large number of inputs. In some cases two or more
multiplexer are enclosed within one IC package.
5-1
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
Data Data
in out
output
S
Data
Input A
S
minterms m1 = R R and m 5 =
R R produce a 1 output, since the output is
1 when BC= 01 regardless of the value of A.
5-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
0 I0
4×1
1
I1 MUX Y F
A
I2 S1 S0
Ā
B
C
(a)
NUMBER A B C F
0 0 0 0 0
1 0 0 1 1
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
(b)
I0R I1 R I2 R I3
R
0 1 2 3
A 4 5 6 7
0 0 1 A
(c)
5-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
APPARATUS:
U U
PROCEDURE:
U
5-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
F = ABC + ABC + AB
DISCUSSION:
U
5-7
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
OBJECT:
U
R Q
S Q
(a)
Input Output
S R Comments
0 0 NC NC No change. Latch remains in present state
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Not allowed
(b)
Fig. (6 -1) Latch circuit with NOR gates.
(a) Logic diagram (active high) (b) Truth table
6-2
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
1 S Q
R Q
1
(a)
Input Output
S R Comments
0 0 N.C N.C No change. Latch remain in present state
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Invalid
(b)
6-3
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
2- RS FLIP – FLOP
This type of Flip – Flop constructed by adding gates to the
inputs of the basic circuit, the Flip – Flop can be made to respond
to input levels during the occurrence of clock pulse. The clocked
RS Flip – Flop shown in Fig. (6 – 3) consists of a basic NOR gate
latch and two AND gates.
The outputs of the two AND gates remain at 0 as long as the
clock pulse is 0. Regardless of the (S) and (R) input values. When
the clock pulse goes to 1, information from the (S) and (R) inputs
is allowed to reach the basic latch.
R
Q
Pulse
CLK Narrowing Positive
Circuit Spike
Q
S
(a)
6-4
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
Inputs Outputs
S R CLK Comments
0 0 X No change
0 1 ↑ 0 1 RESET
1 0 ↑ 1 0 SET
1 1 ↑ ? ? Invalid
(b)
6-5
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
S
Data D 3 1 Q
Input
Pulse
CK Narrowing
Circuit
5
4 2 Q
(a)
Data D Q
Input
CLK Q
(b)
Input Output
D CLK Comments
1 ↑ 1 0 SET (store 1)
0 ↑ 0 1 RESET (store 0)
(c)
Fig. (6 – 4) D Flip – Flop. (a) Logic diagram of D Flip – Flop
(b) Logic Symbol for D Flip-Flop (c) Truth Table
4– J – K Flip – Flop
A J – K Flip – Flop is a refinement of the RS Flip – Flop in that the
indeterminate state of the RS type is defined in the JK type. Inputs J and
K behave liked inputs S and R to set and clear the Flip – Flop (not that in
a J – K Flip – Flop. The letter J is for set and the letter K is for clear).
6-6
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
When high are applied to both J and K simultaneously, the Flip – Flop
switches to its complement state, that is, if Q = 1, it switches to Q=0, and
vice versa. The J – K Flip – Flop shown in Fig. (6 – 5) behaves like an RS
Flip – Flop, except when both J and K are equal to 1. When both J and K
are 1, the clock pulse is transmitted through one NAND gate only, the
one whose input is connected to the Flip – Flop output which is presently
equal to 1. Thus, if Q = 1, the output of the lower NAND gate becomes 0
upon application of a clock pulse and so that the Flip – Flop will be
complement it's output.
J 3 1 Q
CLK Pulse
Narrowing
Circuit
Q
K 4 2
(a)
J Q
Q
CLK
K
K Ǭ
Q
(b)
Inputs Outputs
J K CLK Comments
0 0 ↑ No change
0 1 ↑ 0 1 RESET
1 0 ↑ 1 0 SET
1 1 ↑ Toggle
(c)
Fig (6 – 5) J – K Flip – Flop (a) Logic diagram of J – K Flip – Flop
(b) Logic Symbol (c) Truth Table
6-7
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
Fig. (6 – 6) shows a J –K Flip – Flop with present and clear inputs, this
illustrates basically how these inputs are work. They can be either active
Low or active HIGH.
PRE
J Q
Pulse
Narrowing
CLK
Circuit
Q
K
CLR
(a)
PRE
J Q
CLK
K Q
CLR
(b)
6-8
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
CP CLR J K Q
X 0 1 X X ?
X 1 0 X X ?
0 1 1 X X ?
↑ 1 1 0 0 ?
↑ 1 1 0 1 ?
↑ 1 1 1 0 ?
↑ 1 1 1 0 ?
(C)
Fig. (6 – 6) J – K Flip – Flop with preset and clear.
(a) J – K Flip – Flop circuit with active LOW present and clear
(b) Logic system (C) Truth table.
5 – T Flip – Flop
The T Flip – Flop is a single – input version of the J – K Flip – Flop.
As shown in Fig. (6 – 7), the T Flip – Flop is obtained from a J – K type
if both inputs are tied together. The designation T comes from the ability
of the Flip – Flop to "toggle" or change state, it assumes the complement
state when the clock pulse occurs while input T is logic 1. The symbol
and truth table are shown in Fig. (6-7).
T Q
CLK
Q
(a)
6-9
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
Inputs Outputs
T CLK Comments
1 ↑ Toggle
0 ↑ No change
(b)
6-10
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
J Q Y J Q Q
J
Master Slave
Y
K K Q K Q Q
CLK
CP
Where K = 0
Y
Master
Q
Slave
6-11
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
APPARATUS:
U
6-12
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
6-13
University of Technology Digital Techniques Laboratory
Department of Electrical and Electronic Engineering First Year
DISCUSSION:
U
1- For a master – slave J – K Flip – Flop with the inputs below, sketch
the Q output waveform. Assume Q is initially low. Assume the Flip
– Flop accepts data at the positive – going edge of the clock pulse.
CK
J Q
J 2 : 0111010 K 2 :1101100
R R R R
CK
J 3 : 1111000 K 3 :1010101
R R R R
K Q
6-14