DIGITAL CONTROL SYSTEMS IV

Learning Guide: Second Semester 2017

Module Code: EIDBS4A

VUT
Vaal University of Technology
 Learning Guide – Digital Control Systems IV ii

INDEX

PART I Module Information

1. Word of welcome ……………..………………………….….……………… iii
2. Contact persons …………………………………………………………….. iii
3. Rationale for the module ……...……………………………………………. iii
4. Prerequisites ………………………………………………………………… iii
5. Learning material and reference textbooks .………………………………… iii
6. Assessment ……………………………………………………………...….. iii
7. Icons used in this study guide .…….………………………………...……... v

PART II Learning Units

Unit 1
1. Chapter 1 – Sampled Data Systems .…………..………………….…….…… 1-1
2. Chapter 2 – Transfer Functions …………..…………...………….….…....…. 2-1
3. Chapter 3 – Time Domain Analysis …….…………………...…………....…. 3-1

Unit 2
4. Chapter 4 – Stability Analysis ……………....….…………...………….......... 4-1
5. Chapter 5 – Root Locus Techniques ……….………...……...…………....…. 5-1
6. Chapter 6 – Digital Controller Design …….…………...……….………....…. 6-1

Unit 3
7. Project
7.1 Project outcome ……..……………...…………………….....…...…… 7-1
7.2 Project schedule ……….………………...….……………...……...…. 7-1
7.3 Assessment …………...………..……………..….....………………… 7-10
7.4 Apendix …......………...………..……………..….....………………… 7-10
 Learning Guide – Digital Control Systems IV iii

1. WORD OF WELCOME
The Department of Process Control and Computer Systems, welcomes you as a
student to the Faculty of Engineering at the Vaal University of Technology. The
department strives towards integration of existing knowledge with new knowledge and
to afford the student the ability to think logically, gain knowledge of Electrical
Engineering, and specifically Digital Control Systems, in order to make a positive
contribution to the field of Industrial Instrumentation and Electrical Engineering.
2. CONTACT PERSONS
Title and Surname Office Telephone number and e-mail address
Prof MO Ohanga (HOD) R007 016 950 9323 marcelo@vut.ac.za
Ms. R Mwale (Administrator) R007 016 950 9254 refilwem1@vut.ac.za
Mr. R Fitchat (Lecturer) S115 016 950 9432 bennien@vut.ac.za

3. RATIONALE FOR THE MODULE

On completion of this module you should be knowledgeable in the basic concepts
underlying modern digital control systems, z transforms, pulse transfer functions,
stability analysis, root locus techniques and digital controller design.
4. PREREQUISITES
A firm understanding of classical control systems as well as complex algebra, is
essential in the study of Digital Control Systems IV. It is therefore strongly
recommended that students successfully complete the courses in Control Systems III
(EIBEH III) and Mathematics II (AMISK II), before commencing with their studies in
Digital Control Systems IV.
5. LEARNING MATERIAL AND REFERENCE TEXTBOOKS
This learning guide as well as the course material and previous evaluations, will be
made available to students at the beginning of the semester.
Additional reference textbooks:
a) Ogata, Katsuhiko, Discrete-Time Control Systems.
b) Phillips C.L., Nagle H.T., Digital Control System Analysis and Design.
c) Kuo, Benjamin C., Automatic Control Systems.
d) Min J.L.,Schrage J.J., Designing Analog and Digital Control Systems.
Additional information may be available from: http://home.mweb.co.za/rf/rfitch
6. ASSESSMENT
Module assessment will take place on a continuous basis, and for this purpose the
module is divided into three units.
 Unit 1: Chapters 1 to 3 (weight = 40%)
 Unit 2: Chapters 4 to 6 (weight = 40%)
 Unit 3: Project (weight = 20%)
 Learning Guide – Digital Control Systems IV iv

i) Module assessment: To successfully complete each unit, students must receive a

unit mark of at least 50%. To successfully complete the module, students must
complete all the units. A student that successfully completes the module will
receive a module mark according to the following summative assessment schedule:
Module% = 0.4Unit1% + 0.4unit2% + 0.2unit3%
The continuous assessment programme does not allow for supplementary or
rewritten examinations. Students that fail to complete this module, must resume
their studies by completing all units again during a subsequent semester.

ii) Unit 1 assessment (1½ hour session): Assessment of unit 1 is scheduled for
Thursday 24 August 2017 at 10h00. Students that fail to receive 50% for unit 1,
will be offered a second and final opportunity to complete unit 1 on Thursday
26 October 2017 at 10h00. Students who successfully complete the final
assessment, will however receive a maximum mark of 50% for unit 1. Students
who were unable to attend the first assessment session, will receive the full mark
obtained for the final assessment of unit 1. A student that fails to receive 50% for
the final attempt to complete unit 1, fails the module. The assessment venue is
lecture room S205 (main campus), and as arranged at the Secunda campus.

iii) Unit 2 assessment (1½ hour session): Assessment of unit 2 is scheduled for
Thursday 21 September 2017 at 10h00. Students that fail to receive 50% for unit 2,
will be offered a second and final opportunity to complete unit 2 on Thursday
26 October 2017 at 11h35. Students who successfully complete the final
assessment, will however receive a maximum mark of 50% for unit 2. Students
who were unable to attend the first assessment session, will receive the full mark
obtained for the final assessment of unit 2. A student that fails to receive 50% for
the final attempt to complete unit 2, fails the module. The assessment venue is
lecture room S205 (main campus), and as arranged at the Secunda campus.

iv) Unit 3 assessment: For the purpose of assessing unit 3 (project), each student will
prepare and demonstrate a hardware simulation of a water level control system,
constructed according to the guidelines given in the learning guide for unit 3. A
clear photograph showing the project with the student’s student card (or other clear
identification), must also be available for assessment and moderation. Unit 3 will
be assessed in the lecture room, on the date and time scheduled by the lecturer.
Students that fail to receive 50% for unit 3, will be offered a second and final
opportunity to complete unit 3 on the date and time scheduled by the lecturer.
Students who successfully complete the final assessment, will however receive a
maximum mark of 50% for unit 3. Students who were unable to attend the first
assessment session, will receive the full mark obtained for the final assessment of
unit 3. A student that fails to receive 50% for the final attempt to complete unit 3,
fails the module.
 Learning Guide – Digital Control Systems IV v

v) Module Portfolio: Students will not be required to assemble a module portfolio

individually. The lecturer, however, will assemble a module portfolio that will
include all question papers and memoranda, as well as the study guide, mark sheets
and class registers. The examination office currently archives all examination
scripts in order to be available as assessment evidence for unit 1 and unit 2.
Lecturers should include each student’s project photograph in the module portfolio
as assessment evidence for unit 3. The module portfolio must be safeguarded for at
least three years for moderation purposes.

7. ICONS USED IN THIS STUDY GUIDE

1 2 3 4 5 6

Estimated Opening Outcomes Study the Practical Exam

study time remarks and following work questions
introduction passage and
thoroughly assessment
7.

Section still
under
construction
 EIDBS4 Sampled Data Systems 1-1
Learning Guide Unit 1

1. LEARNING GUIDE - UNIT 1:

SAMPLED DATA SYSTEMS

The objective of this learning unit is to introduce students to the

fundamental properties of sampled data systems.

You should spend approximately 15 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Describe the basic elements of a digital control system and the
fundamental process of sampling a continuous signal.
 Express the input output relationship of digital systems in terms of
difference equations.
 Define the impulse function and step function.
 Determine the z transform of important time functions.
 Use z transform techniques to solve difference equations.
 EIDBS4 Transfer Functions 2-1
Learning Guide Unit 1

2. LEARNING GUIDE – UNIT 1:

TRANSFER FUNCTIONS

The objective of this learning unit is to introduce students to the

methods used to determine the transfer function of single input, single
output discrete control systems.

You should spend approximately 20 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Visualise the sampling process to be composed of an ideal sampling
action followed by a hold action.
 Determine the transfer function of discrete cascaded systems and
feedback systems.
 Obtain the transfer function of a plant preceded by a zero order hold
device.
 EIDBS4 Time Domain Analysis 3-1
Learning Guide Unit 1

3. LEARNING GUIDE – UNIT 1:

TIME DOMAIN ANALYSIS

The objective of this learning unit is to introduce students to the

methods used to analyse the transient response of digital control
systems.

You should spend approximately 10 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Analyse the transient behaviour of a prototype second order
continuous system.
 Map between values in the s plane and the z plane.
 Judge the response of discrete systems by relating the essential
discrete characteristics to the properties of a similar and more
familiar continuous system.
 View the transient response of discrete systems in terms of the
position of the roots of the characteristic equation in the z plane.
 Determine the steady state behaviour of digital control systems.
 EIDBS4 Stability Analysis 4-1
Learning Guide Unit 2

4. LEARNING GUIDE – UNIT 2:

STABILITY ANALYSIS

The objective of this learning unit is to introduce students to the

methods used to establish the stability properties of digital control
systems.

You should spend approximately 10 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Use the Jury test to judge the stability of discrete control systems.
 Prescribe the set of conditions that will guarantee stable operation
of a digital control system.
 EIDBS4 Root Locus Techniques 5-1
Learning Guide Unit 2

5. LEARNING GUIDE – UNIT 2:

ROOT LOCUS TECHNIQUES

The objective of this learning unit is to introduce students to the

analysis of discrete control systems by means of root locus techniques.

You should spend approximately 15 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Construct the root locus from the characteristic equation of a
system.
 Analyse transient and stability behaviour of systems by means of the
root locus.
 EIDBS4 Digital Controller Design 6-1
Learning Guide Unit 2

6. LEARNING GUIDE – UNIT 2:

DIGITAL CONTROLLER DESIGN

The objective of this learning unit is to introduce students to some of

the techniques used to design digital controllers.

You should spend approximately 15 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:
 Improve system response with controller design based on root locus
methods.
 Determine digital forms of the PID control algorithm.
 Realize PID controllers.
 EIDBS4 Project 7-1
Learning Guide Unit 3

7. LEARNING GUIDE – UNIT 3:

PROJECT – LEVEL CONTROL
The objective of this learning unit is to give students the opportunity to
study the operation of a digital proportional and integral controller.
A water level control system will be electronically simulated.

You should spend approximately 20 hours on this learning unit.

7.1 Project Outcome

After completion of this project, students will appreciate some of the
properties of the important PI control algorithm, implemented in a
digital control environment.

7.2 Project Schedule

To complete this project, students will be required to construct a circuit
representing a water level control system. A block diagram of the
system is shown in Figure P1.

Water Control valve Manipulated variable

supply
(water inflow)
Controller
output
Controlled variable
PI control (water level)
Setpoint algorithm
Measured
(tank 50%
value of
or half full) Disturbance
water level
(float position) variable
Figure P1 (water outflow)
 EIDBS4 Project 7-2
Learning Guide Unit 3
The system must monitor the water level in the container, and use a proportional and
integral control strategy, to regulate the water inflow into the container; with the aim
to keep the water level in the tank as close as possible to the set point value (we will
assume a value of 50% for this model). The water level (or measured value) is
presented to the PI controller which calculates an appropriate value for the valve
position of the control valve (water inflow). This value will be sampled and
transmitted to the control valve, which then will adjust the water inflow accordingly.
The water inflow will then remain constant until the start of the next sampling period.

7.2.1 Container, water level and inlet

An elegant way to represent the water tank, water inflow and water outflow, is with a
capacitor and parallel resistor, fed by a current source, as shown in Figure P2. The
water level is represented by the voltage v, across the capacitor, the water outflow by
the current iL (which is proportional to the voltage across the capacitor), and the inflow
by the current i0, injected into the parallel combination. The current i0, is supplied by a
voltage controlled current source which is controlled by a voltage u that represents the
control valve pneumatic signal.

Pneumatic signal
u Current to control valve
source (represented by u) Water inflow
i0 (represented by i0)

Water level
v (represented by v)
iL

Water outflow
Figure P2 (represented by iL)

Using a 1000 F capacitor and maximum source current of 200 A, a real world
situation is simulated, where it takes in the order of one minute to fill up the tank.
Changing the water outflow will be simulated by varying the value of the resistor in
parallel with the capacitor.
Many ways exist to implement a voltage controlled current source, but the circuit in
Figure P3, built around a LM358 operational amplifier, was found to perform rather
well. The source current, i0, will vary linearly between 0 and 200 A (approx), with
the control voltage, u, varying between 0 and 8/9 volt. In order to change the simulated
water outflow iL, two 47k resistors are provided. To increase the water outflow, the
bottom 47k resistor may be short circuited.
 EIDBS4 Project 7-3
Learning Guide Unit 3

390 k

+
10 M 1.5 k i0
3 8 9V
u ½LM358
1 5 8 battery
iL 7
2 4
½LM358
47k v +
MV
6 4
1000F
(64 volt) Volt-
390 k meter
47k
10 M 0-10V

Current source Parallel RC circuit Measured value sensor

The voltage controlled The capacitor represents the water Top view
current source (i0), tank and the current iL through 8 7 6 5
represents the flow control the two 47k resistors, represents the LM358
valve in Figure P1 water outflow in Figure P1. 1 2 3 4

Figure P3

The maximum simulated water outflow with only one 47k across the capacitor
(assuming a maximum voltage of 8V across the capacitor) will therefore be 170A.
This means that the maximum simulated water inflow will always be able to
counterbalance the maximum simulated water outflow. We should therefore in
principle, retain control of the voltage level, under all circumstances.
Note: The current source (valve) and inflow current i0 (water inflow) and 1000 F
capacitor (container) work just like a simple water tap filling up a bucket with a big
hole (47k + 47 k resistors) in it. If u = 0 V (tap closed) the water level (v) will start
to drop to 0 and if u = 9 V (tap fully open) the bucket will begin to fill up (v will begin
to rise to 8/9 V). For the benefit of interested students, an analysis of the current
source circuit is given in Appendix A1.
In order to measure the capacitor voltage without disturbing the charging and
discharging process, the second operational amplifier in the LM358 package is used to
buffer the capacitor voltage, as shown in Figure P3. The output of this amplifier is the
measured value MV of the controlled variable and can be confidently measured at this
point with any voltmeter.
 EIDBS4 Project 7-4
Learning Guide Unit 3

This section of the simulation forms a unit, and students are encouraged to build and
test this section first, before proceeding with the proportional and integral control
section. The value of ‘u’ may be varied by connecting ‘u’ to the battery + rail (fill up
the tank) and by connecting ‘u’ to the battery – rail (drain the tank), as shown in
Figure P4. A small 9 volt battery will be an adequate power source for the circuit.

u = 9V and i0  200 A
MV should rise to approx. 8V

u Current
source i0 5 8
MV +
7
47k 9V
v 4
6
47k 1000F

u = 0V and i0 = 0A 0-10V

MV should fall to 0V

Figure P4

If the bottom 47k resistor is short circuited while the capacitor voltage is increasing,
the rate at which the capacitor voltage rises, will be slowed down a little bit and this
may be verified by careful observation of the voltmeter reading. Similarly, when the
capacitor voltage is going down (that is when u = 0), the rate at which the voltage
diminishes, may be accelerated by short circuiting the bottom 47k resistor. (This of
course corresponds to the behaviour of the water level in a container when the outflow
is increased while filling it up or when the water outflow is increased when draining
the vessel.)
Students that successfully complete this section of the project, demonstrating that they
can control the charging and discharging of the capacitor by switching the control
voltage (u) between plus and negative supply, will receive a minimum mark of 50%
for unit 3.

7.2.2 A proportional and integral controller

For the sake of simplicity, we will not use a digital computer to calculate the
appropriate proportional and integral control action, but rather an analog computer.
This analog device is depicted in Figure P5. The aim with this part of the project is to
establish a continuous control system and when finished, we will progress to the third
and final part of this project, when we will convert the system into a discrete system
by sampling the controller output.
 EIDBS4 Project 7-5
Learning Guide Unit 3

100 k (R2) 10 F (C)

9V
battery
100 k (R1)
10 k +
MV 2 8
1 u
SP ½LM358
3 4

10 k

Figure P5

Referring to Figure P5, the set point value, SP, is fixed and obtained as the mid point
voltage between two 10 k resistors that serve as a voltage divider. This will fix the
set point to half the battery voltage. The set point or desired value will therefore
correspond to a container that is half or 50% full. In terms of our model, this will mean
that the controller will try to drive the capacitor voltage to half the battery voltage or
50% of the maximum voltage that could develop across the capacitor.
The circuit in Figure P5 will calculate the difference between the capacitor voltage at
any moment (MV) and the desired value (SP). This will produce the error value
e=MV-SP. From this, the proper proportional and integral control action, u, will then
be computed. (Quite amazing for one op-amp, one capacitor and two resistors – credit
also to Dr. H van Rensburg for suggesting this circuit. An analysis of the controller is
given in Appendix A2.)
This section can be tested in conjunction with the first section (the same battery is
used for both sections). The controller output, u, should be connected to the input of
the current source, while the feedback loop is closed, by feeding back the measured
value, MV, to the controller. The measured value, will now be forced to follow the set
point value, according to the proportional/integral control law, established by the
controller. For clarity, a block diagram showing the connection of the controller to the
system, is shown in Figure P6.
The behaviour of the measured value MV, when a load change (or disturbance)
occurs, may be studied by putting a short circuit across the bottom 47 k resistor in
Figure P3, causing an increase in the simulated water outflow from the container.
 EIDBS4 Project 7-6
Learning Guide Unit 3

MV PI controller u Water level control MV +

(Figure P5) system (Figure P3)
9V

Figure P6
It is very interesting also to monitor the control voltage u, to observe the controller
behaviour in its effort to keep the level close to set point, when the outflow is changed.
It is safe to measure the voltage u at the output of the PI controller op-amp output in
Figure P5, without disturbing the system operation. As given in Figure P5, the
controller will produce a proportional gain setting of KP = R2/R1 = 1 and the integral
gain setting is KI = 1/R1C = 1. Students should experiment with these values (C may
be electrolytic).
Students that successfully complete the basic continuous control system, depicted in
Figure P6, and demonstrate that the measured value (MV) will be driven to set point
after switch on and revert back to set point after a disturbance (short circuiting one
47k resistor), will receive a minimum mark of 60% for unit 3.
7.2.3 Sample and hold
Again, to keep the system as simple as possible, only the controller signal (u) will be
sampled. A 555 timer will be used to supply the master clock that drives a CD4022
ring counter to provide a short high going pulse to activate one of the analog switches
in a CD4066 that together with a RC circuit and op-amp, will provide the sample and
hold function for the controller signal. This arrangement is shown in Figure P7.
The sampling clock is provided on pin 2 of the CD4022 counter. The operation of
the 555 master clock and CD4022 ring counter may be verified by connecting a LED
test probe at this point. The LED should produce a short flash every second. This
clock pulse will enable (pin 6) the third switch available on the CD4066. The
controller signal (u) is now connected to pin 8 of the CD4066 and the sampled value
will appear on pin 7. The sampled value is stored for the duration of the sampling
period via a 1 k resistor on a 10 F capacitor connected to one amplifier on a LM358
package. The sampled version of u, u*, is available at the output of this amplifier and
it may also be safely monitored with a voltmeter at this point. Some additional design
information for the 555 timer is given in Section 7.2.6 and the pin out configuration
for the CD4022 and CD4066 is given in section 7.2.5.
A block diagram of the complete system is given in Figure P8. The complete system
may derive its power from the same 9V battery. The total current consumption of the
prototype system was measured and found to be in the neighbourhood of 7 mA.
 EIDBS4 Project 7-7
Learning Guide Unit 3

1 k reset inhibit
u
1 k
5 8

10 k
7 u*
clock
6 4
8 7 6 5 16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
555 CD4022 CD4066 ½LM358
1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
9V
battery
+

T0.125s T1s
+ +
1 k
10F LED 10F

Figure P7

u u* MV

+
MV PI controller u Sample & hold u* Water level control MV 9V
(Figure P5) (Figure P7) system (Figure P3)

Figure P8
Before the signal u* is used to control the current source, it may be a good idea to
still operate the system in continuous mode and just connect the continuous output u
from the PI controller, to the input of the sampler and confirm, by monitoring the
signal u* with a voltmeter, that a discrete version of the continuous signal u, is
obtained. When satisfied that the sampler is working, the signal u* may replace u to
control the current source in a discrete fashion.
 EIDBS4 Project 7-8
Learning Guide Unit 3
A model and transfer function will be developed for this system in the future.
Students may however experiment with the PI controller. It was found with the
prototype that when C in Figure P5 was changed to 1 F, the system was still stable in
continuous mode but unstable in digital mode. The sample period was chosen to be
approximately 1 second. Changing the sampling period, is easily accomplished by
changing the RC timing components of the 555 timer. For example, changing RA (see
Figure A3 and P7) from 1 k to 100k, changes the sampling period to
approximately 7 seconds. The prototype definitely displayed instability with this
sampling period.
Students that successfully complete the project including the sampling of the
controller signal will be awarded a minimum mark of 70% for unit 3.
7.2.4 Practical note
Top view

3, 5 8 8 7 6 5

1, 7 + 9V LM358
1 2 3 4
2, 6 4

Figure P9

The LM385 package contains two operational amplifiers, with pin out configuration
as shown in Figure P9. If it is suspected that the LM385 operational amplifier is
faulty, a simple technique to check whether both amplifiers are working is to connect
each one in voltage follower mode, shown in Figure P9. If the non-inverting input is
connected to the positive supply (+9V), the output should be high (8V) while if
connected to the negative rail, the output should be zero volt. If the non-inverting
input is left open, the output should be high.
7.2.5 Pin out details for CD4022 and CD4066
4022 4066
CP1 1 16 Vcc 1X 1 14 Vcc

CP0 2 15 Reset 1Y 2 13 S1 Enable

CP2 3 14 Clock 2Y 3 12 S4 Enable

CP5 4 13 Inhibit
2X 4 11 4X
CP6 5 12 Carry out
S2 Enable 5 10 4Y
NC 6 11 CP4
S3 Enable 6 9 3Y
CP3 7 10 CP7
GND 8 9 NC GND 7 8 3X
 EIDBS4 Project 7-9
Learning Guide Unit 3
7.2.6 Additional information on 555 timer
Figure P10, shows the 555 timer connected as an astable multivibrator.

RA
Figure P10
RB

8 7 6 5
Output
555 +
1 2 3 4

time
+ Output TL TH

C T

The low period is given by: TL = 0.7RBC

The high period is given by: TH = 0.7(RA + RB)C
The total period, is given by: T = 0.7(RA + 2RB)C

7.2.7 Parts list

1×555 (timer)
2×LM358 (dual operational amplifier)
1×CD4022 (8 bit counter)
1×CD4066 (quad switch)
3×1 k (¼ watt resistor)
1×1.5 k (¼ watt resistor)
3×10 k (¼ watt resistor)
2×47 k (¼ watt resistor)
2×100 k (¼ watt resistor)
2×390 k (¼ watt resistor)
2×10 M (¼ watt resistor)
2× 10 F ( 64 V electrolytic capacitor)
110 F ( 64 V non-electrolytic capacitor)
1×1000 F ( 64 V electrolytic capacitor)
1×LED (red)
 EIDBS4 Project 7-10
Learning Guide Unit 3
7.3 Assessment Schedule
Students will prepare this project and demonstrate their work in class
on the scheduled date and time. A very clear photograph (A4 computer
printout is preferred), showing the project together with the student’s
student card (or other clear identification), will also be prepared as part
of the demonstration and assessment. A student that demonstrates a
control system in which the controlled variable manages to stay close to set point if
disturbed, will meet the required outcome for this unit, and will receive at least 50%
for unit 3.
Please note:
1. A project submitted without accompanying photo, will NOT be assessed, and a
photograph displayed on a camera or cell phone or sent via email, will not be
acceptable, as a hard copy is needed for final assessment and moderation of the
project. A well defined photo printed on a color printer (A4), is preferred.
2. Students that demonstrate a system crudely constructed on a medium such as
breadboard, with only the simulation of the container and valve operating
correctly, will receive 50 %. If, in addition, a functioning continuous PI control
system is demonstrated, 10% will be added. If, in addition, a functioning digital
control system is demonstrated, 10% will be added. If, in addition, special
attention is given to the construction (for example the circuit is assembled on
veroboard), 5% will be added. Additional marks may be awarded according to the
judgment and discretion of the assessor. Construction on PC boards will not be
allowed.
3. Students that will demonstrate a partial system, must state beforehand which part
or parts they are demonstrating so as to facilitate in proper assessing of the project.

7.4 APPENDIX
A1. Analysis of current source circuit vo
Refer to the circuit in Figure A1 R1 i0
At node N1: N3
R0
(u – v’)/R = (v’ – v0)/R1 u N1
Riu – R1v’ = Rv’ – Rv0
R v’ v”
Rv’ + R1v’ = Rv0 + R1u
v’ = (Rv0 + R1u)/(R + R1) ………...…….(1)
And at node N2: N2
(v” – v’)/R1 = v’/R R1
Rv” – Rv’ = R1v’
R
Rv” = Rv’ + R1v’ Figure A1
v” = [(R + R1)/R]v’
And using v’ from (1):
v” = [(R + R1)/R][(Rv0 + R1u)/(R + R1)]
v” = (Rv0 + R1u)/R ……………..……….(2)
 EIDBS4 Project 7-11
Learning Guide Unit 3
Finally at node N3:
(v’ – v0)/R1 = i0 + (v0 – v”)/R0  R0v’ – R0v0 = R0R1i0 + R1v0 – R1v”
R0R1i0 = R0v’ + R1v” – (R0 + R1)v0
Using now v” and v’ from (1) and (2):
R0R1i0 = R0[(Rv0 + R1u)/(R + R1)] + R1[(Rv0 + R1u)/R] – (R0 + R1)v0
R0R1i0 = [R0/(R + R1) + (R1/R)][Rv0 + R1u] – (R0 + R1)v0
Assuming now that R0 << (R + R1) and R0 << R1, then,
R0R1i0  (R1/R)(Rv0 + R1u) – R1v0  R0R1i0  R1v0 + (R12/R)u – R1v0
R0R1i0  (R12/R)u
R
i0  1 u
R R
0
A2. Analysis of the proportional and integral controller
R2 C
i

R1 vc
MV i N1
N2 u
SP

SP SP Figure A2

MV - SP
At node N1 in Figure A2: i = …….…..……………………...………… (1)
R
1
dv c
Also i = C ………………………………………...…………....…………… (2)
dt
dv cMV - SP
From (1) and (2): = ……………………………………………… (3)
dt R C
1
For loop N1N2 in Figure A2, by KVL: SP – iR2 – vc – u = 0
R
SP – 2 (MV – SP) – vc – u = 0; from (1)
R iR2 vC
1
R u
vc = SP – 2 (MV – SP) – u SP
R
1
dv c d R d du
 = (SP) – 2 (MV – SP) –
dt dt R dt dt
1
R d du
=0– 2 (MV – SP) – ; because SP = constant
R dt dt
1
 EIDBS4 Project 7-12
Learning Guide Unit 3
dv c R d du
 =– 2 (MV – SP) – ……………………………………….... (4)
dt R dt dt
1
MV - SP R 2 d du
From (3) and (4): = (MV – SP) –
R C R dt dt
1 1
du R d MV - SP R 2 d 1
 =– 2 (MV – SP) – = (SP – MV) + (SP – MV)
dt R dt R C R dt R C
1 1 1 1
We now recognise that the difference between the set point SP and the measured
value MV, is in fact the error signal e = SP – MV
du R de 1
 = 2 + e
dt R dt R C
1 1
R de R
     
du 2 dt + 1 1
 dt = edt  du = 2 de + edt
dt R dt R C R R C
1 1 1 1
R

1
u = 2 e + edt ………………………………………..………….. (5)
R R C
1 1
R 1
Therefore from (5) and with KP = 2 and KI = :
R R C
1 1

u = KPe + KI edt ……………………………………………………….….. (6)

We conclude therefore from Equation (6) that the circuit in Figure P3, provides a
R 1
PI control law with a proportional gain KP = 2 and an integral gain KI = .
R R C
1 1