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EE 598

Digital Design using Verilog


Lecture 7/8: Simulation, Timing, ModelSim
Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic, Emil Petriu, Wikipedia,
Hakim Weatherspoon, Peter M. Nyasulu, David Harris, Sarah Harris
Delay
 To simulate a circuits real world behavior it is
important that propogation delays are included.
-- Each gate has its propagation delay
 The units of time for the simulation can be
specified with timescale.
-- Default is 1ns with precision of 100ps
-- Component delays are specified as #(delay)
`timescale time_unit / time_precision;
Example
Input Signals
• In order to simulate a circuit the input
signals need to be known so as to generate
an output signal.
• The input signals are often called the circuit
stimulus.
• An HDL module is written to provide the
circuit stimulus. This is known as a testbench.
Testbench
 The testbench module includes the module
to be tested.
 There are no input or output ports for the
testbench.
 The inputs to the test circuit are defined
with reg and the outputs with wire.
 The input values are specified with the
keyword initial
 A sequence of values can be specified
between begin and end.
Testbench and Unit
Example
Initial Block
• The initial block is executed only once at
the beginning of the simulation.
• It is typically used to initialize variables and
specify signal waveforms during simulation.
initial
begin
... statements ...
end
System Tasks and Functions
 There are tasks and functions that are used
to generate input and output during
simulation. Their names begin with a sign ($).
 System tasks that extract data, like $monitor
need to be in an initial or always block.
$display, $strobe, $monitor
 Display their values as text on the screen during
simulation.
-- much less convenient than waveform display tools
-- $display and $strobe display once every time
they are executed,
-- $monitor displays every time its parameters
changes.
-- $strobe displays the parameters at the very end
of the current simulation time unit.
$display (“format_string”,par_1, par_2, ... );
$reset, $stop, $finish
 $reset resets the simulation back to time 0
 $stop halts the simulator and puts it in the
interactive mode where the user can enter
commands
 $finish exits the simulator back to the
operating system.
$random
• Generates a random integer every time it is
called.
-- For repeatable sequence, the first time one
invokes random give it a seed.
--Otherwise the seed is derived from the
computer clock.

xzz = $random[(integer)];
Synchronous Testbench
Review of D-FF
• Two inputs: CLK, D
• Function
-- The flip-flop “samples” D on the
rising edge of CLK
When CLK rises from 0 to 1, D
passes to Q
Otherwise, Q holds its previous
value
-- Q changes only on the rising edge
of CLK
• A flip-flop is called an edge-triggered
device because it is activated on the
clock edge
RTL
• In general, all signals start and end in registers
every clock period
-- RTL: Register-Transfer-Level
• In most cases, there is only one clock (in any
one sub-block of the chip) and each flip-flop is
clocked every cycle
Importance of Timing
• Flip-flop samples D at clock edge

• D must be stable when it is sampled

• Similar to a photograph, D must be stable


around the clock edge

• If D is changing when it is sampled,


metastability can occur
Metastability
• Any bistable device has two stable states
and a metastable state between them
• A flip-flop has two stable states (1 and 0)
and one metastable state
• If a flip-flop lands in the metastable state, it
could stay there for an undetermined
amount of time
Input Timing Constraints
• Setup time: tsetup = time before the clock edge
that data must be stable (i.e. not changing)
• Hold time: thold = time after the clock edge
that data must be stable
• Aperture time: ta = time around clock edge
that data must be stable (ta = tsetup + thold)
Output Timing Constraints
• Propagation delay: tpcq = time after clock
edge that the output Q is guaranteed to be
stable (i.e., to stop changing)
• Contamination delay: tccq = time after clock
edge that Q might be unstable (i.e., start
changing)
Dynamic Discipline
• The input to a synchronous sequential circuit
must be stable during the aperture (setup and
hold) time around the clock edge.

• Specifically, the input must be stable


-- at least tsetup before the clock edge
-- at least until thold after the clock edge
Dynamic Discipline
• The delay between registers has a minimum
and maximum delay, dependent on the
delays of the circuit elements
Setup Time Constraint
• The setup time constraint depends on the
maximum delay from register R1 through
the combinational logic.
• The input to register R2 must be stable at
least tsetup before the clock edge.
Hold Time Constraint
• The hold time constraint depends on the
minimum delay from register R1 through the
combinational logic.
• The input to register R2 must be stable for
at least thold after the clock edge.
Timing Analysis
Fixing Hold Time Violation
Clock Skew
• The clock doesn’t arrive
at all registers at the
same time
• Skew is the difference
between two clock
edges
• Examine the worst case
to guarantee that the
dynamic discipline is not
violated for any register
in a system
Setup Time Constraint with
Clock Skew
• In the worst case, the CLK2 is earlier than
CLK1
Hold Time Constraint with
Clock Skew
• In the worst case, CLK2 is later than CLK1
Modelsim
• Multi-language HDL simulation environment by
Mentor Graphics
• ModelSim can be used independently, or in
conjunction with Altera Quartus or Xilinx ISE.
• Simulation is performed using GUI or scripts.
• Free Student Edition
https://www.mentor.com/company/higher_ed/modelsim-student-
edition

• Tutorial:
https://www.microsemi.com/document-portal/doc_view/131618-
modelsim-tutorial

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