2014 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)
Control and Operation of Unified Power Quality
Conditioner with Battery-Ultracapacitor Energy
Storage System
Nafih Muhammad Ismail∗ , Student Member, IEEE and Mahesh K. Mishra, Senior Member, IEEE
Department of Electrical Engineering,
Indian Institute of Technology Madras, Chennai, India.
∗ Corresponding author: Tel.:+91 44 22575459; Fax:+91 44 22574402; E-mail: nafihmuhammad.i@gmail.com
Abstract—This paper proposes a new configuration of UPQC
that consists of battery and ultracapacitor connected to the
DC link through DC/DC converters for compensating voltage
and current related PQ problems. The main objective of this
configuration is to enable UPQC to mitigate voltage interruption
and reduce battery stress with the help of ultracapacitor. The
proposed UPQC can compensate current harmonics, current
unbalance, load reactive power, voltage sag, voltage swell and
voltage interruption. The Shunt inverter inject currents to ensure
a balanced, sinusoidal and unity power factor PCC current except
under source voltage interruption during which shunt inverter
operates in voltage control mode for maintaining balanced and
sinusoidal load voltage. The Series inverter inject voltages to
ensure a balanced and sinusoidal load voltage except under
voltage interruption during which series inverter is isolated from
the system. The combination of battery and ultracapacitor yield a
power source having both high energy density and power density.
Battery delivers average load power during voltage interruption
while ultracapacitor takes all the load fluctuating power. The
performance of the proposed UPQC with battery-ultracapacitor
storage system have been verified through simulation results.
Index Terms—Power quality, UPQC, Battery-ultracapacitor
hybrid storage, DC/DC converter, Voltage interruption.
I. I NTRODUCTION
In the current scenario of power industry, both consumers
and power suppliers are obliged to comply with different
Power Quality (PQ) standards proposed by international bodies
such as IEC and IEEE. Research is being carried out to
integrate active filtering devices especially the combination
of shunt and series active power filters (APF) to mitigate a
variety of PQ problems with a single device. UPQC is such a
device and it has been widely studied to mitigate the current
disturbance in load side and voltage disturbance in source side
[1], [2]. UPQC consists of a series and shunt inverter, series
inverter usually mitigates voltage related PQ problems while
shunt inverter mitigates current related PQ problems. UPQC
can compensate voltage sag and swell, however it cannot
compensate voltage interruption because it has no energy
storage devices connected to the DC link. The Battery and
ultracapacitor are two suitable energy storage devices that can
integrate with UPQC for mitigating voltage interruption.
In [3], a UPQC topology with ultracapacitor (UCAP) con-
nected to its DC link is proposed for mitigating voltage
interruption. The ultracapacitors are becoming popular for its
978-1-4799-6373-7/14/$31.00 ©2014 IEEE
high power density compared to battery and it can respond
very quickly to high fluctuating power. But, the low energy
density of ultracapacitor makes it not suitable to supply the
average load demand for longer time. Battery on the other hand
has high energy density, which makes it suitable for delivering
power for longer duration. The battery charge and discharge
are slower and hence, it is not suitable for highly fluctuating
load demand. A battery-ultracapacitor hybrid storage [4], [5]
is suitable for delivering power to fluctuating loads.
In this paper, a UPQC topology with battery and ultraca-
pacitor connected to its DC link through DC/DC converter
is considered. The DC/DC converter is used to actively
control the power flow between battery, ultracapacitor and
the UPQC DC link, thereby enhancing the power capability
of the system. UPQC mitigates voltage sag, voltage swell,
voltage interruption, load reactive power, load unbalance and
harmonics. Ultracapacitor can respond to sudden DC link
voltage fluctuations, therefore it is controlled in such a way
that the DC link voltage fluctuations are reduced under all
disturbances. Diverting highly fluctuating current from battery
to ultracapacitor reduces battery stress and increases battery
cycle life. Compensating grid voltage interruptions along with
reduced battery stress and extended energy storage device life
are the major considerations of this paper.
This paper is organized as follows. A UPQC with battery-
ultracapacitor energy storage system topology and its op-
eration methodology are explained in Section II. Battery-
ultracapacitor energy storage and its DC/DC converter mod-
elling are given in Section III. Section IV describes the control
algorithm of the proposed system. Simulation results are given
in Section V. The conclusions are given in Section VI.
II. UPQC WITH BATTERY-U LTRACAPACITOR E NERGY
S TORAGE S YSTEM
A. System Topology
The power circuit of the proposed UPQC with battery-
ultracapacitor energy storage system is shown in Fig. 1. UPQC
consists of a series inverter, a shunt inverter, series injection
transformer, DC link capacitor and filter circuits. The three leg
series APF injects voltage according to source voltage level
to maintain a balanced sinusoidal load voltage. The four leg
shunt inverter injects current to the PCC such that the source
 2

vt
vsa Rs Ls isa vfa vla ila i'la Start

N vsb Rs Ls isb vfb vlb ilb i'lb n Yes Yes Shunt APF in current control mode
0.9 d Vs d 1.1pu Series APF OFF
Rs Ls isc vfc vlc ilc i'lc No
Yes Vdc< Vdc(low)
vsc isn iln Battery charges until it
Battery reaches maximum SOC
Cse Cse Cse i'ln standby No
ifa ifb ifc ifn Cf Cf Cf Ultracapacitor charges
Lse Lse Lse Lf
Discharge until it reaches 90%
Lf Lf Lf ultracapacitor Battery charges until it reaches
Rse Rse SOC
Rse maximum SOC
Rf Rf Rf Rf Yes Shunt APF in current control mode
Yes
1.1<Vs d 1.5pu Series APF in voltage control mode

Yes Vdc< Vdc(low) No

Saa Sbb Scc Sa Sb Sc Sd Battery discharges until it reaches
Vdc Discharge minimum SOC
Cdc Ultracapacitor No Shunt APF in voltage control mode
Vs ! 1.5pu Yes
Charge Series APF is isolated from the system
S'aa S'bb S'cc S'a S'b S'c S'd
Ultracapacitor Ultracapacitor charges/discharges
according to the DC link voltage
No
fluctuations
SB1 SSC1
Lb Lsc Yes Yes Battery standby mode
0.5 d Vs <0.9pu
Ib Isc Yes Shunt APF in current control mode
+ + Vdc< Vdc(low) Series APF in voltage control mode
Vbatt Cb SB2 SSC2 Vsc No
Discharge No
Ultracapacitor Ultracapacitor Vs  0.5pu Yes
standby mode
Fig. 1. Power circuit of UPQC with battery ultracapacitor hybrid storage. No

Fig. 2. UPQC operation with battery-ultracapacitor energy storage.

current is maintained balanced, sinusoidal and unity power
factor. The DC link voltage is maintained by the shunt APF
by drawing active power from the source. The neutral leg
of shunt inverter maintains the source neutral current zero.
Capacitor Cf eliminates the switching frequency components
from the load voltage during voltage interruption. An un-
balanced nonlinear load is connected to the system. Battery
and ultracapacitor (UCAP) are connected to the DC link
through DC/DC converters, these converters actively control
the charging and discharging of energy storage devices.
B. Methodology of UPQC
ultracapacitor Energy Storage
The use of battery in this UPQC topology enables UPQC
to mitigate voltage interruption. The operations strategy of
battery, ultracapacitor and UPQC is shown in Fig. 2. Ultraca-
pacitor reduces the stress on the battery and deliver or absorb
energy during sag/swell conditions. Source voltage in per-unit
is represented by Vs . During normal voltage condition (0.9 ≤
Vs ≤ 1.1 pu), the series inverter injects no voltage and shunt
inverter injects required current to mitigate load current power
quality problems. Apart from that, the shunt APF maintains
the DC link voltage by drawing power from the source. A
lower limit is set for DC link voltage (Vdclow ) below which the
UPQC performance is not satisfactory. When DC link voltage
is above this limit and source voltage is normal voltage,
battery and ultracapacitor charges. The maximum SOC of
ultracapacitor is limited to 90% due to safety considerations.
If the DC link voltage goes below the lower limit due to large
disturbances, battery goes to standby mode and ultracapacitor
discharges to support shunt inverter for bringing back the DC
link voltage to rated value. Thus a fast recovery of DC link
voltage can be achieved through this control.
During voltage sag condition (0.5 ≤ Vs < 0.9 pu), series
APF injects voltage to maintain load voltage balanced and
sinusoidal while shunt APF injects current to mitigate load
current PQ problems and also shunt inverter tries to maintain
DC link voltage at rated value. During voltage sag battery goes
to standby mode and ultracapacitor charging and discharging
is determined by the DC link voltage level. The operation
of the system during voltage swell (1.1 < Vs ≤ 1.5 pu)
condition is same as that during voltage sag except battery
charges during voltage swell condition. Compensation of deep
sag require highly rated series inverter and associated injection
transformer and filters. Hence the system works in voltage
interruption mode when source voltage goes below 0.5 pu
or above 1.5 pu (Vs < 0.5 or Vs > 1.5 pu). During voltage
interruption condition the series inverter is isolated from the
Operation with Battery- system while shunt inverter operates in voltage control mode
to maintain load voltage balanced and sinusoidal. Battery
discharges to deliver power to the load through shunt inverter
while the sudden load fluctuations are handled by the ultraca-
pacitor to reduce the battery stress.
III. BATTERY-U LTRACAPACITOR E NERGY S TORAGE AND
DC/DC C ONVERTER
The battery and ultracapacitor are used as energy storage
devices and connected to the DC link of UPQC through
bidirectional DC/DC converters.
A. Battery Model
A lead acid battery with low capacity is used to show
the SOC variations within the small simulation time. Battery
model available in the Matlab/Simulink library is used and the
parameters are chosen to best fit the typical lead acid battery
charge and discharge curves [6], [7].
B. Ultracapacitor Model
Ultracapacitor model available in Matlab/Simulink library
is used for simulation [8]. Simulink model parameters are
selected to suit Maxwell ultracapacitor data sheet parameters
[9]. The maximum energy exchanged with ultracapacitor is
 3

given by (1) which is used for calculating capacitance value The Ploss term is generated using a PI controller to include the
(Csc ). losses. Hysteresis current control [12] is used for generating
1 2 2
switching pulses for shunt inverter. Series inverter operates
Esc = Csc (Vsc − Vscmin ). (1) in voltage control mode. The method of instantaneous sym-
2
metrical component is used for the extraction of symmetrical
C. Parameter Selection of Bidirectional Converter components of source voltages and the complex Fourier coef-
The inductor and capacitor values of bidirectional buck- ficients [13] are used for the extraction of fundamental com-
boost converters determine the correct operation of the con- ponent of source voltages. The equation for source terminal
verters. During buck mode of operation, the filter inductance voltage fundamental positive sequence extraction is given in
and capacitance are given by (2) and (3) respectively [10]. (7).
√  t1 +T
(Vdc − V )D1 + 2 vta + a vtb + a2 vtc −j(ωt− π )
L = (2) V ta1 = e 2 dt. (7)
ΔIf T t1 3
ΔI +
C = . (3) V ta1 is a complex quantity, its magnitude represents rms
8ΔV f
value of fundamental positive sequence terminal voltage and
Where, V is the voltage across low voltage side of the con-
argument represents the phase angle of fundamental positive
verter. During boost mode of operation, the value of inductor
sequence a-phase terminal voltage. Similarly negative and
and capacitor are given by (4) and (5) respectively.
zero sequence components can be calculated for detecting
unbalanced voltage sag and swell. If the source terminal
V D2
L = (4) voltages are balanced, then equation (7) can be modified as
ΔIf given in (8).
ID2
C = . (5) +
ΔV f V ta1 = Vt1  −θ1 . (8)
The highest value of inductance from equations (2) and (4) is Where, Vt1 is rms value of fundamental positive sequence
taken as converter inductance for reducing current ripple and terminal voltage and −θ1 is the phase angle of fundamental
the highest value of capacitance from equations (3) and (5) positive sequence terminal voltage. The series inverter refer-
is taken as converter filter capacitance for reducing voltage ence voltages can be written as given in (9). SPWM control
ripple. is used for generating switching pulses for series inverter. The
sag/swell detection circuit compares the fundamental positive
IV. C ONTROL A LGORITHM
sequence magnitude gets from (8) with the set values for
Overall control strategy of proposed UPQC with battery- detecting source voltage sag, swell and interruption.
ultracapacitor storage system can be divided into two parts,
the first part is control during normal voltage, voltage sag and √
voltage swell and the second part is control during voltage vf∗a = 2Vl sin(ωt − θ1 ) − vta
√
interruption. During voltage sag, swell and normal voltage vf∗b = 2Vl sin(ωt − 2π/3 − θ1 ) − vtb (9)
conditions, UPQC mitigates voltage and current related PQ √
vf∗c = 2Vl sin(ωt + 2π/3 − θ1 ) − vtc .
problems while battery and ultracapacitor operate according
to source voltage and DC link voltage levels. During voltage Where, Vl is the load voltage rms value.
interruption only shunt inverter of UPQC is operating while The battery and ultracapacitor charging and discharging are
battery discharges and ultracapacitor charge or discharge ac- determined by the DC link, source voltage levels and SOCs.
cording to DC link voltage fluctuations. The battery and ultracapacitor DC/DC converter control during
normal voltage, voltage sag and swell is shown in Fig. 3.
A. Control of Proposed System During Normal Voltage, Battery discharges only during voltage interruption.
Voltage Sag and Swell
Shunt APF operates in current control mode. Instantaneous B. Control of Proposed System During Voltage Interruption
symmetrical component theory [11] is used for generating The equivalent circuit of UPQC with battery-ultracapacitor
shunt inverter reference current which is shown in equation storage system during voltage interruption is shown in Fig. 4.
(6). The abc phase leg of shunt inverter operates in voltage control
 
∗ vla mode to maintain a sinusoidal voltage at the load terminal. The
if a = ila −  2 (Plavg + Ploss ) neutral leg of shunt inverter operates in current control mode
j=a,b,c vlj
  to make the current through filter capacitors (Cf ) balanced.
∗ vlb Equation (10) gives the load voltage reference during voltage
if b = ilb −  2 (Plavg + Ploss ) (6)
j=a,b,c vlj interruption.
  √ 
∗
∗ vlc vla = 2Vl sin(ωt + θ)
if c = ilc −  2 (Plavg + Ploss ) ∗
√ 
j=a,b,c vlj vlb = 2Vl sin(ωt − 2π/3 + θ) (10)
√ 
i∗f n = −(ila + ilb + ilc ). ∗
vlc = 2Vl sin(ωt + 2π/3 + θ) .
 4

PI -Ib* PI Db PWM
SOCb(ref)

+
itotal

+
-
Controller
-
Controller SB1
Controller PI Current rate
Vdcref i*batt

+
-
Saturation Saturation Controller Limiter
-1 *
SOCb i batt
Ib itotal -
Vdc i*sc

+
(a) 0 SB2
Dbatt SB1
-Isc* Dsc i*batt PI PWM

+
PI PI PWM -
Controller Controller
SOCsc(ref) Ssc1

+
+

- - SB2
Controller Controller Controller
Saturation Saturation
Saturation
-1 Ib
SOCsc
Isc
(b)
0 Ssc2 Dsc SSC1
i*sc PI PWM

+
-
Controller Controller SSC2
PI Isc* PI Dsc PWM
Vdcref Ssc2
+

Saturation
+

- -
Controller Controller Controller
Isc Isc
Saturation
Vdc (c) 0 Ssc1

Fig. 6. Control of battery and ultracapacitor DC/DC converters during voltage

Fig. 3. (a) Battery charging control (b) Ultracapacitor charging control (c) interruption.
Ultracapacitor discharging control.


V. S IMULATION S TUDIES
Time t = 0 at the instant of supply voltage interruption. Angle
For the complete UPQC compensated system shown in
θ is the synchronizing angle which can be calculated from the
Fig. 1, a simulation study is conducted using Matlab/Simulink
instantaneous value of load voltages at the instant of supply
to verify its operation under different operating conditions. The
voltage interruption. The reference current for neutral leg can
circuit parameters are given in Table I.
be calculated as given in equation (11).
Figs. 7(a)-(d) represent the source terminal voltage, load
 voltage, load current and source current respectively during
i∗ln = −iln . (11) normal voltage condition. Shunt APF injects current such that
the source current is maintained balanced, sinusoidal and unity
Fig. 5 shows the shunt inverter control scheme during voltage power factor as shown in Fig. 7(d). Figs. 7(e)-(i) represent
interruption. The series inverter is isolated from the system DC link voltage, battery discharge current, UCAP discharge
during this period. Fig. 6 shows the control scheme of battery- current, battery SOC and UCAP SOC respectively. Battery
ultracapacitor hybrid storage during voltage interruption. The and ultracapacitor converters are switched ON at 0.05 s. The
rate limiter block limits the battery discharge current rate. The initially charged UCAP discharges at 0.05 s to bring DC link
energy storage system is controlled in such a way that, average voltage to rated value as shown in Fig. 7(g). After DC link
current for maintaining DC link voltage is delivered by battery voltage reaches rated value, battery and UCAP start charging
while the fluctuating current is delivered by the ultracapacitor. as shown in Fig. 7(h) and Fig. 7(i) respectively.
A 50% voltage sag from 0.14 to 0.28 s is simulated and
the results are shown in Fig. 8. Figs. 8(a)-(d) represent the
Unbalanced
source terminal voltage, load voltage, source current and load
Sa Sb Sc Sd vl load current respectively. It is evident from Fig. 8(b) and Fig.
SB1 SSC1
Rf Lf ila i'la Rla Lla
Rf Lf ilb i'lb ' 8(c) that, load voltage is maintained balanced and sinusoidal
Lb Lsc
DC Link Rlb Llb n i ln
Ib
Vdc Cdc R f Lf ilc i'lc Rlc Llc by series APF and source current is maintained balanced,
Isc
+
Vbatt Vsc+
Rf Lf iln sinusoidal and unity power factor by shunt APF. Figs. 8(e)-(i)
Cb
SB2 SSC2
S'a S'b S'c S'd Cf Cf Cf represent DC link voltage, battery SOC, ultracapacitor SOC,
icfn
UPQC Shunt Inverter
TABLE I
Fig. 4. Power circuit of system during voltage interruption. S YSTEM PARAMETERS FOR S IMULATION S TUDY

Parameter Value
UPQC Shunt UPQC DC link Vdc , Cdc 700 V, 2000 μF
inverter Lf R il(abc) vl i'l(abc)
SB1 SSC1 f Unbalanced Utility grid voltage 400 V (L-L)
Lb Ib Lsc Vdc +
- Lf Rf iln load i'ln Fundamental frequency 50 Hz
Vbatt+ Cb
Isc +
Vsc Sa to Sc S'a to S'c SdS'd
Feeder resistance, inductance 0.05 Ω, 0.01 mH
SB2 SSC2
iln i'ln Shunt APF Lf , Rf , Cf 20 mH, 4 Ω, 80 μF
Hysteresis i * Neutral Current Series APF Lse , Rse , Cse 1.1 mH, 1.6 Ω, 200 μF
ln
vt(abc) Symmetrical Current Reference Shunt APF hysteresis band 0.1 A
Voltage Enable
Components SPWM Controller Calculation
Calculation
interruption
Controller v*l(abc) Enable
Battery voltage, capacity 300 V, 20 mAh
Detection
v a Battery converter Lb , Cb 35 mH, 60 μF
| va1 | Control v*l(abc) UCAP voltage, capacitance 251 V, 0.35 F
Fundamental signal
Positive Load voltage Angle calculation Load voltage UCAP converter inductance 30 mH
Sequence ‘va1
reference calculation at the instant of T reference calculation Za = 100+j 20 Ω
Component
Extraction
for series inverter voltage interruption for shunt inverter Zb = 75+j 47 Ω
sin(Zt  ‘v a1 )
Unbalanced nonlinear load Zc = 55+j 24 Ω
3-φ diode bridge rectifier
Fig. 5. Shunt inverter control strategy during voltage interruption. with R-L (100 Ω - 1 H) load
 5

350 700
vta additional stress on shunt inverter for maintaining DC link

Voltage (V)
Voltage (V)

DC Link
Terminal

0
500 voltage. During voltage sag, UCAP supports shunt inverter for
300
0.1(e) 0.2 0.3 Time (s) 0.5
maintaining DC link voltage which is shown in Fig. 8(g) and
-350
0.1 0.12 Time (s) 0.14 (a) 0.16 0 Fig. 8(i). At 0.14 s (sag occurrence instant) UCAP suddenly

Current (A)
350
Load Voltage (V)

Battery
vla -4 discharges to reduce the DC link voltage fluctuations which is
0 -8 shown in Fig. 8(i).
0.1(f) 0.2 0.3 Time (s) 0.5
0
A 45% voltage swell from 0.14 to 0.28 s is simulated

UCAP Current (A)

20
-350
0.1 0.12 Time (s) 0.14 (b) 0.16
and the results are shown in Fig. 9. Figs. 9(a)-(d) represent
0
15 the source terminal voltage, load voltage, source current and
Load Current (A)

ila
10 -20
0 0.1(g)0.2 0.3 Time (s) 0.5 load current respectively. It is evident from Fig. 9(b) and Fig.
0 90
9(c) that, load voltage is maintained balanced and sinusoidal

SOC (%)
Battery
-10
-15
by series APF and source current is maintained balanced,
0.1 0.12 Time (s) 0.14 (c) 0.16 85
sinusoidal and unity power factor by shunt APF. Figs. 9(e)-
Source Current (A)

20 0 0.1(h)0.2 0.3 Time (s) 0.5

isa (i) represent DC link voltage, battery SOC, ultracapacitor
UCAP SOC (%)
50
0
40
SOC, battery discharge current and ultracapacitor discharge
-20
current respectively. During voltage swell, battery continues its
30
0.1 0.12 Time (s) 0.14 (d) 0.16 0 0.1(i) 0.2 0.3 Time (s) 0.5 charging as shown in Fig. 9(f) and Fig. 9(h). UCAP suddenly
discharges at 0.14 and 0.28 s to reduce the DC link voltage
Fig. 7. Simulation results during normal voltage condition: (a) Source
terminal voltage (b) Load voltage (c) Load Current (d) Source current (e) fluctuations which is shown in Fig. 9(i).
DC link voltage (f) Battery discharge current (g) Ultracapacitor discharge The load details used for voltage interruption simulation
current (h) Battery SOC (i) Ultracapacitor SOC. study is given in Table II. A voltage interruption from 0.1 to
350
0.4 s is simulated and the results are shown in Fig. 10. The
vta source terminal voltage is shown in Fig. 10(a). The sensitive
Voltage (V)
Terminal

0 nonlinear load is switched OFF during voltage interruption. In

order to verify the operation of battery-ultracapacitor hybrid
-350
0.1 0.15 0.2 Time (s) 0.25 0.3 0.35
400 vla
Load Voltage (V)

Load Voltage (V) Terminal Voltage (V)

500
vta
325
0
0

325
-400 -500
0.1 0.15 0.2 Time (s) 0.25 0.3 0.35 0.1 0.15 0.2 Time (s) 0.25 0.3 0.35
Source Current (A)

15 isa 325
vla

0 0

15
325
0.1 0.15 0.2 Time (s) 0.25 0.3 0.35 0.1 0.15 0.2 Time (s) 0.25 0.3 0.35
ila
Source Current (A)

15
Load Current (A)

15 isa
10
0
0

-15 -10
-15
0.1 0.15 0.2 Time (s) 0.25 0.3 0.35 0.1 0.15 0.2 Time (s) 0.25 0.3 0.35
87 98
Battery SOC (%)
Battery Current (A) DC Link Voltage (V)

ila
UCAP SOC (%)

Load Current (A)

700 10
96
86
94 0
600 85 92
-10
84 90
0.05 0.14 0.3 0.4 0 0.14 0.3 0.4 0 0.14 0.3 0.4
Time (s) Time (s) Time (s) 0.1 0.15 0.2 Time (s) 0.25 0.3 0.35
Battery Current (A) DC Link Voltage (V)

90 95.3
Battery SOC (%)
UCAP Current (A)

UCAP SOC (%)

0 30
700
88 95.2
20
-5 690 86 95.1
10
680 84 95
-10 0 0.1 0.2 0.3 0.4 0.1 0.2 0.3 0 0.1 0.2 0.3 0.4
0 0.05 0.14 Time (s) 0.3 0.4 0 0.05 0.15 Time (s) 0.3 0.4 Time (s) Time (s) Time (s)
0 20
UCAP Current (A)

Fig. 8. Simulation results during voltage sag: (a) Source terminal voltage
(b) Load voltage (c) Source Current (d) Load current (e) DC link voltage -5 10
(f) Battery SOC (g) Ultracapacitor SOC (h) Battery discharge current (i)
Ultracapacitor discharge current. -10 0
0.1 0.2 0.3 0.4 0.1 0.2 0.3 0.4
Time (s) Time (s)

Fig. 9. Simulation results during voltage swell: (a) Source terminal voltage
battery discharge current and ultracapacitor discharge current (b) Load voltage (c) Source Current (d) Load current (e) DC link voltage
respectively. Battery goes to standby mode during voltage (f) Battery SOC (g) Ultracapacitor SOC (h) Battery discharge current (i)
sag as shown in Fig. 8(f) and Fig. 8(h). This is to avoid Ultracapacitor discharge current.
 6

TABLE II
L OADS FOR VOLTAGE INTERRUPTION SIMULATION currents and require quality voltage and uninterruptible power.

Linear Za = 100+j 20 Ω
unbalanced load Zb = 75+j 47 Ω
VI. C ONCLUSION
Zc = 55+j 24 Ω (connected all the time) Conventional UPQC cannot compensate voltage interrup-
3-φ diode bridge rectifier
Nonlinear load with R-L (100 Ω - 1 H) load
tions without an additional energy sources. Integration of
(disconnected during voltage battery and ultracapacitor with UPQC provides an effective
interruption) solution to overcome this issue. To effectively work in different
Linear balanced load Z= 150+j 30 Ω voltage conditions, control algorithms for proposed UPQC
(connected from 0.3 to 0.4 s)
with battery-ultracapacitor energy storage system was devel-
oped. A detailed simulation study was conducted to analyse the
400 vta
Terminal voltage (V)

combined operation of UPQC and battery-ultracapacitor hy-

brid during different voltage disturbances. From simulations, it
0
was found that the system were giving desired results in all the
-400
cases. During voltage interruption, the battery and ultracapaci-
0.06
vla
0.1 0.2 Time (s) 0.3 0.4 0.45 tor was controlled in such a way that the ultracapacitor took all
325
Load voltage (V)

the DC link fluctuations while battery deliver average power.

0 Adding ultracapacitor reduced the depth of discharge (DOD)
and stress on the battery. This improves the battery cycle life.
-325
The proposed UPQC with battery ultracapacitor hybrid energy
0.06 0.1 0.2 Time (s) 0.3 0.4 0.45
10
storage system has the capability to mitigate source voltage
Load current (A)

sag, swell, interruption, load current harmonics, load current

0 reactive power and load current unbalance.
i'lc
-10
0.06 0.1 0.2 Time (s) 0.3 0.4 0.45
R EFERENCES
5
[1] G. Jianjun, X. Dianguo, L. Hankui, and G. Maozhong, “Unified power
Load Power (kW)
Battery current (A) DC link voltage (V)

700
quality conditioner (upqc): the principle, control and application,” in
Power Conversion Conference, 2002. PCC-Osaka 2002. Proceedings of
690 2 the, vol. 1. IEEE, 2002, pp. 80–85.
[2] H. Fujita and H. Akagi, “The unified power quality conditioner: The
680
0.1 Time (s) 0.3 0.4 0.5
0
0 0.1 Time (s) 0.3 0.4 0.5 integration of series active filters and shunt active filters,” in Power Elec-
10 tronics Specialists Conference, 1996. PESC ’96 Record., 27th Annual
UCAP current (A)

5 10
0 Power, vol. 18, no. 4, pp. 327–343, April 2007.
0 0.1 Time (s) 0.3
Fig. 10. Simulation results during voltage interruption: (a) Source terminal
voltage (b) Load voltage (c) Load current (d) DC link voltage (e) Average
load power (f) Battery discharge current (g) Ultracapacitor discharge current.
storage under fluctuating load condition, a balanced linear
load is switched ON at 0.3 s. The load current variation
and load average power are shown in Fig. 10(c) and Fig.
10(e) respectively. During voltage interruption, shunt inverter
maintains load voltage sinusoidal and balanced as shown
in Fig. 10(b). The DC link voltage variation is shown in
Fig. 10(d). The battery and ultracapacitor discharge currents
are shown in Fig. 10(f) and Fig. 10(g) respectively. During
voltage interruption, battery delivers average load power. The
control scheme limits the battery discharge rate and the highly
fluctuating current required for maintaining DC link voltage
is delivered by ultracapacitor as shown in Fig. 10(f) and Fig.
10(g). Battery-ultracapacitor storage system can be effectively
utilized in fluctuating load environments. In this case the
ultracapacitor increases the battery cycle life considerably and
the frequent battery replacement can be avoided. The UPQC
with battery-ultracapacitor can be effectively used when there
is a highly fluctuating load which is drawing non-sinusoidal
15
IEEE, vol. 1, Jun 1996, pp. 494–501 vol.1.
[3] B. M. Han and B. Bae, “Unified power quality conditioner with super-
capacitor for energy storage,” European Transactions on Electrical
5
0 [4] R. Sathishkumar, S. K. Kollimalla, and Mahesh K. Mishra, “Dynamic
0.4 0.5 0 0.1 Time (s) 0.3 0.4 0.5 energy management of micro grids using battery super capacitor com-
bined storage,” in India Conference (INDICON), 2012 Annual IEEE.
IEEE, 2012, pp. 1078–1083.
[5] L. Gao, R. Dougal, and S. Liu, “Power enhancement of an actively con-
trolled battery/ultracapacitor hybrid,” Power Electronics, IEEE Transac-
tions on, vol. 20, no. 1, pp. 236–243, Jan 2005.
[6] The MathWorks Inc., “Implement generic battery model,”
2013. [Online]. Available: http://www.mathworks.in/help/physmod/sps/
powersys/ref/battery.html
[7] O. Tremblay, “Experimental validation of a battery dynamic model for
ev applications,” World Electric Vehicle Journal, vol. 3, 2009.
[8] “A gouy-chapman-stern model of the double layer at a (metal)/(ionic
liquid) interface,” Journal of Electroanalytical Chemistry, vol. 613,
no. 2, pp. 131 – 138, 2008.
[9] Maxwell Technologies Inc., “Ultracapacitors overview,” 2013. [Online].
Available: http://maxwell.com/products/ultracapacitors.html
[10] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics.
Converters, Applications and Design, 3rd ed. John Wiley and Sons,
Inc, 2003.
[11] U. Rao, Mahesh K. Mishra, and A. Ghosh, “Control strategies for load
compensation using instantaneous symmetrical component theory under
different supply voltages,” IEEE Trans. on Power Del., vol. 23, no. 4,
pp. 2310–2317, 2008.
[12] D. M. Brod and D. Novotny, “Current control of VSI-PWM inverters,”
IEEE Trans. on Ind. Appl., vol. IA-21, no. 3, pp. 562–570, May 1985.
[13] Ghosh, A and Ledwich, G., “Load compensating DSTATCOM in weak
ac systems,” IEEE Trans. on Power Del., vol. 18, no. 4, pp. 1302–1309,
Oct. 2003.