A Test Chip Approach To Routine Process Control

Rochester Institute of Technology
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3-1-1988
A Test chip approach to routine process control

Eric J. Meisenzahl
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A..IEST CHIP APPROACH
TO ROUTINE PROCESS CONTROL
by
Eric J. Meisenzahl
A Thesis Submitted
in
Partial Fulfillment
of the
Requirements for the Degree of
MASlER OF SCIENCE
In
Electrical Engineering
Approved by: Prof. Lynn F. Fuller

Dr. L. Fuller (Thesis AdvisOl;
~
Prof. R. Turkman
Dr. Ri. turkman (Committee)
Prof. S. Ramanan
Dr. S. Ramanan (Committee)
DEPARTMENTOFELECIRICALENGINEERING
COLlEGE OF ENGINEERING
ROCHESlER INSTl1UIE OF lECHNOLOGY
ROCHESlER, NEW YORK
MARCH, 1988
I
PREFACE
In the manufacturing (or Research and Development) of today's
integrated circuits, a large majority of the time seems to be given to
the technical advancement and performance of a device over a
competitors device. The on-going struggle is to produce the fastest
chip using the smallest (and densest) geometries with the lowest
power. New and novel circuits are born every day to perform a
function never implemented before.
To be the first to demonstrate a technology is certainly
desirable for many reasons. One is that it becomes a very powerful
marketing tool because the general public perceives the company
with initial device announcement as being the best. Another reason
is that the device becomes the reference standard for all future
generations.
But what if you cannot fabricate this device with the yields
necessary to deliver at a cost effective rate? Unless you have a
captive market and are not subject to competition, or the number of
units to be delivered is low, this is a very serious question.
Unfortunately, the question is answered many times when delivery

time lines have slipped and large investments have been made
trying to produce the device. Wouldn't it have been nice if detailed
process capabilities and limitations were known at the time of device
conception? To know what the processing lab was capable of doing

in the past is not beneficial (assuming a continual increase in
fabrication quality exists in the lab). The point which I present is
11
that as much attention needs to be focused on the manufacturing
ability of a design at the early stages of device conception. To
determine the manufacturing ability of a fabrication facility requires
process control and yield data from whatever means possible. It is
'process
control'
the topic of which this thesis targets.
Before I jump into and address these issues, I would like to
define the following terms which will be referenced throughout this
report.
PROCESS -
The series of fabrication steps required to define
integrated circuits.
PROCESS AREAS -
The areas responsible for the fabrication of a
circuit such as Furnace, Clean, Lithography, Metalization, Ion

Implantation and Etching.
RUN -
A group of device wafers processed at the same time with the
same process throughout the time of fabrication.
PROCESS CONTROL -
The techniques used by the process areas during
fabrication to evaluate and quantify processing steps. An
'control'
example might be to insert a virgin wafer called a into
'control'
a furnace during an oxidation and then analyzing the
for thickness and refractive index using ellipsometry. This
data is then assigned or associated to that run.
PROCESS YIELD -
The fraction of wafers meeting the designed
specifications at a given processing step.
in
A study was subsequently launched to (1) evaluate present
process control techniques, (2) find out what could be done to
improve those techniques and (3) to determine a vehicle in which to
evaluate process capabilities without actually having to make a
device (which will become important as explained later). Surveys
were conducted of process engineers at a fabrication facility to
determine which critical parameters were necessary to monitor and
control that would indicate current process quality. From these
discussions, it was determined that interactions between processing
steps are equally important. Current techniques of process control
were analyzed along with their effectiveness in describing actual run
parameters as well as projecting process limitations and yields.
'test'
It was deduced that an electrically testable chip was
necessary that would require very short processing times and was
capable of generating data that isolated and quantified key
processing parameters and interactions. It was also determined that
careful thought as to the layout and selection of test structures would
be required to make evaluation and testing quick, yet conclusive to a
wide assortment of process materials and variations.
The following document describes, in detail, the steps and
factors that went into designing the test chip. Included are the
design tools used, the reticle and mask making (and formats used),
fabrication of three different processes for evaluation, test system
and testing algorithms, an analyses of the data, and a conclusion of
IV
this concept of process control. Lastly, a brief word on future work
in this area as well as some after thoughts on the ideas presented.
The main thrust of this document is towards MOS based
processing. Bipolar processing, however different, still uses the same
processing equipment and basic physical properties as does MOS and
thus, when talking process control, really applies to both
technologies.
ABSTRACT
A procedure for determining process control and yield
prediction is presented which primarily serves to evaluate the
quality and repeatability of critical fabrication steps, but also serves
to quantify process capabilities and limitations for future design
considerations. This can be accomplished through the use of a
specially designed test chip. The test chip is designed for use in
determining the process control and fabrication capability of the
Microelectronic Engineering Department's fabrication lab of Rochester
Institute of Technology.
vi
TABLE OF CONTENTS
Page
List of Tables viii
List of Figures ix
I Introduction 1
II Literature Search 3
111 Integrated Circuit Editor (ICE) 1 0
IV Mask Making 1 2
V Test Structures 1 5
VI Chip/Wafer Layout 39
VII Process Descriptions 43
VIII Test Systems 47
IX Test Programs 54
X Process 1 Data Analysis 70
XI Process 2 Data Analysis 79
XII Process 3 Data Analysis 84
XIII Conclusion 9 1
XIV Future Directions 94
XV References 96
XVI Bibliography 100
Appendix A: Fabrication Survey 104
Appendix B: Mask Making Procedures 106
Appendix C: Capacitor Theory and Algorithms 109
Appendix D: Process Detail 119
Appendix E: Process 1 Detailed Data 125
vn
TABLE OF CONTENTS (cont.)
Page
Appendix F: Process 2 Detailed Data 130
Appendix G: Process 3 Detailed Data 137
Appendix H: Error Code Reference Chart 146
Appendix I: CV Custom Circuitry Detail 148
Appendix J: CV Test Program 15 6
Appendix K: DC Automatic Probing Test Program 176
vm
LIST OF TABLES
Page
tl Mask Dimensions 1 4
t2 van der Pauw Dimensions 25
1 3 Line Width Dimensions 27
14 Serpentine Dimensions 29
t5 Comb Dimensions 3 1
t6 Fabrication Survey 104
17 Process 1 Data Printout 12 6
t8 Process 1 Statistics Printout 127
1 9 Process 2 Data Printout 131
1 10 Process 2 Statistics Printout 1 33
1 1 1 Process 3 Data Printout 13 8
1 1 2 Process 3 Statistics Printout 140
11 3 CV Custom Circuitry U03 FPLA Table 1 54
11 4 CV Custom Circuitry U12 FPLA Table 155
IX
LIST OF FIGURES
Page
f1 Probe Pads 1 6
f2 Alignment Marks 1 7
f3 Resolution Charts 1 8
f4 Verniers 20
f5 Capacitor test structure 23
f6 van der Pauw test structure 25
f7 Electrical Line Width test structure 27
f8 Serpentine test structure 29
f9 Comb test structure 3 1
flO Contact Hole test structure 33
fli Contact Resistance/Diode test structure 35
f1 2 Etchback test structure 37
f1 3 Step Coverage test structures 38
fl4 Chip Layout 40,41
f 15 Wafer Layout 42
f1 6 Process Flow Charts 46
f1 7 CV Test System 49
f1 8 DC Automatic Probing Test System 53
f1 9 CV Test Flow Chart 60
f 20 DC Automatic Probing Test Flow Chart 68
f2 1 Process 1, 2, 3 Program Flow 69
f22 Capacitor Size vs. Field Breakdown (Process 1) 74
f23 Capacitor Breakdown Yield (Process 1) 74

LIST OF FIGURES (cont.)
Page
f 24 Serpentine/Comb Yield (Process 1) 77
f 25 Contact Hole Size Yield (Process 3) 8 8
f26 Serpentine/Comb Yield (Process 3) 89
f27 CVPlot 1 1 3
f2 8 CVBT Plot 1 14
f29 CTPlot 1 1 5
f3 0 Zerbst Plot 1 1 6
f3 1 Deep Depleted CV Plot 1 1 7
f3 2 Doping Profile Plot 1 1 8
f3 3 TOX1 Histogram (Process 1) 128
f3 4 TOX1 Wafer Map (Process 1) 1 29
f3 5 TOX1 Wafer Map (Process 2) 134
f3 6 TOX2 Wafer Map (Process 2) 135
f37 TOX1-TOX2 Wafer Map (Process 2) 1 36
f38 LW15_1000 Wafer Map (Process 3) 141
f39 LW30.100 Wafer Map (Process 3) 142
f40 Contact Resistance Wafer Map (Process 3) 143
f4 1 Diode IV Curve (Process 3) 1 44
f42 Diode Breakdown Histogram (Process 3) 145
f42 Error Code Reference Chart 147
f43 CV Custom Circuitry Power/Layout/Parts 150
f 44 CV Custom Circuitry Outputs 15 1
f 45 CV Custom Circuitry Inputs 152
f46 CV Custom Circuitry Relays and Switches 153
XI
I -
INTRODUCTION
'controls'
Many process control techniques involve the use of
which are usually unpatterned virgin wafers inserted into a run
before various processing steps. These controls are then evaluated
using the appropriate test techniques and the derived process
parameters are then reported as synonymous to the run they were
associated with.
The problem with this technique is that many times the control
does not accurately reflect the actual device parameter. In the case
where a gate oxide is grown over a previously grown gate (as is

'control'
common in CCD devices), a bare silicon will not represent the
final thickness on the device and thus, the measurement now
becomes a relative quantity rather than an absolute quantity. What
is meant by a relative quantity is that at some time a correlation
must be made between the measured control and what actually
ended up on the device. This correlation is what determines where
'controls'
process control stands. Many of these are measured using
optical or non-contact methods, (i.e. ellipsometry, optical line width
monitors, etc) which can be accurate for some aspects of the device
but unfortunately give no insight as to the electrical characteristics.
Electrical characteristics, after all, are the only quantities that
determine if the device is going to function properly or not.
'Controls', in general, are still extremely useful and should always be
used because they offer rapid information feedback to process

engineers and can detect relative changes from previous
performance.
Another technique of process control and yield prediction is to
evaluate parameters on finished device wafers. Granted, this is the
most accurate form of process control, but forces process engineers to
wait for the run to complete processing to before receiving feedback.
Process errors and deficiencies can go undetected for long periods of
time before being discovered and corrected. This means that runs
passing an errant or deficient step in the meantime are likely to have
similar problems and could possibly be ruined.
So there seems to be a discontinuity of process control between
having rapid feedback with little or no electrical content (and
sometimes questionable values) from 'controls', and accurate
electrical characterization with long lead times from finished device
wafers. The test chip approach to routine process control attempts to
bridge this discontinuity by combining the desirable traits of rapid
feedback with electrical characterization.

II -
LITERATURE SEARCH
How does this in-

one go about determining what to put on
process control test chip, considering all the variables and processes
involved in making an integrated circuit (IC)? To start with, a
survey was conducted of process engineers at a fabrication facility.
The survey consisted of gathering first hand information of the key

components of IC fabrication and what was most important to
control. Table t6 found in Appendix A is a list of many of the
comments received along with the current routine control tests
performed as well as comments from others1,2.
It was somewhat surprising to see how much visual, non
electrical, and otherwise qualitative or manual type testing is
performed to determine eventual device performance. Many of
these parameters could be easily quantified and characterized from
properly designed test structures. Routine visual inspections are
effective in detecting only gross defects and are not easily or
accurately quantified. Some tests, such as ellipsometry, contain no
electrical content and do not reflect future processing effects on the
film. Electrical characterization can determine much more
information about a process step or steps that would be otherwise
'invisible'
to optical or visual type tests. Other tests such as four
point probe mapping (which is an electrical test) has significantly

improved process control but still has difficulty measuring low dose
materials.
It was identified that several degrees of measurement
sampling would be necessary in order to clearly monitor process
parameters on the test chip. Process engineers were not comfortable
with limited or single point measurement samples and, in general,
the more data points the better. The type of sampling discussed here
is chip to chip, wafer to wafer and run to run (or as a function of
time) samplings. To oblige with these types of concerns would most
certainly involve some sort of automatic data gathering system.
It was also identified that a series of varying feature sizes of
appropriate test structures would be beneficial in determining the
lateral dimension of processing. An example of this is designing a
series of contact hole size test structures above and below the
current design rule limit. This would provide valuable information
for future design considerations and provide a scale with which to
gauge process capabilities over time.
Once key issues of process control were identified, the difficult
task of designing a system that would effectively characterize
processes without long lead times could start. It is called a system
because many different disciplines would be required to make these
ideas work. Disciplines such as IC design and layout, processing,
testing and failure analysis would all have to work together in order
for this concept to be effective. The sequence of (1) fabricate the test
chip, (2) test the device and (3) analyze/record data must be
completed in a minimal amount of time yet provide accurate and
conclusive results.
A literature search of suitable test structures and algorithms
commenced. A criteria for the selection of appropriate test
structures was established based on the previous discussions. These
included that the test structure must:
1) Require no more than three masking steps. This limits the
amount of
processing steps and thus limits the time required
for completion at the expense of increased characterization. No
attempt is made to make a transistor.
2) Not require extremely sensitive or sophisticated (and therefore
expensive) test meters and equipment. By keeping test
parameters within easily obtainable levels insures that
measurements are repeatable and conclusive.
3) With the exception of capacitance measurements, all
measurements must be DC in nature. This limits the amount
and kind of equipment necessary for test and also means that
structures can be easily automated.
4) Require no more th n four I/O (input or output) pins plus
substrate for test. This number was selected primarily because
one test structure requiring a very large area was desired. The
test pads (or probe pads) should be large and their layout
should be consistent with all test structures so that a single
probe placement could be used.
5) Be consistent with the capabilities and technologies of the RIT
Microelectronic Department's fabrication facility (namely the 4-
Level PMOS Process3).

One of the first and foremost electrical test structures for
determining process control has to be the MOS capacitor. The use of
MOS capacitors for evaluating and characterizing MOS processes has
been around since the conception of the field effect devices. The
evolution of the MOS capacitor as an analytic tool may have started
from the work of Terman4, who from the suggestions of Moll,

investigated the effects of surface and interface states (from a new
solid state device he called the MOS diode) using the capacitance-
voltage (CV) relationships of the device. As the MOS and Bipolar
oologies grew, CV analysis of MOS capacitors played an
important role in the understanding and advancement of these
technologies. The number of tests and parameters that can be
extracted from MOS capacitors reveals just how powerful a test tool
the device can be5'6,7. It was also preferred to do CV tests because of
their non-destructive nature over others that were destructive.
There were still difficulties in using these tests, however, because the
theory used to derive parameters consisted of complicated
algorithms and many times required data extraction from curve
plots. Today, with the introduction of inexpensive (but powerful)
computers and instrumentation, CV testing algorithms can be
performed with a large degree of accuracy, efficiency and
repeatability8,9'10. Some of the most commonly used forms of CV
analysis used in routine process control are (1) high frequency CV
plotting for determining oxide thickness, fixed oxide charge,
substrate doping, threshold and flat-band voltage etc.5-6, (2) CVBT

tests for determining mobile ion contamination5
'9'n, (3) CT or carrier
lifetime plotting for heavy metal contamination and surface
states5-12'13'14, and (4) dopant profiling of the substrate15-16.
Another useful electrical test structure that can be easily
fabricated and quickly evaluated is the cross sheet resistor or van
der Pauw test structure. In the late 1950's, van der Pauw introduced
his concept of measuring the sheet resistance of an arbitrarily
shaped disc17. This theory has allowed for the determination of film
conductivity for a wide range of materials and conductance levels to
a certain degree18. The evolution of this measurement led to the
development of the electrical line width test structure which has now
been widely used for many years. By knowing the sheet resistance
of a conducting line, the line width of that line may be determined19,
which when coupled with an automatic data gathering system, allows
for a powerful tool in evaluating lithographic/etching performance.
line intra-
Shorting mechanisms and width continuity, whether
level or inter-level are particularly useful to know because they

often determine a large component of yield. Various test structures
have been designed to quantify these shorting mechanisms and
limitations20*21'22*23
evaluate design rule (among many) and usually
incorporate some form of serpentine or comb test structures.
Serpentine and comb test structures determine intra-level shorting
mechanisms -
the serpentine looks to see if line width can be
maintained in the presence of topography or planar conditions while
comb test structures evaluate spaces in the presence of

topography
or planar conditions. Two different levels of conducting layers (one
be determine inter-
could the substrate), in assorted configurations,
level shorting mechanisms of the layers.
Structures such as contact holes with varying contact sizes
serves to determine via and contact technology21,23, by simply
evaluating whether current will flow through two conducting levels
contacted by a lithographically defined via region. Configuring a
contact hole as a four terminal contact resistor (much like a cross
resistor but with two different conducting levels) allows the
measurement of contact resistance between the two levels24.
PN junctions or diodes, which are used in every integrated
circuit, have long been modeled, characterized and documented25'26.
Diode tests determine the ability of a process to make good PN
junctions by characterizing features such as (1) the diode doping,

which can be determined from van der Pauw tests, (2) the contact
resistance between the diode and the contacting conductive material,
which can be determined from the contact resistance test structure,
(3) reverse breakdown voltage, (4) forward dynamic resistance and
(5) threshold voltage. Items (3), (4) and (5) can be determined on
any structure that is capable of making contact to both sides of the
PN junction.
Also of great benefit is the ability to electrically determine
photolithographic alignment or registration errors between two
levels using devices such as bridge structures. The investigation of
these structures was intentionally omitted for this project, however,
8
due it's RIT and that of
to inconsistency with the process capability
the test chip.

Ill INTEGRATED CIRCUIT EDITOR (ICE)
The design phase of the project begins with ICE27. ICE is a
computer aided design (CAD) tool residing on RIT's VAX central
computer network. ICE consists of a user definable workspace area
in which a circuit is drawn out on. The test chip uses the maximum
5000uM x 5000uM grid for layout. The layout is accomplished by

'drawing'
rectangles of differing colors (representing the different
masking levels) of the appropriate size and position. These
rectangles eventually define the patterning of films on wafers into
the desired integrated circuits. Maximum drawing resolution of ICE
is luM and is limited to rectangular shapes. Alignment keys and
resolution (or reference) patterns are placed on each level at this
time also to provide assistance during fabrication. The files
generated for the test chip can be found in the RIT Microelectronic
Engineering Department's MICROLIB account in the sub-directory
EJM3561.
A total of five masks were designed that targeted three key

areas of fabrication of the 4-Level PMOS process. Namely, these
include Process 1 -
conductors on insulators on silicon (one masking
step), Process 2 -
conductors on etched back insulators on silicon
(two masking steps), and Process 3 -

diffusions or ion implants into
the substrate and contacts (three masking steps). The five mask
levels that were identified to accomplish this were labeled as 1 -
METAL, 2 -
OXIDE, 3 -
CC (contact), 4 -
DIFF (diffusion), and 5 -
EXTRA (a second metal mask). Since the RIT IC lab was to be the
10
fabrication facility of choice for the project, a lOuM design rule limit
was agreed upon. This did not mean that all line widths and spaces
would be lOuM or larger, but rather this would be a point at which
yield would be evaluated above and below the design rule limit.
1 1
IV -
MASK MAKING
'MANN'
Once layout is complete, each level is converted into
files (the format used by the MANN mask making equipment) which
are ASCII (American Standard Code) representations of the XY
coordinates of each rectangle drawn in ICE. These files are converted
to ticker tape format using a Teletype terminal interfaced to the VAX
computer where the ICE drawings were constructed.
The ticker tape can then be read by the MANN 3000 Pattern
Generator. The pattern generator creates master reticles that are ten
times absolute drawn dimensions on ICE. Master reticles are high
resolution photographic glass plates that are exposed on a
programmable XY stage according to the data on the ticker tape and
then developed. Exposure and XY travei . both controlled by the
MANN 3000.
The master reticles used for the test chip were IMTEC POL-
EDGED H.R.P. HIGH RESOLUTION PLATES TYPE 1A and measured
3x3x.06" 'normal'
in dimension. A positive or developing process is
used for all master reticles. A descripric f the developing process
and mask making settings are included in Appendix B. In addition, a
marks'
set of 'fudicial were exposed on each master reticle for
photorepeating.
The photorepeating procedure accomplishes two tasks. The
first is that the lOx reticle is reduced to lx size or actual drawn ICE
dimensions. This is obtained by aligning the post-developed master
marks'
reticle using the 'fudicial and focusing the reticle images onto
12
another photosensitive glass plate which eventually becomes the
photolithographic mask for IC patterning and exposure. The
photorepeater used was the MANN 3000 photorepeater. The mask
plates used were IMTEC POL-EDGED HIGH RESOLUTION PLATES TYPE

4x4x.06"
1A measuring in dimension. The second task repeats the
above process over and over again except in different unexposed
areas. This is accomplished by an automatically controlled XY stage
(which holds the mask) and exposure trigger which are all user
defined. The result is a grid of perfectly repeated and non-
overlapping exposures of the reduced lOx reticle. See Appendix B
for details.
It was predetermined that positive lithography would be used
to fabricate the test chip because that was the lithographic process
most widely used in the RIT lab. Since the developing of masks is
determined by the type of lithography used (positive or negative),
some masks were developed positive (normal) or negative
(reversed). See Appendix B for details.
The actual mask dimensions (after the mask making
procedure), as measured on a Nanometrics Nanoline line width
measuring system, versus ICE drawn dimensions are included in
table tl. Measurements were made using the resolution charts
which will be explained later. Notice that the three masks developed
'reverse'
with the processing (OXIDE, METAL, EXTRA) all have line
widths that are lower than designed whereas the two masks
'normal'
developed (CC, DIFF) had line widths that were larger than
13
designed. Even though the masks are not exactly as desired, this
study will consider all results as if the mask dimensions were as
designed to avoid significant complexity and confusion in evaluating
data. Conclusions will, however, summarize the effects of these
discrepancies where appropriate.
Mask ICE Size Mask Size
OXIDE 2uM 1.3uM
6uM 4.5uM
lOuM 8.3uM
METAL 2uM
6uM 4.2uM
lOuM 7.4uM
DIFF 2uM 3.3uM
6uM 6.8uM
lOuM 11.2uM
CC 2uM 3.3uM
6uM 6.2uM
lOuM 10.4uM
EXTRA 2uM 1.6uM
6uM 5.0uM
lOuM 8.7uM
Table tl -
Mask Dimensions
14
V -
TEST STRUCTURES
The following section describes the selected test structures
included on the test chip and an explanation of what their purpose is.
The design considerations that went into the finalized design are
stated and explained here also. Particulars such as ICE filenames,
test type (optical or electrical), the process number activating the
test structure and the parameters generated by the test (as found in
the test programs) are listed. The methods of test and testing limits
of the parameters due to design or measurement limitations will be
discussed in Section IX under Test Programs.
(1) -
PROBE PADS
Purpose -
Determine the fixed size and spacing of probing pads
in which electrical stimuli are applied and measurements are made
for all electrically testable structures as seen in Figure fl.
ICE file(s): bondpad.cif
Test structure(s): None
Test type: None
Process: 1,2,3
Test parameter(s): None
The size of the probe pads are large (lOOuM x lOOuM) which
reduces the risk of probing failures28. Spacing between the pads are
also large to allow room for test structure layout. The number of
pads (four) was chosen to allow for testing of a large group of square
capacitors in which the contact is made at the four corners and to
15
allow for easier manual
probing capability. This layout is maintained
throughout the design so that a generic test system setup may be
used to characterize the

all electrical test structures. Numbering of
pads is also shown.
100uM 100uM
100uM
iOCuM 300uM
300uM
Figure fl -
Probe Pads
(2) -
ALIGNMENT MARKS
Purpose -
To align masks during photolithographic exposure
steps as seen in Figure f2.
ICE file(s): ccmark2.cif, difmrk2.cif, difmrk3.cif
exmrk3.cif, metmrkl.cif, oxmrkl.cif
Test type: Optical
Process: 2,3
The alignment marks used were identical in form and size to
those found in the RIT MICRO.LIB macros3. Their size and shape are
such that masking levels are easily aligned even if line widths or
16
etching are out of control. Small marks are made nearby to assist the
user in aligning the correct mask to the correct process. There are no
alignment marks in process 1 (because it is only one masking step),
one set in process 2 between the OXIDE and METAL masks, and two
sets in process 3 between CC and DIFF masks and between EXTRA
and DIFF masks.
"* 108 jM ?
12uM
,
t
2
I o
U 12uM
I
12uM
MASK LEVEL N MASK LEVEL N+1
Figure f2 -
Alignment Keys
(3) -
RESOLUTION CHARTS
Purpose -
To provide assistance to the process engineer during
photolithographic and etching steps to optically determine line width
and patterning as shown in Figure f3.
ICE file(s): oxideres.cif, ccres.cif, diffres.cif
extrares.cif, metalres.cif
17
Test type: Optical
Process: 1,2,3
Each of the five masking levels has a pair of resolution charts
to optically gauge photoresist patterning and etching performance
during processing. Although these charts are non-electrical tests,
they are useful as a quick check during processing. They consist of 2,
4, 6, 8 and lOuM lines and spaces running in both X and Y directions
to evaluate any possible orientation effects. Each line width in the
series consists of four legs of which two of the legs are extended
beyond the others to observe the effect of lithography or etching

'loading'
performance to proximity geometries -
sometimes called a
effect.
io
CO
2 4 8 10
Figure f3 -
Resolution Charts
(4) -
VERNIERS
Purpose -
To assist the process engineer during photoresist
patterning to optically gauge alignment accuracy as seen in Figure f4.
18
ICE file(s): verccxO.cif, verccxl.cif, verccyO.cif
verccyl.cif, verdiffx.cif, verdiffy.cif
verextx.cif, verexty.cif, vermetx.cif
vermety.cif, veroxx.cif, veroxy.cif
Test type: Optical
Verniers are similar in function as alignment marks except that
they provide a visual measure of alignment accuracy. They consist
of two parts which I will call the right hand side (RHS) and the left
hand side (LHS) as seen in f4. The RHS or clear section reside on the
masking level after the mask level of the LHS or shaded section. The
LHS consists of lOOuM x lOuM lines that are equally spaced lOuM
apart. A tab is placed at the center line (CL) for user registration
purposes. The RHS consists of identical lOOuM x lOuM lines but are
spaced equally by lluM. The CL of both sections are drawn in ICE to
be perfectly aligned. The way the test structure works is that, with
perfect alignment during processing, the two CL's should line up
exactly and is read as OuM misalignment. If there is exactly luM of
misalignment, then the line indicated as -i-luM (or -luM

depending
on direction) will be perfectly aligned with the line above (or below)
the LHS section's CL and is read as +luM (or -luM) misaligned. Both
X and Y verniers are included at each appropriate masking level.
Resolution of luM was chosen because of ICE resolution limitations.
With X and Y misalignment values, it is possible to generate 2
19
dimensional vectors to describe wafer or die-die variability provided
you have the time and desire to map this out manually. There are no
verniers for Process 1 (only one masking step), one set for process 2
between the OXIDE and METAL masks, and three sets for Process 3
between CC and DIFF masks, between EXTRA and DIFF masks and
between CC and EXTRA masks.
100uM 100uM
-*~4-
3 +3uM
1 +2uM _ _
o
c
o
c 1 +1umE |
Hi 3 0 uM-g =
m
2 3 -1uMS
(0
3 -2uM
J -3uM
Mask level n Mask level n+1
_ + + +
OJ INJ -*
-*
M OJ
c c c c c c c
2 S 2 S 2 2 2
Figure f4 -
Verniers
(4) CAPACITORS
Purpose -
Capacitors are used to determine a large number of
parameters related to metal, oxide and silicon (MOS) behavior and
properties. See Figure f5.
ICE file(s): caps.cif
Test structure(s): CAP1, CAP2
Test type: Electrical
20
Process: 1,2,3
Test parameter(s): Fcapl_200, Fcapl_400, Fcapl_600
Fcapl_800, Fcap2_200, Fcap2_400
Fcap2_600, Fcap2_800, Toxl, Tox2
Delta_tox, Defect_density
(Other parameters determined during
CV testing are found in Appendix C)
There are four capacitors measuring 200 x 200uM, 400 x
400uM, 600 x 600uM and 800 x 800uM. Their layout is such that
the same probe card or probe spacing can be used as all the other
test structures. The sizes of the capacitors were chosen for two
reasons. The first is that sufficient area is required to make
capacitance measurements reliably

-
too small a capacitor can result
in difficult capacitance measurements (which will also be dependent
on oxide thickness). On the other hand, too large a capacitor area can
result in enough oxide leakage current to cause measurement errors
'track'
due to oxide pinholes or the inability of the capacitor to the
small AC signal generated by the capacitance meter at a given
frequency. Process 1 uses two sets of these capacitors but only one
set is tested automatically -

the other is extra. Process 2 uses two
sets also, of which one set is used to monitor an etched oxide and the
other is used to monitor the unetched oxide (see Section VII -
Process Descriptions). Process 3 uses only one set of capacitors.
The amount of useful and relevant process parameters that can
be generated from capacitors is extensive. Appendix C contains the
21
theory and algorithms used to deduce the various parameters of this
study.
Oxide breakdowns on capacitors are used to determine the
voltage at which the oxide passes current. The field breakdown,

which is defined as the breakdown voltage divided by the oxide
thickness is reported to incorporate the effect of oxide thickness.
This value is useful in determining safe operating voltages as well as
reliability. With the varying capacitor sizes, a study of area versus
breakdown can be analyzed which, with enough samplings, one can
determine minimum pinhole densities. Minimum pinhole densities
are defined as the percentage of capacitors that have less than
2MV/cm breakdown field divided by the area of the given capacitor.
'minimum'
It is termed density because more than one defect could
lie beneath a single capacitor. Area/perimeter ratios versus
breakdown voltage can help determine where on a capacitor
breakdown may be occurring (corners, centers etc.).
CV or capacitance versus voltage plots (of which their are many
different varieties) of MOS capacitors are extremely useful in process
control and are widely used in the industry. These plots can
determine such parameters as oxide thickness, flat-band and
threshold voltages, fixed oxide charge, mobile ion and heavy metal
contamination, doping profiles, minority carrier lifetimes and others
(see Appendix C). These plots allow the process engineer to evaluate
the MOS process as a whole as well as determine various qualities of
the metal, oxide or silicon separately. They do, however, sometimes
22
require apparatus in addition to a capacitance meter (such as light
tight fixtures, temperature chucks etc.). Because of the nature of CV
testing, automated test algorithms must contain extensive error
checking and error recovery. For this study, a separate automatic
(non-stepping) test system was used to determine CV behavior and
is described in Section VIII- Test Systems. Within the DC Automatic
Probing Test System, oxide thickness tests are incorporated and
described in Section VIII also.
200 x 200uM
Figure f5 -
Capacitor Test Structure
(6) van der PAUW
Purpose -
To measure the sheet resistance of a conducting
material as shown in Figure f6a and f6b.
ICE file(s): vdpw60.cif, vdpw20.cif
Test structure(s): VDPW1, VDPW2
23
Process: 1,2,3
Test parameter(s): Sheet_rhol, Sheet_rho2
The test chip contains two versions of these test structures.
Many considerations are taken into account when using or designing

the van der Pauw such as symmetry, joule heating, photovoltaic
effects and bulk, surface and oxide leakage currents18. The test
structure consists of four symmetrically oriented legs which are
joined in the center. The measurement is made such that a current
(I) is passed through one adjacent pair of legs while the voltage
difference (V) is measured between the other pair. The sheet
resistance is determined from theory17

to be:
4.53 V/I [ohms/square] [1]

Rs =
The dimensions of the two van der Pauw test structures follow ASTM
standards18. These standards are such that Bm>=6Dm, Am>=5Xj and
Cm>=5Xj (where Xj is the junction depth if applicable) as defined on
the masks and as seen in f6a and f6b. Bm is the distance between
the current carrying pads and the voltage sensing pads while Cm is
the physical distance between the voltage sensing pads. These
dimensions help minimize the possible errors due to the design
considerations listed earlier. Because the van der Pauw is a
potentiometric test, measurements are insensitive to contact
resistance at the current carrying and voltage sensing contacts.
24
.Am Em Cm. Dm
VDPW1 20uM 60uM lOOuM lOuM 60uM 0.333 0.167 2.0
VDPW2 180uM 360uM lOOuM 20uM 20uM 9.000 1.000 9.0
Table t2 -
van der Pauw Test Structure Dimensions
van der Pauw 1 van der Pauw 2
Figure f6a Figure f6b
(7) ELECTRICAL LINE WIDTH
Purpose -
To determine the line width of conductors by
electrical means as seen in Figure f7a and f7b.
ICE file(s): lw30-100.cif, lwl5-1000.cif
Test structure(s): Linewidth 1, Linewidth2
Process: 1,2,3
Test Parameter(s): lw30_100, lwl5_1000
the design considerations are the same as found in the

Many of
van der Pauw test structures because it is a similar type
potentiometric test. In particular, ASTM standards dictate that
Wm>=3Dm, Bm>=2Wm, Am>=5Xj and Cm>=5Xj as shown in f7. By
25
knowing the actual drawn mask dimensions, one can then deduce
from the measurement the amount of lithographic and etching
effects on line widths. The measurement is made such that a current
(I) is passed through the two current carrying legs (labeled II and
12) while the voltage difference (V) is measured between the two
voltage legs (labeled VI and V2). The line width can then be
calculated by first knowing the sheet resistance measured from the
van der Pauw. From theory19:
W,iewidth = RsLmI/V [uM] [2]

and
W delta =
Wmask -
Wiinewidth [uM] [3]
where: Wunewidth => Electrical line width [uM]
Rs Sheet resistance [ohms/square]

Distance between voltage tabs [uM]
W delta Overetch or out-diffusion [uM]
" mask Mask drawn line width [uM]
The lwl5_1000 line width test structure, as seen in f7b, has a much
longer current carrying path to follow than the lw30_100. This is to
allow for measurements of very low resistance materials (such as
aluminum lines) by allowing for a higher voltage drop between the
two voltage measuring nodes.
26
AID Bm Cm Dm Wm Lm # squares between VI. V2
Linewidth 1 30uM 65uM lOOuM lOuM 30uM lOOuM 3.333

Linewidth 2 85uM 25uM 141uM 5uM 15uM lOOOuM 66.667
Table t3 -
Line Width Test Structure Dimensions
Am
Wm
Linewidth 1 Linewidth 2
Figure 7a -
LW30_100 Figure 7b -
LW15.1000
(8) -
SERPENTINES
Purpose -
Serpentine test structures are used to evaluate the
ability of a process to make conducting lines as seen in Figure f8.
ICE file(s): serp5.cif, serplO.cif, serpl5.cif
Test structure(s): SERP5, SERP10, SERP15

Process: 1,2,3
Test Parameter(s): Serp5, SerplO, Serpl5
The test structure consists of a long conductor (of desired line
width) that coils back on itself -

thus the name 'serpentine'. The test
is simply to measure the impedance between the two ends of the
conductor assuming that surface and substrate leakages are
27
negligible. If the impedance is high, then it can be assumed that the
conductor was broken somewhere in the chain due to etching,
lithography or other reasons. If a resistive value is obtained (which
will depend on sheet resistance, line length and line width) then it
can be assumed that the conductor has been successfully fabricated.
The pitch or spacing of the lines should be large compared to
the line width itself to insure that it is line integrity that is evaluated
as opposed to space integrity. This reduces the probability that
defects, generated during the lithographic or etching steps, will not
'bridge'
cause a shorting between two adjacent conductors which
could result in a leakage path other than intended. If the sheet
resistance, line width and line length were known, one could
determine if bridging did occur by comparing the predicted
impedance against the measured impedance. For most cases,
however, it is simply necessary to know that a fault occurred.
A series of three serpentines are used for the test chip with
line widths of 5, 10 and 15uM. The spacing of the lines is fixed at
40uM meaning it would take a defect at least 40uM in diameter to
have a probability of causing faulty readings. All three processes use
this test structure -

Process 1 and 2 use the serpentine to monitor
conductors on oxide on silicon and Process 3 monitors diffusions in
the substrate.
28
Test Structure Linewidth Pitch Line length # Squares
SERP5 5uM 45uM 41,325uM 8265
SERP10 lOuM 50uM 41,410uM 4141
SERP15 15uM 55uM 41,265uM 2751
Table t4 -
Serpentine Dimensions
4000uM
[
I
[
[
[
Linewidth =
5, 10, 15uM
Figure f8 -
Serpentine Test Structure
(9) -
COMBS
Purpose -
Comb test structures are used to evaluate the ability
of a process to make spaces as seen in Figure f9.
ICE file(s): comb5.cif, comblO.cif, combl5.cif
29
Test structure(s): COMB5,COMB10,COMB15
Process: 1,2,3
Test Parameter(s): Comb5, ComblO, Combl5
The test structure consists of a pair of interleaving

'combs'
of
conductors separated by a predetermined spacing and thus are not
electrically connected by design. The test is simply to measure the
impedance between the two pairs of combs assuming that surface
and substrate leakages are negligible. If the impedance is high, then
it can be assumed that the space between the combs was maintained.
If a resistive value is obtained then it can be assumed that a
'bridge'
conducting has occurred somewhere in the chain due to
photolithographic or etching defects.
The line width of the conductors that make up the combs
should be large compared to the space between the combs. This is to
insure that it is space integrity that is evaluated as opposed to line
integrity. This reduces the probability that defects, generated during

'open'
the lithographic or etching steps will not cause an arbitrary in
the comb lines which may result and skew the results.
A series of three combs are used for the test chip with spaces
of 5, 10 and 15uM. The line width of the conducting combs is fixed
at 40uM meaning it would take a defect at least 40uM in diameter
to have a probability of causing faulty readings. All three processes
use this test structure -

Process 1 and 2 use the comb to monitor
conductors on oxide on silicon and Process 3 monitors diffusions in
30
the substrate. The COMB 10 structure on the DIFF mask has a
masking defect that cuts out part of the 'comb'. This defect does not
render the structure useless but rather, it reduces the area in which
the structure evaluates.
Test Structure Comb spacing Pitch Space length
COMB5 5uM 45uM 35,680uM
COMB 10 lOuM 50uM 35,680uM
COMB 15 15uM 55uM 35,680uM
Table t5 -
Comb Test Structure Dimensions
4000uM
10, 15uM
40uM
Figure f9 -
Comb test structure
(10) -
CONTACT HOLES
Purpose -
To determine the ability of a process to make various
size contact holes or via cuts as seen in Figure flO.
31
ICE file(s): contactl.cif, contact2.cif
Test structure(s): CONTl,CONT2
Process: 3
Test Parameter(s): Cont3,Cont5,Cont7,ContlO,Contl2,Contl5
There are two contact hole test structures that are active only
for Process 3 wafers. This is achieved by forming a diffused or ion
implanted region which acts as one node for the measurement. An
overlying and overlapping conductor is used as the the other node.
The two nodes are joined by the contact hole. If the contact hole is
made as designed, a resistive short should occur between the two
nodes. If an open circuit is detected, the contact was not resolved
and thus capability is exceeded. Both test structure layouts are such
that a single connection is made to the overlying conductor allowing
three contact hole size tests per structure using the remaining three
pads. The size of the contacts consist of 3 x 3uM, 5 x 5uM, 7 x 7uM
in CONT1 test structure and 10 x lOuM, 12 x 12uM, 15 x 15uM in
CONT2 test structure. The diffused regions should be reversed
biased with respect to the substrate to avoid unwanted leakage
paths. It is also important to keep all diffusions a good distance from
each other to avoid the depletion regions from meeting each other.
32
3 x 3uM -CONT1
10x10uM -CONT2 EXTRA
DFF
CC
5 x 5uM -CONT1 EXTRA to DIFF overlap = 40uM

12x12uM -CONT2 on all contacts
Figure flO -
Contact Hole Test Structures
(11) -
CONTACT RESISTANCE/DIODE
Purpose -
To measure the contact resistance between a
conducting material and the underlying silicon substrate. This test
structure is also used to evaluate diode characteristics as seen in
Figure fli.
ICE file(s): contact. cif
Test structure(s): CONTRES
Process: 3
Test Parameter(s): Contres, FDR, Vth, Vbr
33
The test structure consists of four highly symmetric legs. Two
of the legs are made from diffusions or ion implants in the substrate
and are joined at the center. The other two legs are made from an
isolated conductor and are also joined at the center. Contact between
the diffusion legs and the overlying conductor legs is made through a
large (20uM x 20uM) contact hole.
For contact resistance measurements, this test structure
requires that the four arm lengths be larger than the arm line width
by at least a 3:1 ratio. High symmetry is also used to improve the
accuracy of the potentiometric measurement. The contact resistance
measurement consists of forcing a current (I) between an adjacent
diffusion and conductor pair of legs and measuring the voltage
difference (V) between the other pair. The contact resistance is then
calculated simply as:
Rc = V/I [ohms] [4]
The diode tests are made using the two attached diffusion legs
of the test structure. The tests that are performed on the diode, such
as forward dynamic resistance (FDR), threshold voltage (Vth) and
reverse breakdown voltage (Vbr), are used to characterize the
quality of a PN junction. The diode tests could also be performed on
the CONT1/CONT2 test structures. Forward dynamic resistance
measurements are made by first forcing a forward current (II) and
measuring the voltage (VI) at which this condition exists. Next, a
different forward current (12 where I2>I1) is applied and the voltage
34
(V2) at which this new condition is satisfied is measured. The
forward dynamic resistance of the diode is then calculated to be:
FDR =
(V2-V1)/(I2-I1) [ohms] [5]
The threshold voltage is defined as the forward voltage at which the
diode begins conducting lOOnA. The breakdown voltage is defined
as the reverse voltage at which the diode conducts luA.
EXTRA
H DIFF
? oc
30uM
Figure fli -
Contact Resistance/Diode Test Structure
(12) -
ETCHBACK TEST REGIONS
Purpose -
To measure the etch rate and uniformity of a
partially etched backed insulating film as seen in Figure fl2. Also, to
measure and quantify the ability to produce lines and spaces in the
presence of topography
-
a step coverage test.
35
ICE file(s): topo.cif
Test structure(s): CAP2
Process: 2
Test Parameter(s): See CAPACITORS
To test the etch rate and uniformity, a group of capacitors is
placed in an unetched region (CAP1) while a second identical group
of capacitors (CAP2) is placed in the etched back region. By
measuring the oxide thickness of both groups, an accurate and
quantitative measure of the amount of insulator removed during the
etching step can be accurately and quickly determined. It is then
possible to determine the uniformity of the initial film, the etched
film and the compounded effects of both non-uniformities together.
See fl2.
36
CAP2
Conductor
Unetched
D!i sulator
Etched
insulator
Etched regions held 10uM

from capacitors
Figure fl2 -
Etchback Test Structure
The step coverage ability can be determined by forming etched
regions of the insulator in the path of the serpentine and comb test
structures. There are a total of eighteen lOOuM x 3150uM strips
that cut the path where the serpentine and comb conductors run.
Depending on the depth and profile of the step created by the
etchback, the ability to make lines and spaces over this topography
should vary and subsequently quantified by the comb and
serpentine tests. See figure fl3.
37
| | Unetched
insulator
|s^sj Etched
insulator
Serp/Comb over
C\N\
^Mfe :538E8B3B3E&::'
unetched region
'^V\>
ii^ji^Ûii X^t> Serp/Comb over
etched region
^mIj^B^B ::::&&&$&;
"::-;^M*>>:*:BM
WX-1
^^*V\ s.
Figure fl3 -
Step coverage test structure
38
VI -
CHIP/WAFER LAYOUT
The size of the wafers used in this study were three inches in
diameter. Each die or chip location contains one of each of the
structures described in the previous section. Each die measures
5000uM x 5000uM with a die separation pitch of JOOmils. Figure
fl4a is a plot of the actual test chip and figure fl4b is a reference
drawing showing the placement of the various structures within each
chip. Figure fl5 shows die placement within the wafer. Since many
of the edge die are only partially fabricated, only those die (total of
36) that are shaded are tested for the analysis. An arbitrary X and Y
numbering system is used to reference each die location for testing
purposes and is in the form xx:yy as seen in Figure fl5.
39
RIT
Figure fl4a -
Chip Layout
40
RIT
a ? 8
D000 ?
00 r?7i 13 14 15 16
17 23
18
24
19
9;
20
26
21
22 27
Legend: 1 CC-DIFF Alignment 10 Linewidth 1 19 COMB15

2 EXTRA-DIFF Alignment 11 Linewidth2 20 SERP5
3 METAL-OXIDE Alignment 12 VDPW1 21 SERP10
4 METAL-OXIDE Verniers 13 VDPW2 22 SERP15
5 CC -
DIFF Verniers 14 CONT1 23 EXTRA resolution chart
6 EXTRA-DIFF Verniers 15 CONT2 24 CC resolution chart
7 EXTRA-CC Verniers 16 CONTRES 25 DIFF resolution chart
8 CAP1 17 COMB5 26 OXIDE resolution chart
9 CAP2 18 COMB10 27 METAL resolution chart
Not shown: Etchback re gions under CAP2 and SERP/COMB structures
Figure fl4b -
Chip Layout
41
Major
Flat
Shaded areas represent
locations used during

automatic testing
Figure fl5 -
Wafer layout
42
VII -
PROCESS DESCRIPTIONS
In this section, a description of the three processes used in this
study for determining process control and is presented.

capability
As mentioned earlier, Process 1 is used to evaluate conductors on
oxide on semiconductors and Process 2 is used to evaluate conductors
on etched back oxides on semiconductors and finally, Process 3 is

used to evaluate diffusions in semiconductors and contacts. Figure
fl6 shows a simplified flow chart of Process 1, 2 and 3. The detail
involved in each block of the flow chart as well as the specific
fabrication equipment used can be found in Appendix D. Three runs
were started for the three processes with each run consisting of six
silicon substrates. Each substrate consisted of 3 inches in diameter,
N-type, <100>, 7.5-12.5ohm-cm phosphorus doped and 20mil
thickness material.
For Process 1, a dry 600Ang gate oxidation is grown with an
overlying 5000Ang sintered aluminum film. This situation simulates
a typical MOS transistor gate condition in the 4-Level PMOS process
except for source and drain diffusions. The capacitor test structures
will characterize the quality of MOS behavior that would exist in a
transistor of this gate oxide thickness and substrate doping. The
capacitors will also be used to determine minimum oxide defect
density levels. The serpentine and comb test structures will evaluate
the ability to pattern and etch aluminum lines and spaces over a
large region. Finally, the van der Pauw and line width test structures
will quantify the sheet resistance and line width of the aluminum
43
respectively. Total estimated fabrication time, assuming equipment
is ready and waiting for wafers, is approximately 5 hours.
In Process 2, the dry is

gate oxidation replaced with a 5000Ang
wet oxidation to resemble a field region in a MOS or Bipolar device.
In addition, an OXIDE mask is introduced for the purpose of etching

back regions of the field. Their are two capacitor test structures
active for this process -

one to monitor MOS behavior in the 5000
angstrom field region and the other to monitor the MOS behavior in
the etched back region. The measured oxide thickness difference
corresponds to the oxide etch rate and uniformity. The capacitors
again are used to determine defect density levels of insulating silicon
dioxide. The serpentine and comb test structures in Process 2 now
evaluate the ability of the lithographic and etching steps to resolve
lines and spaces over some topography to simulate actual device
conditions. The van der Pauw and line width test structures monitor
the same as in Process 1 -
quantify aluminum sheet resistance and
line width. Total estimated fabrication time, assuming equipment is
running and waiting for wafers, is approximately 6.5 hours.
Process 3 is designed to evaluate PN junctions (diodes) and
contact holes. The process starts off with a 5000 Ang wet field
oxidation followed by a diffusion (DIFF) mask. A P-type spin on
dopant is applied followed by the dopant drive in step. The oxide is
completely removed and a new 5000Ang wet field oxide was grown.
Next, the oxide is patterned with a contact hole (CC) mask and the
oxide is again etched until the backside of the wafers are clear. This
44
indicates the point at which contact holes from the front of the wafer
are etched back to the doped silicon. A 5000Ang aluminum layer is
then deposited and subsequently patterned using the EXTRA mask
and sintered. The capacitor structure, like in Process 2, is used to
evaluate MOS behavior of the thick oxide. Serpentines and comb test
structures evaluate the ability to define large diffusion regions and
the van der Pauw and line width test structures evaluate the sheet
resistance and line width of the diffused dopant in the
semiconductor. There are two contact hole test structures active
which are used to evaluate the ability of the process to pattern and
etch different size contact holes. A contact resistance test structure
is also active which is used to quantify the series resistance between
the aluminum and the doped areas. This structure is also used to
characterize PN junction behavior. Total estimated fabrication time,
assuming equipment is ready and waiting for wafers, is
approximately 11 hours.
45
Process 1 Process 2 Process 3
[ Full Clean ) ( Full Clean ) C Full Ctean )
?
^ Grow 600A Dry Oxide ) ( Grow 5000A Wet Oxide ) c Grow 5000A Wet Oxide )
?
^
Deposit 5000A Aluminum
) ( Mask level OXIDE ) c Mask level DIFF )
? 4
[ Mask level METAL ) ( Oxide Etch 2000A
) c Oxide Etch 5000A )
? 4
[ Etch Aluminum ) ( Strip Photoresist ) c Strip Photoresist )
t 4
C Strip Photoresist )(c eposit 5000A Aluminum ) c Quick Clean )
t
l Sinter )( Mask level METAL ) c P-Type Spin on Dopant )
? *
C Test )( Etch Aluminum ) c Dopant Drive In )
( Strip Photoresist ) c Etch Oxide Until Dewet

)
( Sinter ) cGrow 5000A Wet Oxide )

( Test ) c Mask level CC
)
ch Oxide Until Backs Dewet)
c Strip Photoresist )
*
f Deposit 5000A Aluminum )
*
c Mask level EXTRA
)
i
C Etch Aluminum )
c Strip Photoresist
)
*
c Sinter )
?
c Test )
Figure fl6 -
Process Flow Charts
46
VIII -
TEST SYTEMS
For this study, two test systems were designed to collect and
analyze data from the three processes described in Section VII. The
first test system, or the CV test system, is used for characterizing the
MOS behavior of the device using the capacitor test structures. This
test system is automatic only in the sense that it collects and
analyzes data. It can not do automatic stepping across a wafer but
does allow testing of multiple points on a wafer at one time. The
second test system is used to perform all the other tests in a
completely automated fashion.
The CV test system is shown in Figure fl7. It consists of a
Hewlett-Packard HP4277A LCZ Meter as the heart of the
measurement system. This instrument has many features and is
capable of making a multitude of measurements at various test
conditions. Of those related to making CV tests include capacitance
measurements down to O.lpF resolution (apparatus limitations) at DC
voltages ranging from +40V to -40V (with stepping resolutions down
to lmV) at test frequencies ranging from 10kHz to 1MHz. All CV
tests for this project were performed at 1MHz. Other options consist
of capacitance test signal level and measurement speed among
others. All functions are totally controllable through an IEEE-488
parallel interface bus connected to the main controller.
The main controller is a Hewlett Packard HP9816 computer.
This 16 bit computer has 512kbytes RAM of memory of which the
BASIC 2.0 operating system occupies 284kbytes while the CV
47
program itself consumes another 209kbytes. The computer has a
built in monochrome monitor and has graphics capabilities. Attached
to the computer is a Hewlett-Packard THINKJET printer and an
HP9122 dual disk drive which are both interfaced through the same
IEEE-488 interface bus.
Next, a Signatone S-1041 hot chuck system is used for bias
temperature stress tests. The chuck is housed in a light tight box
which also contains a controllable light source and three coaxial
probes multiplexed by the custom circuitry module shown. The
temperature cycling is preset before tests begin and is triggered and
monitored by the custom circuitry. The light tight box is also
nitrogen purged to keep moisture from the device.
The IEEE-488 controlled custom module contains IEEE-

circuitry
488 handshaking hardware, multiplexing circuitry for probe selection,
DC bias selection for bias temperature stress testing, hot chuck
temperature cycle triggering hardware and light on/off control. In
addition, a status byte can be read to verify that the desired switches
have been set and determines the status of the temperature
controller during cycling. The handshaking hardware consists of a
Seitz 6450 General Purpose Interface Board (GPIB). The circuit
diagram of the multiplexing circuitry, DC bias selection, hot chuck
cycle triggering etc. and software calling codes is found in Appendix I.
48
C HP9816 Computer)
< HP9122 Disk Drive)
K THINKJET Printer )
IEEE-488
Bus
( HP4277A LCZ Metei)
8.
SL ' '
u^ .
*J1. . \ Light control
\ Custom Circuitry J 1
Light Light tight box

Hfe^
Chuck
-Nitrogen
Propel P1
Probe 2 P2 ( Chuck) -Vaccuum
Probe 3 P3
^ IT
a
o
a.
3
I -?Water out
O
Q. o
o
O E -Water
3
.C o Nitrogen
o x:
( S-1041 Hot Chuck ")
Figure fl7 -
CV Test System
The DC Automatic Probing Test System is shown in Figure fl8.
This system performs all tests other than CV tests as described
before. The workhorse of this measurement system is the Hewlett-
Packard HP4145 Semiconductor Parametric Analyzer. This is the
piece of equipment that provides all stimulus and metering of test
structures. It is important to know that this machine only supplies a
'low'
single ended signal for testing purposes. The side is internally

tied to a reference ground. The HP4145 begins with four channels
called Standard Measurement Units (SMU's) that can be programmed
as either a ground, voltage source or current source. Current or
voltage measurements are capable at each SMU. Voltage sourcing or
49
metering is limited to +/-100V with maximum current sourcing or
sinking of 100mA (but not at +/-100V ==> see equipment manual for
allowable current/voltage points). These SMU's prove to

operating
be extremely powerful tools when testing and measuring DC
parameters on semiconductors. In addition to the four SMU's, there
are two voltage sources (no current metering capability and only
10mA maximum compliance) and two voltmeters (+/-100V limits).
One distinguishing feature about the HP4145 is that it has
exceptional ability to measure low currents (depending on your test
fixture, it is not difficult to measure at lOOpA resolution) but has
somewhat limited voltage metering capability (VMU's have
lOOuV/lmV resolution at 2V/20V range respectively with IMohm
input impedance while the SMU's have lmV resolution with

>1012
ohm input impedance). The HP4145 has IEEE-488 bus capabilities
and is interfaced to a computer as shown in fl8. There are many
other features of the HP4145 too numerous to mention here but it
does not take long to realize the versatility and capability this
instrument offers. The routing of these channels are also shown in
fl8.
The computer is a Hewlett-Packard HP9817 Series 200
microcomputer. This 16 bit machine has 1Mbyte of RAM and runs
with a BASIC 3.0 operating system that supports graphics, matrix
operations, IEEE-488 bus calls and a host of other binary ROM
support utilities. The operating system requires 484kBytes of RAM.
Program memory consumes approximately 64kbytes. As shown, this
50
controller is interfaced to all other equipment that supports the IEEE-
488 bus and acts as master controller during all tests and
measurements. Attached to the computer is a Hewlett-Packard
HP9133 disk drive which contains one 20Mbyte Winchester 'hard

drive' 5-1/4"
and a single 800kbyte floppy drive. The drive is
interfaced to the computer through the IEEE-488 as is a Hewlett-
Packard THINKJET printer and a Hewlett-Packard HP7470 two pen
plotter. To complete the computer system is a HP monitor.
To allow measurements of oxide thickness, a Princeton Applied
Research PAR M410 CV plotter is integrated in the system. Although
this instrument contains all the functions necessary to make
complete CV plots, it is only the capacitance metering capability that
is used here. The M410 allows a DC voltage to be forced into the X
REC OUT connector to superimpose onto the 1MHz lOmV AC
waveform provided by the M410. This allows capacitance
measurements at programmable voltage conditions. The voltage is
supplied by the VS2 voltage source of the HP4145. The Y REC OUT of
the M410 outputs a voltage that is representative of the capacitance
being measured (depending on the preselected capacitance scale).
This voltage is measured by the VM2 voltmeter of the HP4145.
Capacitance measurements are sensed by connecting the DRIVE
connector through the switching matrix to the substrate and
the INPUT connector, also through the switching matrix,

connecting
to the the topside capacitor contact of choice.
51
The CYTEC switching matrix consists of a series of IEEE-488
controlled switches which can connect one of eight inputs to any

any
one of sixteen outputs. The inputs of the matrix consist of the four
SMU's (SMU1, SMU2, SMU3, SMU4), one voltage source (VS1) and one
voltage meter (VM1) from the HP4145, and the DRIVE and INPUT
signals from the PAR M410. The outputs connect to the four probe
pads of each test structure (matrix line 1 to pinl of device, line 2 to
pin 2, line 3 to pin 3 and line 4 to pin 4) and one to the substrate
(line 0). A total of five outputs are used with the remaining outputs
used for future expansion.
'step'
To or move the wafer to each active die location and test
structure, a Rucker and Koll RK681A automatic stepping prober is
used. This instrument, controlled by the computer via the IEEE-488
bus, provides accurate stepping of the chuck to the exact position
that aligns the probes to the probing pads of the device. The
computer also can lower or raise the probes onto the test structure
and read back the current position. Once a wafer is aligned to the
'home'
probes and a or reference location is stored, two kinds of
stepping are then possible; inter-die or intra-die stepping. Inter-die
stepping consists of moving the chuck between die locations whereas
intra-die stepping involves stepping between test structures within a
single die location. Stepping resolution is lOuM.
52
(^ HP981 7 Computer)
HP9133 Disk Drive )

IEEE-488
Bus
HP7450 Plotter
)
THINKJET Printer )
HP4145 Semiconductor
< Parameter Analyzer
Z3
CM
J
5 >
CO co
XRECOUT YRECOUT
PAR M410 CV Plotter
DRIVE INPUT J
2 3 4 A
0 Substrate
Row
1 Pin 1
I RK681 Prober
Cytec 8x16 Matrix 2 Pin 2
iO 3 Pin 3
Pin 4
)
Figure fl8 -
DC Automatic Probing System
53
IX -
TEST PROGRAMS
This section contains a discussion of the two test programs
written (CV system and DC Automatic Probing system) to evaluate
and analyze the test structures described earlier. Listings of these
programs is found in Appendix J and K. First a few comments of the
testing methodology used. For any test program to be effective
requires the software to provide complete error detection and
correction of any situation such as run time and user input errors.
There is no excuse for having to restart a test and waste precious
time because of
programming deficiencies. A second important
aspect of any test program is knowing what kind of data is to be
expected for a given test and to be able to make intelligent decisions
on the validity or accuracy of the data being collected. Measurement
limitations, whether it be from theory or equipment, must also be
incorporated into the test program. Another important point
regarding designing software for test systems is the issue of 'user

friendly' friendly'
programs. 'User programming in this study
consists of easy to use and read, menu driven screens for driving and
'Softkeys'
selecting various options when running the test programs.
are used wherever possible to reduce the number of keystrokes
when running the program.
Whenever data is collected, whether in large volume or
techniques29
sampled, the use of statistical process control is
essential in reporting to the process engineer the nature or the
relevance of the data to the needs of the design. There are four
54
major techniques which are very well suited to IC processing -
(1)
histogramming, (2) wafer mapping, (3) trend charting and (4)
correlation and For the DC Automatic
variance analysis. Probing
test program, histogramming and wafer mapping are incorporated.
Histogramming is the technique of plotting a parameter against it's
frequency of occurrence in incremental ranges. This method is very
effective in displaying the variability of a parameter or the ability of
the parameter to stay within specified limits. Wafer mapping is the
technique of plotting data values in the orientation in which they

were measured. An advanced extension of wafer mapping is contour
plotting. Wafer mapping or contour plotting is effective in displaying

'shading'
localized variations or of parameters with respect to the
orientation of the wafer. The knowledge of these variations can
point to specific fabrication equipment deficiencies. Trend charting,
which is not incorporated in the program, consists of measuring and
tracking a parameter over time. This technique, which is also used in
conjunction with control charting techniques, is effective in
determining run to run variations and can detect slow

changing
problems in a piece of equipment or process. Correlation and
variance analyses involve the use of statistical models to find the
dependence of one parameter to that of another or the percentage
dependence of a variation due to some factor.
The CV test program flow chart, as shown in figure fl9, begins
with the main menu screen. From the main menu, one can choose
from 1 of 7 sub-menus and 1 of 2 options. These include running of
55
the CV, CVBT, CT, Zerbst and Doping Profile programs, accessing
system default parameters, performing system operation checks,
zeroing the capacitance meter or selecting a test sequence.
The test sequence sub-menu allows one to run a sequence of
tests in any order

automatically without stopping between tests. An
exception to this is the Zerbst program which requires user inputs
during testing. An example of a test sequence is to run a CT test
followed by a CVBT test followed by another CT test. A maximum of
25 tests may be strung together.
The default parameters sub-menu consists of global and test
specific options that are not routinely changed or selected. These
default parameters consist of accumulation and depletion voltage
settings, CT storage time limit, detailed doping data printouts, test
measurement speed, measurement frequency, test signal level,

integration time between capacitance measurements during voltage
ramps, graphics output device (screen or printer), chuck ambient
temperature and wafer type. For N-type wafers, the accumulation
voltage is always assumed to be positive and the depletion voltage is
always assumed to be negative. The opposite is true for P-type
wafers.
The test system self check is an option that serves to make
sure all instruments on the IEEE-488 bus are responding and are in
proper working order. The hot chuck status is checked through the
custom circuitry module's status byte. The LCZ meter has internal
calibration and system self checks that can be read from the bus.
56
The zero meter option is used to zero the capacitance meter
with Probe #1 turned on thus zeroing out to the tip of the probes.
Care should be taken to make coaxial lines of equal length to insure
equal output capacitance to each of the probes.
The CV sub-menu contains a series of user input options for the
purpose of
running the test. These options include identification
inputs, oxide thickness or capacitor area, voltage ramp range and
resolution, wafer type, 1 or 2 or 3 capacitors to test, gate type
(aluminum or N-type doped polysilicon), wafer type and a START
TEST option. Capacitor area or oxide thickness must be known before
the test can start. The test begins by biasing the capacitor with an
accumulation voltage determined from the default parameters. A
depletion voltage is then applied, also determined by the default
parameters at which time the light inside the the dark box is pulsed.
The light is used to establish an inversion condition on the capacitor.
The specified voltage ramp now begins with a delay time between
voltage increments determined by the system defaults. The first five
readings of the voltage sweep are averaged and stored as the
inversion capacitance or Cmin of the test program. The last five
capacitance readings are averaged and recorded as Cmax. When the
ramp finishes, the capacitor is again biased into accumulation and the
capacitance measured at this condition is recorded as the oxide
capacitance or Cox. If Cox<=Cmax then it is assumed that the oxide is
leaky. If Cmax<=Cmin then it is assumed that the flatband
capacitance is out of range, the data is bad or the wafer type is
57
wrong. The remaining CV parameters are derived and calculated
from the theory found in Appendix C. An example of a typical CV
test from a Process 1 device is also included in Appendix C.
The CVBT (capacitance voltage bias temperature stress) sub
menu contains the same user options as the CV sub-menu. The test,
however, consists of three sequential CV tests. An initial CV test is
performed and data is stored. Next, a -10VDC bias is applied through
the custom circuitry to all probes while the chuck is triggered for a
heat cycle. The heat cycle consists of (1) heat to 250C, (2) soak for 5
minutes and (3) cool to ambient setting. A second CV test is
performed and data is stored. A +10VDC bias is then supplied by the
custom circuitry while a second heat cycle is performed. The third
and final CV test is performed and data is stored. The reported
parameters are derived from first CV plot with the exception of the
mobile ion contamination which uses parameters from all three
curves. If a capacitor breaks down or has some kind of run time
error, the capacitor is reported as bad. CVBT calculations and a
Process 1 test are shown in Appendix C.
The CT sub-menu is simplified from the CV sub-menu in that
the only options are wafer identification, wafer type and the number
of capacitors to test. The CT test begins by applying the
accumulation voltage to drive away any electron hole pairs from the
surface. Next, the depletion voltage is applied and the light is pulsed
to create the inversion layer. The capacitance is then measured and
stored (Cmin). The capacitor is again accumulated and depleted.
58
Capacitance measurements versus time begin using the computer's
internal system clock. Measurements continue until either the
capacitance reaches the inversion capacitance (Cmin) or the time
limitation (as defined in the default menu) is exceeded. This is the
storage time. A CT curve from a Process 1 device is found in
Appendix C.
The Zerbst sub-menu contains the same user options as the CT
sub-menu with the addition of oxide thickness/gate area option
which must be entered before starting a test. The Zerbst test is an
extension of the CT test. From the CT curve, it is possible to create a
different plot (as described in Appendix C) that allows the
determination of additional MOS parameters (also found in Appendix
C). A typical Zerbst plot of a Process 1 device is shown also. It is
sometimes difficult to obtain believable and repeatable results of
Zerbst tests because of the resolution and noise levels required to
make good calculations. As mentioned earlier, the test requires user
inputs during the course of the test which makes this test
undesirable as an automatic test.
The Doping Profile sub-menu is identical to that of the CV sub
menu as far as user entries go. The Doping Profile test consists of a
deep depleted CV curve which is generated by pulsing the capacitor
into accumulation and back to the voltage ramp in between each
capacitance measurement. This insures that electron hole pairs do
not form at the surface so that a depletion capacitance can be
measured at each voltage condition. The light is not pulsed during
59
any part of the test. This deep depleted CV curve can now be used to
calculate the doping profile of the substrate as seen in Appendix C
which also contains a doping profile test from a Process 1 device.
f Main Menu )
CV Test
) (l)ser Entries") ?( Start
Test) ?( Output Data )
i
) fr(User Entries )
CT Test
?( Start
Test)
?( Output Data )
CVBT Test
J {user Entries ) ?( Start Test) ?( Output Data
)
-?^Zerbst Test
J fr(user Entries ) ?( Start
Test)
-^ Output Data )
+Q Doping Test ) ?(llser Entries

) ^ Output Data )
Test)
&Q Start
^Sequence
TestsJ
^Select Tests
) ?( User Entries)-^ Start Test #1
)
d^
-?^ Zero Meter
) Q Output Data )
Self Test
)
-?f System Parameters Menu #1 )
c Start Test #N
)
T
[ System Parameters Menu #2 ) -Ôutput Data
)
Figure fl9 -
CV Test Program Flow Chart
The DC Automatic Probing test system program is designed
using the same criteria as was outlined in the beginning of this
60
section. The program flow is shown in Figure f20. The program
resides on the 20Mbyte hard drive while data, collected from tests, is
5-1/4"
always stored and retrieved from the floppy drive. For most
measurements, a multiple number of acquisitions are made and
averaged to increase resolution and repeatability of tests. For most
tests, measurements are made with a IV back bias with respect to
'sneak'
the substrate. This is to avoid current paths (surface, bulk
etc.) when
performing tests with diffusions. Since back bias does not
effect non-diffusion processes (1 and 2), this condition is maintained
to keep programming somewhat simpler. Whenever a voltage is
quoted in this section, the polarity is always referred as being

positive. In actuality, however, the test programs automatically set
the polarity depending on the wafer type selected at the start of the
test.
The program begins with a main menu which consists of a
number of options to choose from. These options, which are
selectable from the softkeys, are date, run, and wafer identifications,
default parameters sub-menu, process number (1, 2 or 3), files sub
menu, graphics sub-menu and a START TEST softkey. The default
parameters sub-menu consist of wafer type and the default forcing

currents used for the van der Pauw, line width and contact resistance
test structures as well as the capacitance meter range of the M410.
The process number can only be 1, 2 or 3.
The files sub-menu consists of a series of options relating to
storage and retrieval of data to or from the user data disk.
61
Specifically, these options include initializing a new data disk, listing
of files on the data disk, loading a previously stored data set, storing
of data currently resident in memory, printing of data or statistics
currently in memory and printing of the error code reference chart.
When storing data, the filename assigned to the data is composed of
the wafer and run identification. This allows for accurate tracking of
process trends which is not supported at present. All data generated
during a test as well as setup and default values are stored for
review purposes.
The graphics sub-menu consists of a series of options relating
to the display of data currently in memory. Specifically, these
options include wafer mapping and histogramming of any parameter.
For wafer mapping, an option of displaying data only or displaying

data plus the number of standard deviations from the mean are
available. Bad data is automatically filtered out of all plots. Also
available is an option to direct plots to the screen, printer or plotter.
Once a process number has been selected and wafer
identification is entered, the test can commence. The program flow
for each process is shown in Figure f21. Wafers are aligned on the
prober chuck with the flat aligned 45 degrees to the right from the
top. This orientation is based on the orientation during lithographic
patterning and places the RIT logo to the top right hand side of the
die as viewed on the wafer. All tests begin with the probes aligned
to the CAP1 test structure at the 20:20 reference location (see fl4,
fl5). The procedure for testing is to step to all test structures within
62
a location before moving on to the next location. At the very
beginning of each wafer test, before the probes are lowered onto the
first test structure, matrix connections are made between the M410
and the probes for measurement of the leakage capacitance. For the
first eight test structures, all three processes step in the same
sequence as seen in f21.
For the capacitor test structures (CAP1 and CAP2) the oxide
capacitance is measured (subtracting off the leakage capacitance) and
by knowing the capacitor area and capacitance meter range, the
oxide thickness can be computed. The program first measures the
400x400uM capacitor and if bad data is detected then the
200x200uM capacitor is measured. If this capacitor is bad then the
measurement is terminated. Since the M410 outputs a 0 to 10V
signal corresponding to a given capacitance scale, bad data is defined
as reading less than 0.1V or greater than 9.9V. If the oxide thickness
can be measured, a lOOnA current is forced into each of the four
capacitors and the corresponding voltage that follows for this
condition is the breakdown voltage. The breakdown voltage is
converted into a field breakdown voltage by dividing the breakdown
voltage by the oxide thickness. A breakdown field of less than
2MV/cm is considered defective. Oxide breakdown voltages are
limited to 100V because of HP4145 limitations. The defect density is
defined and calculated as the percentage of defective capacitors
divided by the area of that capacitor on a per wafer basis. The
63
capacitor with the highest defect density is reported as the minimum
possible density or occurrence.
The two van der Pauw test structures are measured next. Two
pre-tests are performed before measurements begin. The first is a
short to substrate pre-test which is determined by applying a 6V
bias between the four pads of the test structure and the substrate
which is at ground. Resistances of 20Mohms or less are considered
shorted. The second pre-test is to place a 5V bias between adjacent
pads to see if continuity exists between the legs of the structure.
Open contact failures are defined for resistances greater than
20Mohms. The user defined forcing current from the default
parameters menu is forced through one adjacent pair of probe pads
while the voltage difference between the other pair is measured. If
voltage compliance is met (fixed at 10V), the measurement is
aborted (usually a user input error on forcing current value). If a
voltage difference of less than lmV (usually because of system
limitations) is read, then the measurement is also aborted. The
corresponding sheet resistance is calculated when these conditions
are met. If the sheet resistance is greater than 20Mohm/square,

then measurement is considered invalid.
If the sheet resistance from the van der Pauw's can not be
determined than the electrical line width tests, which are performed
next, are omitted. If a value was found then the test structures are
first checked for shorts to substrate (<20Mohms) and open contact
(>20Mohms) in the same manner as the van der Pauw. The line
64
width is then calculated by forcing the pre-defined current through
the two current nodes the voltage

carrying while measuring
difference between the other two. Voltage differences of less than
lmV abort the test as well as if compliance (fixed at 10V) is met.
'delta'
The electrical line width and line width (the difference
between the mask dimensions and the electrical line width) is now
calculated. It is assumed that conductors always lose line width with
positive lithography while line widths increase for diffusions. For
electrical line widths of conductors, values greater than that defined
on the mask or line width losses greater than the width of the
voltage measuring tabs (the smallest geometries of the test
structure) are considered defective. For diffusions, line widths are
defective for values smaller than the mask dimensions and line
widths greater than half the distance between the voltage pads and
the body of the structure.
The comb test structures are first measured with a short to
substrate (<20Mohms) pre-test using the same method as the van
der Pauw and line width test structures. If the pre-test passes, then
the voltage on one of the pads of the test structure drops to IV.
Resistances between the two pads greater than 20Mohms is
considered to be open (spaces maintained) and values less than
20Mohms are considered as resistive shorts (bridging has occurred).
The serpentine tests are tested exacts the same as the comb
tests except that opens between the two pads mean that line width
65
was not maintained and resistive shorts mean that the line width
was maintained.
For Process 2, a second capacitor test structure is measured in
the same manner as was the first one. The oxide thickness of CAP1
minus the thickness of CAP2 is then reported. Negative oxide
differences are considered defective.
The two contact hole test structures for Process 3 are first
measured for short to substrate (<20Mohms) pre-test in the same
way as the van der Pauw, line width, serpentine and comb test
structures. A 5V potential is applied between the diffused region
and the overlying conductor (which is common to all three contact
tests of the structure). Resistances greater than 20Mohms is
considered open (contact and/or contact hole was not made) and
values less than 20Mohms is considered a resistive short (contact
and/or contact hole established). This method of test is performed
for all three contact hole sizes on both CONT1 and CONT2 test
structures.
The contact resistance test structure of Process 3 is measured
for a short to substrate (<20Mohm) pre-test followed by a continuity
pre-test between the two diffused legs and also between the two
overlying conductor legs. Resistances greater than 20Mohms are
considered defective. Contact resistance measurements are made by

conductor-
through one pair of
forcing the pre-defined current
diffusion legs while the voltage difference between the other pair is
66
measured. Voltage differences of less than lmV are considered
defective as are contact resistance values greater than 20Mohms.
Typical test reports of Process 1, 2 and 3 as well as some
examples of wafer mapping and histogramming are seen in Appendix
E, F and G respectively. Notice that statistics are kept for all
parameters as well as statistics on the various failure modes. Default
settings and test times are also reported. Everything that is printed
on these reports can be stored on file for future reference.
67
MAIN MENU
-
Date
-
Run
-
Wafer
-
Process
I
DEFAULT MENU
I FILES MENU
I I
GRAPHICS MENU ( START TES?)
-
Wafer Type Load data -
Histogramming
-
M410 Cap range -
Store data -
Wafer mapping
-
Forcing currents -
Catalogue disk
-
Initialize disk
-
Print data
-
Print Statistics
-
Print error codes
(Inter-die Î
Prober step
~j~c^
^Perform
H Measurement!
E
/Întra-die
I ^
Prober step J^
N f\Last
I of
test
die?
N /7a
Last die
h. wafer?
Print data
Calc stats
Print stats
I
Return
MAIN MENU
ENU "1
J
Figure f20 -
DC Automatic System Program Flow
68
(Measure leakage
j
capacitance J
?( CAP1 Test )
C VDPW1 Test)
zxz
C VI .72
Test)
( Step to Next Die ) f Linewidthl

Test)
I
C Linewidth2 Test
)
I
C COMB5/COMB10
Test)
T
(cOMB15/SERP5Test )
Process 1
( SERP10/SERP15 Test)
Process 2/ \ Process 3
( CONT2 Test )
~ZEZ1
-( CONTRESTest)
Figure f21 -
Process 1, 2, 3 Program Flow
69
X -
PROCESS 1 DATA ANALYSIS
This section deals with a discussion of the data collected from
Process 1 type test structures. As you recall, Process 1 consists of
'dry'
5000Ang of patterned (mask=METAL) aluminum on 600Ang of
silicon dioxide on N-type, 7.5 to 12.5ohm-cm, silicon substrates. A
total of six wafers made

up the run called TEST-1 of which one wafer
was used during processing as a fabrication control.
In figures f27-f32 of Appendix C are plots of the five main
tests performed by the CV test system for Process 1 devices. The
from #4 devices. f28-

plots came wafer They include f27-CV plot,
CVBT plot, f29-CT plot, f30-ZERBST plot, f31-Deep Depleted CV plot
and f32-Doping Profile plot. Each plot contains the important
parameters calculated from the test. Table t7 of Appendix E shows an
example of Process 1 test data performed on a wafer by the DC
Automatic Probing system. Along the left column of the printout are
the die locations (as outlined in Section VI) and the data measured
according to that position. Table t8 is the statistical summary page
that is calculated from the raw data in t7. Also in t8 is the default
settings and test times.
From the CV plot in f27, one can see the threshold and flatband
voltage, oxide thickness/capacitance, fixed oxide charge and other
parameters. From this test, it can be determined that the oxide
quality and MOS behavior appears quite good. The fixed oxide
010 Q/cm2
charge is small (less than 20*1 but varied
considerably
within and across wafers) and the curve shape is as one would
70
expect for a device with few surface/interface states. The substrate
doping correlates well with values obtained from the doping profile
routine (see f32) and from the (7.5-12.5ohm-cm

starting resistivity
3*1014 7*1014
==> -
cm"3). The oxide thickness correlates well on
both the DC Automatic Probing system and the CV system.
The CVBT test, as seen in figure f28, is used to determine
mobile ion charge content in the oxide layer. The red or middle
curve is the initial CV curve. The solid blue or left most curve
represents the CV curve after the positive bias (+10V) temperature
stress (250C for 5 minutes) and the dot-dashed blue or right most
curve represents the CV curve after the negative bias (-10V)

temperature stress (250C for 5 minutes). From the curves, there is
evidence of a large amount of mobile ion charge contamination,
presumably due to sodium in the oxide layer. Calculations form the
CVBT program indicate a flat-band shift between the second and
CV 010
third curve to be 277mV or 9.26*1 mobile ions/cm2.
'dirty'
Contamination is most likely due to furnace oxidation tubes.
The storage time, as seen from the CT plot in f29, is indicative
of a good process. As long as the storage time is several seconds long

means that there is minimal heavy metal contamination in the silicon
unless the application is for very low dark current devices.
Variations across a wafer and between wafers were large. There was
a non-quantified observation that the larger sized capacitors had
lower storage times.
71
The ZERBST plot in f30 was generated from the CT plot of f29.
From the plot, one can determine the carrier lifetime and
minority
the surface generation velocity from the linear least squares data fit
superimposed on the plot, as is shown. In practice, however, it is
usually the case that only the carrier lifetime can be

minority
accurately and repeatedly measured. Usually it is sufficient enough
to use CT tests and it is not recommended, as mentioned earlier, to
use this test as a routine process control tool.
The doping profile plot in f32, which was generated from the
the deep depleted CV plot in f31, determines doping density versus
depth for a substrate. Routine use of this algorithm is somewhat
limited because the result of this test is the interpretation of a curve
describing profiles of dopants in the silicon -
certainly not the kind of
data to track on a routine basis but useful none the less. The
exclamation point at the bottom of the graph indicates the point
where the correction factor is incorporated (twice the debye length).
Correlation between the doping profile and CV curve, as mentioned
before, is good. An interesting feature of the plot is that at the near
surface area, a build up of N-type material (presumably phosphorus)
is evident. This feature is expected to some degree because, during

oxidation, silicon is consumed by the oxidation procedure and the N-
'pushed'
type dopants have a tendency to get back into the substrate
and pile up at the interface. The dopant concentration shown at the
surface of the graph, however, is too much to account for this and
thus some other mechanism must be contributing to the effect.
72
The oxide thickness (TOX1) from the capacitor test structures,
as measured on the DC Automatic Probing system, was a little high
to the target thickness film

(647Ang vs 600Ang). The 4.2% non-
uniformity is probably more of a problem but depends on application
since this variability will cause shifts in the threshold voltages. The
breakdown field of the capacitors (FCAP1_200, FCAP1_400,

FCAP1_600 and FCAP1_800) is good and ranges from 6.77MV/cm to
7.85MV/cm. Several of the other wafers of the run measured well
over 8.0MV/cm. There appears to be a tendency to have a lower
field breakdown as the capacitor size increases as shown in figure
f22. Also, there appears to be a slight dependence that the larger
capacitors have a higher occurrence of breakdowns that are less than
2MV/cm which ranged from 2.8% to 41.7% as shown in figure f23.
This breakdown failure level is rather high and one can conclude that
the oxide film quality is good yet contains random defects causing
oxide leakage. The minimum oxide defect density is calculated to be
93 defects/cm2. Examples of the histogramming and wafer mapping
functions of the Automatic DC Probing test program, using the oxide
thickness parameter, is shown in figures f33 and f34 in Appendix E.
From the plots, one can evaluate wafer variations as well as the
frequency distribution of the oxide thickness across the wafer.
73
200x200 400x400 600x600 800x800
Capacitor Size (uM)
Figure f22 -
Capacitor Size vs Field Breakdown (Process 1)
% <2MV/cm
200x200 400x400 600x600 800x800

Capacitor size (uM)
Figure f23 -
Capacitor Breakdown Yield (Process 1)
It was predicted that a typical sheet resistance for an
aluminum film would be approximately 0.027ohms/square. This
would mean that for the two aluminum van der Pauw tests, (VDPW1,
100mA would generate about 600uV of

VDPW2) a forcing current of
voltage drop. Unfortunately, the measurement resolution of the
HP4145 voltmeters were yielding only approximately lmV which
74
explains the inconsistent and probably incorrect results shown. To
remedy the situation would require a higher resolution (lOuV would
be plenty sufficient), IEEE-488 compatible, voltmeter which could
then be integrated into the unused outputs of the matrix.
Since the van der Pauw measurements were invalid, the line
width test structures (Linewidth 1, Linewidth2) are also invalid
because the sheet resistance of the film must be known in order to
calculate the line width. The lOOOuM line width test structure
provides plenty of voltage drop to accurately measure the aluminum
line width had the sheet resistance been measurable. From
measuring the line width of the resolution charts using a
Nanometrics Nanoline system, 3.0 to 3.5uM was lost during

processing of which 1.8 to 2.6uM is attributed to mask dimension
discrepancies.
For the comb test structures (COMB5, COMB10, COMB15), the
most striking observation one can see is that nearly all the combs
have failed the short to substrate pre-test. This result confirms what
was seen in the capacitor breakdown tests and that is the conclusion
that the oxide has a high occurrence of random defects that cause
oxide leakage. Since the comb test structures cover a large region of
the chip (much larger than the area of CAP1 test structures), it
means that there is a greater probability that a defect will be hit.
From the few die that passed the pre-test, the 5uM structure showed
more of a tendency to have a bridging defect causing resistive shorts
than the 10 and 15uM structures which follow expectations. Since
75
the 10 and 15uM structures look very similar statistically, one might
lean towards saying that lOuM spaces is the process capability.
However, until the oxide breakdowns can be resolved, it will be
difficult to determine where process latitude levels really exist for
defining spaces.
The serpentine test structures (SERP5, SERP10, SERP15)

indicate that the short to substrate failures are much lower in level.
This is expected as the line width of the serpentine structures are
smaller than the comb (5, 10, 15uM versus 40uM) and thus reduce
the chance of a line falling on a defective portion of the oxide. You
will notice that as the line width increases, the percentage of short to
substrate failures increases also. For the 5uM serpentine, 88.9% of
the die had an open in the conductor somewhere between the pads.
The 10 and 15uM serpentines, however, had opens only of the order
of 2.8%. This data implies strongly that somewhere between a 5uM
and lOuM design rule should be imposed for all lines for this process.
Figure f24 shows a graph depicting the ability to make lines and
spaces from the serpentine and comb test structures.
76
Yield
Comb5 Comb/10 Combl 5 Serp5 SerpIO Serp15
Figure f24 -
Serpentine/Comb Yield (Process 1)
The total test time takes 30 seconds per die or 18 minutes per
wafer. If a higher resolution voltmeter is used, these numbers would
increase slightly to account for the line width measurements that
were omitted because of invalid sheet resistance tests. The
aluminum film thickness, as measured from a Tencor Alpha Step

200, ranged from 4400Ang to 6200Ang.
In conclusion, the number one priority task of increasing the
processing quality and yield from Process 1 devices is to reduce and
understand the amount of gate oxide defects that are causing short to
substrate failures. The short to substrate failures can be mapped out
using the wafer mapping option of the test program to determine
any possible orientation effects. No strong orientation effects appear
to be occurring in this case. The only cause for such high failures
which comes to mind is the possibility of dirty furnace tubes or
impure gases which may contaminate the film during oxidation. The
effectiveness and quality of the cleaning procedure might also be
77
investigated. A second conclusion that can be drawn from Process 1
is that the line and space design rule limit appears to lie between 5
and lOuM. From visual inspections of these wafers, it appears that
'bridges'
shorting are caused during the wet aluminum etch which
creates air pockets or bubbles on the surface when etching, resulting
in unetched regions. The problem with line definition seems to be
photoresist patterning related deficiencies (either exposure,
developing or the mask itself).
In general, the wafer to wafer variations almost always
exceeded chip to chip variations within a single wafer. This was also
observed on Process 2 and Process 3 devices. Discussions with the
process engineers during the fabrication survey had noted that it
was more difficult to keep wafer

*
wafer variations in control than
within a single wafer. It can probably be deduced that run to run
variations would be even more difficult to control.
78
XI -
PROCESS 2 DATA ANALYSTS
5000Ang of patterned (mask=METAL) aluminum on 5000Ang of
'wet'
silicon dioxide on N-type, 7.5 to 12.5ohm-cm, silicon substrates.
In addition, regions of the oxide back

were etched (mask=OXIDE)
2000Ang to evaluate step coverage and etch rate/uniformity. A total
of six wafers made up the run called TEST-2 of which one wafer was
used during processing as a fabrication control and another was lost
at an oxide etch step.
Table t9 of Appendix F is an example of Process 2 test data
measured from one of the fabricated wafers while table tlO is the
statistical data calculated from t9. The oxide thickness of the
unetched region (measured from CAP1) was 4046 Ang which is
considerably off from the target oxide thickness of 5000Ang. The
reason for this error could be attributed to insufficient time the
wafers were in the furnace including ramp-in and ramp-out times.
Another possibility might be due to insufficient water vapor flow
during the cycle. The non -uniformity of the film was 5.1% which,
like the dry oxidation, is high but is not so critical since moderate
threshold shifts will not disturb the active regions of the device.
Thresholds from CAP1 and CAP2 test structures, as measured using
the CV system, indicate that a threshold of the order of less than -
40V exists in most of the devices (the lowest measured was about -
13V). The reason for such a high threshold must be due to a very
79
high amount of fixed oxide charge. This to be
would require Qss
about 2x1 012 Q/cm2
in this case. The breakdown fields of this thick
oxide, in virtually every case, exceeds the measurement capability
(+/-100V) of the HP4145. This is in large contrast to the thin dry

oxidation. Because there are large regions of field in most devices, it
can be concluded that the quality of the film to act as an insulator is
good.
As was the case in Process 1, the van der Pauw and line width
test structures were not successful in determining the sheet
resistance and aluminum line width because of insufficient voltmeter
resolution on the HP4145. From line width measurements of the
resolution charts using a Nanometric Nanoline system, the line width
loss of the METAL layer was found to range from 3.7 to 4.1uM with
1.8 to 2.6uM of the variation due to mask deficiencies. The OXIDE
resolution charts were visible but unfortunately could not be
measured on the Nanoline. Visual observations indicate about a 2.5
to 3.5uM loss (1.7 to 2.0uM due to masks) but some wafers had as
much as a 5uM loss.
The comb structures (which now have topography from the
etched backed regions of the oxide) show that for every spacing (5,
10, 15uM), there is a resistive short. The fact that there were no
substrate shorts confirms the results found by the capacitors -

that
the thick oxide is performing very well as an insulator to the
substrate. The fact that every comb has a resistive short indicates
that either (1) the air pockets formed from the aluminum etch are
80
causing the metal not to clear, (2) aluminum
'stringers'
are forming
which are conductive paths
along the the step of the oxide etch
which the aluminum etchant cannot get to very well or (3) that the
thickness of the aluminum the is

along step much greater than
everywhere else longer

requiring a etch time (at the expense of
under
cutting and line width loss). From visual inspection, it appears
the primary problem is due to the aluminum

'blotches'
etch. Many of
residual, unetched metal appear in high frequency on all wafers. A
scanning electron microscope (SEM) would be necessary to determine

'stringers'
whether or not are present. The effect of the additional
topography is really not clear because no baseline was established
with a planar film (recall that Process 1 combs and serpentines were
mostly shorted to the substrate). If Process 1 were performed, with
the substitution of the Process 2 thick oxide, a baseline could be
established and thus the step coverage ability could be more
accurately evaluated.
The serpentine test structures showed no short to substrate
pre-test failures as was seen in the comb test structures. For the
15uM serpentine, 86.1% of the die locations had resistive shorts
meaning that a conducting path was maintained throughout the test
structure. For the lOuM structure this value drops to 38.9% and
finally the 5uM structure measured 2.8%. This would indicate that a
5uM line would not be reliable in any design with this type of
processing. Again, the effect of the topography is unclear because of
the lack of a baseline. Since the comb test structures indicate such a
81
high level of shorts, the mechanisms mentioned earlier be
may
skewing the results.
The oxide thickness of the etched backed regions (measured
from CAP2) was 3509Ang which makes the oxide thickness
difference between the etched and unetched regions to be 601 Ang.
This is considerably lower than the etch back target of 2000 Ang.
'dirty'
The difference is attributed to a weak or buffered HF bath that
had an etch rate of less than lOOOAng/minute which was assumed at
the start. From the results, we can see that the actual etch rate of
the film at the time was 601Ang/2min =

301Ang/min. As was the
case of CAP1 results, CAP2 (or the etched back regions) breakdowns
exceeded measurement capability and had virtually no premature
breakdowns. The non-uniformity of the unetched oxide was 5.1%
while the etched back film had a non -uniformity of 6.2%. The non-
thickness'
uniformity of the difference of CAP1 and CAP2 oxide
(TOX1-TOX2) was 11.1%. This indicates that the oxide growth step
was more uniform than the etch back step. Figures f35, f36, f37 of
Appendix F shows wafer maps of CAF1 oxide thickness, CAP2 oxide
thickness and the oxide thickness differences (TOX1-TOX2) between
the two respectively. Each of these plots were generated by the DC
Automatic test The plots show that (1) TOX1 has

Probing program.
definite from upper left to lower right as seen in f35, (2)

shading
TOX2 shows a similar type shade as seen in f36 and (3) there
the the
spot'
appears to be a 'hot at the center and upper right of
delta oxide thickness difference as seen in f37. The wafer was not
82
oriented with respect to the oxidation orientation during oxide etch
back.
The conclusions we can draw from the Process 2 data is that (1)
the thick (wet) oxidations have very good characteristics
(breakdowns, thresholds) which should provide good field regions in
IC's (2) van der Pauw and line width determination is unavailable
because of measurement resolution (3) 5, 10 and 15uM spaces, in the
presence of a 600 A step, are not resolvable (4) lOuM lines with this
same topography are probably the lower limit for defining lines and
(5) the uniformity of the etching technology is worse than that of the
furnace oxidations.
Test time per die was 35 seconds or roughly 21 minutes per
wafer. This value would be slightly higher if the line width test
structures were measured. The minimum oxide defect density (as
measured from CAP1 data) was 4.4 defects/cm2.
83
XII -
PROCESS 3 DATA ANALYSIS
P-
'wet'
type diffusions (mask =

DIFF) covered by 5000Ang silicon
dioxide field regions. Contact holes are made to the diffusions (mask
=
CC) and contacted by 5000Ang of aluminum (mask = EXTRA).
is N-type, 7.5 to 12.5ohm-cm, silicon substrates. A

Starting material
total of six wafers made up the run called TEST-3 of which one wafer
was used during processing as a fabrication control. One wafer was
aborted due to a bad oxide etch.
Table til of Appendix G is an example of a Process 3 test
performed on one of the wafers while table tl2, also in Appendix G,
contains statistical summaries of the data collected in til. From the
that the oxide thickness measured was

data on CAP1, we can see
like the Process 2 data, is substantially lower

only 3262Ang which,
target. Process 3 furnace operations were

than the 5000Ang
identical to that of Process 2 and the explanation of this discrepancy
The breakdown behavior in the 200 x

can be found in that section.
for the most part, all exceeded

200uM and 400 x 400uM capacitor.,
(+/-100V). The two larger capacitors,

measurement capability
higher occurrence of breakdown -

94.4% for
however, had a much
19.4% for the 800 x 800uM capacitor.

the 600 x 600uM capacitor and
behavior although not as severe.

The other wafers also showed this
600uM capacitor was broken down

The reason why the 600 x
than the 800 x 800uM capacitor is unknown.

more
considerably
84
Process 2, which uses the same field oxidation, did not exhibit this
behavior. The explanation of this phenomena must have something
to do with the difference in processing. The major difference
between the two processes would have to be the growing of a second
field oxide. As you recall from section VII, Process 3 grows a
5000Ang field for defining the areas where the P-type dopant is
introduced. The dopant is thermally driven into the silicon and the
oxide is completely removed. A second field oxide is then grown.
There was no clean step after the oxide etch and before the second
field oxidation. This might be leading to contamination on the silicon
surface and weakening the subsequent oxide. A full or quick clean
procedure in between might provide insight to this effect.
The van der Pauw test structures say that the diffused regions
have a 12.8 and 13.4 ohms/square sheet resistance for the VDPW1
and VDPW2 test structures respectively. The consistency between
the two structures is close and verifies that the design criteria for the
two different architectures or designs are working. Differences
between the two are attributed to subtle processing effects on the
type of design. If we assume a luM junction depth, this sheet
IO20
resistance would correlate to a diffusion doping of the order of
atoms/cm3. Of more concern than the average level of sheet
resistance is the variability within a wafer (approximately 20%).
Assuming a luM lateral diffusion and noting that the mask line
width is approximately luM larger than intended, we can assume
that the two cancel each other out and that the electrical line width
85
measurements should be close to true values. Electrical line width
measurements of the LW15_1000 and LW30_100 test structures
were found to be 3.2 and 2.2uM respectively with high measurement
standard deviations (1.5 and LOuM respectively). The high standard
deviations are believable because the line width variation across a
wafer, from visual inspection, does not appear well controlled. The
difference in the averages of the two test structures is more of a
concern and probably indicates an inability of the design to
overcome processing ambiguities. From visual inspection of the
wafers, the diffused regions have a somewhat odd appearance. The
field spaces do not appear to be straight and clear but rather jagged
as if the oxide etch was degrading the integrity of the photoresist
mask. The Nanoline was not able to measure the line width from the
resolution charts because of insufficient contrast. Measurements
using a micrometer attached to a microscope stage suggest
approximately 2uM larger lines were fabricated. Wafer map plots of
the two line width structures can be found in figures f38 and f39 of
Appendix G
The aluminum to P+ diffusion contact resistance, as measured
on the CONTRES test structure, was found to be 95.2 +/-

16.3 ohms,
which should be acceptable for most designs except for the higher
current circuits where significant voltage drops could affect circuit
performance. The contact resistance had a slight tendency to shade
'flyers'
to of the wafer with a couple of

the top and right side
near the middle as shown in figure f40 of Appendix G.

occurring
86
The diode characteristics look very good. The threshold voltage
was 0.36 +/-

0.02V, the forward dynamic 1.06k
resistance (FDR) was
+/-
.03kohms and the reverse breakdown voltage (VBR) was 77.0
+/-
6.5V with no failures for any of the die. All parameters appear
very uniform and acceptable for most applications except maybe the
forward dynamic resistance. The plot in figure f41 shows a diode IV
curve indicating the forward and reverse characteristics. The
forward biased region shows a gradual increase in current in the 0V
to 8V region. The FDR measurements takes place in this region (at
the 1mA to 2mA level) where the 1.06kohm resistance is seen. In
the 5mA to 10mA region, a 400ohm resistance is seen. Reasons for
this behavior is not understood and may have something to do with a
contaminated junction. Figure f42 of Appendix G contains a
histogram plot of the diode reverse breakdown voltage which shows
good distribution behavior.
The contact hole size test structures (CONT1 and CONT2) show
that the 3 x 3uM contact could not be opened. Surprisingly, 72.2% of
the 5uM contact was opened while this percentage increases to 100%
for the 15 x 15uM contact. This indicates that, for this process, a 5 x
5uM contact is the lower limit for contact hole cuts. See figure f25.
87
3x3uM 5x5uM 7x7uM 1 0x10uM12x12uM15x15uM
Contact Hole Size
Figure f25 -
Contact Hole Size Yield (Process 3)
Next we look at the serpentine and comb test structures. The
5uM comb test structure is always shorted together. This is not
IO20
surprising because if we assume (1) a diffusion doping (2) a
IO14
substrate doping and (3) a 5V reverse bias on the diode, we
'short'
would obtain an 8.5uM depletion width which would all 5uM
comb test structures together when tested. The lOuM spacing was
made 36.1% of the time and the 15uM spacing 69.4% indicating that
somewhere around a lOuM spacing between diffusions is the design
rule limit for this process and is mostly determined by depletion
punch through effects. The serpentine test structures predominantly
were fabricated as designed with 66.7% of the 5uM line intact, 88.9%
for the lOuM lines and 97.2% for the 15uM lines. This indicates that
5uM designs for diffusions would be acceptable but don't space
adjacent diffusions closer than lOuM. See figure f26.
88
C0MB5 COMB10 C0MB15 SERP5 SERP10 SERP15
Test Structure
Figure f26 -
Serpentine/Comb Yield (Process 3)
The conclusions we draw from Process 3 devices is that (1) the
thick oxide is performing well as an insulator but only for the
smaller size areas, perhaps due to the weakening of the oxide, (2)
sheet resistances were very low and moderately consistent,
indicating a good source-drain diode doping, (3) line widths were
variable and the tested values were somewhat suspicious for at least
one kind of the electrical line width test structures, (4) the contact
resistance to the diffused regions was very good but had a tendency
to shade on the edge die, (5) diode thresholds and breakdowns look
excellent, (6) forward dynamic resistance of the diodes are high, (7)
process limitations on contact hole sizes is 5uM and lastly (8) 5uM
diffusions are possible but do not space adjacent diffusions closer
than lOuM.
The test time of Process 3 wafers is 49.7 seconds/die or 30
the of testing three more test

minutes/wafer indicating effect
structures and performing the line width measurements. Minimum
89
defect density is 262 defects/cm2 as measured from CAP1
breakdown data.
90
XIII -
CONCLUSION
A system has been designed and presented which attempts to
bridge the gap between current in-process control techniques and
evaluating process control from finished device wafers. This was
'test'
accomplished using an electrically testable, chip. The system
consists of (1) designing a test chip suitable for characterizing and
quantifying important process control parameters, (2) designing the
test chip process which incorporates the various features found in a
currently used device process, (3) designing a versatile testing
system to evaluate the test structures when completed, (4)
fabricating the test chip, (5) performing the tests and (6) analyzing
and recording the data.
The test chip consisted of structures aimed at analyzing the RIT
4-Level PMOS process. Most test structures were electrical in nature
but several optical structures were also included to act as fabrication
aids. The electrical test structures were selected and designed such
times relative to the

that they would (1) require short processing
device process, (2) can be easily automated as far as testing the
devices, (3) non-complex so that data can be easily interpreted and
range of materials and

measured, and (4) be compatible with a wide
parameter values.
The processes designed for the test chip, as mentioned, were
based on the RIT 4-Level PMOS process. In short, this process
field oxidations, 600Ang gate oxidations, luM

consisted of 5000Ang
source and drain diffusion using spin-on dopant technology, lOuM
91
lithographic design rule limits, 5000Ang metalizations and an all wet
etching technology.
Two test systems were designed built

and including software.
One serves to evaluate capacitance/voltage and capacitance/time
tests of MOS capacitors and while the DC Automatic is

Probing system
capable of
performing full automatic testing of DC parameters plus
oxide thickness measurements and analyze the data.
The ability of this system to evaluate process control and
process capabilities has been successful to a large degree. The test
devices have clearly pointed out where fabrication problems exist
and have quantified process limitations where they could not be
done before. Process engineers can now attack these problems
knowing which areas are causing the highest yield limiting factors.
Designers or product engineers now have the ability to predict the
yield for a given design criteria and thus project device unit costs.
The task of correlating process control data with final device yield is
still be done. Good process control yield data is meaningless if the
device is not yielding to the expectations generated from that data.
It is at this time that I acknowledge the patience and support
of my thesis advisor, Dr. Lynn Fuller and his staff of Microelectronic
Engineering lab technicians (namely Scott) who, without their
assistance, I would still be bumbling throughout the fabrication
RIT. I also like to thank the Microelectronic

facility at would
Division Eastman Kodak Company for use of their

Technology of
92
testing equipment/facilities and for allowing me the time to pursue
this degree.
93
XIV -
FUTURE DTRFPTTOMg
What are the next logical steps in incorporating a system such
as this to a real life manufacturing situation? What should be done
differently or what should be changed? The following comments are
a listing of ideas that have been collected during the course of this
project that might make this concept a stronger and more useful tool
to IC processing.
(1) The process and conditions that were chosen for the test chip are
life'
probably not consistent with 'real conditions in manufacturing.
It is critical to adapt the test chip process to mimic stages of the
device process in order to get good test chip performance to device
performance correlation.
(2) As the lab progresses (film thickness get thinner, dimensions get
smaller, particle counts decrease etc.) it will become necessary refine
the latitude of test structures (5, 10, 15uM dimensions to 1, 2, 3uM

levels).
(3) By no means are the test structures included with this design an
exhaustive set. As needs change with time, new designs may become
necessary to monitor a desired parameter or effect.
(4) An increase in the number of chips or samplings per wafer would
provide more accurate statistics and better characterization within
the wafer. This would require a smaller and more closely spaced
chip size.
94
(5) Extension of the number of pads per test structure would reduce
the number of prober steps (which is a major factor in the
'doubling-up'
cumulative test time) and would allow of test
structures at the expense of a different capacitor layout.
(6) Integration of the CV test system DC Automatic

and
Probing
system into one system should be a high priority item. This would
require adapting a hot chuck to the wafer prober, building a light
tight fixture around the prober and utilize the unused capacity of the
matrix for multiplexing. This would provide for a very powerful
testing system.
(7) Extension of the data collection/evaluation/storage procedures is
a key in any data acquisition system. The options demonstrated in
this system are really the tip of the iceberg. Areas for further work
include (a) trend charting and control charting from run to run data,
(b) application of database techniques for mass storage/retrieval of
data, (c) extended statistics such as linear, radial and wafer to wafer
components of parameter variations (d) contour plotting in addition
to wafer mapping, (e) more user interaction on data display such as
user input scales on graphic plots and data searching and (f)
development of a more useful representation and calculation of
defect densities as pertaining to oxide defects, short/open defects etc.
Research implementation of an electrical alignment test

(8) and
structure for measuring registration errors during lithography.
95
XV -
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Chip Design for Process Problem Debugging and Yield Prediction

Experiments,"
Solid State Technology, Vol. 29, pp. 87-93, March 1986.
(21) A. C. Ipri, J. C. Sarace, "Integrated Circuit Process and Design

Techniques,"
Rule Evaluation RCA Review, Vol. 38, pp. 323-350,
1977.
(22) M. G. Buehler, B. R. Blaes, C. A. Pina, T. W. Giswold, "Pinhole

Analysis,"
Array Capacitor for Oxide Integrity Solid State Technology,
Vol. 26, pp. 131-137, November 1983.
98
(23) L. W. Linholm, "The Design, Analysis
Testing and of a
Comprehensive Test Pattern for Measuring CMOS/SOS Process

Control,"
Performance and Semiconductor Measurement Technology,
National Bureau of Standards Special Publication 400-66, August
1981.
(24) D. K. Schroder, "Semiconductor Material and Device

Characterization,"
Arizona State University, 1985.
(25) R. S. Muller, T. I. Kamins, Device Electronics for Integrated
Circuits. J. Wiley, New York, 1977.
(26) S. M. Sze, Physics of Semiconductor Devices. Wiley -Interscience,

1969.
(27) T. Hogan, T. Nutting, ICE. Microelectronics Department,
Rochester Institute of Technology, 1985.
(28) M. G. Buehler, "Comprehensive Test Patterns with Modular Test

Approach,"
Structures: The 2 by N Probe-Pad Array Solid State
Technology, Vol. 22, pp. 89-94, October 1979.
Control,"
K. Ishikawa, "Guide to Quality White Plains, New York,

(29)
Krause International Publications, 1971.
99
XVI -
BIBLIOGRAPHY
B. S. Baliga, M. S. Adler, "Measurement of Carrier Lifetime

Semiconductors,"
Profiles in Diffused Layers of IEEE Trans. Electron
Devices, Vol. ED-25, April 1978.
M. G. Buehler, B. R. Blaes, C. A. Pina, T. W. Giswold, "Pinhole

Analysis,"
Array Capacitor for Oxide Integrity Solid State Technology,
Vol. 26, pp. 131-137, November 1983.
M. G. Buehler, S. D. Grant, W. R. Thurber, "Bridge and van der
Pauw Sheet Resistors for Characterizing the Line Width of Conducting

Layers,"
650-
Journal of the Electrochemical Society, Vol. 125, pp.
654.
M. G. Buehler, W. R. ber, "An experimental Study of
Structures,"
Various Cross Sheet Resistor st Journal of the
Electrochemical Society, Vol. 125, pp. 645-650, April 1978.
M. G. Buehler, "Comprehensive Test Patterns with Modular Test

Approach,"
Structures: The 2 by N Probe-Pad Array Solid State
Technology, Vol. 22, pp. 89-94, October 1979.
P. S. Burggraaf, "C-V Plotting, C-T measuring and Dopant
Equipment,"
Profiling: Applications and Semiconductor International,
Vol. 3, pp. 29-42, October 1980.
Measurement,"
J. Dey, "In-Process Wafer Test and
Semiconductor International, Vol. 11, pp. 52-55, January 1988.
100
B. J. Gordon, "A Microprocessor-Based Semiconductor
System,"
Measurement Solid State Technology, July 1978.
B. J. Gordon, "On-Line Capacitance-Voltage Doping Profile

Measurement of Low Dose Ion
Implants,"
IEEE Trans. Electron
Devices, Vol. ED-27, pp. 2268-2272, December 1980.
F. P. Heiman, "On the Determination of

Minority Carrier
Lifetime from the Transient Response of an MOS

Capacitor,"
IEEE
Trans. Electron Devices, Vol. ED-14, pp. 781-784, November 1967.
T. Hogan, T. Nutting, ICE. Microelectronics Department,

Rochester Institute of Technology, 1985.
A. C. Ipri, J. C. Sarace, "Integrated Circuit Process and Design

Techniques,"
Rule Evaluation RCA Review, Vol. 38, pp. 323-350,
1977.
Control,"
K. Ishikawa, "Guide to Quality White Plains, New York,
Krause International Publications, 1971.
L. W. Linholm, "The Design, Testing and Analysis of a
Comprehensive Test Pattern for Measuring CMOS/SOS Process

Control,"
Performance and Semiconductor Measurement Technology,
National Bureau of Standards Special Publication 400-66, August
1981.
101
W. Lukaszek, W. Yarbrough, T. Walker, J. Meindle, "CMOS Test
Chip Design for Process Problem Debugging and Yield Prediction

Experiments,"
Solid State Technology, Vol. 29, pp.87-93, March 1986.
E. J. Meisenzahl, "An Automated CV Test Station for Process

Control,"
Kodak Technical Report, No. 178790T, January 1985.
Microelectronic Engineering Department, Rochester Institute of
Technology, EEEE676 -
IC Processing Lab course, 4-Level PMOS
Project, Spring 1986.
R. S. Muller, T. I. Kamins, Device Electronics for Integrated
Circuits. J. Wiley, New York, 1977.
Set,"
E. T. Nelson, "Z7 Process Development Mask Kodak
Technical Report, No. 1787000, November 1983.
F. H. Nicollian, J. R. Brews, MOS Phvsics and Technology. J.
Wiley, New York, 1982.
G. L. Schnable, "Failure Mechanisms in Large-Scale Integrated

Circuits,"
IEEE Trans. Electron Devices, Vol. ED-16, pp. 322-331, April
1969.
E. H. Snow, A. S. Grove, B. E. Deal, C. T. Sah, "Ion Transport
Physics, Vol. 36,

Films,"
Phenomena in Insulating Journal of Applied
pp. 1664-1673, May 1965.
102
S. M. Sze, Physics of Semiconductor Devices. Wiley-Interscience,
1969.
L. M. Terman, "An Investigation of Surface States at a
Diodes,"
Silicon/Silicon Oxide interface Employing Metal-Oxide-Silicon
L. J. van der Pauw, "A method of Measuring the Specific

Shape,"
Resistivity and Hall Effect of Discs of Arbitrary Phillips
Research Reports, Vol. 13, pp. 1-9, February 1958.
K. H. Zaininger, F. P. Heiman, "The C-V Technique as an
Tool,"
Analytical Solid State Technology, Vol. 13, pp. 49-56, May
1970 and Vol. 13, pp. 46-55, June 1970.
M. Zerbst, Z. Agnew. Phys., Vol. 22, pp. 30-33, 1966
K. E. Klausman, S. Kar, "Determination of the

Ziegler,
Semiconductor Profile Right up to its Surface Using the MIS
Doping
Capacitor,"
103
APPENDIX A -
FABRICATION SURVEY
Below is a rather large and extensive summary of the
information collected from process engineers of an IC fabrication
facility. The list does not contain all the data that was collected.
Process Fabrication Processing Common process control
Area Functions Concerns Measurement Techniques
Furnace Oxidations Film thickness Ellipsometry

Nitrides Film uniformity Inspection
Polysilicon Gas purity Interference Reflectrometry
Poly doping Gas flow rates 4pt Probe
LPCVD films Film Nf CV testing
Annealling Contamination Thermocouples
Diffusions Temperature Particle counters
Sintering Temp, uniformity FTIR reflectrometry

Topography Breakdowns
Cleanliness Stylus profilometry
Oxidation rates
Deposition rates
Crystal defects
Mobile ion contamination
contamination
Heavy metal
Fixed oxide charge
Pin hole density

POCL doping
POCL uniformity
Wafer warpage
IC Cleanliness Line width monitors

Lithography patterning
PR application, PR thickness Interference Reflectrometry
PR Inspection
PR exposure uniformity
Environmental monitors
PR developing PR quality/purity
Mask Alignment Particle counters
Exposure quality
Exposure uniformity
Bake temperatures
Bake uniformity
Topography
PR adhesion
Bake temperatures
Bake
Table t6 - Fabrication Survey
104
Plasma Etch Dry material Etch rate Shorts probing
etches Etch uniformity Inspection
End point detection Plasma power meters
Gas purity/quality Particle counters
Gas flow rates Stylus profilometry
Etch profiles
Cleanliness
Plasma power
Loading effects
'Stringers'
Metallization Metal film -

Cleanliness 4pt probe
'Sonogage'
Sputtering depositions Target quality/purity thickness tests
Film resistivity Inspection
Film thickness Bias monitors
Thickness uniformity Particle counters

Resistivity uniformity Stylus profilometry
Vacuum
Bias conditions
Topography
Adhesion
Hillocks
Clean -
Organic clean Cleanliness Inspection
Wet etches Inorganic clean Contamination CV tests
Brush cleans Chemical quality Chemical analysis
Various wet -
Bath temperature Temperature monitors
material etches Bath uniformity Particle counters
Etch profiles
Ion Implant Elemental Implant power 4pt probe
implants Implant dose Particle counters
Implant uniformity Internal machine monitors
Various beam param. Spreading resistance
Cleanliness
Contamination
Table t6 (cont.) -
Fabrication Survey
105
APPENDIX B -
MASK MAKING PROCEDURES
The following appendix contains details of the mask making
procedures used to generate both the master lOx reticle and the lx
mask reticle.
MANN PATTERN GENERATOR 3000
AUTO Mode
Flash Intensity -
B
MANN PHOTOREPEATER 3000
CONTROL UNIT
Exposure spacing -
300mils
Exposures/row -
12
Flash Mode
Shutter - AUTO
Shutter Exposure -
xlO (2.3)
Trigger A
Lamp
-
AUTO STOP Mode
Row Disabled
Skip
RUN Mode
FLASH UNIT
Disabled
Feed/Step -
Flash MED (3.5

Intensity
-
AUTO Mode
106
MASK MAKING
Master Reticle Mask
Mask Developing ID # Developing ID#
CC Normal 040-01-1R Normal 040-01 -1M
OXIDE Normal 040-02- IR Reverse 040-02-1M
DIFF Normal 040-03-1R Normal 040-03-1M
METAL Normal 040-04- IR Reverse 040-04-1M
EXTRA Normal 040-05-1R Reverse 040-05-1M
NORMAL Developing procedure REVERSE Developing procedure
1) Developer 4 minutes 1) Developer 20 minutes
2) Stop 20 seconds 2) Dl rinse 2 minutes
3) Fixer 2 minutes 3) Bleach 5 minutes
Dl 2 4) Dl rinse 30 seconds
4) rinse minutes
blow 5) Clear 5 minutes

5) dry
6) Dl rinse 30 seconds
7) blow dry
8) Green light 30 seconds
9) Developer 5 minutes
10) Stop 15 seconds
11) Fixer 2 minutes
12) Dl rinse 2 minutes
13) blow dry
107
Dl water -
distilled water
Developer 4 parts Dl water
1 part Kodak HRP developer
Stop -
1 part Kodak Indicator STOP Bath
62 parts Dl iter
Fixer -
Premixed sc don
Bleach -
1 liter Dl water
9.5gm Potassium Dichronate (K2Cr207)

12ml Sulfuric acid (H2SO4)
Clear 1 liter Dl water
90gm Sodium Sulfate (NaS03)

CB-1
108
APPENDIX C -
CAPACITOR ALGORITMS
The following appendix contains the theory and algorithms
used for evaluating the capacitor test structures and is integrated
into the CV test system. In particular these include (1) CV tests, (2)
CVBT tests, (3) CT tests, (4) ZERBST tests and (5) DOPING PROFILE
tests. Examples of Process 1 devices are included for each.
T -
Temperature (K)
k -
Boltzman's constant
q
-
Electronic charge (Q)
Eox -
Dielectric constant of silicon dioxide
Esi -
Dielectric constant of silicon
E0 -
Permittivity of free space (F/cm)
Cox -
Silicon dioxide capacitance (F)
Cmin -
Inversion capacitance
A -
Capacitor area (cm2)
CV Test
From capacitance versus voltage curve starting from an
accumulation condition:
inversion condition to an
10"7)T2
Band 1.1785-(9.025 * 10-5)T-(3.05 *
[6]
Gap (V) -
Eg =
Intrinsic carrier Concentration -
(cm'3)
2.51 * IO19
(P3/4) *
((T/300)3'2)
* EXP(-Es/2kT>
[7]
Ni =
P1/2=0.81577+(3.4353*103)*T*[l-T/437.6+(T/814.2)2+(T/1356)3]
109
Work Function (V) Wf = 1/2 (-Eg) N-poly gate [8]
= 1/2 (+Eg) P-poly gate
=
l/2(-0.22-Eg) Aluminum gate
Oxide thickness (cm) -
Tox =
E0XE0A/C0X [9]
Depletion depth Wmax EsiE0A/Cmin [ 1 0]
-
= -
EsiTox/Eox
at inversion (cm)
Substrate -
Ns =
[4EsiE0kTln(Ns/Ni)]/(Wmax2q) [11]
Concentration (cm-3)
Fermi level (V) -
Xb =
kTln(Ns/Ni) [12]
Flat band -
Cn, =
(EoxE0A)/(Tox + P) [13]
Capacitance (Cfb)
P =
(Eox/Esi) *
SQRT[(kTEsiE0)/(qNs)]
The flat band voltage (Vfb in Volts) is the voltage at which Cfb
was found on the C vs V curve.
Metal-semiconductor Wms =
Wf + Xb N-type substrate [14]
Work function (V) =
Wf -
Xb P-type substrate
Fixed oxide -
Qss =
[Cox(Wms-Vfb)]/(qA) [15]
charge (Q/cm2)
Threshold voltage (V) Vt =

Vfb + P [16]
= Vfb-P
P =
2Xb + (A/Cox)SQRT[4E0EsiqNsXb)
110
CVBT Test
Two CV tests are performed. The first test is an initial test.
The second test is performed after the capacitor has been subjected
to a bias temperature stress cycle -
typically this is +/-

10VDC for 5
minutes at 250C.
Mobile ions -
Nl =
Cox (Vfb2 -
Vfbi)/qA [17]
in Oxide (Ions/cm2)
Where: Vfbi -
Flat-band voltage from initial CV curve
Vfb2 -
Flat-band voltage after bias temperature stress
CT Test
Pulse capacitor from accumulation to deep depletion and
monitor time required for capacitor to relax to the inversion
capacitance. The time to recover is called the Storage Time.
Zerbst Test
d/dt(Cox/C)2
Using the data from a CT test, plot -
vs (Cmin/C -
1)
and from this curve:
Bulk lifetime (Sec) -
Tg = (-2CoxNi)/(Slope CminNs) [18]
Surface Generation -
S0 = (Intercept EsiE0Ns)/(-2C0xNi) [19]

Velocity (cm/sec)
111
Donant Profiling Test
From a deep depleted, pulsed CV plot (do not allow electron
hole pairs to collect at the surface):
Define: Ns -
Electron concentration at surface
Nfb- Electron concentration at flatband
* [(CCox)/Cox-C)]2 *
Gl = + (kT/q) d/dV(l/C2) P-type wafer [20]
[(CCox)/C0x-C)]2 *
= -
(kT/q) *
d/dV(l/C2) N-type wafer
(1-G)/(W/L)2
=
-2G/(1-G) + [21]
Where G =
Ns/Nfb [22]
and W/L =
SQRT(G-ln(G)-l) [23]
and 0 =< G <= 1
Solve for G (transcendental function)
G2 = (1/(1-G))[1-2(W/L)2G/(1-G)2] [24]
Bulk -
N(W) =
2/(EsiqA2) * [d/dV(l/C2)]-l *
G2 [25]
Concentration (cm"3)
[(2kTEsi)/(q2N(W))]1/2
Debye Length (cm) L = [26]
Depletion Depth (cm) W = L *

SQRT(G-ln(G)-l) [27]
112
in
r-
o
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Q_
>
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s p CE
\ h-
U)
_1
r-
a: O
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M
U
cr
(E
u
JD s:
<+ +> V)
> > z
in
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s
3DNUlI3UdUD
Figure f27 -
CV Plot
113
CO
h-
o
_l
Q.
>
u u
fX
r-
a: _l
o O
r- >
t-i
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CE
Q_
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Q
BDNbllDUdbD
Figure f28 -
CVBT Plot
114
' i i 1
r-
1 1 in cd
i
in
r^
\
-
r-
O \
_J
Q.
h-
m \ o
\ Ld
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h- U)
i
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z
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rx u
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u
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CD
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Figure f29 -
CT Plot
115
s
cn
co
h-
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_J o
Q. (U
O W
r-
Q3 \
cn w E
co
PQ _. o
a: o
u
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ro
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Z Ql
i-h =)
z cn
1 j 1 s
r^ to in ^ m oj
cn od
E^(D/x3)^P/P
(NdON)
Figure f30 - Zerbst Plot
116
1 1 1 1 1
in
1 1 1 1
o
_J
CL -
_
s
>
-
CJ
o
u
cn
_i
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n
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OJ
E
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cn
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-
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I
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-
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Ld in
-q-
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"
I
11 1
II
Ld c cn
J X X Ld M .Q X _
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cjuui-cr:o>>z
in
1 1 1 1 1 1 1 1 i 1 l
Aia/Jd
01
E
BDNUlIDUdUD
Figure f31 -
Deep Depleted CV Plot
117
rffH s
-HfH fff CD
^3-
in
cn
D)-
O CD
^3"
C
CE in
<r%
*
t
u Ld cn
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_J
CD 00 z
n
cn OJ o
L_ OJ Ql
O OJ U
K ll CD M
CL c II cn z
w
CJ Ll.
z S o
cn
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o i
o r-
rr Z
OJ Ld
r-
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~~
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r-
o
r-
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i
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OJ Q
U
CE
CL
CE
U
CD
trrft-
S
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Ld Ld Ld Ld
ceîuo) DNidoa
Figure f32 -
Doping Profile Plot
118
APPENDIX D -
PROCESS DETAIL
This section contains the detail that was used to

processing
perform the steps shown in fl6 of Section VII.
SUBSTRATES: Silicon
<100> orientation
N-type (phosphorus doped)

7.5-12.5 ohm-cm resistivity
20mils thickness
Monsanto vendor
FULL CLEAN: Scrub wafesrs (MTl scrubber)
APM 15 minutes
Dl soak 1 minutes
HF 2 minutes
Dl soak 2 minutes
HPM 15 minutes
Dl soak 4 minutes
Spin dry 5 minutes
Dl soak -
Distilled H20
Scrub -
2000rpm brush scrub 9.0sec
Brush 2.0sec
delay
Dl dispense 5.0sec
4000rpm spin 8.0sec
5000rpm spin 9.0sec
119
APM -
5 parts H20
1 part H2O2 hydrogen peroxide (30% unstabilized)
1 part NH4OH ammonium hydroxide (27% )

Temperature = 75C
HF- 10 parts H20
1 part HF hydrofluoric acid
HPM- 5 parts H20
1 part H2O2 hydrogen peroxide (30% unstabilized)
1 part HC1 hydrochloric acid (37%)

Temperature = 75C
Spin dry -
Digital Equipment Corporation spinner
1500rpm
5 minutes
QUICK CLEAN: Scrub
H2SO4/H2O2 10 minutes
Dl soak 4 minutes
Spin dry
H2SO4/H2O2-3 parts H202 Hydrogen peroxide (30%)
1 part H2S04 Sulfuric acid (35%)
120
600Ang DRY OXIDE: MARK IV M300 diffusion furnace
Wet O2 purge: 10 minutes
Middle tube
Temperature: 1100C
Dry O2 environment
O 2 flow rate: 8 1pm
Time: 15 minutes
5000Ang WET OXIDE: MARK IV M300 diffusion furnace
Wet O2 purge: 10 minutes
Middle tube
Temperature: 1100C
Wet O2 environment
Bubbler temp.: 100C
O2 flow rate: 2 1pm
Time: 30 minutes
5000A Al DEPOSIT: Consolidated Vacuum Corporation (CVC) Metal
Evaporator.
1 pellet (0.60 grams)
IO"5
Vacuum = 3 " Torr
ALUMINUM ETCH: Phosphoric/Nitric/Acetic acids+ H20 (16:1:1:2)

Temperature: 40C
Time: visual
OXIDE ETCH: Buffered (10:1) HF
121
PHOTORESIST MASKING:
GCA Wafertrac for PR application and developing

Kasper Model 2001 lx contact aligner for exposure
Step 1: PR application High pressure scrub
Dehydration bake: Temperature: 350C
Time: 300sec
HMDS (Hexamethyldisilazane) coat
12000 A Photoresist coat
Pre-bake: Temperature: 90C
Time: 120sec
Step 2: PR exposure Using appropriate mask and Kodak 820 resist
Energy = 55mJ =
Lamp Intensity *
Time
Step 3: PR developing Develop photoresist
Post-bake: Temperature: 140C
Time: 120sec
For aluminum films -

No high pressure scrub
250C Dehydration bake
No HMDS application
HMDS coat: Dispense: 2.0sec, 500rpm
Spin: 60.sec, 5000rpm
122
Photoresist coat: Dispense: 1.5sec, Orpm
Spin 5.0sec, 500rpm
Spin 20. sec, 5000rpm
Develop PR: Dl pre-wet 5.0sec
Dispense 7.0sec, Orpm
Soak 23. sec, Orpm
Dl rinse 30. sec, 500rpm
Spin 20.sec, 500rpm
>HOTORESIST STRIP: TEGAL Plasmaline asher
O2 flow rate: 1.5 1pm
Forward Power: 275 Watts
Reflected Power: <10 Watts
Pressure: <2.5 torr
5PIN-ON DOPANT: Apply liquid dopant with syringe
Using Headway Research Ine photoresist
spinner (Model 1-EC101-R485)
Spin: 30 sec, 3000rpm
This yields approximately 2000A of dopant to surface
123
DOPANT DRIVE-IN: MARK IV M300 diffusion furnace
Top tube
Temperature: 1100C
N2 environment
N2 flow rate: 5 1pm
Time: 30 minutes
This yields a erfc distributed diffusion of approximately luM
SINTER: MARK IV M300 diffusion furnace
Temperature: 450C
Forming Gas environment
Flow rate: 5 1pm
Time: 30 minutes
Forming Gas: 90% N2
10% H2
124
APPENDIX E - PROCESS 1 DATA
of selected detailed
The following section contains examples
data from Process 1 devices.
125
DATE : 1 1 / 1 0/87
RUN : TEST 1
WAFER : 0 4-
PROCESS 1
PAGE 1 OF 2
< CflPI > UDPU1 UDPU2 UJ30.100 LU15 1000 <--

-cone -->
< SERP-
~>
CHIP Jul 200 100 600 BOO Rhosl Rhos2 Delta linewidth 5 10 15 s 10 15
XX:YY (BNG) > (Phns/sc (rfl) (un> (Oner Short pr Resistive)
20:20 671 7.67 7.68 7.36 7.21 -3.00 -2.00 -10.00 -10.00 S s 0 ! 0 s r :
21:20 660 8.00 7.80 7.57 -1 00 1.11 .72 -50.00 -30.00 R R R ! 0 R R 1
22:20 667 7.11 7.17 7.36 1 20 .23 1.75 -10.00 -30.00 R S R i 0 R R 1
23:20 660 7.16 7.50 7.02 2 21 1.18 2.57 50.00 -50.00 R S S 1 0 R R !
21:20 616 8.02 7.67 7.23 6 57 .16 .27 -50.00 -50.00 R R R 1 0 S S 1
25:20 615 7.63 7.36 7.10 1 32 -3.00 -3.00 -10.00 -10.00 S S R 1 0 R R i
20:21 662 7.81 7.72 7.16 -1 00 .13 3.10 -10.00 -50.00 0 S S : o R R i
21:21 661 7.72 7.72 7.52 -1 00 3.62 .07 -10.00 -3.31 S 0 R 1 0 R R !
22:21 675 7.17 7.22 -1.00 7 26 .07 .07 -10.00 -1.68 S S S i 0 S R 1
23:21 1 615 7.17 7.75 7.16 6 50 -3.00 -3.00 -10.00 -10.00 S 0 S 1 0 R R :
21:21 1 636 7.80 7.71 7.36 -1 00 -1.00 .09 -50.00 -20.00 S s S 1 0 R R 1
25:21 ! 639 7.51 7.60 7.12 6 99 .13 .10 -50.00 -50.00 R s s i 0 R R :
20:22 1 619 8.00 7.82 -1.00 7 11 .08 .93 -30.00 -50.00 S 0 s : o R R i
21:22 ! 728 7.22 -1.00 6.71 -1 00 .09 .06 -50.00 -1.83 S R R 1 0 R S 1
22:22 1 611 7.97 7.30 3.69 -1 00 -3.00 .09 -50.00 -50.00 R R 0 1 0 R R I
23:22 i 633 7.69 7.80 7.10 -1 00 .05 .05 -50.00 -50.00 5 R 0 I 0 S R 1
21:22 ! 626 7.90 7.71 7.38 -1 00 -3.00 -3.00 -10.00 -10.00 S S S i s S S !
25:22 i 635 7.62 7.70 -1.00 -1 00 -3.O0 .07 -1.19 -50.00 5 S S 1 0 R R 1
20:23 I 611 8.01 7.81 7.59 7 18 .06 -1.00 -10.00 -50.00 R S S 1 s R S 1
21:23 1 631 6.22 7.96 7.72 7 61 .11 .22 -10.00 -50.00 S S R : o R R :
22:23 i 625 8.23 7.96 -1.00 7 60 .09 .98 -50.00 -50.00 S 5 5 i 0 R R 1
23:23 i 621 6.32 8.03 7.78 -1 00 .05 .32 -50.00 -50.00 S R 5 1 0 0 0 1
21:23 ! 691 7.00 -1.00 6.91 -1 00 6.77 .26 -50.00 -50.00 S R S : o S R 1
25:23 ! 710 7.12 -1.00 -1.00 6 58 -1.00 -3.00 -10.00 -10.00 S S S i 0 R S 1
20:21 I 611 8.01 7.77 5.53 -1 00 .05 .71 -10.00 -50.00 S S S : o R 5 1
21:21 ! 65B 7.79 7.59 -1.00 7 19 1.85 1.70 -10,00 -50.00 S S 0 : o R S 1
22:21 ! 620 8.33 B.02 1.09 7 66 .19 -3.00 -50.00 -50.00 S S R 1 0 R S 1
23:21 I 619 8.35 8.01 -1.00 7 69 -3.00 -3.00 -10.00 -10.00 S S 5 i 0 R R i
21:21 ! 617 8.21 8.01 -1.00 -1 00 -3.00 .08 -8.91 -50.00 R S R : o R R !
25:21 i 621 -1.00 7.91 -1.00 7 56 -1.00 -3.00 -10.00 -10.00 5 S S 1 s R R :
20:25 1 650 7.93 7.66 -1.00 -1 00 .06 .07 -50.00 -50.00 R 0 s : o R R :
21:25 631 8.12 7.82 7.61 7 19 .05 -1.00 -10.00 -50.00 S 5 s 1 0 R R 1

22:25 622 8.25 7.96 -1.00 -1 00 -3.00 .10 -20.00 -20.00 S S s ! 0 S s :
23:25 623 8.18 7.85 -1.00 7 55 .09 .07 -6.68 -2.63 S S s i 0 R S i
21:25 619 6.21 7.96 7.71 7 56 -3.00 .06 -10.00 -3.93 5 R s : o S s :
25:25 621 8.18 7.89 7.58 7 18 -3.00 .09 -50.00 -50.00 S S s i s R S !
Table t7 -
Process 1 Data Output
126
DATE 11/1 0/87
RUN TEST 1
WAFER 04
PROCESS 1
PAGE 2 OF
Parameter Jko. Std X JL Z-1 1-2 H H fcL

TDX1 -
CflPl <flnfl) 617.19 26.99 36.00 100.0 0.0 0.0 0.0 0.0 0.0
FC6P1.200 -
CflPl (HU/cn) 7.85 .37 35.00 97.2 2.8 0.0 0.0 0.0 0.0
rCRPI.100 -
CflPl fllU/cn) 7.76 .21 33.00 91.7 8.3 0.0 0.0 0.0 0.0
IWUOO -
CflPl OHI/cn) 6.99 1.06 21.00 66.7 33.3 0.0 0.0 0.0 0.0
ftflPI.800 -
CflPl (HU/cn) 6.77 1.13 21.00 58.3 11.7 0.0 0.0 0.0 0.0
SHEETRH01 -
U0PU1 (Ohns/sq) 1.01 1.88 22.00 61.1 6.3 0.0 30.6 0.0 0.0
SHEETRH02 -
U0PU2 (Ohns/sq) .68 1.15 26.00 72.2 5.6 2.6 19.1 0.0 0.0
LU15.1000 -
LU15.1000 (utl) -3.28 1.21 5.00 13.9 19.1 5.6 5.6 0.0 55.6
LU30JOD -
LU3OJ00 (il) -5.67 1.01 3.00 8.3 22.2 2.8 2.8 25.0 38.9
C0HB5 -
CH1B5/C0HB10 (S.O.R) 0.00 0.00 0.00 0.0 72.2 2.8 25.0 0.0 0.0
CO1B10 -
conss/coriBio <S,0,R) 0.00 0.00 0.00 0.0 66.7 11.1 22.2 0.0 0.0
C0HB15 -
C0H815/SERP5 (S.0.R) 0.00 0.00 0.00 0.0 63.9 11.1 25.0 0.0 0.0
SERP5 -
C0H81S/SERPS (S,0,R> 0.00 0.00 0.00 0.0 11.1 88.9 0.0 0.0 0.0
SERP10 -
SERP10/SERP15 (S.0.R) 0.00 0.00 0.0 22.2 2.6 75.0 0.0 0.0
SERP15 -
SERP10/SERP15 (S.0.R) 0.00 0.00 0.0 33.3 2.8 63.9 0.0 0.0
lest tine 1079.98 Sec

lest tine per die *
30 Sec
liafer type N
Capacitance Range =
200 pF
U0PU1 forcing current s

.10
MJPU2 forcing current .1 fl

UI30JOO forcing current .1 fl
tUI 5.1000 forcing current .1 fl
C0HIRES forcing current .1 fl
Minim* oxide defect density 93 DEF/cn2
Table t8 -
Process 1 Statistics Output
127
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TOX1 Histogram
128
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TOX1 Wafer Map
129
APPENDIX F -
PROCESS 2 DATA
The following section contains examples of selected detailed
130
DATE 11/1 0/87
RUN TEST2
WAFER 04
PROCESS 2
PAGE 1 OF
< CflPl --> UDPU1 UDPU2 LU30.100 LU1 5.1000 <COMB

> (SERP
>
CHIP loxl 200 100 60 Rhosl Rhos2 Delta linewidth 5 10 15 5 10 15
HXW (RNG) ( <Hu/cn2) (Ohns/souare) (il) (ufl) (Open. Short or Resistive)
20:20 306? .00 -2 00 -2 00 -2. -3.00 6.19 10.00 -50.00 ! R R R R I
21:20 3993 .00 -2 00 -2 00 -2. -3.00 6.27 iO.OO -50.00 ! R R R R I
22:20 3931 .00 -2 00 -2 00 -2. 00 .26 3.56 10.00 -30.00 I R R R R i
23:20 3881 .00 -2 00 -2 00 -2. 00 I .07 -3.00 iO.OO -30.00 ! R R R R I
21:20 3691 .00 -2 00 -2 00 -2. 00 -3.00 -3.00 0.00 -10.00 I R R R R I
25:20 3913 .00 -2 00 -2 00 -2. 00 -3.00 -3.00 0.00 -10.00 R 0 I
20:21 1106 .00 -2 00 -2 00 -2. 00 -3.00 -3.00 0.00 -10.00 R R I
21:21 1007 .00 -2 00 -2 00 -2. -3.00 .16 IO.OO -30.00 R R !
22:21 1089 .00 -2 00 -2 00 -2. .06 -3.00 0.00 -30.00 R R i
23:21 3929 .00 -2 00 -2 00 -2. -3.00 -3.00 0.00 -10.00 R 0 I
21:21 3911 .00 -2 00 -2 00 -2. -3.00 -3.00 0.00 -10.00 R 0 0 R i
25:21 3912 .00 -2 00 -2 00 -2. .09 -3.00 -50.00 -30.00 R R I
20:22 1137 .00 -2 00 -2 00 -2. -3.00 -3.00 -10.00 -10.00 R R R R
21:22 1055 .00 -2 00 -2 00 -2. -3.00 .17 -50.00 -30.00 R R R R
22:22 3995 .00 -2 00 -2 00 -2. .06 -3.00 -50.00 -30.00 R R
23:22 3962 .00 -2 00 -2 00 -2. .05 -3.00 -.15 -30.00 R 0 R
21:22 3951 .00 -2 00 -2 00 -1. -3.00 -3.00 -10.00 -10.00 R I 0 0
25:22 3989 .00 -2 00 -2 00 -2. -3.00 -3.00 -10.00 -10.00 R I 0 0
20:23 1217 .00 -2 00 -2 00 -2. .66 -3.00 -50.00 -50.00 R I 0 R
21:23 1132 .00 -2 00 -2 00 -2. -3.00 -3.00 -10.00 -10.00 R R R I 0 R
22:23 1069 .00 -2 00 -2 00 -2. .13 -3.00 -50.00 -30.00 R R R I 0 R
23:23 1061 .00 -2 00 -2 00 -2. .78 .05 -50.00 -30.00 R R R I 0 0
21:23 1036 .00 -2 00 -2 00 -2. -3.00 .05 -.11 -30.00 I R R R I 0 R
25:23 1053 .00 -2 00 -2 00 -2. .19 1.30 -50.00 -30.00 I R R R I 0 R
20:21 1267 .00 -2 00 -2 00 -2. .05 -3.00 -50.00 -50.00 I R R R i 0 R
21:21 1192 .00 -2 00 -2 00 -2. .32 .05 -50.00 -50.00 ! R R R i 0 R
22:21 1137 .00 -2 00 -2 00 -2. .52 -3.00 -50.00 -50.00 ! R R R I 0 R
23:21 1108 .00 -2 OO -2 00 -2. .51 -3.00 -50.00 -30.00 I R R R I 0 R
21:21 1106 .00 -2 00 -2 00 -2. .10 -3.00 -50.00 -30.00 R R R I 0 R
25:21 1126 .00 -2 00 -2 00 -2. .23 -3.00 -50.00 -30.00 R R R I 0 R
20:25 1339 .00 -2 00 -2 00 -2. -3.00 .05 -50.00 -50.00 R R R I 0 R
21:25 1261 .00 -2 00 -2 00 -2. -3.00 -3.00 -10.00 -10.00 R R R 0 R
22:25 1212 .00 -2 00 -2 00 -2. .15 .05 -50.00 -50.00 R R R 0 R
23:25 1190 .00 -2 00 -2 00 -2. .06 -3.00 -50.00 -50.00 R R R 0 R I

21:25 1189 .00 -2 00 -2 00 -2. .07 -3.00 -50.00 -30.00 R R R 0 R I
25:25 1198 .00 -2 00 -2 00 -2. .16 -3.00 -50.00 -30.00 R R R 0 R !
Table t9 -
131
DATE 11/1 0/87
RUN = TEST2
WAFER : 04
PROCESS 2
PAGE 2 OF 3
< CBP2 >

CHIP Tox2 200 100 600 800 To*1-lox2
KK:VY (AN6) ( -
(IWcn2> (HNG)
20:20 3550 -2.00 -2.00 -2.00 -2.00 I -1 !
21:20 3121 -2.00 -2.00 -2.00 -2.00 i 569 :
22:20 3367 -2.00 -2.00 -2.00 -2.00 I 561 i
23:20 3326 -2.00 -2.00 -2.00 -2.00 I 553 i
21:20 3330 -2.00 -2.00 -2.00 -2.00 I 561 1
25:20 3355 -2.00 -2.00 -2.00 -2.00 I 558 1
20:21 3530 -2.00 -2.00 -2.00 -2.00 576 1
21:21 3121 -2.00 -2.00 -2.00 -2.00 586 i
22:21 3362 -2.00 -2.00 -2.00 -2.00 727 !
23:21 3336 -2.00 -2.00 -2.00 -2.00 593 1
21:21 3338 -2.00 -2.00 -2.00 -2.00 576 !
25:21 1573 -2.00 -2.00 -2.00 -2.00 -1 1
20:22 I 3578 -2.00 -2.00 -2.00 -2.00 559 1
21:22 i 3168 -2.00 -2.00 -2.00 -2.00 587 i
22:22 I 3379 -2.00 -2.00 -2.00 -2.00 616 1
23:22 ! 3365 -2.00 -2.00 -2.00 -2.00 597 !
21:22 I 3371 -2.00 -2.00 -2.00 -2.00 583 1
25:22 ! 3161 -2.00 -2.00 -2.00 -2.00 525
20:23 I 3635 -2.00 -2.00 -2.00 -2.00 582
21:23 ! 3170 -2.00 -2.00 -2.00 -2.00 662
22:23 ! 3125 -2.00 -2.00 -2.00 -2.00 611
23:23 ! 3127 -2.00 -2.00 -2.00 -2.00 631
21:23 I 3159 -2.00 -2.00 -2.00 -2.00 577
51'
25:23 I 3512 -2.00 -2.00 -2.00 -2.00 !
20:21 1 3678 -2.00 -2.00 -2.00 -2.00 ! 5t
21:21 ! 3601 -2.00 -2.00 -2.00 -2.00 I 5s;
22:21 1 3513 -2.00 -2.00 -2.00 -2.00 j 591
23:21 i 3530 -2.00 -2.00 -2.00 -2.00 ! 578
21:21 I 3522 -2.00 -2.00 -2.00 -2.00 i 586
25:21 I 3198 -2.00 -2.00 -2.00 -2.00 I 628
20:25 I 3706 -2.00 -2.00 -2.00 -2.00 I 633
21:25 I 3700 -2.00 -2.00 -2.00 -2.00 I 561
22:25 ! 3682 -2.00 -2.00 -2.00 -2.00 I 530
23:25 I 3621 -2.00 -2.00 -2.00 -2.00 1 566
21:25 ! 3151 -2.00 -2.00 -2.00 -2.00 ! 738
25:25 ! 3326 -2.00 -2.00 -2.00 -2.00 1 B72
Table t9 (cont.) -
132
DATE : 1 1 / 1 0/87
RUN : TEST2
WAFER : 04
PROCESS : 2
PAGE 3 OF 3
Parameter Ova Std H ZN M X-2 X-3 M 1-5

TOM -
CflPl (flng) 1015.83 205.36 36.00 100.0 0.0 0.0 0.0 0.0 0.0
rCftPI.200 -
CflPl (tlU/cn) 0.00 O.OO 0.00 0.0 0.0 100.0 0.0 0.0 0.0
FCAPMOO -
CflPl (HU/cn) 0.00 0.01! 0.00 0.0 0.0 100.0 0.0 0.0 0.0
FCAP1.600 -
CRP1 (MU/cn) 0.00 0.00 0.00 0.0 0.0 100.0 0.0 0.0 0.0
FCAP1J00 -
CAP1 (HU/cn) 0.00 O.OC 0.00 0.0 2.6 97.2 0.0 0.0 0.0
SHEEIRH01 -
U0PU1 (Ohns/sq) .27 .23 20.00 55.6 0.0 0.0 11.1 0.0 0.0
SHEE1RH02 -
U0PU2 (Ohns/sq) 1.66 2.15 it. 00 30.6 0.0 0.0 69.1 0.0 0.0
LU15J000 -
LU15.1000 (ufl) 0.00 O.OC -.00 0.0 27.8 0.0 17.2 0.0 25.0
UI30.1OO -
LU30.1O0 (ifl) -.13 .o: 2.00 5.6 27.8 0.0 8.3 2.8 55.6
T0K2 -
CBP2 (flng) 3509.11 215.92 36.00 100.0 0.0 0.0 0.0 0.0 0.0
T0XW0X2 -
CAP1/CRP2 (Rng) 601.06 66.9! 31.00 91.1 5.6 0.0 0.0 0.0 0.0
fCRP2_200 -
CP2 (HU/cn) 0.00 o.ot 0.00 0.0 0.0 100.0 0.0 0.0 0.0
FCAP2.100 -
CAP2 (HU/cn) 0.00 0.01 0.00 0.0 0.0 100.0 0.0 0.0 0.0
rCHP2.600 -
CAP2 (HU/cn) 0.00 0.01 O.OC 0.0 0.0 100.0 0.0 0.0 0.0
FCRP2.B00 -
CRP2 (HU/cn) 0.00 o.ot) O.OO 0.0 0.0 100.0 0.0 0.0 0.0
C0HB5 -
CB1B5/C0HB10 (S.O.R) 0.00 0.01 0.00 0.0 0.0 0.0 100.0 0.0 0.0
C0HB10 -
COHfiS/COHBIO (S.O.R) 0.00 D.0I) 0.00 0.0 0.0 0.0 100.0 0.0 0.0
C0HB15 -
C0HB15/SERP5 (S.O.R) 0.00 0.H 0.00 0.0 0.0 0.0 100.0 0.0 0.0
SERP5 -
C0HB15/SERP5 (S.O.R) 0.00 0.0 1 0.00 0.0 0.0 97.2 2.8 0.0 0.0
SERP10 -
SERP10/SERP15 (S.O.R) 0.00 0.011 0.00 0.0 0.0 61.1 38.9 0.0 0.0
SERP15
~
SERP10/SERP15 (S.O.R) 0.00 0.0 ) 0.00 0.0 0.0 13.9 86.1 0.0 0.0
Test tine 1263.12 Sec

Test tine per die 35.09 Sec
Uafer type N
Capacitance Range 50 pF
UDPU1 forcing current *

.1 fl
U0PU2 forcing current .1 fl
LU30.100 forcing current .1 fl
LU15.1000 forcing current ,1 fl
C0H1RES forcing current .1 R
Hininun oxide defect density 1 0F/cn2
Table tlO -
133
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134
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135
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TOX1-TOX2 Wafer Map
136
APPENDIX G -
PROCESS 3 DATA
The detailed
following section contains examples of selected
137
DATE * 1 1 /08/87
RUN : PROC3
WAFER ; 0 1
PROCESS 2 3
PAGE 1 OF 3
uir UDPU1 UDPU2 LU30.100 LU15 1000 <-

-core > < SERP-
-->
CHIP Toxl 200 100 600 600 Rhosl Rhos2 Delta linewidth 5 10 15 5 10 15
JCXiVY (ANG) ( --
<hVcn2) ~ -
> (Ohnp/piuare) (ifl) (ufl) (Onrn. Short or Resistiue)

20:20 3256 -2.00 -2.00 -1.00 -2.00 13.11 12.71 -50.00 .96 R 0 0 1 0 R R 1
21:20 3233 -2 00 -2.00 -2.00 -2 00 13.35 13.05 1.33 2.86 R 0 0 1 S R R 1
22:20 3232 -2 00 -2.00 -2.00 -2 00 13.77 13.00 1.63 3.27 R R R ! R R R 1
23:20 3105 -2 00 -2.00 -1.00 -2 00 13.50 13.10 2.30 1.19 R R 0 1 R R R 1
21:20 3335 -2 00 -2.00 -1.00 -2 00 13.50 12.71 1.16 3.12 R R 0 1 R R R 1
25:20 3210 -2 00 -1.00 -1.00 -2 00 12.60 13.05 1.57 3.38 R R 0 1 S R R 1
20:21 3218 -2 00 -2.00 -1.00 -2 00 13.32 12.36 -50.00 .98 R 0 0 1 0 0 S 1
21:21 3168 -2 DO -2.00 -1.00 -1 00 13.32 13.00 1.52 3.15 R R 0 1 R R R 1
22:21 3210 -2 00 -2.00 -1.00 -2 00 13.23 13.05 2.01 3.85 R 0 R 1 R R R i
23:21 3220 -2 00 -2.00 -1.00 -2 00 13.23 12.55 .86 3.32 R R R 1 R R R 1
21:21 3203 -2 00 -2.00 -1.00 -2 00 13.32 13.05 2.18 1.12 R R R I R R R 1
25:21 3359 -2 00 -2.00 -1.00 -2 00 13.11 12.71 -50.00 3.53 R R R 1 R R R 1
20:22 3282 -2 00 -2.00 -1.00 -1 00 13.50 11.95 -50.00 .01 R R 0 1 0 R R 1
21:22 3251 -2 00 -2.00 -1.00 -2 00 13.50 13.19 2.30 1.05 R 0 0 1 R R R i
22:22 3127 -2 00 -2.00 -1.00 -2 00 13.77 12.91 1.76 3.89 R 0 0 ! R R R i
23:22 3151 -2 00 -2.00 -1.00 -2 00 13.05 13.31 2.86 1.83 R R 0 i R R R i
21:22 3377 -2 00 -2.00 -1.00 -2 00 13.50 10.67 -50.00 .99 R R 0 1 R R R I
25:22 3171 -2 00 -2.00 -1.00 -2 00 13.10 28.52 -50.00 -50.00 R R R 1 R R R 1
20:23 3321 -2 00 -2.00 -1.00 -1 00 13.05 12.61 -50.00 1.08 R R R i 0 0 R 1
21:23 3262 -2 00 -2.00 -1.00 -2 00 13.32 13.75 3.17 1.75 R R 0 i R R R :
22:23 3215 -2 00 -2.00 -1.00 -1 00 13.23 13.00 1.91 1.07 R 0 0 1 0 R R i
23:23 3219 -2 00 -2.00 -1.00 -2 00 13.23 12.81 1.72 3.99 R 0 0 i R R R 1
21:23 3281 -2 00 -2.00 -1.00 -2 00 13.11 13.18 3.39 1.87 R R 0 1 R 0 R i
25:23 3115 -2 00 -2.00 -1.00 -1 00 3.96 13.19 1.9S 1.20 R R 0 ! 0 R R :
20:21 3252 -2 00 -2.00 -1.00 -1 0D 13.59 12.90 -50.00 .12 R 0 0 1 0 R R 1
21:21 3209 -2 00 -2.00 -1.00 -2 0G 13.11 13.11 .99 2.16 R R 0 i R R R 1
22:21 3372 -2 00 -2.00 -1.00 -2 00 11.88 13.65 2.72 1.25 R R 0 1 R R R 1
23:21 3312 -2 00 -2.00 -1.00 -1 00 13.50 13.10 1.39 3.61 R R R I R R R 1
21:21 3185 -2 00 -2.00 -1.00 -2 00 2.99 13.86 3.65 1.91 R R 0 1 R R R 1
25:21 3192 -2 00 -2.00 -1.00 -2 00 13.15 13.30 2.02 1.03 R R 0 1 R R R 1
20:25 3200 -2 00 -2.00 -1.00 -2 00 -2.00 -2.00 -10.00 -10.00 R 0 0 i 0 0 R 1
21:25 3116 -2 00 -2.00 -1.00 -2 00 13.80 13.05 -50.00 .69 R 0 0 1 0 R R 1
22:25 3268 -2 00 -2.00 -1.00 -2 00 13.50 11.10 2.29 3.69 R 0 0 ! R R R i
23:25 3089 -2 00 -2.00 -1.00 -2 00 11.10 13.19 -50.00 2.99 R R R : r R R :
21:25 3092 -2 00 -2.00 -1.00 -2 00 11.01 15.82 5.63 6.07 R 0 R i R R R 1
25:25 3188 -2 00 -2.00 -1.00 -2 00 13.11 8.79 -50.00 -50.00 R R R 1 0 R R 1
Table til -
138
DATE : 1 1 Z08/87
RUN : PROC3
WAFER : 0 1
PROCESS : 3
PAGE 2 OF 3
C0HT1- <C0HT2-
< --> ) COHIRES/DIODE UMblOiit)
CHIP 3utl 5(11 Tufl 10ifl 12ufl I5ufl Re Fdr Oth Obr
XK:YY (Ooen. Short or Resistive) Ohns kOhns (U) (0)
20:20 1 0 0 R R R r ; 93.26 1.09 .37 86.06 !
21:20 1 0 0 0 R R r : 92.76 1.07 .36 77.00
22:20 1 0 0 R R R R 1 B7.19 1.07 .36 71.55
23:20 ! 0 0 R 1 R R R 1 87.16 1.07 .36 78.11
21:20 i 0 0 R i R R R 1 91.02 1.09 .36 70.32
25:20 i 0 R R 1 R R R i 103.72 1.13 .36 12.98 I
20:21 i 0 0 R 1 R R R ! 91.02 1.01 .36 78.57

21:21 ! 0 0 R : r R R 1 88.10 1.01 .36 76.11
22:21 1 0 0 R i R R R ! B3.29 1.05 .36 76.23

23:21 1 0 0 R I R R R 1 81.21 1.06 .36 75.11
21:21 1 0 R R i R R R I 86.10 1.07 .36 80.91
25:21 I 0 R R i R R R 1 100.79 1.08 .36 78.99 1
20:22 ! 0 0 R 1 R R R 1 89.60 1.03 .37 82.37 !
21:22 ! 0 R R 1 R R R 1 91.60 1.03 .37 76.19 1
22:22 ! 0 R R 1 R R R
'
181.20 1.11 .36 75.97 !
23:22 ! 0 R R i R R R 90.50 1.06 .36 76.85 !
0 R R i R R R 85.80 1.06 77.11 !

21:22 I .36
0 R R 1 R R R 91.22 1.07 75.91 !

25:22 ! .36
R ! R R R 88.10 1.01 78.83 !

20:23 ! 0 R .37
0 R R 1 R R R 87.19 1.02 78.28 !

21:23 ! .37
R 1 R R R 88.10 1.03 77.96 1

22:23 1 0 R .36
R 0 i R R R 89.86 1.06 77.20 !

23:23 ! 0 .36
: r R R ! 101.39 1.06 73.13 !

21:23 ! 0 R R .36
: r R R I 91.20 1.07 73.79 I

25:23 ! 0 R R .36
1 R R R 1 91.80 1.02 76.93 I

20:21 I 0 R R .36
R R ! 103.31 1.03 81.52 !

21:21 ! 0 R R : r .37
R R I 89.36 1.01 81.77 1

22:21 I 0 R R : r .37
R R ! 92.16 1.05 80.11 !

23:21 I 0 R R 1 R .36
R R 1 90.86 1.05 77.82 !

21:21 ! 0 R R ! R .36
R R ! 88.92 1.07 79.15 I

25:21 0 ! R R : r .33
R i 1.06 75.19 I
20:25 ! 0 R 0 1 0 0 -2.00 .28
R ! 95.20 1.01 78.72 I

21:25 ! 0 R R 1 R R .36
R 1 96.00 1. 05 80.63 I
22:25 1 0 R R : r R .36
R ! 100.79 1.06 80.00 I

23:25 1 0 R R i R R .36
R ! 111.16 1.09 81.38 !

21:25 ! 0 R R 1 R R .27
! 96.20 1.09 80.77

25:25 I 0 R R 1 R R R .36

Table til (cont.) -
139
DATE 1 1 /0S/8V
RUN PROC3
WAFER 0 1
PROCESS 3
PAGE 3 OF
Paraneter flya Std N XN X-1 _fcZ LL M X-5
3261.75 93.32 36.00 100.0 0.0 0.0 0.0 0.0 0.0

T0X1 -CRPI(Rng)
rCAP1.200 -
CRP1 (HU/cn) 0.00 0.00 0.00 0.0 0.0 100.0 0.0 0.0 0.0
fCRPMOO -
CflPl (HU/cn) 0.00 0.00 0.00 0.0 2.8 97.2 0.0 0.0 0.0
CRP1 (HU/cn) 0.00 0.00 0.00 0.0 91.1 5.6 0.0 0.0 0.0
fCRpf 600 -
CRP1 (HU/cn) 0.00 0.00 0.00 0.0 19.1 80.6 0.0 0.0 0.0
rCBP1~800
-
U0PU1 (Ohns/sq) 12.80 2.37 35.00 97.2 0.0 2.8 0.0 0.0 0.0
SHEE1RH01 -
UDPU2 (Ohns/sq) 13.10 2.B3 35.00 97.2 0.0 2.8 0.0 0.0 0.0
SHEEIRH02 -
LUIS 1000 <ufl> 3.25 1.52 33.00 91.7 2.8 0.0 0.0 0.0 5.6
LU15 1000
-
2.19 1.03 21.00 66.7 2.8 0.0 0.0 0.0 30.6

LU30"l00 -
LU30_100 (ul)
95.21 16.31 35.00 97.2 0.0 2.8 0.0 0.0 0.0
C0H1RE5 -
C0N1RES (Ohns)
36.00 100.0 0.0 0.0 0.0 0.0 0.0
U1H -
C0N1RE5 (U) .36 .02
1.06 36.00 100.0 0.0 0.0 0.0 0.0 0.0

fDR -
CONIRES (kOIra) .03
77.06 6.51 36.00 100.0 0.0 0.0 0.0 0.0 0.0

UBR -COHTRES(U)
0.00 0.00 0.00 0.0 0.0 0.0 100.0 0.0 0.0

C9IB5 -
C0HB5/COHB10 (S.0.R)
0.00 0.00 0.00 0.0 0.0 36.1 63.9 0.0 0.0
CB1B10 -
C0HB5/C0HB10 (5.0.R)
0.00 0.00 0.0 0.0 69.1 30.6 0.0 0.0
CU1BI5
-
C0HB15/SERP5 (S.0.R) 0.00

0.00 0.00 0.0 5.6 2?.f 66.7 0.0 0.0
SERP5 -
C0HB15/SERP5 (5.0.R) 0.00
0.00 0.00 0.0 0.0 11.1 88.9 0.0 0.0
SERP10 -
SERP10/SERP15 (S,0,R> 0.00
0.00 0.00 0.0 2.8 0.0 97.2 0.0 0.0
SERP15 -
SERP10/SERP15 (S,0,R) 0.00
0.00 0.CC 0.0 0.0 100.0 0.0 0.0 0.0
C0HI3 -
C0N11 (S.0.R) 0.00
0.00 0.00 0.0 0.0 27.8 72.2 0.0 0.0
C0NT5 -
C0HT1 (S,0,R) 0.00
0.00 0.00 0.0 0.0 8.3 91.7 0.0 0.0
C0N17 -
C0NI1 CS.0.R) 0.00
0.00 0.00 0.0 0.0 2.8 97.2 0.0 0.0
C0NT10 -
C0HI2 (S.0.R) 0.00
0.00 0.00 0.0 0.0 2.8 97.2 0.0 0.0
C0HI12 -
C0N12 (S.0.R) 0.00
0.00 0.0 0.0 0.0 100.0 0.0 0.0
C0HT15 -
C0NI2 (S.0.R) 0.00 0.00
Test tine 1790.52 Sec

Test tine per die 19.71 Sec
Uafer type H
Capacitance Range =
50 pf
U0PU1 forcing current .01 B

O0PU2 forcing current .01 fi
LU30.100 forcing current -
.01 fl
LU15J000 forcing current * .0035 R
COHTlES forcing current =
.01 fl
flininun oxide defect density 262 0EF/cn2
Table tl2 -
140
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Figure f38 -
LW15_1000 Wafer Map
141
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Figure f39 -
LW30_100 Wafer Map
142
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Figure f40 -
Contact Resistance Wafer Map
143
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Figure f41 -
Diode IV Curve
144
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Figure f42 -
Diode Reverse Breakdown Histogram
145
APPENDTX H -
F.RRQR CODE REFERENCE SHEET
This following page contains a printout of the Error Code
Reference Sheet that is available for printout from the DC Automatic
Probing test program. This list is intended to insure that data
acquired from the system is reasonably valid and believable. Notice
that the failure codes are either -1, -2, etc. except for the line width
failure codes which use -10, -20, etc. This is because these
parameters could conceivably have valid data exactly equal to the
error codes which would lead to much confusion. When reading data
output from a typical test or statistics report, the user is expected to
interpret -1 failure codes as -10 etc. for only the line width data.
146
Er-i-gr-
ccsle r-cfci-once chart
T0X1 -
CftPI (ftnr.)
Code3! -> Meter out of range, leaky cap or no contact
FCftPt 208 -
CftPI (Ml'/cm)
[CftPI 4BB -
CAP1 (MvVcV)
CftPI EBB -
CAPl (Hl'Tc^H
-CftPI BOB -
CftPI (Hy/cw)
4MUZ
ode -I ; riele breakdown
Held is <2Mv7cn
Code -2 > Exceeds measurement capability (100V)
Code -3 -> Bad data Field breakdown) IBMvVcm
-
SHEETRH01 -
VOPU) (Ohms/so)
sheetrhq; -
Oopij;Short
<0hms/is5)
Code -1 -> to substrate (R'.20Mohms)
Code -2 -> Open contact <R:20Mohms)
Code -3 -> Exceeds meas capability Umv), R> IBBKOhms/sq or compliance met
LUI15 1000 LUI5-

1000 (uM)
LU3S 108 LU30-
IBB
Code -10 = > =
Sheet resistance not known
Code -20 --> Short to substrate <R<2BMohms>
Code -30 --> Open contact ( R>201ohms )
Code -40 > Exceeds meas capability 1 Inv) or compliance met
Code -50 Invalid measurement (Ualue not possible)
tox: CAP2 (ftno)

Code -1 =-
Meter out of range .leaky cap or no contact
T0X1-T0X2 CAP1/CAP2 (ftno)

Code -=> Tox from CAP1 or CAP2 bad
FCftP2 20B -
CAF2 (MvVcm)
FCftP2 4B0 -
CAP2 (Ml'/TiP
rcftr: ebb -
Cftr2 <Mi'/cm)
FCftF2 8BB -
CftP2 (My/cm)
Code I -
") Field breakdown is <2MV/cm
Code -2 > Exceeds measurement capability (100V)
Bad data Field breakdown) 10MV/cm
-'.'
Code '> -
CONTRES CONTRES (Ohms!

Code -1 -=> Short to substrate (R;20Mohms)
Code -2 -> Open contact (R)20Mohms>
Ccae -3
-=
Exceeds meas capability (ImU) or R)100i.ohms
?0N7RES (I1)
"
Short to substrate <R<20Mohms)

.-de -; Open contact (R)2BMohms)
Code > Threshold > 10V
FDR CONTRES UOhms)

> Short to substrate (R<20Mohms >
==) Open contact (R>2BMohms)
) Exceeds meas capability (ImW) or R>100kohms
CONTRES (V)
Code -1 --y Short to substrate (R<20Mohms)
Code -2 => Open contact (R>20Mohms)
Code -3 > Vbr 100V
COMES/COMBIB IS. .R)
C0MEE/COMB1B (S. SI
COTi
OME 1 b C0MB15/SERP5 (L O.R)
sT^FT C0MB15/SERP5 ('.'.
grjpia SERP1B/SERPI5 ' : .O.R)
-
SERP10/SERP15 PTr7
C0NT1 R)
COrJT 1 (1
C0NT1 <sdo.R)
TiT CONT? (SlotST
CONT 12 CONTI (i .O.R)
CONT IS cont; Tl
Code S -
Short to substrate <R(20Mchms )
Code 0 Open contact <R)20Mohms )
Code R Resistive contact <R<20Mohms >
Figure 43 -
Error Code Reference Chart
147
APPENDTX T -
TV CUSTOM CIRCIITTRY DETAIL
The following pages contain documentation of the custom
hardware designed to (1) multiplex three different probes for
measurement, (2) select various DC bias voltages for use in bias
temperature stress tests, (3) turn a light, located inside the light tight
box, on or off to establish inversion conditions during testing, (4)

trigger a heat cycle for bias temperature testing and (5) read back a
status byte to determine system status.
Software Codes:
Select_code;"Character_string"
Writing Format: OUTPUT
Select code: IEEE-488 address (i.e. 707)
Character_string: P0 Disconnect all probes from cap meter
and activate DC bias settings
(either B0,B1,B2,B3)
PI Connect probe 1 to capacitance meter
P2 Connect probe 2 to capacitance meter
P3 Connect probe 3 to capacitance meter
BO Float probes
Bl Positive DC bias
B2 Negative DC bias
B3 Ground probes
LO Turn off lamp

Ll Turn on lamp
148
L2 Must follow with LO code after 500ms
which will then activate a heat cycle.
Reading Format: ENTER Select_code;String$
Select_code: IEEE-488 address (i.e. 707)
String$ : 1 character long, 8 bit ASCII byte is returned.
Format is as follows.
Bitl 0 -
Probe 1 disconnected from capacitance meter
1 -
Probe 1 connected to capacitance meter
Bit2 0 -
1 -
Bit3 0 -
1 -
Bit4,5 0,0 -
Probes are floating
1,0 -
Positive DC bias
0,1 -
Negative DC bias
1,1 -
Probes are grounded
Bit 6 0 -
Lamp off
1 -
Lamp on
Bit 7 0 -
Heat cycle
completed/'
die
1 -
Heat cycle active
Bit 8 Always 0
149
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Figure f44 -
CV Custom Circuitry Power/Layout/Parts
150
2
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Figure f45 -
CV Custom Circuitry -
Outputs
151
1-
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o ru rr-, c> id r- tr
r-xin^r cu o
L.U.U. u.u.u.iLli.
*. * en m f-. icir: ? m cu o|i.ijl
a;
ii ii ii
tc cd io cr tr to cb
gDQQCJDD AisliiiiiiiAi
<<<<<<<
c y tr tr ifl (j: w
sblsU
fcPUt
R
sppfcfel
ifiaocc
t to cjdDECL; |A :4 S2"i S3l ft^l s.

TL."lfltJl'^""<rU
i-n*->
rl
uj to cr in
1 * 7 *-
Z ru
5w pry
Q- "3
-J "3
O "3
Figure f46 -
Inputs
152
,u
tn fe
cn tn
fr
UJ Lu UJ CD CD *~
3
M
pooooocntD in in > X w
-i
ss
ttttttt ---<jMIHp--<p^^ tn
V
<
-
''
^
a:
g 3
f
,_
LU X
UJ
IUC/J 5
>O
%
U. LU D C
A A
o X
cu o
Figure f47 -
Relays/Switches
153
BIPOLAR MEMORY PRODUCTS
FIELD PROGRAMMABLE LOGIC ARRAY 82S100 (T.S.J/82S101 (O.C.)

(16x48x8)
INTEGRATED f USE LOGIC
SERIES 28
FPLA PROGRAM TABLE
POLAWTY
AND i
T--r-
-r -, ,
| -
T OR
E
1 R
M
i
s
1
4
1
3
1
2
1
1
1
0 9 e 7 e 5 4 3 2 1 0 7 e
OLITPlJT(
8 4 3 2 i 0
0
Jt L H t rt
i S 1
2
t
H-
ff (.
ft
w ft i, <. L. rt
3 3 fc. f*
a 4
L t ft
ff H1
{. fl.
5
fl_
6
UJ ff
7
r*
s:
H A.
H-
J 5 5 ii *
B_
C 9 J. A
10
N 11
L A
L rt
12
V A * 8
13 rt
14
t A r>
H ft A A
IS H A f A
16
17
rt R Pi A
16
19 1
i i H 20
21
e!
ZI
*
tm
I 22
23
24
Oi
25
26
: i 27
1 Z '** 26
29j
30
j
31
i I! s:
33
34
n * 35
IS 36
37
< mi
36
1 E 39
?-
i
u
1 40
is
41
42
43
"t" 44
45
n, I 1 46
47
i *
u X - i PIN 2 2 2 2 2 2 2 3 9 6 7 e i 1 i
2 2 4 i 1 1 i 1
Ul oj NO. 0 1 2 3 4 5 e 7 0 1 2 3 i e 7
ml z
<<
l
m Ml
t
Ul
s <
J s
2
s
K 1 i!
ft
>
t
4
>
1
Vo
e s
>
11
\3
cn
>0
3-
TS
cs
11 !
L
w Signetics
Table tl3 -
U03 FPLA Table
154
BIPOLAR MEMORY PRODUCTS
FIELD PROGRAMMABLE LOGIC ARRAY 82S100 (T.S.)/82S101 (O.C.)

(16x48x8)
INTEGRATED FUSE LOGIC
SERIES 28
FPLA PROGRAM TABLE
POLARITY
AND -1 -T-r -T
~rm
-7
T OR
E
8 R 1 1 1 1 1 1 OUTPUT (F,)
M s 4 3 2 1 0 9 6 7 e 6 4 3 2 1 0 7 e rs 4 Ts 2 1 0
0 L L L * a_ ...j
1 L L
! JL ^
m.
*
o 2 L L 1
3 L L L
ft 21 **.'
4 L L L
5 E
L
H f~,
3L"
0 } L. m.
t*
6 L i. L
ft \
7 L H L
-1 ff
6
ja_ E ii'
= m o u. . i- L ft (i
...
0 9
n
H A
10
N H A
11 L r- " fi
12
13
14
15
16
17
ii
is
ji
i i
r-r-
n 20
21
1
i is
1 22
23
ZI 24
Oi
25
1 1 p jp c
26
27
26
29
30
31
i
1 %.
u
1-
32
33
r^
34
8*
-i 35
36
<C|
37
36
i
.'
li
s ;
39
40 ;
i .
Mi
4;
X-mS
43
-
+ 44
45
M 46
i
1
1
'
47
Ul x PIN 2 2 2 2 2 2 2 3 4 5 6 7 e 9 1 1 1 1 1 1
.
2 2 1 1
Ul o! NO 0 1 2 3 4 5 6 7 0 1 2 3 5 e 7 (
mi z
a
>
Ul
u
<
V n >
^44 I f
cc
<*>
8
E iii V <3 5 a a *
a.
S4 Signetics
Table tl4 -
U12 FPLA Table
155
APPENDIX J -
CV TEST PROGRAM
The following section contains the BASIC 2.0 code written to
perform tests on the CV testing system.
156
te CV Test System Program
20 Eric J. Meisenzehl
30 Revised 07/12/85
40
50
E0
70
80
90
100 Init
1 10 DIM A<9,100! ).B(9 J001 ) >I25D ,Test*<25
120 DIM Title*! 50 5 ,Z*rS0].Sequence*tS0jrStatusSt50j,Epror$<9)[25j

130 DIM WaferlHS0].Run*[23j,Date*[25J
140 Hp4277-7I7
150 Cv interface-707
Cv_interfacet"P0"
150 OUTPUT I Turn probes off
170 OUTPUT Cv_interfacei"L0" I turn light off
180 OUTPUT Cv
lnterfacerB0"
I turn bias off

190 graphics Off
200 printer is 701
210 PRINT USING "*.K"iCHR*(27)cV"&11L
220 PRINTER IS I
230 I
240 Eox3.453l3E-13 I Oxide permittivity
250 Esi-I.03594E-12 I Silicon permittivity
250 Q-l .6021E-19 Electronic charge <C)
270 K-8.B171E-5 I Boltzmann constant <eU/K)
280
290 Flagl-1 I Flag l">oxlde entered 0->area entered
3OT Flag3"0 I Flag used In branch at AROX
310 Flag40 I Sequence flag used in IDPA6E
320 FOR 1-1 TO 3
330 Area (I )-0 I Gate area
340 ToxU )-0 I Oxide thickness
350 NEXT I
350 I
370 Type-"tr I Wafer type
6ateS-"AL"
380 I 6ate type
390 Number-3 I Number of ceps to test
Number$*3"
400
410 Ramp_stert-5 I CU ramp start
420 Ramp~stop"5 I CU ramp stop
430 Ramp step.1
T-30-
I CU ramp step
440 I Temp in Kelvin
450 ncc_voltage"15 I Accumulation voltage
460 Oep voltage-15 I Depletion voltage
470 WaiT_time"0 I Wait time in between CU data points
460 Ct_max200 1 CT cuttoff time
490 Frequency" 1000 I measurement frequency in Khz
500 Test_level*-"LO <20mUr ! Test signal level
Doping_dateS"YES"
510 I Print doping profile data pints
speedS-'SLOU"
520 Meas 1 HP4277 measurement speed

530 I
540 Clear-CHR< 255 )&CHR*( 75 )
550 I
SS0 Malnmenu: I Select tests/functions
570 OUTPUT 2 i Clears i
580 OFF KEY
590 PRINT TABXY<21 >CHRS< 129 )&"
,1 WELCOME TO THE CU STATION "&CHRSM28
) CUBT"
600 PRINT TABXY(30,4M"k0 TEST"
-
610 PRINT TABXY(30,5)|"k1 CU -
TEST"
520 PRINT TABXY<30,6>i"k2 CT -
PROFILE"
630 PRINT TABXY(30,7>rk3 DOPING -
ZERBST"
640 PRINT TABXY<30,8)i"k4 -
TESTS"
650 PRINT TABXY(30,10>rk5 SEQUENCE -
PARAMETERS-
660 PRINT TABXY(30,12>l"k7 SYSTEM -
TEST"
670 PRINT TABXY(30,13)|"k8 SYSTEM DIAGNOSTIC

-
METER"
680 PRINT TABXYt 30,14 >i"k9 ZERO CAPACITANCE

-
690 I "CVBT"
700 ON KEY 0 LABEL CU" 60T0 Test cvbt

71 ON KEY 1 LABEL "CT" GOTO Test_cv
720 ON KEY 2 LABEL
., ,._, .. 60T0 Testct
...._.._
PROFILE"
730 ON 'EV 3 LABEL "DOPING GOTO Test_dope

"ZERBST"
740 ON f.Zi 4 LABEL 60T0 Test zerbst

PARAM"
750 ON KEY 7 LABEL "SYSTEM GOTD System_param
"SEQUENCE"
760 ON KEY 6 LABEL GOTO Sequence

"DIAGNOSTICS"
770 ON KEY 8 LABEL 60T0 Diag_test

METER"
780 ON KEY 9 LABEL "ZERO GOTO Zero_meter

790 I
157
600 GOTO 800
810 I
820 I
III '"Tesuti ,-UjENCE"

Sel6Ct ' ,erleS f *"t8
Ii*ie*:":**,#
IfS SEQUENCE PROGRAM
THE SEQUENCE OF THE TESTS YOU WISH TO PERFORM (DO NOT USE COMM
SI?.
?> ,CHR '29 >&Sequence$&CHR< 128>i
870 INPUT Sequence!
680 L-LEN( Sequence!)
890 Y-2
900 Flag4-0
Z*-*"
910
920 FOR Z-1 TO L
Sequence$tZ,Zj"0"
132
940
IE
IF Sequence*CZ,Zj-"1"
THEN TestK Y
>-"CVBT"
>-"CU"
THEN TestK Y
950 IF Sequence*! Z,Zl-"2"
THEN Test*( Y
>-"CT"
Sequence$tZ.Z]-"3" PROFILE"
?,2
970
JE
IF SequenceStZ
THEN TestK Y )-"DOPING
>-"ZERBST"
THEN Test$( Y
980 X-NUMi Sequenced Z,Z3>
990 IF X>53 OR X<48 THEN 1030
1000 IF X-48 OR X-49 OR X-51 OR X-52 OR X-53 THEN Flag4-1
1010 Y-Y+1
Z*-Z*&*k"&Sequence*[Z,Z]&"
1020
1030 NEXT Z
1040 Sequencee-Z*
1050 OUTPUT 2iCleart|
10S0 IF Y-2 THEN Main_menu
1070 End_sequence-Y-1
1080 I
1090 FOR Z-2 TO End sequence
*"
1100 PRINT USING "OO.K.K'i'TEST |Z-1 lTest*( Z )
1"-"
1110 NEXT Z
1120 I
1130 BEEP
1140 INPUT "ENTER OK TO CONTINUE" ,Z*
ZS-'OK"
1150 IF THEN Idpage
1 160 60T0 Main menu
1170 I
1180 I SYSTEM f^.sETERS
1190 I
1200 I
1210 Systen_param: ! Alter system global parameters
1220 OUTPUT 2 i Clear* t
PARAMETERS"
1230 Menu*-"SYSTEM
1240 OFF KEY
1250 PRINT TABXY(2S,0)|CHRS( 129 )&" SYTSTEM PARAMETERS "&CHRK 128 >
1260 PRINT TABXY(?C F'i"k0 AMBIENT TEMPERATURE <C>
-
-
"iT-273
"
:
1270 PRINT TABXY'iJ t
.-.k1 ACCUMULATION UOLTAGE 
- -
"lAcc voltage
"
1280 PRINT TAB> ><tii,'i) I "k2 DEPLETION UOLTAGE (V)
-
iDep~voltage -
1290 PRINT TA6Xi'<20,B>i"k3 MEASUREMENT FREQUENCY (KHz) - "iFrequency

-
1300 PRINT TABXY(20,9)i"k4 UOLTAGE SETTLING TIME (SEC) - "|Uait_time

-
"
1310 PRINT TABXY(20.10)i"k5 TEST SIGNAL LEUEL
- -
iTest_level*
1320 PRINT TABXY(20J1 )|"k6 CT CUT-OFF TIME
-
(SEC) "iCt max -
1330 PRINT TABXY(20.12)i"k7 WAFER TYPE

-
Slype*
MENU"
1340 PRINT USING "/ ,19X

i "k8 RETURN TO MAIN
-
1350 I "TEMPERATURE"
1360 ON KEY 0 LABEL 60SUB Temperature
UOLTAGE"
1370 ON KEY 1 LABEL "ACC 60SUB Acc_voltage
UOLTAGE"
1380 ON KEY 2 LABEL "DEP GOSUB Dap voltage
"FREQUENCY"
1390 ON KEY 3 LABEL GOSUB Frequency

TIME"
1400 ON KEY 4 LABEL "SETTLING 60SUB Wait_time

LEUEL"
1410 ON KEY 5 LABEL "TEST GOSUB Test_level
TIME"
1420 ON KEY 6 LABEL "CT 60SUB Ct_max
TYPE"
1430 ON KEY 7 LABEL "WAFER GOSUB Type
MENU"
1440 ON KEY 8 LABEL "MAIN GOTO Maln_menu

>"
1450 ON KEY 9 LABEL "MORE 60T0 More

1460 DISP
1470 I
1480 60TO 1360
1490 !
1500 I
1510 More: I More system parameters
1520 OUTPUT 2iClear*i
lltl PRINTETABXY(26,0>|CHR*<129>&" SYTSTEM PARAMETERS

DOPING DATA PR:i'OUT
"&CHRK
"
128 )
iDoping_dataS
1550 PRINT TABXY(20,5)i"kS -
"
1550 PRINT TABXY(20,6)i"k6 -

MEASUREMENT SPElu iMeas_speed$
1570 I DATA"
1580 ON KEY 5 LABEL "DOPING 60SUB Doping_data
158
1590 ON KEY 6 LABEL "MEAS SPEED"
GOSUB Meas speed
MENU"
1600 ON KEY B LABEL "MAIN GOTO Main menu
1610 ON KEY 9 LABEL "MORE >"
GOTO System _param
1620 I
1630 60T0 1630
1640 I
1650 I
1660 I
1670 Test_cvbt: I
1680 TestK 1 )-"CVBT"
Title*-"
1690 CU/BT PR06RAM ..."
1700 GOTO Idpage

1710 I
1720 Test cv: I
>-"CU"
1730 TeslK 1
1740 Title*-"""* CU PROSRAM "
1750 GOTO Idpage

1760 I
1770 Test ct: 1
)"CT"
1780 TesT*(1
1790 Title*-"-"*" CT PROGRAM "
1800 60T0 Idpage

1810 !
1820 Test dope: I
PROFILE"
1830 TesTK 1 )-"DOPING
Title*-"
1840 DOPING PROFILE PR06RAM
"
1850 GOTO Idpage

1860 I
1670 Test zerbst: I
>-"ZRBST"
1880 TesT*(1
1890 Title*-"""* ZERBST PROGRAM
"""
1900 60T0 Idpage

1910 I
1920 Idpage: I Enter wafer ID/ start test
Menu*-"IDPA6E"
1940
1950 OFF KEY
I960 Sequence- 1
lnterfacei'PB"
1970 OUTPUT Cv
interfacei"B0"
1980 OUTPUT Cv
interfacei"L0"
1990 OUTPUT Cv
2000 Title_length-40-LEN(Tltle*)/2
2010 PRINT TABditle length >|CHRK 129 >&Tltle*&CHRK 128 >
2020 PRINT TABXYdl ,4)|"k5
-
DATE "iDate*
2030 PRINT TABXY< 11 ,6)|"k6
-
RUN "iRun*
2040 PRINT TABXYdl ,8>t "k7 -
WAFER ID "iWafer*
1>-"CT"
2050 IF TestK THEN 2180
)-"SEQUENCE"
2060 IF TestK 1 AND Flag4-0 THEN 2180
(-"BREAKDOWN"
2070 IF TestK 1 THEN 2110 ,
2080 IF Flagl-0 THEN PRINT TABXY( 1 1 10 )i"kB . "&CHRK 129 )&"AREA"1CHRK 128fa"/0X
-
IDE cm2 "|Area( 1 >

2090 IF Flagl-1 THEN PRINT TABXY( 1 1 0 )i "kB
.1 AREA/"&CHRK 129 )&"OXIDE"&CHRK 126
-
)&"
ANG "(Toxd )*1.E+8
>-"ZERBST"
2100 IF TestK 1 THEN 2160

"
2110 PRINT TABXYdl ,12)i"k3 UOLTAGE RAMP (U)

-
--"T iRamp_start-.
2120 PRINT TABXY< 40,13)1 "STOP "tRamp_stop

2130 PRINT TABXY< 40,14 >i "STEP "iRamp_step *
2140 PRINT TABXY(35,15)r
2150 Points-ABS< ABSiRamp start-Ramp stop >/Ramp_step )
2160 PRINT TA6XY(35.16)|T* DATA POINTS - "iFoints
2170 I
21 80 I
2190 ON KEY 0 LABEL "WAFER TYPE-"lType* 60SUB Type
2200 Z*-UALK Number >
2210 ON KEY 2 LABEL "* CAPS-"&Z* GOSUB Caps
MENU"
2220 ON KEY 9 LABEL "MAIN 60T0 Mam menu

60T0 Start
""
2230 ON KEY 4 LABEL "* START

"DATE"
2240 ON KEY 5 LABEL GOSUB Date

"RUN"
2250 ON KEY 6 LABEL GOSUB Run

ID"
2260 ON KEY 7 LA6EL "WAFER 60SUB Wafer
>-"CT"
2270 IF TestK Sequence THEN 2190

AND Flag4-0 THEN 2190
(-"SEQUENCE"
2280 IF TestK Sequence "AREA/OX"
2290 ON KEY 8 LABEL 60SUB Arox

)-"ZERBST"
2300 IF TestK 1 THEN 2320

"RAMP"
2310 ON KEY 3 LABEL GOSUB Ramp

2320 ON KEY 1 LABEL "GATE-"&6ate* 60SUB 6ate
2330 I
2340 60T0 2190
2350 I
2360 Start: I Start Test
159
2370 OUTPUT Hp4277|"C2U1T1F1P0"
2380 IF Frequency-1000 THEN OUTPUT Hp4277TA4"
2390 IF Frequency<>1000 THEN

2400 OUTPUT Hp4277i*A2"
2410 OUTPUT Hp4277| "FR"
iFrequency t
"EN"
2420 END IF
2430 IF Test_level*[1 THEN OUTPUT
Hp4277i"V2"
2440 IF Test_level*[1 THEN OUTPUT

Hp4277i"V1"
Meas_speed*-"FAST"
2450 IF THEN OUTPUT
Hp4277i"M3"
2460 IF Meas_speed*-"MEDIUM" THEN OUTPUT Hp4277i"M2"
2470 IF Meas speedl-'SLOW"
THEN OUTPUT
Hp4277i"MI"
2480 IF Testld )-"SEQUENCE TEST" AND Flag4-0 THEN 2560

2490 Flag3-1
2500 IF Aread )-0 AND Tox( I )-0 THEN GOSUB Arox
2510 Flag3-0
2520 FOR 1-1 TO 9
2530 Error( I )-0
2540 NEXT I
2550 !
2560 OUTPUT 2 t Clear* i
KEY-
2570 OFF
2580 PRINT TABXY(Title_length,3)iCHR*( 131 >&Title*&CHRK 128 >
2590 GOSUB Probe_check
2600 Inltial_time-TIMEDATE
2610 I
2620 I
)-"SEQUENCE"
2630 IF TestK 1 THEN I Test sequence loop
2640 FOR Sequence-2 TO End sequence
2650 PRINT TABXY(26,3>|CHRS< 131 )&Tltle*&CHRK 128)
2660 FOR Z-2 TO End sequence
2670 Tit le_length-4B-LEN< "êstK Z ) )/2
26B0 PRINT TABXYUitle length )|Testi Z >
,5+Z
2690 IF Z-Sequence THEFJ FRINT TABXY(Title_length ,5+Z (iCHRK 131 (STestK Z (tVCHR
K128
2700 NEXT Z
)-"CUBT"
2710 IF TestK Sequence THEN GOSUB Cvbt
>-"CU"
2720 IF TestK Sequence THEN 60SUB Cv
)-"CT"
2730 IF TestK Sequence THEN GOSUB Ct
PROFILE"
2740 IF TestK Sequence )-"DOPINS THEN 60SUB Doplng_prof i le
(-"ZERBST"
2750 IF TestK Sequence THEN GOSUB Zerbst
2760 NEXT Sequence
2770 END IF
2780 I
2790 I
2800 Sequence-1
"CUBT"
2810 IF TestK 1 THEN GOSUB Cvbt
"CT"
2820 IF TestK 1 THEN GOSUB Ct
"CU"
2630 IF TestK 1 THEN GOSUB Cv
PROFILE"
2840 IF TestK 1 "DOPING THEN GOSUB Doping_prof ile
"ZERBST"
2850 IF TestK 1 THEN GOSUB Zerbst
2860 GOTO Idpage
2870 BEEP
2880 STOP
2890 !
2900 I
2910 1
2920 Cvbt: I CUBT test algorithm
2930 FOR K1-1 TO 3
2940 IF K1>1 THEN 60SUB Probe_check
2950 FOR L-1 TO Number
2960 I-K1+3*(L-1 )
2970 IF K1-1 THEN Error (L)-0 RUN"
2980 Bias run-"INITIAL RUN"
2990 IF KT-2 THEN Bias run*-"POSITIVE BIAS RUN"
3000 IF K1-3 THEN Bias_run*-"NEGATIUE BIAS

3010 OUTPUT Cv interfacei"P"&CHRKL> I Turn Probe On
3020 60SUB Cv Hat a
3030 IF ErrorTD-1 AND K1>1 THEN 3070
3040 GOSUB Oxide_cap
3050 GOSUB Data_comp
3060 IF Error(L)-1 AND K1-I THEN 2960
Cv_lnterfacei'P0"
3070 OUTPUT
3080 NEXT L "
3090 IF K1-1 THEN OUTPUT Cv_lnterfacei "Bl I Positive bias stress

"B2"
3100 IF K1-2 THEN OUTPUT Cv interface! I Negative bias stress

3110 IF KI-1 OR K1-2 THEN 60SUB Heat_cycle
Turn
interfacei"B0"
3120 OUTPUT Cv I bias off
3130 NEXT K1 Hp4277|"BI0EN"
3140 OUTPUT
3150 GOSUB Title
160
3160 GOSUG Cv graph
3170 I
3180 PRINTER IS 701
3190 PRINT CHRK27(fc"&k3S"
" "
?8
3210 ?R.1SJ,,XAf CIf
Z-LEN(Date*&" "&Run*&"
""BILE ION CONTAMINATION SUMMARY
"Wafer*)
Z-Date*6." 'IRunti'
illi "&Wafer*
3230 PRINT TAB(40-Z/2)|Z*
3240 PRINT CHRK27>&"&k0S"
3250 PRINT USING "//"
2?l? "CftPACITOR t MOBILE IONS (I0NS/cm2) FLATBAND S

HIFT (mU)
"
3270 PRINT
3280 !
3250 Z-0
3300 Avg-0
3310 Avg2-0
3320 FOR 1-1 TO Number
3330 PRINT
3340 IF Error(3*I-2)-1 THEN
3350 PRINT TAB(3)iItTAB(20)i" BAD DATA
"
|TAB(50 )|Error( I )
3360 GOTO 3470
3370 END IF
3380 Shlft1-Ufb(3*I-1 )-Ufb(3*I-2) I Positive-Initial
3390 Shift2-Ufb(3*I-1 )-Ufb(3*I ) 1 Positive-Negative
3400 Avg-Avg+A6S( Shift 1 )+ABS( Shif t2 )
3410 Avg2-Avg2+AB5( Shift 1 >*2+ABS< Shi f t2 >*2
3420 Z-Z+2
3430 Mi 1-Cox( 3*1-2 )*Shif 1 1 /( Q*Area( 3*1-2 )>/1.E+9
3440 Ml2-Cox(3*I-2)*Shlft2/(Q*Aree(3*I-2)>/1.E+9
"POSITIUE-INITIAL"
3450 PRINT USIN6 3540, 1, 1 1 /
,Mi .Shift .001
3460 PRINT USING 35501 "POSITIUE-NEGATIUE" Shif t2/. 001

,Ml2
,
3470 NEXT I
3480 IF Z-0 THEN 3560
3490 Std-SQR(ABS(Avg2/(Z-1 )-Avg*Avg/( Z*( Z-1 )>))
3500 Avg-Avg/Z
TAB(57)i" "
3510 PRINT
3520 PRINT USING '57X
i"AU6-"
,K ,3X .DDDD.D
DDDD.D"
i INT( l0*Avg/.001 +
"STD-"
)/10 .5
3530 PRINT USING "57X ,K.3X.

i i INT(10*Std/ + 5 1/10 .001 .
3540 IMAGE 3X ,D,6X ,18A .SX .6D.3D ,20X .SD.D
3550 IMAGE 10X ,f8A,5X .fo.aD b ,20X .50.
3560 PRINT CHRK 12)

3570 PRINTER IS 1
3580 RETURN
3590 !
3600 I
3610 i
3620 Cv: I CU test elgorithm
3630 FOR 1-1 TO Number DATA"
3640 DISP "CAPACITOR *"|I|"CU
3650 Error(I)-0
3660 OUTPUT Cv lnterfacei"P"SCHRK I ) I Turn Probe on
3670 605UB Cv_Bata
3680 G0SU6 Oxide.cap PROFILE"
3690 IF TestK Sequence >-"DOPING THEN 60SUB Inv_cap

3700 GOSUB Data comp
3710 IF Error ( IT- 1 THEN 3640
interfacei"P0"
3720 OUTPUT Cv
3730 NEXT I
Hp4277|"BI0EN"
3740 OUTPUT
3750 GOSUB Title
3760 GOSUB Cv_graph
3770 RETURN
3780 I
3790 Ct: I CT test algorithm
3800 FOR 1-1 TO Number *" TIME"
3810 DISF "CAPACITOR ill "STORAGE
3820 OUTPUT Cv lnterfacei"P"liCHRK I )
3830 J-0
3840 GOSUB Inv cap
3850 GOSUB Oxide cap
Hp42"7i"BI"lDep_voltages"EN"
3860 OUTPUT
3870 60SUB Ct_data i*P0"
3880 OUTPUT Cv interface

Test(5"equence)-"ZERBST*
3890 IF THEN GOSUB Data_comp

3900 NEXT I Hp4277i"BI0EN"
3910 OUTPUT
3920 60SUB Title
3930 GOSUB Ct_graph
161
3940 RETURN
3950 I
3960 I
Dopin0-ppofile: '
llsl Doping Profile test algorithm
3990 60SUB Cv
4000 I
4020 Counter-0
4030 Correction* I >-0
4040 Cutoff(I)-0
4050 FOR J-2 TO Points
4060 DISP "PROFILE CONVERTING"!
I. J
JF A/<cox( i )-a< k j ) )
4212 9rniv
IFAtl.J ><-A(I
i?I2
4100 6g1-KTC*C
) THEN 442^0
.J-1
4110 Gg1-Gg1/(B(I.J)-B(I.J-1 ))
41a0 6g1-A6S(6gl )
4140 I
4150 IF A(I.J><-A(I.J-1 ) THEN 4420
4160 Counter-Counter+1
4170 IF 6g1>2/3 THEN 4430
4180 62-1
4190 IF 6oK.05 THEN 4310
4200 6-. 0005
4210 X1-G
4220 X2-1-6
4230 X3 (2*G/X2
(+X2/(G-L0G(S )-1 >-6g1
4240 X4
(2/X2-2)+<X2+L0G(G(-X2*(1-T/G))/(6-L06(S)-1 ("2
4250 6-G-X3/X4
4260 IF G<0 THEN G-1.E-150
4270 IF ABS((X1-G)/6)>.0001 THEN 4210
4280 X1-1-G
4290 X2-6-L0G(G>-1
4300 62-1 /X1( 1-2*X2*6/X1"2)
4310 X1-2*(S(I,J >-B(I.J-1 ))*G2/(Esi*Q*Area(I>*2)
4320 A( 1+3.Counter )-ABS( XI /( I /Ai I J CZ-1 /A( I
, )"2 >)
.J-1
4330 L-SQR<2*K*T*Esi/( Q*A( 1+3 ) ) )

.Counter
4340 IF GgK.05 THEN

4350 B( 1+3 )-Esi*Area( I )/C
.Counter
4360 Correction* I )-B( 1+3, Counter ) 1 Correction factor pointer (G2>

4370 END IF
4380 IF Gg1>-.05 THEN B( 1+3 )-L*SQR( 6-L0G( 6 (-1 )
.Counter
4390 IF Counter- I THEN 4420

4400 IF B(I.J)-Ufbd) THEN Cutoff ( I )-B( 1+3 > ! Depth et flatband
.Counter
4410 IF B( 1+3 >>B( 1+3

.Counter > THEN Counter-Counter-1
.Counter-)
4420 NEXT J
4430 Dope_polnts( I )-Counter-1
4440 IF JT-Points THEN Dope_points( I )-Cutof f ( I >
4450 NEXT I
4460 OUTPUT 2iCleari
4470 OISP
4460 (
4450 1
4500 Doping_graph: I Doping Profile graphics
4510 FOR T-1 TO Number
4520 GOSUB Doping scales
4530 CLIP 0,Xmax,T4,l9
4540 MOVE BU+3.1 >*1 .E+4A( 1+3.1 ))
,L6T<
4550 FOR J-1 TO Oope_points( I )

4560 DRAW B(I+3,J)*1.E+4,L6T(A(I+3.J>)
4570 NEXT J
4580 DUMP GRAPHICS
4590 PRINTER IS 701
"3/"
4600 PRINT USING
4610 IF 1-2 AND Number-3 THEN PRINT CHRK12)
4620 PRINTER IS I
4630 NEXT I
data*-"N0"
4640 IF Doping 15"
THEN 4960
4650 PRINTER 701 POINTS"
"
4660 PRINT D0PIN6 PROFILE DATA
4670 PRINT 3"
"
4680 PRINT CAP 1 CAP 2 CAP
N"
"
4690 PRINT * W N W N W
" (cM-3)"
4700 PRINT (uM) (cm-3) (uM> (cm-3) < uM )
"
4710 PRINT
4720 Z-0
162
N|)(D-op(e-polnts(IZ THEN Z-Dope_polntsd >
4750
4760 FOR J-1 TO Z
4770 WI-INTd00*1.E+4*B(4.J)+.5)/100
47B0 Z1-INT(LGT(A(4,J>))
4790 N1-INT(100*A(4lJ>/10"Z1 + .5)/100
4800 IF Number- 1 THEN
6OTOT49l0N6 "* 'DDD,6X D-DD '3X 'DD-DD -A ,J Wl 'N1 -Z1
4820
4830 END IF
4840 W2-INT(100.1.E+4*B(5.J)+.5>/100
4850 Z2-INT<LGTCA<5.J>>>
48G0 N2-INT( 100*A(5.J )/10'Z2+.5 )/100
4870 IF Number-2 THEN
78?5 ,.
USING "X.DDD.6X.D.DD,3X,DD.DD,A.DD,5X,D.DD,3X.DD.DD.A.DD"iJ,U1
,,P,RINd
,N
1, E ,Z1 ,W2 ,N2 ,"E",Z2
4890 GOTO 4950

4900 END IF
4910 W3-INT( 100*1 .E+4*B(6.J )+.S)/100
4920 Z3-INT(LGT(A(6,J)>)
4930 N3-INT( 100*A(6 J )/ 10*Z3+.S)/100
,
4!*0 PRINT USING "X.DDD.ex.D.DD.SX.DD.DDjA.DD.SX.D.DD.SX.DD.DD.A.DD.SX.D.DD
DD.DD1A,DD"!J,W1.N1,''E",^1.W2,N2,"E,',Z2.ui,N3,',E"
,3X
Z3
4950 NEXT J
49B0 GRAPHICS OFF
4970 PRINTER IS 701
4980 PRINT CHRK 12)
4990 PRINTER IS 1
5000 RETURN
5010 I
50Z0 Doping scales: ! Doping Profile graph scales
5030 GPAPHTCS ON
5040 GCLEAR
5050 GINIT
50B0 CSIZE 4, .6
5070 Xmin-0
5080 Xmax-INT(B<I+3.1 )*1.E+4+1 )
5090 Xstep-Xmax/10
5100 Ymin-14
5110 Ymax-19
5120 WINDOW -2*Xstep,Xmax+Xstep,13.19.5
5130 CLIP 0,Xmax,14,19
5140 AXES Xstep.1 ,0.14
5150 AXES Xstep.1 ,Xmax,14
5160 AXES Xstep.1 ,0,19
5170 CLIP OFF

5180 FOR Z-14 TO 18
5190 FOR Y-1 TO 10
5200 IF Z-14 AND Y-1 THEN 5320
5210 MOVE Xmax-Xstep/10,LGT(Y*10-Z>
5220 DRAW Xmax+Xstep/10.LGT(Y*I0"Z)
5230 MOUE Xmln-Xstep/10,L6T(Y*10-Z >
5240 DRAW Xmin+Xstep/10,LGT(Y10"Z)
5250 IF Y-1 THEN
5260 LINE TYPE 3
5270 DRAW Xmax,L6T< 10"Z)
5280 LINE TYPE 1
5290 MOUE -1.2*Xstep,Z-.1
"
5300 LABEL 1E"&VALKZ )
5310 END IF
5320 NEXT Y
5330 NEXT Z
5340 DEG
5350 LOIR 90
5360 MOUE -1 .5*Xstep,15.5
(cm"3>"
5370 LABEL "DOPING

5380 LDIR 0
5390 FOR Z-0 TO Xmax STEP Xstep
5400 MOUE Z-Xstep/2.5,13.6
5410 LABEL Z*10
5420 MOUE Z,14
5430 LINE TYPE 3
5440 DRAW Z,19
5450 LINE TYPE 1
54B0 NEXT Z
5470 MOUE 2*Xstep,13 MICRONS)"
5480 LABEL "DEPTH (TENTHS OF

5490 IF Correction I >-0 THEN 5520
5500 MOUE Correctiond >*1.E+4,I3.3
"I"
5510 LABEL
163
5520 MOUE Xstep.19.0
5530 LABEL "CAPACITOR t"ili "DOPING PROFILE"
5540 MOUE 5*Xstep,18.5
5550 LABEL "Wmln-''iINTd I+3,Dope_points( I > >+.5 >r
.E+8*B<
Ang"
5560 MOUE 5Xstep,18

5570 Z-INT(L6T(A( 1+3, Dope oolntsd )))>
5580 LABEL USING "K i "(Ns-
"
,INTd00*A(I+3 ,Dope_polnts( I ) )/10'Z+.5 )/10
"E" " >"
0 ,Z cm3
5590 RETURN
5600 I
5610 I
5620 Zerbst: I Zerbst test algorithm
5630 60SUB Ct
5650 Z-0
5660 Norm fac(I)-0
5670 FOR 7-2 TO Ct polnts(I)
CONVERSIONS"
5680 DISP "ZERBST il i J
5690 IF A(I.J)-Ad,J-1 X-0 THEN
5700 IF J-2 THEN
5710 A(I ,J)-A(I,J)+1 .E-13
5720 G0T6 5680

5730 END IF
5740 B(I+3,J>-B(I+3,J-1 )
5750 Ad+3,J(-A(I+3.J-1 >
5760 60T0 58 IB
5770 END IF
5780 A(I+3,J)-Cmin(I)/A(I,J)-1 I X-ZERBST
5790 Bd+3.J(-Cox(I ) "2* (1 /Ad, J) "2-1 /Ad. J-1 ("2 >
5800 B(I+3.J >-ABS(B(I+3,J)/(B(I.J)-B(I,J-1 ))) I Y-ZERBST
5810 Norm feed (-Norm fac( I )+B( 1+3 , J )
*"
5820 NEXT~J
5830 Norm_fac( I >-4*Norm_fac( I )/Ct_points( I >
5640 NEXT I
5850 DISP
5660 I
5870 I
5680 Zerbst graph: ! Zerbst graphics
5890 Zerbst smooth-0
5900 FOR I-T TO Number
5910 60SUB Zerbst scales
5920 CLIP 0,Xmax.0"..92
5930 MOUE A(I + 3,2i.Bt(I+3,2)/Norm_fac(I>
5940 FOR J-3 TO Ct_points(I)
5950 IF Zerbst smooth-0 THEN 5980
5960 Ad+3,J >-TA< 1+3, J-1 )+A( I+3.J )+A( 1+3, J+1 > 1/3
5970 Bd+3,J)-(B(I+3,J-1 )+B(I+3,J )+B(I+3 ) )/3
,J+1
59B0 DRAW A(I+3,J),B(I+3,J>/Norm_fac(I >

5990 NEXT J
6000 CLIP OFF
6010 Zerbst_smooth-0
B020 MOUE .7*Xstep..97
X-EXPAND"
6030 LABEL "ENTER S-SMOOTH C-COMPRESS

6040 MOUE 1.6*Xstep..92 I-I6N0RE"
6050 LA6EL "A-ACCEPT
6060 BEEP
6070 INPUT Z*
Z6-"X"
5080 IF THEN Norm_f ac( I )-Norm_fac( I >/2
THEN Norm fac*2
Z*-"C"
6090 IF
Z*-"S"
6100 IF THEN Zerbst 1
smooth-
Z*-"X" Z*-"C"
6110 IF
Z*-"S"
OR OR THEN 5910
Z*-"I"
B120 IF THEN 6740
6130 MOUE .2*Xstep,.97
6140 PEN -1 X-EXPAND"
6150 LABEL "ENTER S-SMOOTH C-COMPRESS

6160 MOUE 1.6*Xstep,.92 I-IGNORE"
5170 LABEL "A-ACCEPT

6180 PEN 1
6190 MOUE .2*Xstep..97
(X1.X2)"
6200 LA6EL "INPUT RANGE

6210 BEEP
6220 INPUT X1_range,X2_range
6230 XI range-X1_range*Xstep
6240 X2 range-X2 range'Xstep
6250 IF~XI range;X2_range THEN
6260 Z-5f2_range
6270 X2_range-X1_range
6260 XI range-Z
6290 END IF
6300 FOR Z-1 TO 7
164
6310 S(Z)-0
6320 NEXT Z
6330 FOR J-3 TO Ct joints! I >
jj40 IF A(I+3.JX2_range THEN 6410
52? IF ft<I+3,JXX1_range THEN 6420
6a60 Sd)-S(1)+1
6370 S(2)-S(2)+A(I+3.J)
6380 S(3)-S(3)+Ad+3.J>"2
6390 S(4)-S(4)+A(I+3.J)*B(I+3.J)
6400 S(5)-S(5)+B(I+3,J)
6410 NEXT J
6420 M1-(S(2)*S(5)-Sd >*S(4 ) )/( S(2 )*S(2 )-Sd >*S(3)>
6430 B1-(S(5(-M1*S(2))/Sd )
5440 IF B1>0 THEN MOUE 0.B1/Norm feed)
64s0 IF BK-0 THEN MOVE -< Bl /Ml XXstep ,0
6460 CLIP 0.10.0,1

6470 DRAW 10Xstep,(M1*10*Xstep+B1 )/Norm feed)
6480 CLIP OFF
6500 PEN -1
(X1.X2)"
6510 LABEL "INPUT RANGE
6520 PEN 1
(Y/N)"
6540 LABEL "OK7
6550 INPUT Z*
Z*-"N"
6560 IF THEN 5910
6580 PEN -1
(Y/N)"
6530 LABEL "OK7
6600 PEN 1
6610 Llfetlme(I)-2*Cox(I)*Ni(I >/(M1*Cmln( I )Ns(I ) )
6620 Surface veld )-B1*Esi*Nsd )/(2*Cox( I )Nld ) )
5630 T0d >-2Lifetime(I )*Ns(I)/Nid)
6B40 MOUE .2*Xstep..97
" "
6650 LABEL "MINORITY LIFETIME-

usee1
I INT(Llfet lmed )*1 .E+6+.5 )|

6660 MOUE .2*Xstep..92
" "
6S70 LABEL "SURFACt VELOCITY-

cm/sec"
i INT< Surface vel( I >+.5 )i

6680 DUMP GRAPHICS
6690 PRINTER IS 701
6700 IF 1-2 AND Number-3 THEN PRINT CHR$(12)
"3/"
6710 PRINT USING
6720 PRINTER IS 1
5730 GRAPHICS OFF
6740 NEXT I
6750 PRINTER IS 701
6760 PRINT CHR$( 12)
6770 PRINTER IS 1
6780 RETURN
6790 I
6800 Zerbst scales: I Zerbst graphics scales
6810 GRAFHTCS ON
6820 GCLEAR
6830 6INIT
6840 Xmin-0
6850 Xmax-Ad+3.2)
6860 Xstep-Xmax/10
6870 WINDOW -2*Xstep,Xmax+Xstep,-.2,1.1
6860 CLIP 0,Xmax,0,1

6890 AXES Xstep,.1 ,0,0
6900 AXES Xstep.,1 .Xrnax ,0
6910 CLIP OFF

6920 CSIZE 4
6930 FOR Z-0 TO 10
6940 IF Z-0 THEN 7000
6950 MOUE Z*Xstep,.9
6960 LINE TYPE 3
6970 DRAW ZXstep,Ymln+.02
6980 LINE TYPE I
6990 DRAW ZXstep,Ymin-.02
7000 MOUE ZXstep-.4*Xstep,-.1
7010 LA6EL Z
7020 NEXT Z
7030 MOUE 3*Xstep -.2 (NORM)"
7040 LABEL "Cmin/C-1

7050 MOUE -1.5*Xstep,.2
7060 DEG
7070 LDIR 90 (NORM)"
7080 LABEL "d/dt(Cox/C >"2

7090 LDIR 0
7100 FOR Z-1 TO 10
165
7110 MOUE -1*Xstep,Z/l0-.02
7120 LA6EL 2/10
7130 NEXT Z
7140 MOUE 2'XstepJ .03
7150 LA6EL "CAPACITOR "iIi"ZERBST PLOT"
7160 RETURN
7170 I
7180 MIIII!IIMI!)III!IIMI!MIIIIIII!III!!!I!|||||!||||||||!|||MIIIII
71 90 I
7200 Date: I Enter date
Z*-""
7210
7220 DISP "ENTER DATE "&CHRK 129 >&Date*&CHRK 128 )i
7200 INPUT Z*
Z*-""
7240 IF THEN RETURN
7250 Date**ZS
7260 PRINT TABXY(40,4)iDate*i"
7270 RETURN
7280 I
7290 Run: ! Enter run number
Z*-""
7300
7310 DISP "ENTER RUN NUMBER "fcVCHPK 129 >&RunS&CHRK 128 >i
7320 INPUT Z*
Z*-""
7330 IF THEN RETURN
7340 Run*-Z*
7350 PRINT TABXY(40,6)|Run*|"
7360 RETURN
7370 I
7380 Wafer: I Enter wafer number
Z*-""
7350
7400 DISP "ENTER WAFER IDENTIFICATION "&CHRKI29 >&Wafer*&CHRK128 >i
7410 INPUT Z*
Z*-""
7420 IF THEN RETURN
7430 Wafer*-Z
TABXY(40,8)iWafer*i"
7440 PRINT
7450 RETURN
7460 !
7470 Ramp: ! Enter voltage ramp
7480 DISP "ENTER UOLTAGE RnMP START . STOP (U), STEP (V) "&CHRK129 )iRamp_s
"," "
tart i i Ramp stopi |Ramp_stepiCHRS( 1 28 > i
7490 INPUT Ramp start , Ramp stop step
" .Ramp
1.18)1"
7500 PRINT TABXV(
7510 Ramp_start-INT( 100*Ramp_start + )/100 .S
7520 Ramp stop-INT( 100*Ramp_stop+.5 )/100

7530 Ramp step-INT( 100*Ramp step+.5)/100
7540 I
7550 IF (ABS(Ramp_start )>9.99 OR ABS( Ramp_stop )>9.99 > AND ABS(Ramp_step X 1 THE
.
N Ramp step-. 1
7560 TF ABS(Ramp start X10.0 AND ABS( Ramp_stop X10.0 AND ABStRamp step X. 01 THE
N Ramp step-. 01
7570 IF ABS(Ramp_start )>40 THEN
7580 IF Ramp start<0 THEN Ramp start 40
7590 IF Ramp~start>0 THEN Ramp start-40
7600 END IF
7610 IF ABS(Ramp_stop>>40 THEN
7620 IF Ramp_stop<0 THEN Ramp_stop 40
7630 IF Ramp stop>0 THEN Ramp_stop-40
7640 END IF
7650 Points-AB5( A65(Ramp_start-Ramp_stop )/Ramp_step >
branch:
7660 Ramp Type*-"N" I
7670 IF THEN Remp_step-ABS( Ramp_step )
Type*-"P"
7680 IF THEN Ramp_step ABSiRamp_step )
Type*-"N"
76S0 IF AND Remp start<Ramp_stop THEN 7740

AND RampIstart>Ramp_stop THEN 7740
Type*-"P"
7700 IF
7710 Z-Ramp start
7720 Remp_sTart-Ramp_stop
7730 Ramp_stop-Z TABXY(50.1Z)|Ramp_starti"
7740 PRINT TABXY(50,13)iRamp_stop!"
7750 PRINT stepi"
7760 PRINT TABXY(50,14)!Ramp )|PolnTsi"
7770 PRINT TABXY(51 ,16
IF
77I0 PRINT'TABXYdoTjS)!"!!! MAXIMUM NUMBER OF DATA POINTS EXCEEDED (MAX-10
HI"
00 )
7800 BEEP
7810 SOTO Ramp
7820 END IF
10,18)|"
7830 PRINT TABXY(
7840 RETURN
7850 !
166
TT-T-273Ure: ' E"ter tenPer8ture
7H0
INPUT"fNTER
TEMPERAnmE in CELSIUS "&CHRK129>.T,CHRKI28>.
7ll0
7900 IF T<20 THEN 7880
7910 T-ABS(T+273)
aW55'5)lH73''
77ii00
7940 I
%al* An?ToUf,??; JLSTLATIN

Enter accumulation
W0LTASE
voltage
"&CHR*(T29)iAcc_voltage.CHR*d28>.
7l70 INPUT Ace 5o It
?oin 2CC-VOwageV?Jt!E,y Acc_voltage-INT<100*Acc_voltage+.S>/100
il
2112 I 5STAOHao?r,eiTHEN A=c_voltage-INT<10*Acc_voltage+.5>/10
1292 ABSTAcc voltage >>40 THEN 7960
If- Jype!"l'S!,'
IH!N A_voltage-ABS(Acc_voltage)
'g IEtI*"?!^*
II \-THEN
18-5
80^0 PRINT TABXY(55,6)iAcc
ABS( Acc_voltage )
ncc.voltage
voltagei"
8040 RETURN
8050 I
DS-voltaDe:
f22 ?*IP "EN"ER
Enter depletion voltage
DEPLETION
fg'g
8080
?.,xr..
"ltn utruciiuw UOLTAGE
INPUT Dep voltage
vuLinot &I.HKH T29
"&CHRK 1 ^3 )iDep_voltageiCHR$<128
> lUepvol tege |UHHS< 1 Zb )i
- v"
B090 Dep_voTtaged0
8100
IE THEN Dep
IF Dep voltege>-10 THEN Dep_vol
voltage-INT( 100Dep voltage*. 5 >/!00
tage-INT(l0*Dep voltage+.S )/l0
6110 IF ABSiDep voltage >>4 THEN 8070
f!2 IF Type*-"R" THEN bep.voltage
Type*-'P" ABS(Dep voltage)
!8140
S IE, THEN Dep_voltage-ABS( Dep Voltage)
T
PRINT TABXY(55,7)iDep voltaSei"
8150 RETURN
6160 I
8170 Frequency: I Enter measurement frequency
8180 DISP "ENTER MEASUREMENT FREQUENCY IN KHz "&CHRK129 )|Frequency |CHPK126 ) 1
6190 INPUT Z
8200 Z-ABS(Z)
8210 Res-1
8220 IF Z<10 THEN Z-10
6230 IF Z>-I0 AND Z<-20 THEN Res-.l
8240 IF Z>20 AND Z<-50 THEN Res-. 2
8250 IF Z>50 AND Z<-100 THEN Res-. 5
8260 IF Z>100 AND Z<-200 THEN Res-1
8270 IF Z>200 AND Z<-500 THEN Res-Z
6280 IF Z>500 AND Z<-1000 THEN Res-5
8290 IF Z>I000 THEN Z-1000
8300 Frequency-INT( Z/Res+.5 )*Res
TA6XY(55.8)|Frequencyi"
8310 PRINT
8320 RETURN
8330 I
8340 Test_level: I Enter test signal level
]-"L0" RMS)"
63E? IF Test level*! 1 THEN Z*-"HI ( IU
.2
RMS)"
B3S0 IF Test_level*t1 THEN Z-"LO (20mU
6370 Test levelC-Z*
TABXY(56,10)|Test_level*i" "
8380 PRINT
8390 RETURN
8400 I
8410 Wait time: I Enter wait time berween voltage ramp steps
8420 DI5~P "ENTER SETTLING TIME (IN SECONDS) FOR READINSS'&CHRK 129>iWait tlmei
CHR*(128)|
8430 INPUT Walt time
8440 Walt time-TNT( ABS (Wait time X1000+.S )/1000
8450 PRINT TABXY(55,9)iWait_timer
6450 RETURN
8470 I
8480 Ct max: I Ente CT cuttoff time
128)1"
8490 BlSP "ENTER STORAGE TIME CUT-OFF"SCHRK 129 )iCt_max|CHRK (MAX-500)
B500 INPUT Ct max

8510 Ct max-lT3T(ABS(Ct max X1000+. 5 1/1000
8520 IF~Ct max>500 THER Ct_max )iCt_maxi"
8530 PRINT~TABXYi55,11
B540 RETURN
8550 I
6560 !
Print/don'
8570 Doping data: I print doping dtat pints
Z*-"NO"
date*-"YES"
8580 IF Doping THEN

Doping~data*-"NO" Z*-"YES"
8590 IF THEN
8600 Doping daTa*-Z*
8610 PRINT TA6XY(56.5)iDoplng_data*r
8620 RETURN
6630 I
167
8640 I
Mea|-8.Peed!
Irkct Select HP4277 measurement
2ea_speedS-"FAST" speed
IPS II THEN Z*-"SLOU"
Meas_Bpeed*-"SLOW"
IcoS II *s_speed$
THEN Z*-"MEDIUM"
"MEDIUM"
Ilia
BfaaB Meas speedS-Z*
THEN Z-"FAST"
8720 I
PI ^Flegl-O ?HEN^-Ar^,t)hlCkne"/"PaClt'-
IfJÊ;10^1-1 THEN Z-Toxd X1.E+8

145
B|70 DISP "ENTER 6ATE AREA ( cm2 ) OR OXIDE THICKNESS (A) "&CHRK129 ) I ZiCHRSi I 28
8780 INPUT Z
8790 Z-ABS(Z)
BB00 IF Z-0 THEN 8770
8810 IF Z<1 THEN
8820 FOR Z1-1 TO 9
8630 Area(Z1)-Z
8840 NEXT ZI
8850 Flaol-0
8880 IF Flao3l THEN RETURN
a
inrea(
PRI,NI BXY(I1
1 )i
,10>,"k8
-
"&CHRK129)&"AREA"&CHRK128)&"/0XIDE cm2
8880 ELSE
8890 FOR Z1-1 TO 9
8900 Tox(Z1 )-Z*l .E-8
8910 NEXT ZI
8920 Flagl-1
8930 IF Flaa3-I THEN RETURN
894? lTox( PRINT
T
1 )1
TABXYdl k8 -
AREA/"&CHRK 129 >&"OXIDE"&CHRK12B >&"
ANG
.E+8i
8950 END IF
89E0 RETURN
8970 I
8980 Caps: I Select number of capacitors to test
BS30 IF Number*--!" THEN Z*-"2"
Number*-"2"
903e IF THEN Z*-"3"
9010 IF Number*-"3" THEN Z*-"1"
9020 Number*-Z*
9030 Number-UAL( Number*)
9040 RETURN
9050 I
9060 Type: I Select wafer type
Type*-"N" Z*-"P"
9070 IF THEN
Type*-"P" Z*-"N"
9030 IF THEN
9050 Type$-Z*
TypeS-"N"
9100 IF THEN
9110 Ace voltage-ABS(Acc_voltage )
9120 Dep_voltage
A6S(Dep voltage)
9130 Break_stop-ABS(Break~stop >
9140 END IF
Type*-"P"
9150 IF THEN
9160 Acc_voltage ABS( Acc_voltage )
5170 Dep_voltage-ABS(Dep_voltage >
9180 Break_stop ABSiBrea' stop)
9190 END IF
TestKSequence)-"CT-
9200 IF
-"ZERBST"
OR TestK Sequence >-"BREAKDOWNS" OR TestK Sequence
' >
THEN RETURN
MenuS-'IDPAGE"
9210 IF THEN Ramp branch
9220 PRINT TABXY(55,6)iAcc
voltagei"
9230 PRINT TABXY(55,7)|Dep

voltagei"
9240 PRINT TABXY(56.12)|Type*

9250 RETURN
92S0 I
9270 Gate: I Select gate type
GeteS-"AL" Z*-"NP0LY"
9280 IF THEN
GateS-'NPOLY" Z*-"AL"
9290 IF THEN
9300 6ate*-Z*
9310 RETURN
9320 !
9330 Probe check: I Perform probe check -->cap is not broken down or open
9340 FOR T-1 TO Number
9350 DISP "PROBE CHECK "il
9360 OUTPUT Cv interfacei "P "HCHR$( I )
9370 GOSUB 0xi3e_cap
9380 IF Coxd )>5.0E-12 THEN 9510
9350 DISP "PROBE *"iIi"BAD ENTER T-TRY AGAIN
-
C-CONTINUE R-RETURN TO ID
168
PAGE"
i
9400 BEEP
9410 INPUT Z*
Z*-"T"
9420 IF THEN 9350
Z*-"R"
9430 IF THEN Idpage
9440 IF Cox(IX5.00E-10 THEN 9510
9460 BEEP
fill"
9470 DISP "OUERFLOW ON ENTER T-TRY AGAIN C-CONTINUE R-RETURN TO ID_F
"
AGE i
9480 INPUT Z*
Z*-"T"
9490 IF THEN 9350
Z*-"RM
9500 IF THEN Idpage

9510 NEXT I
9520 OUTPUT Cv
interfacei"P0"
HpZ277rBI0EN"
9530 OUTPUT
9540 RETURN
9550 I
95E0 I
9570 Cv_data: I Collect C vs V data
9580 Z-I
>-"CVBT"
9590 IF TestK Sequence THEN Z-L
9600 DISP "CAPACITOR *"|Z|
)-"CUBT"
9610 IF TestK Sequence THEN DISF " CV DATA "iBias run*
DATA"
PROFILE" "
9620 IF TestK Sequence (-"DOPING THEN DISF PULSED CU
>-"CU" " DATA"
9B30 IF TestK Sequence THEN DISP CU
9640 J-0 voltaaei"EN"
9650 OUTPUT Hp4277("BI"iDep

PROFILE"
9B60 IF TestK Sequence (-"DOPING THEN 9710
PULSE LIGHT FOR 1 SEC
"
9670 OUTPUT Cv_interfacei"Ll t
9680 WAIT .1
"L0"
9690 OUTPUT Cv interfacei
9700 WAIT 2
9710 stop STEP Ramp step
FOR Volt-Ramp_start TO Ramp PROFILE" " "EN"
9720 IF TestK Sequence )-"D0PING THEN OUTPUT 717i "Bl iAcc_voltagei

9730 IF ABS(UoltX.01 THEN Volt-0
Hp4277|"Br'iUolti"EN"
9740 OUTPUT
9750 IF Volt-Ramp_start THEN WAIT .5
57S0 WAIT Wait time

Hpl277r'EX"
9770 OUTPUT
9780 J-J+l
9790 ENTER Hp4277|Ad I
,J)
CAPACITANCE ARRAY
9800 Bd,J)-Volt I VOLTAGE ARRAY
SS10 NEXT Volt
9620 Cmax(I)-0
9830 Cmln(I)-0
9840 IF J<10 THEN
9850 Cmax( I )-Ad .Points)
9850 Cmind )-A(I )

,1
9870 RETURN
9880 END IF
9890 FOR Z-1 TO 5
9500 Cmax( I )-Cmax( I )+A( I > )
,Points-(5-Z
9910 Cmind (-Cmind >+A< 1, 5+Z )

9920 NEXT Z
9930 Cmaxd (-Cmaxd )/5
9940 Cmind )-Cmln( I >/5
9950 RETURN
9560 I
9970 !
Heat.cycle:
|||| J J^Î'ShUCK ^ ^ pREsg .^^
10000 BEEP
10020 IF K1-1 THEN DISP "POSITIVE BIAS HEAT CYCLE "_

10030 IF K1-2 THEN DISP "NEGATIVE BIAS HEAT CYCLE
Cv_interfacei"L2"
10040 OUTPUT
10050 WAIT .5
"L0"
100B0 OUTPUT Cv interfacei

10070 ENTER CvJTnterfaceiZ*
10050 WAIT 1 _
10090 ON ERROR GOTO 10070

10100 IF NUM<Z*>>-192 THEN 10070
101 10 OFF ERROR
10120 I
COflT"
10140 DISP "RAISE PROBE tl . CLOSE HOT CHUCK BOX AND PRESS
10150 BEEP
10160 PAUSE , ,
10170 OUTPUT Cv interfaceTPI
169
101B0 WAIT .5
10190 OUTPUT Hp4277i"ZO"
10200 WAIT 7
!2?i2 DISP "ZEROING METER
INPUT "ZEROING OK 7
MUt
10230 IF Z-"N" THEN 10190
ENTER
c"itn Y-YES
i " N-N0"7i
n no ,Z
"LWER PRBE #1
10250 BeIp D0UN' CL0SE H0T CHUCK B0x AND -CONT'"
10260 PAUSE
10270 RETURN
10260 !
10290 I
Collect c
?SI?i Ct!^!mIdate vs T data
10320 J-0
10330 J-J+1
10340 IF J-1000 THEN 10410
iSlfg OUTPUT
HpI^X"20 ' ftPPROXIÊLY 1.8SPTS/SEC
I?I\ER
]|IIi &Wti.Ui\ timÊatyan
Mt *****
ARRAY
85IS IE 4<I.JCtTHEN max10410

4?? If "<I.J><-95*Cmind> THEN 10330
5U5
104^0
?iora9SUne( J >"TIMEDATE-T1
IF J-70^0 THEN 10480
10430 J-J+1
10440 OUTPUT Hp4277i"EX"
'
iSiS
Sill fc
^T^nA^M \
6?M "TIMEDATE-TI 1
d^T
CAPACITANCE ARRAY
TIME ARRAY
5115 IE. B<I,JXStorage_time<I)+5 THEN 10430
10480 Ct jointsd )-J
10490 RETURN
10500 I
10510 !
!2I I"v cap: ! Determine inversion capacitance
10530 OUTPUT Hp4277|"BI"iAcc voltage. "EN"
10540 WAIT 1
10550 IF ABS(Ramp_start >>ABS(Dep voltage) THEN
SP4Z77'"BIV'Ra"P-st"rt??EN"
lIPS
Hp4277'"BI"'DeP-voltagei"EN"
I0H0
10B00 OUTPUT Cv interfacei "Ll"
10610 WAIT .1
1062L OUTPUT Cv_interfacai"L0"

1063-
WAIT 2
10640 Cmini I )-0
10B50 FOR Z-l TO 5
10SS0 OUTPUT Hp4277t"EX"
10E70 ENTER Hp4277iZ1
10580 Cmind )-Cmin(I )+Z1
10690 NEXT Z
10700 Cmim I )-Cmin( I )/5
10710 RETURN
10720 !
10730 I
10740 Oxide cap: I determine oxide capacitance
10750 IF ABS<Ramp_stop)>ABS(Acc_voltage> THEN OUTPUT Hp4277i "Bl"
iRamp stop
TEN"
10/60 IF ABs(Ramp_stopX-ABS(Acc_voltage) THEN OUTPUT Hp4277i "Bl"

lAccIvoltagei "E
10770 WAIT I
Hp4277|"EX"
10780 OUTPUT
10790 ENTER Hp4277(Cox( I >
10S00 RETURN
10810 I
10820 I
10830 Datajomp: I Calculate MOS parameters
COMPUTATIONS"
10840 DISP "DATA
10850 IF Cox(IXCmaxd) THEN Error
10860 Eg( I >-1 l785-( 9.025E-5*T )-(3.05E-7*T"2 )
.
10670 Nc-.81577+(3.453E-3*T*( 1-(T/437.B )+< T/81 4.2 >"2+( T/13SE )"3 ) >
10880 Nid >-2.51E+19*i(Nc*T/300)-1.5)*EXP(-Egd )/(2*K*T>)
6ate*-"AL"
10590 IF THEN Wf ( I ) 1 1-Eg( I )/2
.
Gate*-"NPOLY"
10900 IF THEN Wf (I ) EgTl )/2
10910 IF Flag1-0 THEN Tox( I )-Area( I >*Eox/Cox( I )
10920 IF Flagl-1 THEN Area( I )-Tox( I )*Cox( I )/Eox
10930 Wmaxl lT-Esl*Area( I )/Cmln( I )-Esi*Tox( I )/Eox
10940 Ns(l)-1.E+I5
10950 Z-Nsd )
10960 Nsi I >-4*Esi*K*T*L06(Ns( I )/Ni >/(Wmax( I )*Wmax( I )*Q)
170
0970 IF Nsd><0 THEN Error
Son5 II ABS<<2-Ns(I))/Ns(I))>.00001 THEN 10950
V Test*1
(-"ZERBST"
?a5 E?}* Sequence THEN 11180

I >-K*T*L06<Ns/Ni )
2?2 5tb<!
SIS "E?x*A':ead(/(Tox(I)+(Eox/Esi>.SQR(K.T.Esi/(Q*Ns(I>)>)
Cmin(I)^Cfbd) OR CmaxdXCfbd) THEN Error
5-5 Guess-Points/2
10^0
1040 Imin-0
1050 Imax-Points
!22 IE Efb(IXA(I.6uess> THEN Imax-Guess
IF Cft>(I >>-!}< I. Guess) THEN Imin-Guess
5=5
1080 t>uess-INT((Imin+Imax)/2)
1090 IF GuessOImin THEN 11060
1 100 Z-6uess
' B(
11 'g Vc6^ '"fd I.-,?+ll),;f
1120 IF
Type*-"N" I >-B( J
-Z+' > >< <""Cfb/< A-A( I ) ) )
,Z+1 ,Z
1130 IF Type*-"P" THEN W2-Wf (I XFermid )

140 Qssd )-Cox(I)*<W2-Ufbd >)/(Q*Aread))
12 Z-2*Fermi ( I )+Area(
1160 IF Type*- N
I )*SQR( 4*Esl*Q*Ns+Z
1180 RETURN
1190 I
1200 !
1210 Error: I Error in MOS parameter calculation
1220 Probe-I
>-"CUBT"
1230 IF TestK Sequence THEN Probe-L
1240 Error ( Probe )-1
1250 IF Cox(IX.95*Cmax(I ) THEN
1260 Error*(Probe)-"LEAKY OR BROKEN
DOWN"
1270 GOTO 11340

1280 END IF
1290 IF Ns(I X0 THEN
0"
1300 ErrorK Probe )-"Ns LESS THAN
1310 60T0 11340
1320 END IF
1330 IF Cfbd)>Cmaxd) OR Cf b( I XCmlnf I ) THEN ErrorK Probe )-"Cfb OUT OF RANGE"
TestKSequenee)"CUBT"
1340 IF THEN
1350 IF K t > 1 THEN 1 1 I 80
13G0 END IF
ErrorKProbeJi"
1370 DISP ON CAP t"i Prober T-TRY AGAIN B-BYPASS R-RETURN T
PAGE"
i ID i
1360 6EEP
13SE INPUT Z*
Z*-"T"
1400 IF THEN 11180
ZS-"R"
1410 IF THEN Idpage
1420 Error ( Probe )-2
1430 GOTO 1 1180
i440 I
1450 !
1460 Cv graph: I 6reph C vs V data
1480 PRINTER IS 701
1490 FOR 1-1 TO 3*Number
1500 I )-"CUBT"
1510 IF TestK Sequence AND (1-2 OR 1-3 OR 1-5 OR 1-6 OR 1-8 OR 1-9) THE
N 11580
1520 I
1530 Z-0
1540 ON ERROR 60T0 11670
1560 IF A(I,J)>Z THEN Z-Ad.J) I Find maximum capacitance for scaling
1570 NEXT J
1580 Yranged )-INTi Z/5.0E-1 1 + 1 X5.0E-11
1590 IF Yranged J-5.0E-1 1 THEN Yranged )-INT( Z/1 1 + 1 )*l 1
.0E-1 .0E-1
1600 I >-"CU6T"
1610 IF TestK Sequence AND (1-1 OR 1-4 OR 1-7) THEN G0SU6 Cv scales
PROFILE"
1620 IF TestK Sequence
>-"CU"
OR Test*( Sequence >-"D0PING THEfl 60SUB Cv_
scales
1630 MOUE Bd,1(,A(I,1) I B->Uoltage array, A->Capacitance array
1640 CLIP Xmin.Xmax .Ymin.Ymax

1660 DRAW B(I,J>,A(I.J)
1670 NEXT J
1680 OFF ERROR
1690 CLIP OFF PROFILE"
1700 IF TestK Sequence

(-"CU"
OR TestK Sequence (-"DOPING THEN
1710 DUMP 6RAPHICS "ZI"
1720 PRINT USINS

171
\"U ^T0"^rTHEN,,83e
11760 END IF
11770 IF 1-3 OR 1-6 OR 1-9 THEN
1730 DUMP GRAPHICS
11790 PRINT USING "3/"
AN Nu"ber"3 THEN PRINT CHRK12)
END^F1"6
118*8
11820 NEXT I
11830 GRAPHICS OFF
PR0FILE"
*-18tHENF11670t$(SeqUenC
R TestK Sequence >-"CU6T"
> AND Number
liSIS AN Nunbr"3 EN ,,B70

1 1870 PRINTER IS 1
11860 RETURN
11890 !
11900 Cv_scales: I
11910 IF Type*-"N" THEN
11920 Xmln-Ramp start
11930 Xmax-Ramp~stopP
"
1 1 940 ELSE
11950 Xmln-Ramp_stop
119B0 Xmax-Ramp start
11970 END IF
X8tP"nBS<
!1 !1 115
990 Ymin-0
(Ramp_start-Ramp_stop >/10 )
12000 Ymax-Yranged >
12010 Ystep-Yrange(I)/l0
12020 GINIT
12030 6CLEAR
12040 GRAPHICS ON
ISIS
!12060 n1^v ,("15-z*xS*P.5"'+X.tp,Yiiin-2Yitp>VnaK4.Yitep
CLIP Xmin.Xmax .Ymin.Ymax
12070 AXES Xstep.Ystep.Xmin,0

12080 AXES Xstep,Ystep.Xmax,0
12050 AXES Xstep.Ystep.Xmin.Ymax
12100 MOVE 0.0
12110 LINE TYPE 4
12120 DRAW 0.Ymax
12130 LINE TYPE 1
12140 CLIP OFF
12150 CSIZE 4.0, .6
12160 MOVE Xmin+3'XstePjYmln-Ystep

"VOLTS/DIV"
12170 LABEL Xstepi
12160 MOUE Xmin+4*Xstep.Ymin-2*Ystep
"UOLTAGE"
12190 LA6EL
12200 MOVE Xmin-Xstep/2,Ymin+3*Ystep
12210 DEG
12220 LDIR 90
"pF/DIU"
12230 LABEL Ystep/1 .E-12i
12240 MOVE Xmin-1. 5*Xstep,Ymin+3*Ystep
"CAFACITANCE"
12250 LABEL
12260 LDIR 0
12270 MOUE Xmin-Xstep/4,Ymin-Ystep
12280 LABEL Xmin
12290 MOVE Xmax-Xstep/4,Ymin-Ystep
12300 LABEL Xmax
12310 MOUE -Xstep/15,-Ystep/2
"0"
12320 LABEL
12330 MOVE Xmin-1 .25*Xstep ,Ymin-Ystep/4
12340 LABEL Ymin

12350 MOVE Xmin-1. 25*Xstep .Ymax-Ystep/4
12360 LA6EL Ymax/1 .E-12
12370 Z-Xmin+.5*Xstep
Type*-"P"
12380 IF THEN Z-Xmln+5*Xstep
12390 Z1-.S5*Ystep
12400 MOVE Xmln+2.SXstep,Ymax+Ystep/3
H'CV" "CAPACITOR" PLOT"
12410 IF TestK Sequence THEN LABEL 1 1
1"
CV
)-"CVBT"
12420 IF TestK Sequence THEN
12430 IF 1-1 THEN Z3-1
12440 IF 1-4 THEN Z3-2
12450 IF 1-7 THEN Z3-3
PLOTS"
12460 LABEL "CAPACIT0R"iZ3i"CV
12470 END IF
PROFILE" "CAPACITOR"
12480 IF TestK Sequence )-"DOFINS THEN LABEL 1 1 TPULSED CV PL
OT"
12490 MOUE Z.Ymax-Z1

12500 Probe-I
>-"CUBT"
12510 IF TestK Sequence THEN Probe-L
172
2520 IF Error ( Probe )-0 THEN 12570
12530 LABEL "* BAD DATA ?"
12540 MOVE ZiYmax-2*Z1

12550 LABEL ErrorK Probe )
12550 GOTO 12750
12570 LABEL "6ATE- "i6ate*
12580 MOUE Z,Ymax-2*Z1
Sox MNT('-8E+'3,,Coxd)+.5)/10,"pF"
lilll
12600 WPIL7
MOUE Z.Ymax-3Z1
Sman :INTd.0E+13*Cmln(I)+.5)/l0rPF"
!iS m?^L-
12620 MOUe i,Ymax-4*Z1

:'INT<'-E+8.Toxd)+.5)."Ang"
tilfS MOUE
12540 Mn^L7
Z,Ymax-5*Z1
111-8 :'INTd.E+4*Area(I)+.5)rE-4 cm2"
126o0 MOUE z\.Ymax-6*Z1

12670 IF QssdX0 THEN LABEL "Qss <1EI0
Q/cm2"
"
LABEL "58 ^TC 1 E-9.QSS( I >+ 5 >/ 1 B, "E 1 0
. .
Q/cm2"
12690 MOUE'z'Ymex-WI
bnPI1/^^ :iINT(ie0.Vfb(I>+.5>/l00, "VOLTS"
!???
12710 MOVE Z.Ymax-S*Z1
"
12720 LABEL ,rUth I INTd 00*Vt ( I )+.5 )/
I00TVOLTS"
12730 MOVE Z ,Ymax-9*Z1
LftBEL 'Ms "|INT(100.|.E-14*N5(I)+. 51/100. "E14

\Utl
12750 RtTURN
cm-2"
12760 !
12770 I
12780 Ct graph: ! 6raph C vs T data
12800 PRINTER IS 701
12820 G0SU6 Ct.scales
12830 CLIP Xmln.Xmax.Ymin.Ymax
tÊ >,n(I,1 ) f B->TIME ARRAY, A->CAPACITANCE ARRAY
!?|i2
I28a0
,B<V
FOR J-2 TO Ct jointsd )
12660 DRAW Bd.JI.Ad.J)
12870 NEXT J
12880 CLIP OFF
12890 MOUE 0..95Cmin(I >
12900 IF Storage timedXCt max THEN 12950
12910 DRAW Xmin+7.5*XstepJ.'9S*Cmin(I>
12920 MOUE Xmin+5*Xstep,.95*Cmind)
"Cmin-"
12930 LABEL t INT< 9.5E+l2*Cmind >+.5 >/ 1 0
12940 GOTO 12990
12950 DRAW Storage_timed),.95*Cmln(I>
12960 DRAW Storage_timed ) ,0
12970 MOVE Storage timed )-Xstep/2 ,Ymin-Ystep/2
12980 LABEL INT(T0*Storage t lmed >+.5 )/10

12990 DUMP GRAPHICS
"3/"
13010 PRINT USING
13020 NEXT I
13030 GRAPHICS OFF
(-"ZERBST"
13040 IF TestK Sequence AND Number-1 THEN 13060
13050 FRINT CHRS(12)
13060 PRINTER IS I
13070 RETURN
13060 1
13090 Ct scales: I
13100 GRAPHICS ON
13110 6CLEAR
13120 GINIT
13130 IF Cmin(IX0 THEN Cmind )-1 .E-12
13140 Ymin-0
13150 Ymax-INT(Cmin(I)/5.0E-11 + 1 XS.0E-1 I
13160 IF Cmind X5.0E-11 THEN Ymax-INTi Cmind )/1 1 + 1 )*1
.E-1I .E-1
13170 Xmin-0
13180 Xmax-INT( Storage t ime( I )/5+.5 )*5+5 ! ROUND TO NEAREST 5 SECONDS (+5)
13190 IF Storage time(T)>Ct max THEN Xmax-Ct_max
13200 Ystep-Ymax7l0
13210 Xstep-Xmax/10
13220 WINDOW Xmin-2*Xstep,Xmax+Xstep,Ymin-2*Ystep .Ymax+Ystep
13230 CLIP Xmln.Xmax.Ymin.Ymax

13240 AXES Xstep.Ystep.0,0
13250 AXES Xstep,Ystep,Xmax.0
13260 AXES Xstep.Ystep.Xmin.Ymax
13270 CLIP OFF
13280 CSIZE 4, .6
13290 MOVE Xmln+4*Xstep,Ymin-2*Ystep

"TIME"
13300 LABEL
13310 MOUE Xmin+2.5*Xstep,Ymin-Ystep
173
13320 LABEL Xstepi"SECONDS/DIV"
13330 MOUE Xmin-Xstep/S.Ymin-Ystep
V
13340 LABEL Xmin
13350 MOUE Xmax-Xstep/3,Ymin-Ystep
13360 LABEL Xmax
13370 MOUE Xmln-1.5Xstep,Ymin+3*Ystep
13360 DEG
13390 LDIR 90
"CAPACITANCE"
13400 LABEL
13410 MOUE Xmin-Xstep/2JYmln+3Ystep
13420 LABEL Ystep/1
13430 LDIR 0
13440 MOUE Xmin-1 .25*Xstep.Ymin-Ystep/4
13450 LABEL Ymin
13460 MOVE Xmin-1. 25*Xstep,Ymax-Ystep/4
13470 LABEL Ymax/1.E-12
13480 MOVE Xmin+3*Xstep,Ymax
"CAPACITOR" PLOT"
13490 LABEL i I i "CT
13500 RETURN
13510 I
13520 !
13530 Title: I print title
CHRS(27)6"tVk3S"
13550 PRINT
"
13560 FRINT
"
*>**
>&"
13570 Z-LEN(Test*d TEST")

>i"
TEST"&"/"&Test*< Sequence > >
/-"SEQUENCE"
13580 IF TestK 1 THEN Z-LEN< TestK 1

)<>"SEQUENCE" TEST"
"
13590 IF TestK 1 THEN PRINT TAB< 40-Z/2 (iTestK 1 >i
(-"SEQUENCE" )|"
13600 IF TestSd THEN PRINT TAB(40-Z/2 JiTestK I TEST"&"/"&Test*( S
equence)
Z-LEN(Dete*&" "iRun*&"
13510 "&Wafer*>
Z*-Date$&" "&Run*&"
13620 "iWaferS
13630 PRINT TA6(40-Z/2)|Z*
13640 PRINT "
13650 PRINT
CHR*(27)&"&k0S"
13660 PRINT
13670 PRINTER IS 1
13680 RETURN
13650 I
13700 I
13710 Diag test: I System diagnostic test
13720 OFF KEY
13730 ON TIMEOUT 7.5 GOTO Err
13740 ON ERROR GOTO Err
13750 I
137B0 Begin: I
13780 DISP CHECK"
13790 PRINT TABXY(20.5)|"SELF TEST

ERROR"
13800 Z*-"TIMEOUT
interfacei"P0"
13810 OUTPUT Cv interfacei"80"
13820 OUTPUT CvCvIinterfacei"L0"
13830 OUTPUT
13840 ENTER Cv interfaceiStatus* STATE"
13850 Z*-"INCOPRECT REST

13860 IF NUM( Status* >-64 THEN 13890
13870 60T0 Err
13880 I ERROR"
13890 Z*-"PROBE DECODING

13900 FOR 1-1 TO 3
13910 OUTPUT Cv_interfacei"P"fcCHRKI >
13920 WAIT .25
13930 ENTER Cv interfaceiStatus*

13940 IF NUM( Status* )<>64+I THEN Err
13950 NEXT I "P0"
13960 OUTPUT Cv interfacei

13970 I ERROR"
13980 ZS-"8IAS DECODING

13990 FOR 1-1 TO 3
14000 OUTPUT Cv_lnterfacei"B"&CHRKI )
14010 WAIT -z5
, r. , .
14020 ENTER Cv interfaceiStatus*

14030 IF NUM(STatus*X>64+4*I THEN Err
14040 NEXT I B0"
14050 OUTPUT Cv_interfacei

14060 ERROR"
14070 Z*-"LAMP DEC0DIN6 "
14080 OUTPUT Cv_lnterfacei"L1
174
14090 WAIT .25
14100
14110 fcTMR1M?=T1rterface,s*atus
14120
OUTPUT*
rTa*uJ*><>80
THEN Err
OUTPUT Cv_interfacei "L0"
14130
14140 PRINT TABXY(40,5)i"OK"
14150
14160 OFF TIMEOUT 7
14170 OFF ERROR
14180 60T0 Haln menu
14190
14200 Err:
14210 OFF ERROR
14220 DISP Z*i" CALL ERIC MEISENZAHL FOR SERVICE'
14230 BEEP
14240 I
14250 I
14260 I
14270 Zero meter
14280
2,Cleer*,Zer
Mp "eler
"OUTPUT
14290 "RAISE PRBE *' FF 0F WAFER ftND PRESS 'CONT'
14300 PAUSE
14310 OUTPUT Cv interface i "PI"
14320 OUTPUT Hp7277i"Z0"
14330 DISF ^ZEROING CAPACITANCE METER "
14340
14350 60T0 Mein_menu
14360 END
175
APPENDIX K -
DC AUTOMATIC TEST PROGRAM
The BASIC 3.0 written tc

following section contains the code
perform tests on the DC Automatic Probing test system.
176
10 DC Automatic Probing Test Progrem
20 Rochester Institute of Technology
30 By Eric J. Meisenzahl
40 Revised 01/31/87
50
60
70 The following program contains code necessary to test and analyze
80 devices made from the Process Control Test Chip. The main program
90 flow Is listed just below this text. Subroutines are listed below this
100 main section and they are listed in alphabetical order. Wherever
1 10 appropriate comments are added throughout the code for documentation
120 purposes.
130
140 Matrix configuration
150 Inputs (rows ) 0 SMU1 ( from HP4145)
160 1 - -
SMU2 ( from HP4I45)
170 m-
-
VS1 ( from HP4145)
180 3 -
VMI ( from HP4145)
190 4 -
DRIVE ( from PAR M410)
200 5 - -
INPUT ( from PAR M410)
210 6 -
SMU3 ( from HP4145)
220 7 -
SMU4 ( from HP4145)
238
24B Outputs ( cols ) 0 Substrate
250 1 Pin 1 of device
2G3 Pin 2 of device
270 Pin 3 of device
280
290 NOTE: Voltages sent to the PAR M410 are passed through an Inverting
300 stage. The program automatically compensates for this.
310
320
330 Dimension/declare variables
34C
350 DIM Diex(50 > (50),Fcap1 200(50) , Fcapl 400(50 ), Fcapl 600(50 >
.Diey
3E0 DIM Fcapl 800(50) 200T50),Fcap2 400T50 )

,Fcap2
600(50 ).Fcap2_800( 50 )
,Fcap2
370 DIM DelteltoxISO) ( 50 ).Sheet_rho2(

,Sheet~rho1 ,Lu15_1 50 ) 000( 50 )
380 DIM Lw30 100(50). foxl(50'>.ToxZ(50).IndeA(3,15,2>,TestI[2Sj
390 DIM CombT5$(50)l5 j Comb 10K 50)15] 3 50 U53
,Serp15*<
,Comb5S<50>[5
400 DIM SerplOK 50)15 ],Serp5K 50)153

410 DIM Cont3KS0H5J fiont5S(50H5 3 )I5] 10K5O )[SI
,Cont7K50 .Cont
420 DIM Cont12K50)t5 j Cont 15$( 50 >C5 3 , Cont res ( 50 ) 50 ) 50 ) Vbr(50 )

,Vth( ,Fdr<
Z$t 1503 r 1*t 150] 3,Header3SM50 3 1 50 3

430 DIM .Heade
,Header2S[150
,Header4$L
1 503 1 503 1503

440 DIM Header5It 1503 HeaderBS[1503 ,Header7$[
,Header9$[
,Header8J[
DIM N(35),Avg(35) Std(35 ) Error (5, 35) 100 3 50 U50 3

.Parameter*!
450 ,YS(10)[
460 DIM Ualue(50) ueK 50)153

.Val
470 !
480 i
490 i
500
GOSUB Default values I Assign initial values
510
520 LOOP
GOSUB Main_menu Select test/defaults
530
OUTPUT 2iMenuSi Turn off softkeys
540
GOSUB Init_hp4145 Initialize HP4145 meters .sources
550
Initialize variables
560 GOSUB Zero_vanables
570
Timel-TIMEDATE Test stert time
580
590 FOR Chip-1 TO Number of_die
600 FOR Test-1 TO Number jf_t est 5
Move prober to chip location
610 GOSUB Move prober
GOSUB Test_wafer Test structure
620
630 NEXT Test
640 NEXT Chip
Test_time-TIMEDATE-Tlme1 Test time
650
6B0
Reset test equipment
670 GOSUB Reset_test
Calculate statistics
680 GOSUB Calc stats
Print test results
690 GOSUB Printout
Print statistics
700 GOSUB Prmt_stats
Turn on softkey menu
710 OUTPUT 2;Menu*i
720 END LOOP
730
740
750
7E0
770 l ji
780 nnnnnMMnMM
j^ SUBR0UTINES
(alphabetized)"*"
790
800
177
810
820 C 1rADtSts: Calculate avg, std. N and ^failures of each parameter
830 FOR Parameter-1 d ,, TO 31
840 GOSUB Transform I Copies parameter variables to general
850 ...
I to general variables 'Value' or 'Value*'
8G0 Nl -0
870 X-0
880 S-0
890 IF Parameter<-7 THEN GOSUB Calc stats!
900 IF Parameter-8 OR Parameter-9 THEN 60SUB Calc_stats3
910 IF Parsmeter>-20 AND Parameter<-25 THEN GOSUB Calc stats2
920 IF Process=2 THEN
930 IF Parameter>-10 AND Parameter<-1 5 THEN GOSUB Calc statsl
940 END IF
950 IF Process-3 THEN
960 IF Parameter>-16 AND ParameterC-1 9 THEN GOSUB Calc statsl
970 IF Parameter>-26 THEN GOSUB Calc stats2
980 END IF
990 NEXT Parameter
1000 I
1010 l This section determines the minimum defect
density based on capacitor
1020 I breakdowns <2MV/cm.
1030 !
1040 Area-. 0004
1050 Defect density-tErrort 1 ,2 1/100 !/Area
1060 Area-.001E
1070 Z-(Error( 1 ,3 >/1 00 )/Area
1080 IF Z>Defect density THEN Defect density-Z
1090 Area=.003B
1100 Z-(Error< 1 ,4 )/100 )/Area
1110 IF Z>Defect_density THEN Defect_density-Z
1 120 Area-.00E4
1 130 Z-(Error(1 ,5 )/100 (/Area
1 140 IF Z>Defect density THEN Defect_density-Z
1 150 Defect_densTty-PROUND(Defect density .0)
1 1E0 i
1 170 RETURN
1 180
1 190
1200 t 31 31 3t ][ 3t 3t It 3111 3t 3t 31 31 31 3131 3t 3[ 3t 31 3[ 3t 3t ]t 3t 3MC3I 3t ]t ]t ][ 3(3t 3t 3
1210
1220
1230 Calc_statsl: I Calculate statistics for parameters having failure codes
1240 ! -1,-2 or -3 that are real number parameters
1250 FOR 1-1 TO Number of_die
1260 IF Valued )<0 THEN
1270 IF Valued) 1 THEN Errorf 1 )=Error( 1
.Parameter )+ 1 .Parameter
12B0 IF Ualue(I) 2 THEN Error( 2 )-Error( 2

.Parameter
)+ 1 .Parameter
1290 IF Valued) 3 THEN Error* 3 )-Error( 3

.Parameter )+1 .Parameter
1300 ELSE
1310 Nl -N1 + 1
X- X + Value( I )
1320
1330 S= S+Value(I XValued )
1340 END I F
1350 NEXT I
1360 I
1370 I Change Error<,*) to be a percentage ( format-xxx.x )
1380 Errort 1 Parameter )-100*PROUND( Errorf 1 )/Number_of_die
.Parameter ) ,-3
1390 Error! 2 , Parameter )-1 00*PROUND< Error ( 2 )/Number_of_die

.Parameter
> ,-3
1400 Errort 3 Parameter )-100*PROUND( Errort 3 )/Number_of_die

.Parameter ) ,-3
1410 I
1420 IF N1-0 THEN RETURN
1430 N(Pareme ter)-N1
1440 AvgtPara meter )-PR0UND( X/N1 ,-2)
1450 IF N1-1 THEN RETURN % ,
14S0 StdlPara meter )-PR0UND! SQRt ABSt ( N1 S-XX )/( Nl *(N1 -1 )))>,-2>
1470 RETURN
1480
1490
1500 t 3t3[3t3[3t3t3t]t]t]t]t]t3t]t3t3t3I3I]t]t3[]t3[)I]I]I3t3I)t3[3I3[]t]t3[3
1510
1520
1530 Calc stats2: I Calculate stats from parameters that have failure code
'S* '0' 'R'
1540 I .
or
1550 FOR 1-1 TO Number of die

>-"5"
THEN Errord (-Error* 1 )+
IF UalueKI
.Parameter
I5S0 .Parameter
)-"0"
THEN Errort 2 )-Error(2 )+l
IF Value*! I
.Parameter
1570 .Parameter
)-"R"
THEN Error! 3 >-Error< 3 )+1
IF UalueSd
.Parameter
1580 .Parameter
1590 NEXT I
1600 I
178
1610 ! Change Errort ,) to be a
percentage ( format-*** *)
.
1B20 Errort 1 >- 1

00*PROUNO< Error! T
.Parameter
1B30 Errort 2; Parameter )- 1 00*PROUND( Error ( 2 (/Number of die -3)

.Parameter
1640 Parameter (/Number of die '-3

Error(3 Parameter
1650 RETURN (-lOO.PROUNDtErrorfSiParameteri/Numblrlofldie:-!)
16G0 I
1670 I
1B80
1690 innnni]t3MnnnunNnt3nt)i3i3t3i3r3t3[3i3tjnt]ntu]t]ntJt]i]
1
1700 !
1710 Calc stats 'CaIc stats for linewidth
1720 FOR 1-1 TO Number_of
k, ?n
die
parameters
1730 IF Ua lued x 10 then

1740 IF Valued) 10 THEN Error! 1 .Parameter
(-Error! 1 (+1
1750
.Parameter
IF Value I 20 THEN Error! 2 .Parameter

(-Error! 2 .Parameter )+ 1
1760 IF Value I 30 THEN Error! 3 .Parameter )-Error( 3 .Parameter )+ 1
1770 IF Valued 40 THEN ErrorU .Parameter )-Error< 4 .Parameter H 1
1780 IF Valued) 50 THEN Error! 5 .Parameter >-Error( 5 .Parameter )+1
1790 ELSE
1800 Nl -N1+1
1810 X X + Valued )
1820 S^
S+Valued )*Value(I )
1830 END I
1840 NEXT I
1850 I
I860 1 Change Errort*,*) to be a percentage < format-xxx.x )
1870 Errort 1 Parameter >-l00*PROUND( Errort T Parameter (/Number of
1880
, die. -3)
Errort 2 Parameter )-1 00*PROUND! Error! 2 >/Number~of_die -3 )
.Parameter
1890 Errort 3 Parameter )-100*PROUND( Errort 3 >/Number~of~die '-3 )

.Parameter
1900 Errort 4 Parameter )-! 00PROUND( Error! 4 . Parameter (/Number of die -3)
1910 Errort 5 Parameter )-100PROUND< Error( 5 (/NumberôCdie [-3 )
.Parameter
1920 !
1930 IF N1-0 THEN RETURN
1940 N( Parame ter)-N1
1950 Avg! Para meter 1-PR0UND! X/N1 -2)
19E0 IF NI-1 THEN RETURN
1970 Std(Paraimeter >-PR0UND(SQR!ABS( < Nl *S-X*X )/< Nl ( Nl -1 ) ) ) ) -2 )
1980 RETURN
1990 1
2000
2010 t It 3t 3t 3t 3t 3I3t 3t 3t 31 ][ 31 31 31 3t 31 31 3t ][ ]!][ ]t It ]t It ]t 3t ]t ][ ]t 3I3I][ ]t 3
2020
2030
2040 Cat disk: ! Display contents of floppy disk files
Store_or_loadS="CAT"
2050
2068 ON ERROR GOTO Disk error ~
2070 OUTPUT 2iClearI;

2080 CAT ":
2090 DISP TAB(2S)i"Press <RETURN> to continue";
2100 INPUT Z*
2110 Cat error: I
2120 OFF ERROR
2130 Menu flag-1
2140 RETURN
2150
21G0
2170 t 3t 31 It 3t 3t 31 31 3 1 ]I Hit ]I ]t It Jt ]!][ ]t ]t 3t3t 3t 3t ][ ]t Hit 31 3t 31 3 1 31 U 31 3
2180
2190
2200 Capl: I
TestS-"CAP1"
2210
2220 GOTO Cap
2230 Cap2: !
Test*-"CAP2"
2240
2250 Cap: 1 I CAP1/CAP2 test algorithm
22B8 GOSUB Display_status I Display current status

2278 GOSUB Reset_equip ! Reset meters/matrix
"335" 'INPUT'
2280 OUTPUT Matrix; ! PAR410 to 408uM cap
"304" 'DRIUE*
2290 OUTPUT Matrix i PAR410 to substrate
2300 OUTPUT Hp4145;"DS2."|-5Type +/-5U accumulation
2310 Test*="CAP1"
2320 IF Chip-1 AND THEN

2330 CALL Meast
"TUB"
,Cap_leakage,5> I Meas leak cap from VM2
",K";"D"
2340 OUTPUT Prober USING ! Lower probes on wafer
2358 WAIT .5
23B0 END IF
2370 I
2380 Area-1 .6E-3
I 400x400uM cap area ( cm2 )
"TUB"
2390 CALL Meast 5) .Cox,
I Measure capacitance
2400 IF Cox<.1 OR Cox>9.9 THEN I Cap out of meter scale
179
"325"
2410 OUTPUT Matrix; ! PAR410 'INPUT' to 200uM cap
2420 OUTPUT Matrix ("304"
I PAR410 'DRIVE' to substrate

2430 WAIT .1
2440 Area-4 .E-4

! 200*200uM cap area ( cm2 )
"TVE"
2450 CALL Meas! .Cox ,5)
I Measure capacitance
2460 IF CoxC.1 OR Cox>9.9 THEN I Cap out of scale again
2470 IF TestS-'CAPI" THEN
2480 ToxMChip > 1
2490 Fcap1_200(Chip ) 1
2500 Fcapl 400(Chip) 1
2510 Fcap1_600(Chip ) 1
2520 Fcap1_800(Chlp ) 1
2530 RETURN
2540 ELSE
2550 To*2!Chip 11
2560 Fcap2 200(Chip> 1
2570 Fcap2_400(Chip ) 1
2580 Fcap2_600!Chip ) 1
2590 Fcap2_800(Chip > 1
2G00 Delta_to*(Chip)=-1
2610 RETURN
2620 END IF
2G30 ELSE I 200*200uM cap is OK
2E40 Cox-Cox-Cep_leekage ! Subtract leakage capacitance
2B50 Co*-Co**(Cap_range/10)l 2
.E-1 ! Convert to pF units
2660 Z-PROUND(Eox*Area/(Co*l .E-8) .0
1 Calc oxide thickness
TestS="CAP1"
2670 IF THEN ToxKChip)
Test*="CAP2"
2B80 IF THEN Tox2(Chip)
2B90 END IF
2700 ELSE
2710 Cox-Co*-Cap_leakage I Subtract leekage capacitance
2720 CoxCox1 .E-l2Cap_range/10 ! Convert to pF units
2730 Z-PR0UND(Eo>.*Area/!Cox*1 .E-8),0) ! Calculate oxide thickness
Test*-"CAP1"
2740 IF THEN To*HChip)-Z
Test$-"CAP2"
2750 IF THEN
2760 Tox2(Chip )-Z
2770 Delta_tox(Chip )-Tox1 (Chip )-Z ! Calculate etchback To*
2780 IF To>.1(ChipX0 OR Delta tox(Ch ip)<0 THEN Delta_tox(Chip ) 1
2790 END IF
2800 END IF
2810 !
2820 GOSUB Reset_equip ! Reset meters/matrix
"320"
2B30 OUTPUT Matrix; I Connect SMU1 to 200x200

"331"
2840 OUTPUT Matrix: I Connect SMU2 to 400*400

"316"
2850 OUTPUT Matrix; ! Connect SMU3 to E00*E00
"347"
28E0 OUTPUT Matrix; I Connect SMU4 to 800*800
Matnx;"302"
2870 OUTPUT I Connect USt to substrate
2880
2890 FOR 1-1 TO 4
I Force 100nA 9 100U comp
Hp4145;"DI" ;I;'
2900 OUTPUT 100E-9

,4
,
;-100*Type
2910 NEXT I
2920 OUTPUT Hp4145; "DS1 I Substrate-8V
2930 I
2940 FOR 1-1 TO 4
2950 CALL Meast "TV'&VALKI ),Z1 ,3) I Meas breakdown at SMU T
29E0 I
2970 Z-ABS!PR0UND'Z1/( 1 .E-2*To* 1 ! Chip 1 ) , !))! Convert to field breakdown
2980 IF Z<2 THEN Z 1 ! <2MV7cm
2990 IF Zl>99 THEN Z 2 ! out of meas capabilities
3008 IF Z>10 THEN Z--3 ! don't believe it
Test*-"CAP1"
3010 IF THEN
3020 IF THEN Fcap1_200(Chip)=Z
3030 IF THEN Fcapl 400(Chip )-Z
3040 IF THEN FcapC608(Chip)-Z
3050 IF THEN Fcap1_800(Chip)-Z
3060 ELSE
3070 IF THEN Fcap2 200(Chip)-Z
3080 IF THEN Fcap2_400(Chip )=Z
3090 IF THEN Fcap2_E00(Chip)-Z
3100 IF THEN Fcap2_800(Chip)-Z
3110 END IF
3120 NEXT I
3130 GOSUB Reset_equip
3140 RETURN
3150 !
3160 i
j-mmcji nil jnnnnn
3170 nnt jntuinnnnnt jnrunjMt n jmmi jt
3180
3190
3200 Cap_range: Toggles selected PAR M410 capacitance range
180
3210 fro" MftIN-"ENU subroutine
3220 TF
ir r,n ,..!= c THEN
Lap_range=.5 Turn 7
Z-1,
3230 IF Cap_range-1 THEN Z-5
3240 IF Cap_range=5 THEN Z-10
3270 IF Cap_range=50 THEN Z-1 00
3280 IF Cap_renge-100 THEN Z-200
3290 IF Cap_range200 THEN Z-500
3320 IF Cap_range2000 THEN Z-.5
3330 Cap_range=Z
3340 RETURN
33S8
33E0
3370 t3[3t3[3I3[3[]t3[3t ][3t 2131 3t3t3[ 31 31 3f3r3r][3t 3t3t]t]t]I 3t3t 31 313! 313
3388
3398
3408 Contl : l
3410 Test* "C0NT1"
3420 60T0 C ont
3430 Cont2: I
"C0NT2"
3440 Test*
3450 Cont : j Contact hole size test algorithm
34E0 GOSUB Display_status
"306"
3488 OUTPU Matrix ; Connect substrate to SMU3
349e OUTPUT Matrix ; "331 "
Connect pin 3 to SMU2
"340"
3500 OUTPUT Matrix; Connect pin 4 to SMU1
3510 l
3520 OUTPUT Hp4145;"DU1 ,1 I SMU1 Force 6V , 100mA comp.
3530 OUTPUT Hp4145; "DV2 ,1
;-E*Type;"
! SMU2 Force 6U , ..1

"
100mA comp
"
3540 OUTPUT Hp4145;"DV3.1 1 ,0,. ! SMu3 ground
3558 GOSUB Cont test ! Peform contact test
t$-"C0NT1"
35E0 IF Tes THEN Cont3S(Chip (-Contacts
t*-"C0NT2"
3570 IF Tes THEN Cont 10S( Chip )-Contact$
3580 I
"
3590 OUTPUT Matrix; "231 ! Disconnect SMU2 from pin 3
"
3600 OUTPUT Matn> ;"31 1 ! Connect SMU2 to pin I
3610 GOSUB Cont_test
t$-"C0NT1"
3620 IF Tes THEN ContSSt Chip )-ContactS
tS="C0NT2"
3630 IF Tes THEN Cont I2S! Chip (-Contact*
3640 I
"
3E50 OUTPUT Matrix;"2l 1 ! Disconnect SMU2 from pin 1
"
3660 OUTPUT Matrix; "321 I Connect SMU2 to pin 2
3670 GOSUB Cont test
t*-"C0NT1"
3680 IF Tes THEN Cont7S(Chip )=ContactS
tS-"C0NT2"
3698 IF Tes THEN Cont 15S( Chip (-Contact*
3700 I
3710 RETURN
3720
3730
3740 I 31 3t 3t 3t 3t 31 3t 3t 3t 3t ][ 3[ 31 3t 3t 31 3t 3t 3I3t 3t 3t 3t 31 31 3t 3t 313131 3t ]I It ]
3750
37E0
3770 Cont test: I Perform contact hole test
3780 WATT .05
Meas("TI3"
3790 CALL .Leakage,
3) ! Measure substrate leakage
3800 R-ABS(E/(Leakage+1 .E-15))
3810 IF R<2.0E+7 THEN ! Substarte short if R<20Mohms

Contact*-"S"
3820
3830 RETURN
3840 END IF
SMU1
;-Type;"
3850 OUTPUT Hp414S;"DV1 ,1 Force IV, 100mA comp.
3860 WAIT .05
"TI2"
3870 CALL Meast .Current ,3) Measure current

3888 R-ABS! 5/ < Current +1 .E-15>) Resistance between diff and metal
ContactS="0"
3890 IF R>2.0E+7 THEN Open contact if Ri20Mohms

Contact*="R"
3900 IF R<-2.0E+7 THEN Resistive contact otherwise

" "
3910 OUTPUT Hp4145! "DV1 .1

, ;-6*Type; ,. SMU1 Force 6V , 100mA comp.
3920 RETURN
3930
3940
3950 I3I3I It 3I3MI 3t 3t3t 3t 3t 3t 3I3I3I 3t 3t 3t 3t 3t3t 3t 3I3t3t3I3t 3t 3t 3[ 3t 3t 3t K 3
3960
3970
3980 Contres: ! Contact resistance/diode test algorithm
TestS-"C0NTRES"
3998
4000 GOSUB Display_statu5
181
4010 GOSUB Pretest 1
4020 IF Short to substrate pretest
Resistance-1 THEN
4830 ContrestChip > 1
4040 FdrtChip ) 1
4050 Vth(Chip) I
40E0 VbrtChip) 1
4070 RETURN
4080 END IF
4090 GOSUB Pretest2
4100 IF Resistancel-1 THEN Open contact pretest
4110 FdrlChip ) 2
4120 VbrtChip ) 2
4130 Vth(Chip) 2
4140 ContrestChip )2
4150 RETURN
41E0 END IF
4178 IF Resistance-1 THEN
4188 l ContrestChip >
2
4200 GOSUB Reset equip
4210 OUTPUT Matrlxi"310"
4220 SMUl to pin 1
OUTPUT Matrix; "321"
4230 SMU2 to pin 2
OUTPUT Matrix;"33S"
4240 SMU3 to pin 3
4250 SMU4 to pin 4

4260 VSl 1 o sub
4270 OUTPUT Hp4145;"DIl ";-Contres curr*Type;n 10"
4280
,0
SMUl I , 10U c omp
OUTPUT Hp4l45;"DI3 0
0,10"
4290 SMU3 l'i, 10U comp

OUTPUT Hp4145;"DI4 V 0,10"
SMU4 1-0, 10V comp

4300 OUTPUT Hp4145;"DU2 1 ";-Type;"
1
"
,.
SMU2 v-iu. ioe mA comp
4310 OUTPUT Hp4145;"DS1 VSl V-0
4320
4330 WAIT .05
4340 CALL Meast "TV2" .Voltagei ,5)
Meas("TU3"
4350 CALL ,Voltage2 5)
43E0 Delta_v-ABS(Voltage1-0oltage2 ) Volt age drop
4370 ContrestChip (-PROUNDt Del ta v/Contres curr -2) cont act resistance
4380 IF Delta_v<.001 THEN Contres! Chip > 3 fail if <lmV
4390 IF ContrestChip )>-1 THEN ContrestChip
.00E+5
>--
3 ! fai 1 ir Rc>10Ei
4400
4410 Contrest Chip >2
4420 END IF
4430
4440 Icurr-1 ! Current
.E-3
setting for FDR meas
"320"
44E0 OUTPUT Matrix; SMUl to pin 2
"330"
4470 OUTPUT Matrix; SMUl to pin 3
"301"
4488 OUTPUT Matrix; SMU2 to substrate
4490 I
4500 OUTPUT Hp4145;"DIl ; IcurrType;
"
SMUl Force
,0
1mA, 20V comp

4510 OUTPUT Hp4145;"DV2,l SMU2 force
IV. 100mA comp
4528 CALL Meast "TV1"VoltsQe1 ,3)
4530 OUTPUT Hp4145;"DII ; 2*Icurr*Type;

,0/
"
SMUl force 2mA, 20U comp

4540 CALL Meas("TV!",Voltase2,3)
4550 Oeltav-ABSt Voltage2-l'b;tage1 ) voltage difference
45E8 FdrtChip )-PROUND(Deltav/( 1000Icurr).-2) diode FDR in kohms
4578 IF Deltav<.001 THEN FdrtChip ) 3 fail if VdropdmV
4580 IF Fdr(Chip>>1 THEN Fdr(Chip) 3
,.00E+5 fail if FDR>100kohms
4590 I
4B00 Icurr-1 .00E-7
" "
4610 OUTPUT Hp4145;"DIl ,0, ; Icurr*Type; SMUl force l00nA,20U comp

"
4620 CALL Mees! "TV1 ),5)
,Vth!Chip
4630 Vth! Chip )-PR0UND< Vt ht Chip ) ) ,-2 Diode threshold

4640 IF ABS(Vth(Chip))>10 THEN Uth(Chip) 3 fail if vth>10V
4650 I
4EE0 Icurr 1 .00E-6
" '
4670 OUTPUT Hp4145;"DI1 ; Icurr*Type;
.0 . SMUl force luA, 100V comp
"TV1"
4680 CALL Meast VbrtChip), 3)
4690 Vbr ( Chip (-PROUNDt ABSt VbrtChip)) -2) Diode breakdown
4700 IF Ubr(Chip)>99.5 THEN Vbr(Chip) 3 meas limited
4710 RETURN
4720 I
4730 i
4740 it 31 3t ]t 3t 3t 3t 3t It 3t It 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t ]t 3t 3t 3t 3[ 31 3t 3t 3t 3t 3t It ]t ]
4750 I
4760 i
4770 Contre5_curr :~
I Set contact resistance measurement forcing current
4780 ! from main menu
4790 CONTROL 1,10;! I Turn on cursor
structure"
4800 ZS-"Enter forcing current (Amps) for CONTRES test
182
ZS&" (max-100mA,min-10nA)"
4810 DISP ;
4820 INPUT Contres_curr
4830 IF Contres_curr<1 .0E-8 OR Contres curr> 1 THEN Contres_curr
.
4840 CONTROL 1 ,10;0
4850 RETURN
4860
4870
4880 t 3t 3t 3t3t ]t It 3t 3t3t 3t ][ 3MI3I ]t 3t 3t 3t Hit ]t 3t 3t 3t 3t 31 3t 3t 3t 3t ]t 3t 3t3
4890
4908
4910 Date: ! Set date from Main_menu
4920 CONTROL 1,10|1 l Turn on cursor
4930 DISP "Enter Date (format- mm/dd/yy)";
4940 INPUT DateS
4950 IF LEN(Date$X>8 THEN Date
49B0 CONTROL 1 ,10;0
4970 RETURN
4980
4990
5000 t 3t 31 3t 3t ]t 31 3t 3t 3t 31 3t 31 3t 3t 3t 3131 It It ]t 3t ][ 3t 3t 31 3t 3t 3t 31 3t 3t 3t ][ ]
5010
5020
5030 Default values: i Start up default values
5040 PRINTER IS 1 Output is screen
5050 GCLEAR Reset graphics
5060 ClearS-CHRS! 255 l&CHRS! 75 ) Assign Clear* to clear screen
5070 SystemS=CHRS(255 l&CHRS! 125) System softkeys
50B0 MenuS-CHRS! 255 (iCHRS! 1 24 ) Assign Menu* to turn on/off softkeys
5090 UserS=CHRS!2S5)&CHRS( 123) Assign UserS to turn on user softkeys
5100 Userl*=CHRS!255)&CHR$( 12E ) Assign userlS to select softkey sets
5110 InverseS-CHRS! 129) Inverse video (screen)
5120 Of fS-CHRS( 128) Normal video (screen)
5130 OUTPUT 2;ClearS; Clear Screen
5140 Hp4I4S=717 HP4145 select code eddress
5150 Prober-707 Prober select code eddress
51E0 Matnx-709 Matri* select code address
5170 Plotter-705 PLotter select code address
5180 LOCAL Prober Release prober from computer control
5190 Xdim-762 X-steppmg distance
5200 Ydim-7G2 Y-stepping distance
5210 Cap_range-2O0 PAR M410 Capacitance range
5220 Eox-3.45E-13 Permittivity of oxide
5230
Uafer_type*="N"
Default wafer type
5248 Type=1 Type=1 for N-type, -1 for P-type
5250 GOSUB Die_pattern Generate die stepping pattern
5260 GOSUB Step_pat_table Lookup table for inter-die stepping
5270 GOSUB Pnnter_setups Printer variables
5280 GOSUB Parameters Assign numbers to parameters
5290 Process-1 Default process number
Menu_page$="MAIN"
Default menu page
5300
5310 Udpw1_current=. 1 Default forcing current VDPU1
5320 Udpw2_current=. 1 Default forcing current VDPW2
5338 Lw38_188 curr-. 1 Default forcing current LW30_100
Lwl5_!000"_curr=. 1 Default forcing current LUIS 1000
5340
5350 Contres curr-.l Default forcing current CONTRES
53E0
Param_type*-"NUM+STD"
Default data type for wafer mapping

5370 6raphics_output*-
"SCREEN"
Default output for wafer mapping
5380 RETURN
5390
540O
it3t3t3[3t3t3[3t]t]t]t]l]t]t]t]I3[3t]tlt]t3I]t3t3t3t3t]fU3t3I3t3t3t3
5410
5420
5430
5448 Die_pattern: I I Die stepping pattern
5450 1-0
54G0 MAT Diex- (20)
5470 MAT Diey- (20 >
54S0 FOR Y-20 TO 25
5490 FOR Z-20 TO 25
5500 1=1+ 1
Diexd )-Z ! X-die coordinates
5510
Dieyd >-Y ! Y-die coordinates
5520
5530 NEXT Z
5540 NEXT Y
5550 Number_of_die=I
55B0 RETURN
5570
5580 !t][][]t3t]t]I]I3t3MI3[3t3I3t3[]t3t3t][3[3t3l]t3I3t3[3I3t3t3t3[3t3t3I3
5590
5600
183
5S10
5620 Disk_error: ! I Error recovery from disk operations
5638 SELECT ERRN
5640 CASE 54
5650 "Duplicate filename
5660
915?
GOTO Disk
press <RETURN> to continue";
Jump
5E78 CASE 5B
5680 "Filename is
5B90
Bllf,
GOTO Disk
undefined press <RETURN> to continue";
jump
5700 CASE B4
5710 glSP "Mass storage media overflow press <RETURN> to continue";
5720 GOTO Disk Jump
5730 CASE 80
5740 DISP "Media changed or not in drive press <RETURN> to
continue"
5750 GOTO Disk jump

57B0 CASE 85
5770 DISP "Media not initialized press <RETURN; to continue";
5780 60T0 Disk jump ~
5790 END SELECT

5800 DISP "Disk error press <RETURN) to continue";
5810 Disk_jump: !
5820 INPUT ZS
Store_or_load*-"ST0RE"
5830 IF THEN Store_error
Store_or_loadS-="LOAD"
5840 IF THEN Load_error
load**"CAT"
5850 IF Store_or THEN Cat error
5880 RETURN
5870
5880
5890 t 3t 3t 3t 3t 3t 3[ 3t 3t 3t 31 3t 3t 31 3t 31 3t 3t 3t 31 3t 3t 3t 3t 3t 3t 3t It It It ]t ]t ]f 3l3t 3
5900
5910
5920 ' test/position
Display status:
"CHIP-"
Display current
"
during testing
5930 DISP TAB<5>;
"
sDiextfchip ); ": ;Diey( Chip >;
5940 DISP CHIPS LEFT-";Number_of_die-Chip;
" STRUCTURE*"
5950 DISP TEST ; Test*
5960 RETURN
5970 !
5980 i
5990 it 3t 31 3t 3t 31 3t 31 3t 3t 3t 3t 3t 3t 3C 3t 3t 31 3t 3t 3t3t 3t 31 3t 3t 3I3t 3t 3t 3t 3t 3t 31 3
6000 l
6810
B020 Fi les_menu: I Files sub-menu
6838 Menu_f lag-0
6040 LOOP
6050 OUTPUT 2;ClearS;
60E8 FOR 1-0 TO 23
6070 OFF KEY I
6088 NEXT I
6090 I
6100 PRINT Inverse*
61 10 PRINT TABXY(20,I >; Load/Store/Pr int date files "lOffS
" disk"
6128 PRINT TABXY<20,5>; f1 Store all data on floppy

6130 PRINT TABXY(20,E>; f2 Load previous data from floppy disk
disk"
6140 PRINT TABXY(20,7);"f3 Catalogue floppy

disk"
6150 PRINT TABXY(20,8);"f4 Initialize floppy

memory"
6168 PRINT TABXY(20,9);"f5 Print current data in

6178 PRINT
, ., TABXY(20,l0);"f6
_.. . ,._.. ._ Print current statistics in memory table"
6188 PRINT TABXY(20,1 1 ); "f7 -

Print error code reference
menu"
6198 PRINT TABXY(20.12);"f8 -
Exit files
6200 " data"
6210 ON KEY 1 LABEL Store .3 GOSUB Store_deta

"
6220 ON KEY 2 LABEL Load data". 3 GOSUB Load_data

disk"
6230 ON KEY 3 LABEL Cat

"
GOSUB Cat_disk
,3
6240 ON KEY 4 LABEL "Initial floppy", 3 GOSUB Init_floppy

data"
6250 ON KEY 5 LABEL Print GOSUB Printout

,3
stats", 3 GOSUB Pnnt_stats

"
62S0 ON KEY 6 LABEL Print

Codes"
6270 ON KEY 7 LABEL Print

"
GOSUB Print codes
,3
"
6280 ON KEY 8 LABEL Exit". GOTO Exit_files

6290 LOOP _,
6300 DISP TAB(25);"Select desired softkey

B310 EXIT IF Menu flag-1
6320 END LOOP
6330 Menu_f lag-0
B340 END LOOP
6350 l
E3E0 Exit_files: I
6370 Menu_f lag-1
6380 RETURN
6390 l
6400 i
184
6410
Jt3[3t313[3t]13[][3[]t]13t3[]t]l][3[313t3t][3[3[3[3[3t3t3t3t3t3t3t3[3
?td<Paâ,,,eter,-0 THEN RETURN

1*80 ! Parameter not in memory
EN RETURN ! Parameter not in "anorY

6500
Hi 2VJ,?tT 2'clear*;MenuS; Clear screen/turn off softkeys
|
fi^g
E530 SiflL
6CLEAR i
'
Initialize graphics
clear graphics buffer
crrS ?Ir ..
iLiri?St)lf,-output$*. . - . ,,..-
PLOTTER"
' Select degrees for angles
THEN PLOTTER IS Plotter
HIS
"HPGL"
,
E5E0 GRAPHICS ON i Turn on "
graphics
p
6570 Xmin-MIN(Diex(*)>
6580 Xma*-MAX!Diex( ) )
6590 Ymin=MIN(Diey< ) )
6B0O Ymax=MAX(Diey( ! )
6E10 WINDOW Xmin-1 +2
.Xma* ,Ymln-1 ,Ymax+2 I Graph scales
EB20 FOR 1-1 TO Number of die
6E30 MOUE Die*! I ),Diey(I )
6B40 RECTANGLE 1.1 ! Draw chip locations
BB50 NEXT I
6660 CSIZE 2 | Character sizes
6B70 FOR I-Xmin TO Xmax
6680 MOUE I+.4,Ymin-.25
6690 LABEL I I Label X chip coordinates
6700 NEXT I
6710 LDIR 90 ! labels are at 90 degrees
6720 FOR I-Ymin TO Ymax
6730 MOVE Xmin-.l .I+.4
B740 LABEL I ! Label Y chip coordinates

B750 NEXT I
E7E0 !
E770 PEN 2
6780 LDIR 0 I labels or at 0 degrees
6790 CSIZE 4
6800 MOVE Xmin.Ymax+1 .6
"&DateS&" "&Run$&"
E810 LABEL "Date : Run: Wafer : "SUaferS ! Label ID
6820 MOUE Xmin,Yma*+1 1 .
"Process-" " Parameter-"
EB3B LABEL iProcess ; iParameterSt Parameter )[ 1 ,93
6848 !
E858 CSIZE 3
E8E0 X-.1
6870 Y-.4
E88B IF Flag-1 THEN X-.4
6890 i
E9BB FOR 1=1 TO Number of_die I Place parameter values in chip locations
6910 !
B92B IF Flag=8 AND Stdt Parameter >>0 THEN
6930 Num_std-PROUND< (Valued )-Avg< Parameter ) )/Std( Parameter ) ) ,-2
6940 END IF
E95B !
69E8 MOVE Diexd )+X I )+Y .Dieyt
6970 IF Value(I)>-0 OR Flag=1 OR Valued )>-10 AND (Parameter-8 OR Parameter-9

) THEN
6980 IF Flag-0 THEN
Param_typeS="NUM" typeS-"NUM+STD"
B990 IF OR Parem THEN LABEL Ualue( I >

AND Stdt Parameter )>0 THEN LABEL Num_std
Param_typeS="STD"
7000 IF
type$="NUM+STD"
7810 IF Param AND Stdt Parameter )>0 THEN

7020 MOVE Diexd )+X.Diey( I )+ 1 .
7030 LABEL Num_std

7040 END IF
7050 ELSE
7060 LABEL ValueSt I )
7070 END IF
7080 END IF
7098 NEXT I
7100 l
7110 IF Flag=0 THEN
7120 MOVE Xmin+2,Ymin-1
"
7130 LABEL "Std- ;Std< Parameter )
7140 MOVE Xmin+2,Ymin-.5

"
7150 LABEL "Avg- ;Avg( Parameter )
71E0 ELSE
7170 MOVE Xmin+1 ,Ymin-1
7180 ZS="S Short to sub

-
(RC20Mohm) (
)"
7190 LABEL USING "K , 3D. D ;ZS 1 ), "X

.Errort .Parameter
185
7200 MOUE Xmin+1 ,Ymin-.75
Z512 Z*="0 Open

-
contact <R>20Mohm)
<"
:K;3D-^K"'ZI.E'"^(2.Parameter)."!d"
77$
ti.5VS fcn?j|LUSI5?
MOVE Xmin+ 1 .50
7240 ZS-"R -
Resistive short (R<20Mohm)

("
USIN6 "K-3D-D.K"'z$.E<-ror<3, Parameter). '%)
7260 END IF
7270 MOVE Xmin.Ymin
7280 PEN 0
7290 !
7300 IF Graphics outputS-"PRINTER"
THEN
7310 DUMP GRAPHICS
7320 PRINTER IS 701
7330 PRINT FfS
7340 PRINTER IS 1
7358 END IF
736B !
7370 IF Graphics_output*-"SCREEN" THEN INPUT Z*
7380 !
7390 GINIT
7400 GRAPHICS OFF
7410 OUTPUT 2;MenuS;
7420 RETURN
7430 !
7440 I
7450 lt]n[][][][]n[][][J[][][)[][][][][][]t][]I3[][][lt][][][][3I][][][]
74E0 !
7470 !
Gr2P,Si.c5-nenu: ! Sel=t wafer mapping or histogramming of any parameter
Zf5
7490 OUTPUT 2;ClearS; ! clear screen
7580 GOSUB Userl I softkeys
7510 Flag=0
7520 Flagl=0
7530 Parameter-0
7540 FOR 1-0 TO 23
7550 OFF KEY I
75E0 NEXT I
7570 !
7580 LOOP
InverseSS"
7590 PRINT TABXY(20,1 > ; PARAMETER WAFER MAPPING "iOffS
7600 FOR Ii-1 TO 15
7610 IF Ii<l0 THEN PRINT TABXYdS 1 ) ;UALS( 1 1
,Ii+
)
)&"
"UParameterS! Ii )I I ,
93
)&"
7620 IF Ii>9 THEN PRINT TABXY! 1 5 + 1 ) ; VALS! Ii
,11 ) "&ParameterS( I i )[ 1 ,93
7B30 NEXT Ii
7648 FOR I1-I6 TO 31
)5"
7650 PRINT TABXY(43,Ii-14);UALS(Ii ) "SParameterSt Ii )f 1 ,93
7660 NEXT II
-"
7670 PRINT TABXY! 15. 1 8 ); "Selected test

7680 IF Parameter-0 THEN PRINT TABXY! 31 1 8 ) ; InverseS8,"N0NE"&0f f $
,
"
7B90 IF ParameterOO THEN PRINT TABXY! 31 1 8 ) ; InverseS;Parameter ;0f f S;

.
7700 !
" PARAM"
7710 ON KEY 1 LABEL SELECT GOSUB Select param
,5
"
7720 ON KEY 3 LABEL PLOT "&Peram_type* 60SUB Param type
,5
7730 ON KEY 5 LABEL "OUTPUT -"&Graphlcs_outputS GOSUB Graphics output

,5
7740 ON KEY 6 LABEL "*HIST0<",5 GOSUB

""MAP""
Histogram
7750 ON KEY 7 LABEL 5 GOSUB Graph
"EXIT"
77G0 ON KEY 8 LABEL GOTO Exit_graphics
.5
7770 END LOOP

7780 !
7790 Ex-it graphics: !
7800 Menu flag-!
7810 RETURN
7820 I
7830 I
7840 !t 3t3t 3t ]t It It 3t3t][ 3t3Mt ]C 31 ]I ]t 31 31 3t 3t 3t 31 31 31 3t 3t 3t 3t 3t 3t3t3t3t 313
7850 !
7860 !
7870 Graphics output: ! Select output destination for wafer mapping
output$-"SC ZS-"PRINTER"
7880 IF Graphics THEN

ZS="PLOTTER"
7890 IF Graphics THEN

GraphicsIoutputS-"PLOTTER" ZS="SCREEN"
7900 IF THEN
7910 Graphics_output$=ZS
7920 RETURN
7930 !
7940 I
7950 innt junnnnnnnc unit jnnnnnnnt jnnt Jtjnnnnnt mM
7960 !
7970 i
7980 Histogram: I Histogram graphics tclasses -
10 (fixed)
186
7990 IF Parameter-0 THEN RETURN
8000 IF Flag-0 THEN
8010 IF Stdt Parameter (-0 THEN RETURN
8020 ELSE
8030 IF UalueSd)-"" THEN RETURN
8040 END IF
8050 OUTPUT 2;ClearSiMenuSi
8060 MAT Class- (0)
8070 GINIT
8080 GCLEAR
8090 DEG
THEN PL0TTER
InO IS Plotter
B120 FOR I-Number of die+1 TO 50

8130 IF Flag-0~THE"N Ualue! I )-Avg( Parameter )
8150 IF Flag-0 THEN

81 B0 IF Parameter<>8 AND Parameter<>9 THEN
8170 Xmln-1.E+10
8188 FOR 1-1 TO Number of die
81 SB IF Valued )>-0 THEN
S2:. IF Valued XXmin THEN Xmin-Value! I )
82 10 END IF
8220 NEXT I
8230 ELSE
8240 Xmin-1.E+10
8250 FOR 1-1 TO Number of_die
>>-10"
8260 IF Valued THEN

8270 IF ValuedXXmin THEN Xmin-Ualuet I )
8280 END IF
8290 NEXT I
8300 END IF
8310 Xme*-MAX( Value! ))
8320 Xstep=!Xmax-Xmin)/10
8330 Ymin-0
834B FOR 1=1 TO 10
8350 FOR J-1 TO Number_of_die
83G0 IF Valued )>-Xmin+( 1-1 XXstep AND Value< J XXmin+I*Xstep THEN
8370 Classd )-Classd )+1
838B END IF
8398 IF Value(J)-Xma* AND 1-10 THEN Class< 1 0 (-Class! 10 )+l
8400 NEXT J
8410 NEXT I
8420 Yma*-MAX(Class(* ) )
8430 Ystep=Ymax/IB
8440 ELSE
8450 Xmin-0
8460 Xmax-4
8470 Xstep-4/5
8480 Ymin=0
8490 FOR 1=1 TO Number of die
>-"5""
8500 IF UalueKI THEN Class( 1 )=Class( 1 )+l

)="0"
8510 IF ValueS./10
85G0 END IF
8570 IF Ymax-Ymin<-0 OR Xmax-Xmin<-0 THEN
8580 OUTPUT 2;ClearS;MenuS;
859B RETURN
8B0O END IF
8E10 i
8620 WINDOW Xmin-Xstep + Xstep
,Xma*
,Ymin-2*Ystep ,Ymax+3*Ystep
8E30 CLIP Xmin.Xmax + Ystep

.Ymax
.Yrnin
8E40 AXES Xstep.Ystep.Xmin.Ymin.l ,1 ,3
BE50 AXES Xstep.Ystep.Xmax , Ymax+Ystep ,

1 .1 ,3
8660 CLIP OFF

8670 !
8680 Classes-10
8690 IF Flag=1 THEN Classes=3
8700 FOR 1-1 TO Classes
8710 IF Flag=0 THEN MOUE Xmin+d-1 HXstep .0
8720 IF Flag=1 THEN MOVE Xmin+( I )*Xstep ,0
8730 RECTANGLE Xstep. Classd )

8740 NEXT I
8750 !
8760 I
8770 CSIZE 4
8780 MOVE Xmin-Xstep 25Ystep
.Yrnin-.
187
8790 LABEL Ymin
8800 MOVE Xmin-Xstep
,Ymax-.25Ystep
8810 LABEL PROUNDt Ymax -2 >
8830 MyES---SXsteP.Ymin+3.Ystep
|IgfEL0PROUND<Ystep'-2,'',/Dly"
II50
88E0 IF Flag-0 THEN
111%
8880 T2HI, Xmln-.S.Xstep
LABEL PROUND! Xmin )
.Ymln-Ystep
.-2
Iq
8900 M2yj Xmax-Xstep.Ymin-Ystep
LABEL PROUNDt Xmax ) .-2
8910 MOUE Xmln+4.Xstep, Ymln-Ystep

PRUND<Xstep,-2);"/DIV"
oaiS r,
8950
ÊLXm|n+'-3*^tep .Classd)
ÊLX?0n+-3*XstaP.Class(2)
8970
ÊLX^+3-3-^tep.Class<3
HIS
9080 END IF
9018 I
9828 !
9030 PEN 2
9040 CSIZE 4
9050 MOUE Xmin, Ymax+1 .BYstep
IS6,0. LABEL "Date:"&DateS&" Run: "&RunSS."
Wafer: "&WaferS
9070 MOUE Xmin, Ymax+1 .lYstep
lj-flBEL "Pi"oces5 ";Process;"
= Parameter-"
iParameterK Parameter )t I
9038
,93
9100 I
9110 CSIZE 3
9128 IF Flao=0 THEN
9130 MOVE Xmin+8.5Xstep Ymax + 1 .2*Ystep ,
"
9140 LABEL "Std- ;Std< Parameter )
9150 MOUE Xmln+8.5Xstep Ymax + 1 .8Ystep ,
"
91E0 LABEL "Avg- ;Avg( Parameter )
9170 ELSE
9180 MOUE Xmin+.5*Xstep ,Ymin-2*Ystep
9190 ZS="S Short to sub
-
(R<20Mohm) C
92e8 LABEL USING "K D .3D.
; ZS Error! 1
, ). "X
.Parameter
)"
9210 MOVE Xmin+.5Xstep ,Ymin-l

.35Ystep
9228 ZS="0 Open contact
-
<R>20Mohm)
("
9230 LABEL USING "K D .3D. ;ZS ,Error(2 )

.Parameter
"id"
9248 MOUE Xmin+.SXstep .EB'Ystep

9250 ZS="R Resistive short <K:28Mohm)
- ("
92E0 LABEL USING "K D .3D.

; ZS 3
.Errort ) "X
.Parameter
)"
9278 END IF
9288 MOUE Xmin, Ymin
9290 PEN 0
9300 l
Graphics_outputS="PRINTER"
9310 IF THEN
9320 DUMP GRAPHICS
9330 PRINTER IS 701
9340 PRINT Ff$
9350 PRINTER IS 1
9360 END IF
9370 !
outputS-"SCREEN"
9380 IF Graphics THEN INPUT Z*

9390 !
9400 GINIT
9410 6RAPHICS OFF
9428 OUTPUT 2;Menu*;
9430 RETURN
9440 !
9450 !
9460 !I3t 3t 31 3t 3t 3t 3t 3t 3t 31 3 1 3t 3t It 3t 31 3t 3t 31 ]t It ]t 31 3t 3t 3t 3t 3t 3t 3t 3t 3t 31 31 3
9470 I
9480 !
9498 Init floppy: I Initialize o new floppy disk
9508 OUTPUT 2; Clear* ;
9510 Menu flag=1
9528 PRINT Inverses
"
9530 PRINT TABXYt 10 );

,5
Initializing floppy will destroy all data
"
9540 PRINT TABXYt 10.6 ); previously stored on disk. Do you really

10,7);"
9550 PRINT TABXY! want to do this? Enter (YES/NO).

95E0 CONTROL 1 1
,10;
9570 INPUT Z*
9580 CONTROL 1 ,10,0
188
ZSO"YES"
9590 IF THEN RETURN
9S00 I
9610 OUTPUT 2;ClearS;
9E20 DISP "Initializing disk "
9E30 INITIALIZE ":

9640 RETURN
9650 I
9E60 !
9E70 !t 3l3I3t3t3t3t][3I3t3[3[]t3t][3t3[3t3t][3[]t][3t3[3[3t3l3t]t][]t]t3I3t3
9E80
9690 !
9700 Init hp4145: ! Initialize HP4145
9710 OUTPUT 2;Clear*;
"
9720 DISP "Calibrating Meters
Hp4145;"IT2"
9730 OUTPUT I Medium Integration
Hp4145;"CA1"
9740 OUTPUT Calibrate on
Hp4145;"BC"
9750 OUTPUT Clear buffer
Hp4145;"US"
9760 OUTPUT User mode
9770 GOSUB Reset_equip ! Turn off all channels
9780 DISP "Align wafer over 20:20 die location and press <RETURN>";
9790 INPUT Z*
9800 OUTPUT 2;ClearSi
)8,"
9810 PRINT TABXY(28,10);CHRS< 131 PROCESS ';Process;CHRS( 128)
9820 RETURN
9830 |
9840 i
9850 it ]t 3t 31 31 3t 3t 31 3I3t 3t 3t 3t 3t 3I3t 3t 3t 3t ][ ][ 3t 3t 3t 31 3t 31 It ]t ][]t 3t 3t 3t3
98E0 I
9870
9880 Load data: i load data from floppy from a previous test
or_load*="L0AD"
9898 Store
File*-""
99B0
9910 CONTROL 1 ,10;1
9920 DISP "Enter filename of data you wish to receive <RETURN> to exit";
9930 INPUT FlleS
9940 CONTROL 1 ,10;0
FlleS-""
9950 IF THEN RETURN
99B0 I
"
9970 DISP "Loading data from disk
9980 ON ERROR GOTO Disk_error
9990 GOSUB Zero_vanables
10000 I
leS&" "
10010 ASSIGN SPath I TO Fi : ,7001
10020 ENTER SPath T USING "7A ,2A ,8A (RunS .DateS
.Wafer* .Process
10E30 ENTER ePath 1 ;Tox 1 ( > , Fcapl 200! * ) )

,Fcap1_600(
,Fcapl_400( >
10040 ENTER SPath_1 ;Fcap1_800(* ) ,S"heet_rho1
(? )
,Sheet_rho2<
,Lwl ) 5_I000( )
10050 ENTER @Path_1 ;Lw30 100! ) Comb5S<* ) * )
,Comb10S(
,Comb15S(
,Serp5S(
* ) )
100E0 ENTER SPath 1 ; SerpTOS! ) ,Serp15S( )
10070 IF Process-? THEN
10088 ENTER SPath 1 ;To>.2( ) .Delta tox( > )
,Fcap2_400<
,Fcap2_200( >
* )
10090 ENTER ePathll ;Fcap2_E00! ) ,Fcap2_800<
10100 END IF
101 18
10120 ENTERS|path 1 ; Cont res! * ) ,Uth( ) * )
,Fdr< )
.Vbr! ,Cont3S( ) ContSS! * )
),Cont12S(* ),Cont15S< >
10130 ENTER ePethlt ;Cont7*( ),Cont10S(
10140
10150 ENTER 8Path 1 ;Test t ime ,Uafer_typeS Type
,Udpw1
,Cap_range
,
current
10IE0 ENTER PPathTl ; Vdpw2"_current ,Lw30_1 00_curr ,Contres_curr

,Lw15_1000_c
10170 ENTER @Path_1 ;Defect_density

10180 ASSIGN SPath_1 TO
10190 GOSUB Calc_stats
10200 !
10210 Load error: !
10220 OFF ERROR
10230 RETURN
10240 !
10250 ![3I3t3I]I3t3t]I3t]t3t3t]t3I3t3t3t3t3t3t3t3[]t]t]t3C3[]t3[3t3I3t3I3l3[3
10260
10270 i
10280
10290 Lw15_1000: I tabs
Length-1000
Distance between voltage
10300
Conductor linewidth
10310 Linewidth-15
1000"
10320 TestS-"LW15
10330 Current-Lw15"_1000_
10340 GOTO Linewidth
10350 Lw30_100: I
Length- 100
10360
10370 Linewidth-30
Test$-"LW30_100"
10380
189
10390 Current -Lw30_100_curr
10400 Linewidth: I
10410 Electrical linewidth test algorithm
GOSUB Display status
10420 IF Process-3 THEN Current
Current
10430
10440 IF Sheet_rho1
(Chip X0 THEN
10450 IF Sheet_rho2(Chip X0 THEN
10460 Teo+.I-"L.U|30 100"
10470 ?r ~
THEN Lw30 100<Chip> 10
"
EN L""S_1000(Chip)-10
10480 RETURN
10498 ELSE
10500
10510 Sht_rho-Sheet_rho2(Chip )
10520 ELSE
10530 IF Sheet_rho2(Chip ><0 THEN
10540 )
ELS|heet_rho-Sheet_rho1(Chip
10550
I05B0 S|jeet_rho-Sheet_rho2<Chip>
10570
10580 END IF
10590 !
10600 GOSUB Pretest I
10E20 IF TestS="LU3B_100" THEN Lw30 1 00!
10E30 |PTTe5tS="LW15_1000" Chip ) 20
THEN Lw15"_l000< Chip ) 20
10E40 RETURN
10E50 END IF
10E6B GOSUB Pretest2
1068B IF TestS-"LW3B_100" THEN Lw30 100! Chip) 30
10690 IF TestS-"LW15 1000'
THEN Lw15"_1000(Chip) 30
10700 RETURN
10710 END IF
10728
"310"
10740 OUTPUT Matrix; i "321
" j"33E";"347";"302"
10750
10760 Ttype-1
10770 IF Process=3 THEN Ttype 1
10780 OUTPUT Hp4145; "DI1 ,1
0,10"
10790 OUTPUT Hp4 1 4S;"DI2,0, "i Current Type;"
10800 IF TestS="LW30_100" THEN OUTPUT Hp4145;"DV3 1 "
;TypeTtype;
, 1
"
,.
"
Tes*.S="LW15_l000"
10810 IF THEN OUTPUT Hp4145;"DI3 1
100"
10820 IF Test$="LW30 THEN OUTPUT Hp4145;"DI4 1
TestS="LW15_1000"
10830 IF THEN OUTPUT Hp4145;"DV4 1 "
;TypeTtype; 1
"
.
'
, ,
10840 OUTPUT Hp4 1 45 ; "DS1
10850 WAIT .05
"TV1"
108EB CALL Meas! .Voltagei ,5)
TestS="LU30_100" "TU4"
10870 IF THEN CALL Meast tage2
,Uol ) ,5
1000" "TV3"
10880 IF TestS="LU15 THEN CALL Meas! ,Voltage2) .5
10898 CALL Meas! "TV2T',Ucomp ) ,3
10900
10910 Delta v=ABS< Vol tagel -Vol tage2 )
10920 R=ABS(Delta_v/Current )
10930 IF Delta v<.00! OR Vcomp>9.9 THEN
TestS="LW30_100"
10940 IF THEN Lw30 100(Chip)=- 40
TestS-"LU15_1000"
10950 IF THEN Lwl5 1000! Chip (40
109E0 RETURN
10970 END IF
10980 Wcalc-Sheet_rhoLength/R
10990 Lw=PR0UND(Wcalc-Linewidth,-2)
1 1000 IF Process=3 THEN
1 1010 IF ABS(Lw)>10 OR Lw<0 THEN Lw 50
1 1020 ELSE
1 1030 IF Lw<-Linewidth/3 OR Lw>0 THEN Lw 50
1 1040 END IF
1000"
1 1050 IF Test$="LW15 THEN Lw1 5_1000( Chip )-Lw
TestS-"LW30ll00"
1 1060 IF THEN Lw30_100( Chip )-Lw
1 1070 RETURN
1 1080 |
1 1090 i
1 1 100 !t 31 3t 3t 31 3t 3t 31 31 3t 31 3 1 3t 3t ]t 3t 3t3I 3t 3[ 31 3t 31 3t 3t 3t 3t 3t 3t 3[ 3t 3t 3t 31 3
11110 I
1 1120 j
11 130 Lw30 100_curr:l set default forcing current
1 1 140 CONTROL 1 1 ,10;
structure"
1 1150 ZS="Enter forcing current (Amps) for LW30_100 test

ZS&"
11 160 DISP (max=100mA,min-10nA)";
1 1170 INPUT Lw30 100 curr
100"
1 1 180 IF Lw30 curr<l.0E-8 OR Lw30 100 curr> 1 THEN Lu30_1 00_curr .
190
11190 CONTROL 1 ,10:0
11200 RETURN
1 1210
11220
1 1230 t 3t 31 )t 31 3 1 ][][][][ 3t 3t It It 3t3t 3t 3t 3t 31 3t 3t UK 31 It 3t 31 3t It ]t ]t 3t 3t 3
1 1240
1 1250
11260 Lw15 1000 curr: ! set default forcing current
1 1270 CONTROL 1 ,10; 1
structure"
1 1280 ZS-"Enter forcing current (Amps) for LW15_100C test

Z*&"
11290 DISP tmax-l00mA,min-10nA>";
1 1300 INPUT Lw15_1000_curr
11310 IF Lw15_l000_curr<1 OR Lwl5_1000 curr) 1 THEN Lw15_1000_curr
.0E-8 .
11320 CONTROL 1 ,10;0
1 1330 RETURN
1 1340
1 1350
1 13E0 t 3MI3I 3tU 3t3I3[]t]t 3t K U U K K ]I ]t 3t 3t3t3t U 3t3t]tK]t]t 3t 3t3tK JI)
11370
11380
11390 Main_menu: ! Main menu (program beginning)
1 1400 I
11410 CONTROL 1 ,10;0
1 1428 LOOP
1 1430 OUTPUT 2;ClearS;
11440 GOSUB Userl
1 1450 FOR 1-0 TO 23
1 1460 OFF KEY I
1 1470 NEXT I
1 1488 !
11490 Z*-InverseS
Electrical In-Process Control Test Chip Program
Z$=Z*&"
I 1580
11510 PRINT TABXYtE 1 );ZS
1 1528
ZS="
Rochester Institute of Technology
11530 ZI=ZSf,Off$
1 1540 PRINT TABXY(6,2 2);Z$
11550 I
Date"
11560 ON KEY 1 LABEL GOSUB Date

Run"
11570 ON KEY 2 LABEL GOSUB Run

Wafer"
1 1580 ON KEY 3 LABEL GOSUB Wafer

Process"
11590 ON KEY 4 LABEL GOSUB Process

TEST"
11600 ON KEY 5 LABEL START GOTO Exit

Menu"
ON KEY 6 LABEL Files GOSUB Files_menu

1 1610 Menu"
ON KEY 7 LABEL Graphics 60SUB Graphics_menu

1 1B20 Menu"
ON KEY 8 LABEL Default GOSUB User2

11630
i
1 1640
1 1650 i TrT"
ON KEY LABEL
'
Wafer GOSUB Type
1 1660
GOSUB Cap_range
lange"
11670 ON KEY LABEL Cap Current"
ON KEY LABEL
"
VDPW1 GOSUB Vdpw1_current
1 1680 Current"
ON KEY LABEL
"
VDPW2 GOSUB Vdpw2 current
11690 Current"
LABEL
"
LU30 GOSUB Lw30_T00 curr
1 1700 ON KEY Current"
LABEL
"
LWI5 GOSUB Lu15_1008_curr
1 1710 ON KEY Current"
ON KEY LABEL "CONTRES GOSUB Contres_curr

11720
GOSUB Userl
Menu"
"
11730 ON KEY LABEL Main

1 174B I
11750 LOOP
IF Menu THEN
1 1760
11770 FOR 7=5 TO 15
Z*="
11780
11790 ZS-ZS&ZS
11800 PRINT TABXYf 1 ,Z);ZS
1 1810 NEXT Z
1 1820 LOOP (Date*
PRINT TABXY! 15,5)|"f 1 Date
11830 "iRun*
PRINT TABXYt 15,6);"f2 Run
1 1840 ";UaferS
Wafer
1 1850 PRINT TABXY(15,7);"f3 "
iProcess
PRINT TABXYt 15,9);"f4 Process
11860
1 1870 DISP TAB(25);"Select desired
11880 EXIT "IF Menu_pageS="PARAMETERS
1 1890 EXIT IF Menu_flag=1
1 1900 END LOOP
1 1910 ELSE ,
.,.
11920 FOR Z-5 TO 15

Z$="
1 1930
Z$Z$&ZS
11940
1 1950 PRINT TABXY! 1 ,Z);ZS
11960 NEXT Z
1 1970 LOOP , ,
Z$="f1 Wafer -
type
1 1980
191
11990 PRINT TABXY(S.5>;ZS|Wafer type*
12000 i5r"t^,~
CaPaci tance meter range

12010 PRINT
TABXY(5.6);ZS;Cap range;"
(pF)|
12020 Z*-"f3 VDPWf forcing current
-
12030 (A)
PRINT TABXY!5.7),Z*;Vdpw1 current,'
12040 Z*-"f4 VDPWi forcing cuFrent

-
12050 (A)
PRINT TABXYt 5 >;ZS; Vdpw2 current ,8
12060 ;
LW30_100 forcing"current (A)
12070 PRINT TABXYt 5,9); ZS;Lw30 100 curr;'
12080 ZS="f6 LW15_I000 forcing cuVrent

-
12090 (A)
,
12100 PRINIJ"BXY(5.10);Z$iLw15 1000 cudr,'
CONTRES forcing current (A)

'
121 10 pRI NT_T ABXY(.S,11>;ZS; Contres_curr "
12120 ;
12130
12140 BXY(61.Z+6);"Vcomp=10V (fixed)'
NEXT Z
12158 !AB(25);"Select desired softkey"
12160 rvr?1^
EXIT IF Menu_pageS-"MAIN"
12178 END LOOP

12180 END IF
12190 EXIT IF Menu flag-1
12200 END LOOP
12210 Menu_f lag=0
12220 END LOOP
12230 I
12248 i
12250 Exit menu: !
122E0 IF Process-1 THEN Number of tests=8
12270 IF Process-2 THEN Number~of~test s=9
12280 IF Process=3 THEN Number~of tests=11 - ~
12290 OUTPUT 2;Clear$;

12300 RETURN
12310
12320
12330
12348
I3t3I3[3t3t3t3t3t3t3[3tt3I3t3t3I3I3I3t3t3t3t3I3t]t3t3[3t3f 3t U 3t 3t 3t 3t 3
12350
123E0 Move prober: I Step RKE81 prober
12370 IF Chip-1 AND Test-1 THEN
1238C OUTPUT Prober USING "f,K";"SH" ! Set home location
12390 END IF
12400 OUTPUT Prober USING ".K";'U'
! Raise probes off wafer
12410 IF Test-1 THEN
Prober_modeS="M"
12420 I MOVE mode
12430 Xinc Xdim< Die*
(Chip )-20) I X move from 20:2C location
12440 Yinc--Ydim*(Diey(Chip (-20 ) ! Y move from 20:20 location
12450 ELSE
" "
124E8 Prober_modeS= I
! INDEX mode
12478 Xinc = Index( Process, Test.1 ) ! X move from present spot
12480 Yinc= Index (Process
)
.Test .2 I Y move from present spot
12490 END IF
"
1258B OUTPUT Prober USING "f ;Prober_modeS
,K l Select move mode
12510 OUTPUT Prober USING " ;Xinc
,U ,Yinc
I Move prober
12520 IF Test-1 AND Chip-1 THEN RETURN ! Skip for CAP1/Chip=1
"f.K";"D"
12530 OUTPUT Prober USING ! Lower probes on wafer
12540 WAIT .5
12550 RETURN
125B0
12570
12580 t3t3I3t]t]t]l]t3[]t 3l3t3t3t3t 3t3t3t3tU3tK][]t3t3t ]t][]t]I3t3t 3t3t3
12590
12B08
12610 Param_type: ! Choose type of data to wafer map
Param_type*="NUM" ZS="NUM-fSTD"
12620 IF THEN
Param_typeS="NUM+STD" ZS="STD"
12630 IF THEN
Param_typeS="STD" ZS="NUM"
12648 IF THEN
12650 Param typeS=ZS
126E0 RETURR
12E70
12680
12690 t It 31 31 3 t 31 3t It 3t )t 3t 3t 3t U 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t3t 3t 3t 3t 31 3t 3t 3t 3
12700
12710
12720 Parameters: ! Parameter assignments/labels
(Ang)"
12730 Parameters! 1 )="T0X1 CAP! -
(MV/cm)"
12740 Parameter*; 2 )="FCAP1_200 CAP1

>"
12750 ParameterS(3)="FCAP1_400 CAP1 ( MV/cm

-
>"
12760 ParameterS(4)="FCAP1_600 CAP1 < MV/cm
(MV/cm)"
12770 Parameter*! 5 >-"FCAP I 800 CAP1

(Ohms/sq)"
12780 Perameter*(6)="SHEETRH01 VDPW1
192
12790 Farame terS! 7>- "SHEETRH02 UDPU2 (Ohms/sq)
12800 Parame terS! B>- "LW15_1000 LW15_1000 (uM)"
12810 Parame terS! 9(- "LW30 100 LW30 100 tuM>"
12820 Parame terS! 20) "COMB'S COMB"5/COMBI0 <S,0,R)"
12830 Parame terS! 21 ) ""COMB10 COMB5/COMB10 (S.O.R)"
12840 Parame terS! 22) "COMB 15 C0MBI5/SERP5 <S,0,R>"
12850 Parame terS! 23) ""SERP5 C0MB15/SERP5 (S.OjR)"
128E0 Parame terS! 24) "SERP10 SFRP10/SERP15 (S.O.R)"
-
12870 Parame terS! 25) "SERP15 SERP10/SERP15 (SiO'R)"

12880 Parame terS! 10) "T0X2 CAP2 (Ang)"
12890 Parame ter$( 11 ) "T0X1-T0X2 CAP 1 /CAP2 (Ang)"
12900 Parame terS( 12)> *"FCAP2_200 CAP2 (MV/cm)"
12910 Parame ter*( 13) "FCAP2 400 CAP2
(MV/cm)"
12920 Parame ter$( 14 ) '"FCAP2_60O CAP2 (MV/cm)"

12938 Parame terS( 15) "FCAP2 800 CAP2 (MV/cm)"
12940 Parame terSt IE) *"C0NTRE"S CONTRES (Ohms)"
12950 Parame terS( 17) "UTH CONTRES
<V>"
129E0 Parame ter$( 18) "FDR CONTRES (kOhms)"

12970 Parame terS! i a > "VBR CONTRES
(V)"
12980 Parame terS! 26) "C0NT3 CONTI (S.O.R)"

12990 Parame terS! 27)-
"C0NT5 CONTI (S.O.R)"
13000 Parame terS! 28)' "C0NT7 CONTI (S.O.R)"

13010 Parame terSf 29)' ="CONT10 C0NT2 (S.O.R)"
13020 Parame terS! 30) "C0NT12 C0NT2
(S.O.R)"
13030 Parame terS! 31 )- '"C0NT15 C0NT2

(S.O.R)"
13040 RETURN
13O50
130E0
13070 t][3t]t3I3[3t3t3t3IU3t3t3t]I3t]t]t]tK]I][3[3[3I3[3[3t3t3tU3t3I3[3
13080
13090
13100 Pretestl : I I Check for sub shorts
13110 Resistance-0
13120 Curr=1 .00E-7
! Force 100nA
13130 IF Process-3 THEN Curr Curr
13140 Rmin-2.0E+7 ! Resistance limit
13150 GOSUB Reset_equlp
"340"
13160 OUTPUT Matrix; "320 ; "330"; "310"; ! Connect PINS 1-4 to SMUl
13170 OUTPUT Mstn*;"301 I Connect substrate to SMU2
13180 OUTPUT Hp4145;"DIl 5 ;CurrType;
"
! SMU1=100nA, Vcomp=5V
13198 OUTPUT Hp4145; "DV2 1 ! SMU3=0V , Icomp-100mA
13288 WAIT .05
"
13210 CALL Meas! "TV! ,Z1 ,3)
1 Measure voltage on SMUl
13228 R=ABS(Z1/Curr)
13238 IF RRmin THEN Resistance=1 I Fail if R<Rmin
13248 RETURN
13258
132GB
13278 t 3t 3t 31 3t 3t 3131 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 31 3t 3I3t 3t 3t 3t 3t 3t 3t 3t 3t 3I3t 3t 3t 3
13288
1323B
13388 Pretest2: ! Check for opens on all pads
13310 Resistance=0
13320 Resistancel -0
13338 Resistance2=0
13348 Rma*=2.0E+7
13350 Curr=I .00E-7
13360 IF Process-3 THEN Curr--Curr

13370 GOSUB Reset_equip " "
13380 OUTPUT Hp4145;"DIl ;CurrType ;

.5
,
1 SMU1 I-100nA,Vcomp-EV
13390 IF Process-3 THEN OUTPUT Hp4 1 45; "DV2 1 , ;-Typ e;; ,.1"! SMU2 BACK BIAS IV
"
13408 IF Process<>3 THEN OUTPUT Hp4 I 45; "DV2 1 .;Typ e ;

13410 OUTPUT Hp4145;"DV3,1 !-SMU3 Com
Matrix;"310"
13420 OUTPUT ! SMU1 to pin 1

Matn*;"341"
13430 OUTPUT ! SMU2 to pin 4

Matnx;"306"
13440 OUTPUT 1 SMU3 to sub

13450 WAIT .05
"TV1"
13460 CALL Meast ,Z,3)
13470 Delta_v-1-ABS(Z)
13480 R-ABS(Delta v/Curr)
13490 IF R>Rmax OR ABS!Z)>5.9 THEN Resistancel-1 ! Open contact if R>20Mo
"000"
13500 OUTPUT Matrix;

"320"
13510 OUTPUT Matrix; ! SMU1 to pin 2

"331"
SMU2 to pin 3
"30E"
i SMU3 to sub
13540 CALL Meas! "TV1 ,Z,3)
13550 Delta v-l-ABS(Z

13560 R-ABS~Delta v/Curr)
13570 IF R)Rma* OR ABS(Z)>5.9 THEN Resistance2-1 ! Open contact if R>20Mohm
13580 IF Resistancel-1 OR Resistance2-1 THEN Resist ance=1
193
13590 RETURN
13600
13610
13620
13630 tK3t3t]t3t3t3[][3[]t3[]t3[][][3I]t3t][][3[3I3I3t3t3t3t3t3t][]t][]t3
13G40
13650 Pj^St.stats:! Print statistics
13660 DISP Printing statistics "

13B80 GOSUB Title
13E90 IF Process-1 THEN PRINT
ExpandedS5"PAGE 2 OF 2"&Normal*
0,Norr,als
13700 IF^ProcessOl THEN PRINT ExpandedS&"PASE 3 OF
13710 "UNormalS
13720 PRINT CompressedSiUnder on*
13730
13740 Z*="Parameter
XN Avg Std
X-3 X-4 X-5
13750 PRINT USING ;ZS&Under offS&Crlf*
13760 l
13770 FOR Perameter-1 TO 31
13780 Z*=Parameter*< Parameter )
13790 A-Avg( Parameter )
13800 B=Std(Parameter )
13810 C-N( Parameter )
13820 D- 100* PROUND!
13S30
C/Number_of_die. -3)
E-Error! 1 .Parameter)
13840 F-Error(2 .Parameter)
13850 G-Error! 3 .Parameter)
13860 H=Error< 4 .Parameter)
13870 I -Error (5 .Parameter)
13BS0 Flag3-0
13890 IF ParameterC-9 THEN Flag3=1
13900 IF Parameter>-20 AND Parameter -25 THEN Flag3-
13910 IF Process=2 AND Parameter)-! 0 AND Parameters 15 THEN Flag3-1
13920 IF Process-3 AND Parameter>-1E AND Parameter^ 19 THEN Flag3=1
13930 IF Process-3 AND Parameter>=2E THEN Fla 1 =
13940 IF Flag3=1 THEN PRINT USING I3970;ZS,A. .C.D.E.F.G.H.I
13950 NEXT Parameter

13960
13970 IMAGE 35A.5D.2D.4X 5D.2D.4X ,3D.D,4X,3
D.D.4X.3D D
13980
13990 PRINT
1403B Test time=PR0UND(Test_time,-2 )
14010 Time_per die-PROUND! Tes t_t lme /Number of
"
14020 PRINT "Test t ime ;Test_t ime ; "Sec
"Sec"
14030 PRINT "Test time per die ;Time_per_die;
14040 PRINT
14858 PRINT Wafer type - ";Wafer typeS
Capacitance Range - T;Cap_range ;
"pF"
140G0 PRINT
" "A"
14070 PRINT VDPW1 forcing current - ; Vdpwl_current ;
" "A"
14080 PRINT VDPW2 forcing current ; Vdpw2_current ;

14090 PRINT LW30_100 forcing current - ";Lw3B 100_curr;
" 'A"
14100 PRINT LW15_1000 forcing current - ;Lw15"_1008_curr ;
" "A"
14110 PRINT "CONTRES forcing current - ;Contres_curr;
14120 PRINT
-" "DEF/cm2"
14130 PRINT "Minimum oxide defect density ;Oefect_density ;

14140 PRINT Normals
14150 PRINT Ff$
14160 PRINTER IS I
14170 RETURN
14180
14190
14288 t 3t 3t3t 3t3t 3t 3t3t3t 3t3t 31 It 3t3t3t3t 3t 3t 3t 3t 3t 31 3t ]t 3t 3t 3t 31 ]t ][ 3t 3t 3t 31 3
14210
14220
14230 Print_codes: I Print error code reference chart
14240 DISP "Printing er codes. .

14260 PRINT ExpendedS&Under on$f>"Error code reference chart "&Under_of fS&NormalS
14270 PRINT Tight spscingS
14280 I
14290 FOR Paramett-=1 TO 31
" "
14300 MAT YS= ( )

14310 ZS=Parameter*( Parameter )
14320 I
14330 IF Parameter-1 OR Parameter' = 10 THEN contact'
14340 Y*( 1 )-"Code -I ) Meter out of range. leaky cap or no

14350 END IF
14360 I
194
14370 IF Parameter>-2 AND
14380
Parameter<-15 THEN
0R parameter> = 12 THEN
14390
"i 111 Plai breakdown is <2MV/cm"
14400 YS t-
Y$(2
YS(.)-) -"Cod*
Cod* -2
"Code .. i
-.
Exceeds measurement
txteeas (100V)'
14410 YS(3) "Code Bad data capability (10
capability
14420 Field breakdown) 10MV/cm
-
END IF
14430 END IF
14440 I
14450 IF Parameter-E OR Parameter-7
THEN
144E0 Y*( 1 ) "Code -1 Short to substrate (Rs'20Mohms >"
14470 Y*(2 ) "Code -2 Open

_
(R/20Mohms)"
14480 V contact
YS(3) "Code -3 > Exceeds meas
comp liance
met"
capability dmv), R) 100KOhms/sq or
14490 END IF
1450B I
14510 IF Parameter-8 OR Parameter-g
THEN
14520 !!^!lr2e known"
14530 "ig "I !"} rlstance

to
not
( R<20Mohms >"
14540 vs S l!-rS2!
I-rSn6 ~ "I 2PSn ""tact
substrate
<R>20Mohms>"
14550 vi 4
YS!4) "5S "I
Code -40 --> Exceeds meas capability dmv) or compliance met
14560 Y*(5)-"Code -50 --> Invalid
14570 END IF
measurement (Value not
possible)"
14580 I
1459B IF Perameter-1 1 THEN
14600 YSd )-"Code -1 > Tox from CAP1 or CAP2 bad"
14610 END IF
14E20 I
I4E30 IF Parameter>-1E AND Parameter<-1 9 THEN
14640
~\ ""? S.nort to substrate (R<20Mohms
>"
1465B
~l "I P-pen ""tact
'.r2e <R)20Mohms>"
14EE8 v5 5 R>I00kohms"
14E78 TF P.r.S??".
IF na5 capability (lmV) or
Parameter-7 THEN Y*(3)="Code -3 --> Threshold )
.'tVtuc^SS6^ 10V"
146B8 ^.,nI^Paâ^, THEN YS(3)="Code -3 --> Vbr > 100V"

14E98 END IF
14788
14718 IF Parameter>=20 THEN
14728 YS(l)=-Code S -
Short to substrate <R<20Mohms)"
14738 YS(2 )-"Code 0 Open contact <R)20Mohms)"
14748 YS(3)-"Code R Resistive contact (R<20Mohms)"
14758 END IF
147GB
14778 Z-Parameter
14788 PRINT Under_onS;ZS; Under off*
14798 Flao3=0
14808 IF ?)=2 AND Z<-4 THEN Flag3=1
14810 IF Z6 THEN Flag3-1
14828 IF Z=8 THEN Fleg3=1
14838 IF Z>-12 AND ZC-14 THEN Flag3=1
14848 IF Z>=20 AND Z<=30 THEN Fleg3=1
14850 IF Flag3=0 THEN
148E0 FOR 1=1 TO 5
><)""
14870 IF YS< I THEN
14880 PRINT TAB(5);Y$(I)
14898 END IF
14980 NEXT I
14910 PRINT
14920 END IF
14930 NEXT Parameter
14940 PRINT Normal spacing*
14950 PRINT Ff*
14960 PRINTER IS 1
14970 RETURN
14980
14990
15000 t 3t 3t 3t ][ 31 3 1 31 31 3 1 3t 3t 3t 3t 3[ 3[ 31] I 31 3 1 UU 3t 3t 3t 31 3t 3t U It K K 3t 3t 3
15010
15020 I
15030 Pnnter_setups : ! Define various primting features
Normal*=CHRS!27)t."&k0S"
15040 Print in normal mode
ExpandedS=CHRS!27)&"&k1S"
15058 Print In expanded mode
)&"&k2S"
15060 Compressed*=CHRS< 27 Print in compressed mode
)&"&dD"
15070 Under_onS=CHRS( 27 Turn on underline printing

)&"&d@"
15080 Under_of f S-CHRS! 27 Turn off underline printing
spacingS=CHR$(27)&"&18D"
15090 Tight )&"&1BD"

8 lines/inch
15100 NormaT spacingS-CHRS! 27 6 lines/inch
151 10 CrlfS=C"HRS< 13)&CHRS( 10) Carriage return, Line feed
SeolS="*,K"
15120 Suppress EOL sequence
15130 Ff$=CHR$(12) Form feed
195
15150
15160
PRINTER0lSfl1$iUnder-0ff$&Nor"al-Spaclno$il
Reset prlnte
15170 l
15180 i
ZS="
15190 < CAP1
1520B UDPWt
ZS-ZS&"UDPW2 LW30 100 LW15 1000
15210
-COMB
>
ZS=ZS&"< SERP
>"&C"rlfS
15220 Headerl*=ZS
15230 ZS-"CHIP Tox1 200 400 600 800 Rhosl
15240 "=2J&"Rhos2 Delta linewidth 5 10 15
15250 ZS=Z*&"10 15"iCrlf*
152G0 Header2S=Z*
15270 Z*="XX:YY (ANG) < (Mv/cm2)
15280 ZS=ZS&"(Ohms/square ) (uM) (uM)
15290 ZS=Z*8."(0pen, Short or Resistive) "&CrlfS
15300 Header3*=ZS
15310
ZS="
15320 CAP2 ->"&CrlfS
15330 Header4*-Z*
15340 ZS="CHIP Tox2 200 400 600 800 Tox1-Tox2 "&CrlfS
15350 Header5S=Z*
15360 ZS="XX:YY (ANG) (Mv/cm2) (ANG) "SCrlfS
15370 Header6*=ZS
15380
ZS="
15390 -CONTI
-
<
C0NT2 > CONTRES/DIODE (10uMx1
0uM)"f,CrlfS
15400 Header7S-ZS
15410 Z$="CHIP 3uM 5uM 7uM 10uM 12uM 1 5uM Re Fdr Uth
Vbr"lCrlfS
15420 Header8S-ZS
15430 Z$="XX:YY (Open, Short or Resistive) Ohms kOhms (V)
(U) "SCrlfS
15440 Header9$=ZS
15450 I
15460 I
15470 RETURN
15480 I
1549B i
15500 !!][][ 3t 3t 3t 3t 31 3t 31 3t3t 3t 31 ][][1M[][ UKKKKK 31 3f 3t3t 3t3t 3131313
15510
15520 I
15530 Printout: ! Data output printout
"
15540 DISP "Printing data
15550 PRINTER IS 701 I Output is printer
155EB GOSUB Title I Print title page
15570 IF Process-1 THEN PRINT ExpandedS&"PAGE 1 OF 2"
3"
15580 IF ProcessOl THEN PRINT ExpandedSS "PAGE 1 OF
15590 PRINT Normal*
15E00
15610 PRINT USING SeolS;CompressedS&Header1S I Print 1st header
15E20 PRINT USING SeolS;Header2$ I Print 2nd header
15630 PRINT USING SeolS;Under on*&Header3S8,Under_of f* ! Print 3rd header
15B40
15E50 FOR Chip=l TO Number of die
ZS=",9A,SD,2X,2D72D,2X,2D.2D,2X,2D.2D,2X,2D.2D,"
15660
15E70 ZS=ZS&"2X ,A ,2X .5D.2D ,2X .5D.2D ,2X ,A ,2X
15680 Z$=ZS&"3D.'2D,4X,3D.26 ,5X.A,2X,
15698 ZS=ZS&"AJ4X,A.4X,A,3X
AS=UALS(Diex<Chip>>&" "&VALS(Diey(Chip))f," "
! Printing format
15700 1
15710 A=Toxl(Chip)
15720 B-Fcapl_200!Chip)
15730 C=Fcapl_40B(Chip)
15740 D=Fcapl 600(Chip)
15750 E=FcapC80B(Chip )
1576B F=Sheet_rhol (Chip)
15770 G=Sheet_rho2(Chip )
15788 H-Lw30_10B(Chip )
15790 I-Lw15_1000!Chlp)
15800 J*=Comb5S< Chip )
15810 KS=Comb10S(Chip )
15820 LS=Comb15S(Chip >
15830 MS=Serp5*(Chip)
15840 NS=Serp10S(Chip)
15850 0S=Serp15S(Chip)
A.B.C.D.E,"!" " "
15860 PRINT USING Z$;AS .F.G,

,H.I I ! ,MS,NS,0S,
"I"
,Crlf*
15870 NEXT Chip

15880 PRINT NormalS&FfS I Formfeed paper
15890
196
15910 GOSUB Title
3"
15920 PRINT Expanded*". "PAGE 2 OF
15930 PRINT Normal*
15940
15950 PRINT USING SeolSiCompressedS&Header4S I Print first header
15960 feol$.Header5S
15970 EEtKt
PRINT HUMS
USING SeolS;Under_on$&HeaderES&Under_offS
I Print second header
! Print 3rd header
15990
15990 FOR Chip=1 TO Number_of die
16000 !;S=."!-9Aa5D'2x.:d-zdT2><.2D.2D,2X,2D.2D,2X,2D.2D,2X,A,2X,5D,2X,A,2A"
A*-VAL*(Diex(Chip))&":"&VAL*(Diey<ChipS)&"
16010 I
"
16020 A=To*2(Chip)
16038 B=Fcap2 200(Chip )
16040 C-Fcap2 400(Chip >
16058 D-Fcap2_600(Chip )
16068 E-Fcap2_800(Chip )
16878 F-Delta_tox(Chip )
Z*;AS,A,B,C,D,E."1"
16B8B PRINT USING .CrlfS
16890 NEXT Chip

16100 PRINT NormalS&Ff* ! Formfeed paper
161 10 END IF
16120
IE 130 IF Process-3 THEN
16140 GOSUB Title Print title
3"
16150 PRINT ExpandedS&"PAGE 2 OF Print page number
16160 PRINT Normal*
16178
16 188 PRINT USING SeolSiCompressed$&Header7S I Print 1st header
16198 PRINT USING Seol*;Header8S I Print 2nd header
16200 PRINT USING Seol*iUnder_on*&Header9S&Under_off* i Print 3rd header
16210 I
16220 FOR Chip-1 TO Number_of_die
16230 Z$-",9A,X.A,4X
ZS=ZS&"SD.2D,2X,3D.2D,2X,3D.2D,2X,A,2A"
16240
)&" >&" "
16250 AS-VAL*(Diex!Chip ) : "&VALS! Diey! Chip ) I
16260 B$=Cont3S(Chip )
16270 C*=Cont5S(Chip )
16288 DS=Cont7S!Chip )
16298 E*=Cont10S(Chip )
16300 FS=Cont12S(Chip )
16310 GS=Contl5$(Chip )
16320 H=Contres(Chip )
16330 I-Fdr(Chip)
1E340 J-Uth(Chip )
1E350 K-Vbr(Chip)
"
16360 PRINT USING ZSiAS.BS ! ,ES

,FS,GS,
.H.I
,J,K,
.CrlfS
16370 NEXT Chip

16380 PRINT NormalS&FfS ! Formfeed paper
16390 END IF
1E408
16410 PRINTER IS 1 Output is screen
1G420 RETURN
16430
1644B
16450 tU3f U]t]t][][3[3I3[3tK3t3t3t3l3[3t3r3t3[3t3I3t3[3I3l3t3t3t3t3[3I3
16460
16478
16480 Process: i Select Process number (from Main_menu)
16498 IF Process-1 THEN Z=2
16520 Process-Z
16530 RETURN
16540
16550
nnnntuuuuuuinnnnnnnnnnnnnnnnnt 31 3
16560 [ it u 3t 3t 3
16570
16580
16598 Reset equip: ! Reset HP4145 and matrix
16688 OUTPUT Hp4145;"DVl"000"

16620 RETURN
1G638 I
16E40
16650 ![][][][ 3IUUUU 3tU3t3t3t 3I3t3t3I3t 3t3t3tUU 31
3t3t3t3t3t 3t3t3t3t 3
16660 i
16670
I Reset test equipment
16680 Reset test : "t,K"i"H"
I Return prober to home position

16E90 OUTPUT Prober USING
Release computer control
16700 LOCAL Prober !
197
16720 OUTPUT 2;ClearS; ! Clear screen
16730 RETURN
16740 I
16750 l
16760 jnnnnnnnnnnMMnnnt innn i uuuuun] nnnnnnnt i
16770
16780 i
16790 Run: ! Select run number (from Main_menu)
16800 CONTROL 1 .10; 1
16810 DISP "Enter run number (max characters-7
)"
;
16820 INPUT Run*
16830 IF LEN(RunS)>7 THEN Run
16840 WHILE LEN(Run$X7
Run$-RunS&" "
16850
16860 END WHILE
16870 CONTROL 1 .1010
16880 RETURN
16890 !
16900 i
16910 it 3t 3t 3t3t 3t 3t3t 3 13t U 3t 3t 3t 3t 3t 3t U 3f] tit UU U U U3t3t 3t 3t 3tU ][][ 3
16920 I
16930 i
16940 Select param: ! Select parameter for wafer mapping or histogramming
16958 Flag=B
16960 CONTROL 1 1 ,101
16970 DISP "Enter desired parameter to map";

16980 INPUT ZS
16990 CONTROL 1,1010
17000 ON ERROR GOTO Select_param
17010 Parameter-VAL(ZS)
17020 IF ParameterOO OR Parameter)31 THEN Select_param
17030 IF Parameter>-20 THEN Flag-1
17040 GOSUB Transform
17050 OFF ERROR
17060 RETURN
17070 l
17080 i
17090 it 3t 3[]t 3t U 3t ][ 31 31 3t 3t U 3t 3t 3t 3t 3 1 3t 31 3t 3t 31 31 3t 3t 31 3t 31 31 31 31 3t3t 3

17100 I
171 10 i
17120 Comb5_comb10: !
Test*-"COMB5/COMB10"
17130
17140 GOTO Serp_comb
Comb15_serpS: '
17150 Test*-"C0MB15/SERP5"
17160
17170 GOTO Serp_comb
17180 SerpIO serp15: !
Test*-"SERP10/SERP15"
1-'
33
17200 Serp_comb: ! Serpentine/Comb test algorithm
172:0 GOSUB Display_status

17220 GOSUB Reset_equlp
17230 i
17240 Ttype=1
Ttype 1
17250 IF Process-3 THEN " "
17260 OUTPUT Hp4!45s"DVl t6TypeTtype; ,1

,
,. 1
"
17270 OUTPUT Hp4145; "DV2.1 ;6TypeTtype;
17280 OUTPUT Hp4145;"DV3,1

17290 I
Matrixi"330" ";"30S"
17300 OUTPUT ; "321

17310 GOSUB Serp comb_test
THEN CombSK Chip )-Serp_comb*
Test*="COMB5/COMB10"
1732B IF
THEN Combl5S( Chip )-Serp_combS
Test*-"C0MB15/SERP5"
17330 IF
THEN Serp 10S( Chip )-Serp_combS
Test*="SERP10/SERP15"
1734B IF
17350 I
"340" T30E"
"000"
17360 OUTPUT Matrix i I ;"31 1

17370 GOSUB Serp comb test
THEN Comb10*( Chip )-Serp_combS
Test*="C"OMB57COMB10"
17380 IF
THEN Serp5S( Chip )-Serp_combS
Test*-"C0MB15/SERP5"
17390 IF
THEN Serp15S( Chip >-Serp_combS
Test*-"SERP10/SERP15"
17400 IF
17410 I
17420 RETURN
17438 !
17440 lt3t3t3t3[3I3I3I3tUU]t3I3t3t3IU3t3t3I3tU3I3[3tU3t3I3t3t3t3t3
17450
17460
17470
test: Serp/Comb measurment
17480 Serp comb
17490 WAIT .05
"TI3"
17500 CALL Meast .Leakage ,5)
198
17510 .-- -.
jge+1 .E-151)
17520 IF R,2.0E+7 THEN

17530 Serp
comb*-"S"
17540 RETURN
17550 END IF
17560 OUTPUT Hp414Si"DV2. ,";TypeTtypei.1
"
100E-3"
,
17570 WAIT .05
17580 CALL Meast "TH" .Leakage, 5)

17590 R-ABS(5/(Leakage+l 5)
.E-T5
17680 IF R)2.0E+7 THEN Serp comb*-"0"
17610 IF R<=2.0E+7 THEN Serp comb*-"R"
17620 OUTPUT Hp4l45i"DV2,1 , "T6*Type*Ttype;

17630 RETURN
17648
17E58
17BE8 nnnnnntuuuuuuu uuinnnt snnntuu 3t 3t 3t uinnt 3t3
17E78
17E88 Format Index(a,b,c) -=) a - process number (1,2,3)
17698 b - test number
17708 c 1 or 2 --) x or y direction
17710
17720 Step_pat table: I Intra-die stepping coordinates
17730 FOR 1=1 TO 3
17740 Inde I 1 1-0
17750 Inde* 1:2 2)- 105
17760 Inde* 1,3 1 ) 35
17778 Index 1.3 2)-0
17780 Index 1,4 1 )-105
17790 Index 1.4 2)-0
17800 Index I 1 ) 35
,5
17810 Inde* 1,5 2)-0

17820 Index I 1 ) 375
.5
17830 Index 1.6 2)-68

17840 Inde* 1 )=0
17850 Inde* 2)=1 14
17860 Index 1 )=0
17870 Inde* 2J-95
17S80 NEXT I
17898 Inde* 2,9. 1 1-180
17900 Inde* 2,9, 2) 382
17910 Index 3,9. 1 )-27l
17920 Index 3,9, 2> 278
17930 Inde* 3,10 ) 35
,1
17940 Index 3,18 ,2)=0
17950 Inde* 3,11 )35

,1
17560 Index 3.11 ,2)=0
17970 RETURN
17980
17990
18000 t 3t 3t 3t 3t 3t 31 3t 3t 3t 3t 3t 31 3t 3t 31 3t 3t 3t ]IU 3t 3t 3t It It It U ]tlt 3I3I3I 313
18010
18820
16030 Store_data: ! Store data on floppy disk currently in memory
load*="ST0RE"
18040 Store_or
18050 CONTROL T,10;1
18060 DISP "Store data routine Enter (Y/N) to continue"!
18870 INPUT ZS
18080 CONTROL 1 ,1010
ZSO"Y"
18090 IF THEN RETURN
18100 IF LEN(Run*X)7 THEN GOSUB Run
181 10 IF LEN! Wafer* )<>2 THEN GOSUB Wafer
18120 DISP "Storing data on disk.
18130 ON ERROR 60T0 Disk_error
18140 l
File$=Run*&"
18150 "&WaferS
leS&" "
18160 CREATE BDAT Fi : 1

,700
leS&"
50
,
"
SPath 1 TO Fi , 1
18170 ASSIGN : ,700
18180 OUTPUT SPath~1 USING "7A ,2A iRunS .Date*

.Wafer* .Process
18190 OUTPUT SPath 1 ;Tox 1 < (.Fcapl 200< * ) ? ) ,Fcapt_600!

,Fcap1_400< >
18200 OUTPUT SPath ItFcapl 800! > rhol (
.Sheet ),Sheet_rho2< ) Lwl 5_1000< )
),Serp5S(* )
18210 OUTPUT SPathll ;Lu30 T00( ).Comb5sT* ),Comb10S(* )
18220 OUTPUT SPath 1 iSerpTOS! ) 5S(
.Serpl )
18230 IF Process=2~THEN
18240 OUTPUT @Path_1 ;Tox2(* ), Delta tox( * ) )
,Fcap2_400(
,Fcap2_200< )
* )
18250 OUTPUT 6Path_1 ;Fcap2_600< ) ,Fcap2_800(
18260 .END IF
18270
0UTPUT56Path 1 ;Contres( > ) * ) > ) ContSK )
18280 ,Vth< ,Fdr( ,Vbr( ,Cont3$(
),Contl2K* ).Contl5S( )
18290 OUTPUT SPathJj iCont7S(* ),Cont10*(*
18300 END IF
199
18310
18320 nnTPNT
Ia4t;-!!Tst^tl,,'e'Us1fer4):p?LTYPe,Cap_r6noe,Vdp^l_current
RHtdHt Pstt|_ tVdpw2 current ,Lw30_100_curr,Lwl5_100B
-
curr ..Contres _
curr
18330 OUTPUT SPath liDefect
_
~ density
16340 ASSIGN 6Path~1 TO *
18350 I
18360 Store error: I
18370 off Error
183B0 RETURN
18398
18400
184 IB tint uuuuuuuuinnnnnnruuuuuuuuuuuuinnnn
18420
18430
1B440 Test wafer: Test structure program flow
18450
18460 IF Test-1 THEN GOSUB Cap1
18470 IF Test-2 THEN GOSUB Vdpwl
~
18488 IF Test- THEN GOSUB Vdpw2

18490 IF Test=4 THEN GOSUB Lw3B_100
1850B IF Test-5 THEN GOSUB Lwl5 1008
18510 IF Test-6 THEN GOSUB Comb5"_comb 10
18520 IF Test=7 THEN GOSUB Comb15 serp5
1 8530 IF Test-8 THEN GOSUB Serpl 0_serp 15
18540
18550 IF Process=2 AND Test-9 THEN GOSUB Cap2
t856C
18580 IF Test-9 THEN GOSUB Cont 1
18598 IF Test-10 THEN GOSUB Cont2
18608 IF Test-1 1 THEN GOSUB Contres
18610 END IF
18B20 I
18630 RETURN
18E48
18658
18BE8 t 3t U ]t U U U 3t 3t 3t 3t 31 3t 3t 3t 3t 3t 3t 31 U 3t 3t 3t 3t 3t 3t 31 3t 3t 3t 3t 3t 3t 3t 3
18678
18580
18690 Title: Print title
18700 PRINT Expanded*;
"
18710 PRINT "DATE ; DateS
"
18720 PRINT "RUN i Run*

"
18730 PRINT "WAFER ;Waf erS

"
18740 PRINT "PROCESS iProcess
18750 PRINT Normal*;
18760 RETURN
18770
1878C
18798
18800
18810
18828 Transform: ! Th is subroutine maps parameter into Value() or ValueS()
I883C MAT Value- (0
ValueS= ( >
18840 MAT
18B5C IF Parameter- 1 THEN MAT Value= To*!
18860 IF Parameter- 2 THEN MAT Value- Fcapl 00 "
_
18870 IF Parameter 3 THEN MAT Value Fcap1_4B0

18880 IF Parameter 4 THEN MAT Value Fcapl
18890 IF Parameter-!5 THEN MAT Value Fcapl
18900 IF Parameter-!6 THEN MAT Ualue Sheet_rho1
16910 IF Parameter 7 THEN MAT Ualue Sheet_rho2
18920 IF Parameter 8 THEN MAT Ualue Lw15_1000
18930 IF Parameter 9 THEN MAT Value Lw3fl_100
Value'
18950 IF Paramet er-10 THEN MAT Tox2
IF Paramet er-1 1 THEN MAT Value Delta_to*
189G0
18970 IF Paramet er=12 THEN MAT Value Fcap2_200
18980 IF Paramet er-1 3 THEN MAT Value Fcap2_4BB
18990 IF Paramet er-1 4 THEN MAT Value Fcap2_600
IF Paramet er-15 THEN MAT Value Fcap2_800
19000
19010 END IF
Value= Contres
19030 IF Paramet er=16 THEN MAT
Value= Vth
19040 IF Paramet er=17 THEN MAT
Value- Fdr
19858 IF Paramet er-18 THEN MAT
Value- Vbr
190G0 IF Paramet er-1 9 THEN MAT
19070 END IF
IF Parameter 20 THEN MAT Values- CombSS
Values-
19080
ComblBI
19090 IF Parameter 2! THEN MAT
ValueS- Comb15S
19100 IF Parameter 22 THEN MAT
200
191 10 IF Parameter-;3 THEN MAT Value* SerpSS
19120 IF Parameter-24 THEN MAT ValueS Serp 10$
19130 IF Parameter-25 THEN MAT ValueS SerpISS
19150 IF Parameter-26 THEN MAT ValueS- Cont3S
19160 IF Perameter-27 THEN MAT ValueS- ContSS
19170 IF Parameter=28 THEN MAT ValueS- Cont7S
19180 IF Parameter-29 THEN MAT Value*- ContlOS
19190 IF Parameter-30 THEN MAT ValueS- Cont12$
19200 IF Paremeter-31 THEN MAT Value*- ContlSS
19210 END IF
19220 RETURN
19230 l
19248 I
19258 [t U3t U UUUU UUU U3t3t U]t3I3[U3t3[][3I3[][3t][3t3t 31 3I3[3Nt3
I92E0
1 9278 i
1928B Type: I Select wafer type (from main_menu)
19298 IF Wafer ty THEN
Wafer_type$-"P"
19300
19310 Type 1
1932B ELSE
Wafer_typeS="N"
1933B
19340 Type=1
19350 END IF
I93G0 RETURN
19378
193B0
1939B t 3t 3t ]t U ][][][ U][ ]I3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3[ 3t 3t 3t 3t 3t ][][ U]
19400
19410
19420 Userl: ! Select softkeys 1-8
19430 OUTPUT 2;SystemS;UserS;
Menu_pageS="MAIN"
19440
19450 RETURN
1946B
19470
1948B [ It 31 U ][ ][ U ][ ][][ 31 3t Jt 31 3t 3t 31 3t 3t 3t 3I3I3I 3t 3t 31 3t 3t U3t 31 31 3t U ]
19498
1 9500
19510 User2: ! Select softkeys 9-1E
19520 OUTPUT 2;SystemS;UserS;User1S;
"
19530 Menu_page$= "PARAMETERS
19540 RETURN
19550
19568
19578 int u uu u 3t u uu u 3t uu uu u u u u u u u u u u 3t uu ir u mm ]
19588 !
19598 i
19608 Vdpwl: !
"
19610 TestS="VDPU1
19E20 Current =Vdpwl_current
19E3B GOTO Vdpw
19E40 Vdpw2: i
Test*="VDPW2"
19E5B
19EEB Current=Vdpw2 current
19S70 Vdpw: i van der Pauw test algorithm
19E80 IF Process-3 THEN Current- -Current
19E90 GOSUB Display_status
19700 GOSUB Pretest I .
-,,.,- .,.,
.
19710 IF Resistance-1 THEN ' Fail if Sub resistances 1 9Mohms

THEN Sheet_rho1 ( Chip ) 1
Test*-"VDPW1"
19720 IF
THEN Sheet_rho2( Chip ) 1
TestS="VDPW2"
19730 IF
19740 RETURN
19750 END IF
19760 GOSUB Pretest2
THEN Sheet_rho1 ( Chip > 2
"
19780 IF TestS="VDPW1
THEN Sheet_rho2( Chip ) 2
TestS="VDPW2"
19790 IF
19B00 RETURN
19810 END IF
19820
19830 GOSUB Reset equip "347"
OUTPUT ! "321 "; "336";

Matrix;"3l0"
"302
19840
19850
! SMUl current
19860 OUTPUT Hp4145;"DI1 .10
,0,"lCurrent*Type;
" "
,10Ucomp
19870 IF Process-3 THEN OUfPUT Hp41 45; "DV2 1 , t-Type

" J0BE-3"
19880 IF Process03 THEN OUTPUT Hp41 45; "DV2 . 1 .

;Type
l SMU3 -
voltmeter
19890 OUTPUT Hp4145; "DI3.1
! SMU4 -
voltmeter
19900 OUTPUT Hp4145; "DI4.1
201
19910 OUTPUT Hp4145;"DS1 i US1-0V
b "
19920 WAIT .05
"TV3"
19930 CALL Measf 5)
.Voltagei
"TV4"
19940 CALL Meas! 5)
,Voltage2
"
19950 CALL Meas! "TV1 .Vcomp .3)
199E0
19970 Delta_v-ABS(Voltage2-Voltaoel )
19980 R-ABS(Delta v/Current )
19990 Z-PR0UND(4.5"*R
"
-2)
Tests-"
28888 IF VDPWf "'"THEN Sheet_rho1 ( Chip >-Z
TestS-"VDPW2"
20010 IF lestS-"VDPWZ"
THEN Sheet rho2(Chip)-Z

20020 IF Delta_v<.00l OR Z>1.00E+5 OR ABS!
Vcomp )>9. 9 THEN
20030 IF TestS-"VDPW1" THEN Sheet rhol(Chip)-
"
20040 IF TestS="VDPW2" THEN Sheet_rho2(

Chip )
20050
20BE0 RETURN
2007B
20080
20090 t3t 3t 3I3t3t 3t3t3t 3t3t 3t 3t 3t 3t 3t 31 ][ 3t 3t 31 3t 3t 3[3t3t3t3t3t ][3I][3t]t]
20100
201 10
20120 Vdpw! current: I Select default vdpw forcing current (from Main menu)
20130 CONTROL 1 1,10;
20140 ZS-"Enter forcing current (in Amps) for VDPW1 test structure"
ZS&"
20150 DISP (me*-l00mA,min=10nA)";
201EB INPUT Vdpw!_current
20170 IF Vdpwl current<! OR Vdpwl current). 1 THEN Vdpwl current
.0E-8
201B0 CONTROL T,10;0

20190 RETURN
20200
20210
20220 t 3t 3t U 3t 3t 3t 3t 3t U 3t 31 3t 3t 3t 3t3t 3t3t 3t 3t 3t U 3t3t 3t3t 3tU 3t 3t 3t 3t 3t 3
20230
20240
20250 Vdpw2 current:! Select defaqult forcing current (from Main_menu)
20260 CONTROL 1 1,10;
structure"
2B270 Z$-"Enter forcing current (Amps) for VDPW2 test

ZS&" >"
20280 DISP <ma*-!00mA ;

,min-10nA
20298 INPUT Vdpw2_current

283BB IF Vdpu2 current<1 OR Vdpw2_current> 1 THEN Vdpw2_current
.0E-8 .
20310 CONTROL T,10;0

20320 RETURN
20330
20340
20350 t 3t 3t 3tU U U 3t 3t U U 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t 3t ]t U 3t 3t 3t 3t 3t 31 ][][ U 3t 3
203G0
2037B
283B8 Wafer: I Select wafer number ID (from Main_menu)
28398 CONTROL 1 1
,10;
)"
2B4B0 DISP "Enter wafer number ( f ormat-nn ;

28410 INPUT Wafers
20420 IF LEN(Wafer$)<>2 THEN Wafer
20430 CONTROL 1 ,10;0
20440 RETURN
20450
20460
t3I3I3t3t3I3[3I3I3[3t3I3t3[3t3t3t3t3I3[3[3t3[3t3I3tU]t][]t3t3t3t3t3
20470
20480
20490
20500 Zero_varlables: I Intialize parameters
20510 MAT Fcap1_200= (0)
Fcap1_400- (0)
20520 MAT
20530 MAT Fcap1_600- (0)
- -"-
20540 MAT Fcap1_800" (0)

20550 MAT Fcap2_200= (0)
20560 MAT Fcap2 400" (0)
20570 MAT Fcap2 600- (0)
20580 MAT Fcap2_800- (0)
20590 MAT Delta_tox= (0)
20600 MAT Sheet_rhol- (0)
20610 MAT Sheet rho2- (0)
1000- (0)
20620 MAT Lw15
20S30 MAT Lw30~j00= (0)
20640 MAT To*1- (0)
20650 MAT Tox2- (0)
C"
20EE0 MAT Comb15S= )

""
20670 MAT ComblOS- < )

""
20E80 MAT Comb5S- < )

15*- <"">
20690 MAT Serp
(""
20700 MAT SerplOS- )
202
"
20710 MAT Serp5S- (
"
20720 MAT Cont3S- (
"
20730 MAT ContSS- (
20740 MAT Cont7- (
20750 MAT ContlOS- (
20760 MAT Cont12S- (
20770 MAT ContlSS- (
20780 MAT Contres- (0)
20790 MAT Fdr- (0)
20800 MAT Vbr- (0)
20810 MAT Vth- (0)
20820 MAT N- (0)
20830 MAT Avg- (0)
20840 MAT Std- (0)
2085B MAT Error- (0)
208EB RETURN
20870 I
20880 I
20890 END
209B0 I
20910 l
20920 SUB Meest Channel* ,Avg_value .Number ) measure channel and average
20930 Hp414E=717
20940 Value-0
20960 OUTPUT Hp4145;ChannelS
20970 ENTER Hp4145;Z
20980 Value-Value+Z
20990 NEXT I
21000 Avg value-Value/Number
21010 SUBEND
203

A Test Chip Approach To Routine Process Control

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A Test Chip Approach To Routine Process Control

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Rochester Institute of Technology

RIT Scholar Works

A Test chip approach to routine process control

Follow this and additional works at: http://scholarworks.rit.edu/theses

Approved by: Prof. Lynn F. Fuller

In the manufacturing (or Research and Development) of today's

integrated circuits, a large majority of the time seems to be given to

the technical advancement and performance of a device over a

competitors device. The on-going struggle is to produce the fastest

function never implemented before.

To be the first to demonstrate a technology is certainly

desirable for many reasons. One is that it becomes a very powerful

marketing tool because the general public perceives the company

with initial device announcement as being the best. Another reason

necessary to deliver at a cost effective rate? Unless you have a

captive market and are not subject to competition, or the number of

units to be delivered is low, this is a very serious question.

Unfortunately, the question is answered many times when delivery

trying to produce the device. Wouldn't it have been nice if detailed

process capabilities and limitations were known at the time of device

conception? To know what the processing lab was capable of doing

fabrication quality exists in the lab). The point which I present is

ability of a design at the early stages of device conception. To

determine the manufacturing ability of a fabrication facility requires

process control and yield data from whatever means possible. It is

the topic of which this thesis targets.

Before I jump into and address these issues, I would like to

define the following terms which will be referenced throughout this

circuit such as Furnace, Clean, Lithography, Metalization, Ion

same process throughout the time of fabrication.

for thickness and refractive index using ellipsometry. This

data is then assigned or associated to that run.

specifications at a given processing step.

process control techniques, (2) find out what could be done to

improve those techniques and (3) to determine a vehicle in which to

evaluate process capabilities without actually having to make a

device (which will become important as explained later). Surveys

were conducted of process engineers at a fabrication facility to

determine which critical parameters were necessary to monitor and

control that would indicate current process quality. From these

discussions, it was determined that interactions between processing

steps are equally important. Current techniques of process control

were analyzed along with their effectiveness in describing actual run

parameters as well as projecting process limitations and yields.

capable of generating data that isolated and quantified key

processing parameters and interactions. It was also determined that

careful thought as to the layout and selection of test structures would

be required to make evaluation and testing quick, yet conclusive to a

wide assortment of process materials and variations.

The following document describes, in detail, the steps and

fabrication of three different processes for evaluation, test system

and testing algorithms, an analyses of the data, and a conclusion of

in this area as well as some after thoughts on the ideas presented.

The main thrust of this document is towards MOS based

processing. Bipolar processing, however different, still uses the same

processing equipment and basic physical properties as does MOS and

thus, when talking process control, really applies to both

A procedure for determining process control and yield

prediction is presented which primarily serves to evaluate the

quality and repeatability of critical fabrication steps, but also serves

to quantify process capabilities and limitations for future design

considerations. This can be accomplished through the use of a

determining the process control and fabrication capability of the