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Analog IC Design

Lab Assignment 3

gm/Id Method for Analog Circuit Design

Aim: Design of MOS amplifiers using gm/Id method


Q1. Characterization of MOS-T
Plot the following curves for NMOS
(a) gm/ID vs Vov
(b) ID/(W/L) vs gm/ID
(c) ft vs gm/ID
(d) gm*ro vs VDS

Q2. Design of Common Source amplifier with resistive load


(Take VDD=3.0v and CL= 25ff)
(a) Design for maximum gain
L = 2Lmin, ID < 100uA
(b) Design for maximum Bandwidth
DC Gain = 2, ID < 100uA
(c) Optimum performance
DC Gain = 5, -3 dB freq= 1 GHZ, ID < 100uA
Make transistors as small as possible.
Do transient and ac simulation to get gain and -3dB frequency

Q3. Design of Differential amplifier with resistive load (single ended output)
(Take VDD=3.0v and CL= 25ff)
(a) Design for maximum gain
L = 2Lmin, IBias < 200uA
(b) Design for maximum Bandwidth
Gain = 2, IBias < 200uA
(b) Optimum performance
L = 2Lmin, DC Gain = 5, (W/L)max = 40
Maximize Bandwidth

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Theory: The methodology is intended for low-power analog and digital circuits where
the weak as well as moderate inversion regions are often used because they provide a
good compromise between speed and power consumption. The gm/ID ratio indeed is a
universal characteristic of all transistors formed by the same process.
MOS transistors are either in strong inversion or in weak inversion. Mainstream
methods assume generally strong inversion and use the transistor gate voltage overdrive
(VOV) as the key parameter, where VOV = VGS –VT.
If we consider a simple common source amplifier, the power and bandwidth are given by
following equations

With the assumed fixed design specifications, and a given technology (µ, Lmin), both
power and bandwidth of our circuit are completely determined by the choice of VOV
Making VOV small to save power also means that we lose bandwidth.
This makes intuitive sense since

With gm and L fixed, smaller VOV translates into a bigger (wider) device, and thus larger
Cgs. So we conclude from this that the VOV is not a good design parameter
What we really want from MOS transistor
– Large gm without investing much current
– Large gm without having large Cgs

To quantify how good of a job our transistor does, we can therefore define the following
"figures of merit"
Performance Metrics of Interest:
• Transit Frequency:

• Trans-conductor Efficiency:

• Intrinsic Gain:

We find that VOV is not "directly" related to performance metric. Hence, we switch
towards a strategy called "gm/ID design methodology", in which gm/ID, rather than VOV
is used directly as a central design variable.

Generation of Performance Curves:


1. fT Simulation:

Steps:
1) After the simulation of above circuit, we get all current and voltage plots in
waveform window.
2) Plot gate overdrive Vov = Vgs – Vt
3) Plot gm curve by taking derivative of ID Vs Vgs
4) Divide gm curve by ID curve to get gm/ID.
5) Divide gm curve by Cgs to get fT.
6) Plot (fT Vs gm/ID) transit frequency chart by taking FT as Y-axis and gm/ID as
X-axis

2. Intrinsic Gain Simulation:

Steps:
1. After the simulation of above circuit, we get all current and voltage plots in
waveform window.
2. Get 1/ro curve by taking derivative of ID Vs Vds.
3. To get ro plot, take the reciprocal of above curve. At very small value of Vds, gm
is constant. Take that value as gmo. gmo can also be find out by dividing Id by
(Vgs-Vt). Then plot gm = gmo*(1+Vds), where  = 1/(ro*ID)
4. Get gm*ro Vs Vds plot.

3. gm/ID Simulation:
Steps:
1. After the simulation of above circuit, we get all current and voltage plots in
waveform window.
2. Find out gate overdrive Vov = Vgs – Vt. Vt can be seen in log files after running
simulation after making the transistor in saturation.
3. Plot gm curve by taking derivative of ID Vs Vgs.
4. Divide gm curve by ID curve to get gm/ID.
5. Divide ID curve by W/L value to get ID/W/L plot.
6. Setting gm/ID as X-axis, plot ID/W/L which is called current density plot.

Using the above method, gm/Id plots are generated for various Ls. This helps in design
process.
1. Plots for FT
The following is the plot for FT Vs gm/Id for four different L’s

It had been stated earlier that the -3dB bandwidth is inversely proportional to L2. Similar
same effect can also be seen in case of FT.
2. Plots for Intrinsic Gain

The plot for intrinsic gain (gm*r0) has been given below.
Note how drastically the gain increases with increase in L.

gm*r0 Vs Vds
3. gm/Id Plots
A comparative plot for gm/Id Vs Vov is given below:

Since gm/Id Vs Vov plots are very important in the design procedure, Separate plots for
each L have been generated.
gm/Id Vs Vov ( L=0.36µm)
gm/Id Vs Vov ( L=0.72µm)
gm/Id Vs Vov ( L=1.44µm)
gm/Id Vs Vov ( L=3.6µm)
4. Id/ (W/L) Vs gm/Id Plots
These plots help in determining the required W/L for a given current. If we have
chosen the gm/Id values, we can choose the aspect ration of the MOST from these
plots.
First, a comparative plot is shown. Here L varies from 0.36µm to 3.6µm.

Separate Id/(W/L) Vs gm/Id plots have been generated for each L


(0.36µm,0.72µm,1.44µm,3.6µm)
Id/(W/L) Vs gm/Id plot for L = 0.36µm
Id/(W/L) Vs gm/Id plot for L = 0.72µm
Id/(W/L) Vs gm/Id plot for L = 1.44µm
Id/(W/L) Vs gm/Id plot for L = 3.6µm
Design of Common Source and Differential amplifiers using Gm/Id
method.

This part of the experiment was done using TSMC 0.25m technology files.
So the Gm/Id plots given previously were not used.
Library used is:
/edatools/dk/tsmc025/models/eldo/logic025.eldo

Gm/Id plots for this technology have been given below.


These plots will be used for designing the amplifiers in the subsequent stages.
W/L = 10/0.25

Plot 1:
FT Vs gm/Id
Plot 2:
Gm/Id Vs Vov :
Plot 3:
Id/(W/l) Vs Gm/Id
Plot 4:
Gm*r0 Vs Vds
Design of Common Source Amplifier

The circuit diagram is given below.

Design for Maximum Gain

When designing for maximum gain, we need to get the maximum gm possible, since the
gain of CS amplifier is simply -gm*RL. Apart from increasing gm, RL can also be
increased, but in case of a resistive load, the resistance will be set be the output common
mode voltage requirements.

From the gm/Id Vs Vov plot, we can see that to obtain higher transconductance
efficiency, we need to work at lower overdrive voltages. At the same time, the overdrive
voltage cannot be arbitrarily small otherwise the W/L of the transistor will be very large.

So we select a gm/Id value of 15 from this plot and read the corresponding Vov.

Next, we refer to the Id/(W/L) Vs gm/Id plot and read the Id/(W/L) value from it.
Id/(W/L) = 1.6 ( approximate value)

Setting Id= 100A,


we get W/L = 60
If L= 0.5m, W= 30m
To get a 1.0v as output common mode voltage,
RL = (3-1)/100A = 20K

The simulation results using these values are shown below:


Note that, according to the gm*r0 plot, the maximum gain achievable is around 50 v/v but
we are getting only about 20 v/v. This is because R L is much smaller compared to r0.
Ac Plot (L=0.5m):

Gain = 19.95 v/v -3dB frequency = 260MHz

Ac plot (L=0.25m):

Gain = 14.1 v/v -3dB frequency = 397MHz


Design for Maximum Bandwidth

For designing to obtain maximum bandwidth, the first thing we need to consider is the
effect of parasitic capacitances. As the W and L of the MOS increases, the parasitic
capacitances increase, thereby reducing the bandwidth. The W/L ratio will be set be the
minimum gain required. So we should use small L to obtain large bandwidth.

Set L= 0.25m.
Next, we turn out attention to the ft vs gm/Id plot. From the nature of the plot we can
deduce that we need to work at lower gm/Id values to obtain a high bandwidth.

From the condition that gain =2,


we have, gm*RL = 2
also Id= 100A
If we choose a very small gm/Id value (i.e. Small gm) we'll have to set R L to a higher
value, which will reduce the bandwidth.
So we select a slightly higher value of gm/Id
gm/Id=6
from Id/(W/L) vs gm/Id plot
Id/(W/L) = 8
W/L = 12.5
If L= 0.25m, W=3.125m.
RL = 2/(gm/Id * Id)
= 3.3K
Note that using this value of resistance will give a higher output DC common mode
voltage of 2.67v for a VDD of 3v. This means a reduced output voltage swing.

Simulation results:

Gain = 2 v/v -3dB frequency = 1.94GHz


Design for Optimal Performance

For optimal performance, we need a gain of 5 and -3dB frequency greater than 1GHz.

GmRL = 5
and
1/(2*π*RL CL) = 1GHz
using only CL as the load capacitances and neglecting the effect of parasitic capacitances
RL = 6.36K

hence gm = 5/RL = 0.786mS

For Id= 100A,


we get gm/Id = 7.86  8

from gm/Id vs Vov plot


Vov = 0.24v
Id/(W/L) = 5
W/L = 20
Let L = 0.25m then W=5m
Simulation results:

Gain = 4.75 v/v -3dB frequency = 1.057GHz


Design of Differential Amplifier

Circuit diagram:

The Design of differential amplifier is very similar to the design process for common
source amplifiers. The only additional steps are design of the current mirror which is
going to supply the bias current.

Before designing the amplifier for either maximum gain or maximum bandwidth or for
optimal performance, we shall design the current mirror for the circuit. This will be
common to all the simulations.

The first thing we have to decide upon is the overdrive voltage of the current mirror. This
overdrive should be small otherwise it will limit the ICMR and output voltage swing.
We keep a small overdrive of 0.2v for the current mirror.
Assuming Iref available is 50A
Ibias needed is 200A. Multiplication factor = 4.

From the gm/Id plots:


for Vov = 0.2v
gm/Id = 9
=> Id/(W/L) = 4
=> (W/L)4 = 50    for M4 ( Id= 50A)
We choose L=0.5m to reduce Vds effect.
=> W4=6.25m

=> (W/L)3 = 200    for M3 ( Id= 200A)


=> W3=25m

This completes the design of the current mirror. Now we can use this current mirror for
all the subsequent steps.

Design for Maximum Gain

We shall take up the same values for gm/Id as we had taken for CS amplifier designed for
maximum gain.
gm/Id = 15
Vov= 0.09v
RL = 20K
Id/(W/L) = 1.5 ( approximate)
W/L = 66.6
keeping L=0.5W=33.3
Next, we need to set the input common mode voltage

Vb is calculated as:
Vb = VGS1 + Vov3
= VT1 + Vov1 + Vov3
= 0.442 + 0.09 + 0.2 (Neglecting body bias effect)
= 0.732v

However, due to body bias effect, the VT1 will change substantially, so we need to do a
DCOP simulation, and a few iterations to arrive at the Vb which gives us a Vov1 of 0.09
v. We obtain the value as 1.06v
Simulation results:
Single ended gain = 10.
-3dB frequency = 213 MHz
Simulation results for maximum gain design:
Design for maximum bandwidth

The bias circuit is same as above.

Gm/Id = 6
gm = 6*Id = 600
Single ended gain = -gmRL/2
=> RL = 2*2/gm = 6.6K
Id/(W/L) = 8
=> (W/L)1,2 = 12.5
Keeping L = 0.25, W1,2= 3.125
Vov = 0.24v
Similar to the case above, we need to iterate for obtaining this value at M1.
The final chosen value of Vbias = 1.1v

Simulation results:

Ibias = 183
Single ended gain = 1.7
-3dB frequency = 762MHz
Design for Optimal Performance

The constraints are :


minimum single ended gain = 5 v/v
(W/L)max = 40
We can approach the design as follows:
=> Id/(W/L) = 2.5
=> gm/Id = 11.5 => Vov =0.17v
=> gm = 1.15mS
=> RL = 5*2/gm = 8.7K
L= 0.5W1,2= 20

Simulation results:

Single ended gain = 4.3 -3dB frequency = 500MHz

The gain obtained is a slightly smaller value. We can increase R L and obtain the required
gain (at the cost of bandwidth).

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