1

2
 3

DESIGN OF POWER MOSFETS USING SILVACO TCAD TOOLS

MOHD AFIZUL FAIS BIN OTHMAN

A report submitted in partial fulfilment of the

requirements for the award of the degree of
Bachelor of Engineering (Electrical – Microelectronics)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

JUNE 2012
4
 iii

ACKNOWLEDGEMENT

All praise to Allah S.W.T, for giving me opportunity to complete my final year
project report titled Design of Power MOSFETs using Silvaco TCAD Tools. Firstly, I
would like to express my sincere appreciation to my supervisor, Prof. Dr. Razali Bin
Ismail for encouragement and supervision.

Apart of that, I would like to thank my friends, course mate, senior and my family for
their support and help. Their word of motivation to keep me completing this thesis is always
an encouragement for me to move further.
 iv

ABSTRACT

The planar power metal–oxide–semiconductor field-effect transistor (MOSFET) is

considered to be ideal power switches due to their high input impedance and fast switching
speed. In this thesis, the structure of planar power MOSFET were designed and developed
using Synopsis Silvaco Technology Computer Aided Design (TCAD) tools using several N+
source implant dose with dose varies from 3x1014cm-2 to 3x1016cm-2, P-Body implant dose
varying from dose of 3x1014cm-2 to 1x1013cm-2,gate oxide thickness of 20 Å , 40 Å , 60 Å , 80
Å , 100 Å and finally the diffuse time of arsenic doping with time of 20,40,60,80,and 100
minutes. The performance of the planar power MOSFET was analyzed from the Ids vs Vgs
curves. The electrical characteristic such threshold voltage, subthreshold swing and current
ratio for the proposed device structures were investigated. As a result, planar power
MOSFET show that it has higher ion/ioff ratio compare to the conventional MOSFET, while
the threshold voltage can be adjusted to be between 2 to 5 volt for gate voltage of 10 to 15
with proper choose of the device parameters.
 v

ABSTRAK

MOSFET kuasa berbentuk satah telah dianggap sebagai mempunyai ciri-ciri

pensuisan kuasa ideal disebabkan input impedannya yang tinggi dan kelajuan pensuisannya
yang tinggi . Dalam tesis ini, struktur MOSFET kuasa berbentuk satah telah direka dan
dibangunkan menggunakan Sinopsis Silvaco Reka bentuk bantuan teknologi komputer
(TCAD) menggunakan dos implan untuk „N+ Source‟ dengan dos berbeza dari 3x1014cm-2 ke
3x1016cm-2, dos implan „P-Body‟ yang diubah-ubah dari nilai dos 3x1014cm-2 kepada
1x1013cm-2 , ketebalan „Gate Oxide‟ 20 Å, 40 Å, 60 Å, 80 Å, 100 Å dan akhirnya „diffuse
time‟ arsenik dengan masa 20,40,60,80, dan 100 minit. Prestasi MOSFET kuasa berbentuk
satah telah dianalisis dari menggunakan graph Ids vs Vgs. Ciri-ciri keelektrikan seperti voltan
„threshold‟ , „subthreshold swing‟ dan nisbah arus untuk struktur peranti yang dicadangkan
itu telah disiasat. Hasilnya, MOSFET kuasa berbentuk satah telah menunjukkan bahawa ia
mempunyai nisbah arus yang lebih tinggi nisbah berbanding dengan MOSFET konvensional,
manakala voltan „threshold‟ boleh diselaraskan antara 2 hingga 5 volt untuk voltan „gate‟ 10
hingga 15 dengan betul memilih parameter peranti yang betul .
 vi

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii
ACKNOWLEDGEMENT iii
ABSTRACT iv
ABSTRAK v
TABLE OF CONTENTS vi
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF ABBREVIATIONS xv
LIST OF SYMBOLS xvi
LIST OF APPENDICES xvii

1 INRODUCTION
1.1 Overview 1
1.2 Objectives 2
1.3 Scopes of Project 3
1.4 Problem Statement 3
1.5 Outline of Report 4

2 LITERATURE REVIEW
2.1 Introduction 5
2.2 The Planar Power MOSFETs Structure 6
2.3 On State Characteristics 8
2.3.1 First Quadrant Operations 8
2.3.2 Third Quadrant Operations 9
 vii

2.4 Threshold Voltage 10

2.5 The On-Resistance ( ) 11
2.5.1 Source Contact Resistance 12
2.5.2 Source Region Resistance 13
2.5.3 Channel Resistance 13
2.5.4 Accumulation Resistance 13
2.5.5 JFET Resistance 14
2.5.6 Drift Region Resistance 15
2.5.7 N+ Substrate Resistance 15
2.6 Capacitance 16
2.7 Breakdown voltage 18
2.8 Blocking Voltage 20
2.9 Transconductance 21
2.10 Dynamic Characteristics 21
2.11 Safe Operating Area 23
2.12 Avalanche Breakdown 24
2.13 Performance analysis 25
2.13.1 Ion / Ioff Current Ratio 25
2.13.2 The Subthreshold Current 25
2.13.3 DIBL and Punchtrough 27
2.14 The Fabrication Process of Power MOSFET 29

3 RESEARCH METHODOLODY
3.1 Overview 31
3.2 Silvaco TCAD Tools 32
3.3 Summary of Project‟s Methodology 33
3.4 Deckbuild 36
3.5 Device Structure Design 38
3.6 Process Development 38
3.6.1 Generating Meshes 38
3.6.2 Adding a Substrate Region and Epitaxy 40
Layer
 viii

3.6.3 Polysilicon Deposition and Polysilicon 42

Oxidation with Photoresist mask
3.6.4 Polysilicon and Oxide Etching 43
3.6.5 P-Body Implantation 45
3.6.6 Nitride Deposition 46
3.6.7 Nitride Etching 48
3.6.8 Photoresist Etching 50
3.6.9 N+ Source Implantation 52
3.6.10 Etching of all Nitride 53
3.6.11 Polysilicon Oxidation 53
3.6.12 Aluminium Deposition 54
3.6.13 Mirroring the Structure 55
3.6.14 Adding Contacts to electrode 56
3.7 Device Simulation 59
3.8 Summary 60

4 RESULTS AND DISCUSSIONS

4.1 Device Structure 61
4.2 Data Extraction 62
4.2.1 Threshold Voltage 62
4.2.2 Drain Induced Barrier Lowering 64
4.2.3 Subthreshol Swing 65
4.3 Variation of N+ Source Implant Dose 66
4.4 Variation of Gate Oxide Thickness 67
4.5 Variation of P-Body Implant Dose 67
4.6 Variation of Diffuse Time of Arsenic Doping 70
4.7 The Pattern of data 71
 ix

5 CONCLUSIONS AND RECOMMENDATIONS

5.1 Conclusion 73
5.2 Recommendations 74

REFERENCES 75

APENDICES
APPENDIX A 77
 x

LIST OF TABLE

TABLE NO. TITLE PAGE

1.0 Table of investigation parameters 35

1.1 Device doping specification 38

1.2 Result of Variation of N+ Source Implant Dose 66

1.3 Result of Variation of Gate Oxide Thickness 67

1.4 Result of Variation of P-Body Implant Dose 68

1.5 Result of Variation of Diffuse Time of Arsenic Doping 70

 xi

LIST OF FIGURES

FIGURE NO TITLE PAGE

1.1 Planar Structure of Power MOSFETs with junction 6

indicator

1.2 The other representation of cross section of Planar 7

Structure of Power MOSFETs.

1.3 I-V curves for 1st quadrant mode of operation 8

1.4 I-V curve for third quadrant operation 9

1.5 Internal Resistance of planar power MOSFETs 11

1.6 vs. gate bias and temperature 12

1.7 Illustration of MOSFETs parasitic capacitances 16

1.8 Capacitance vs Vds 17

1.9 Gate Capacitance vs Vgs 17

2.0 Power MOSFETs Soft Breakdown Characteristics 18

2.1 Current-Voltage Characteristics of Power MOSFETs 19

2.2 Power MOSFET (a) Transfer characteristics, 22

(b) Equivalent Circuit Showing Components

That Have Greatest Effect on Switching

2.3 Safe Operating Area of planar power MOSFET 24

2.4 Surface potential of Device γ for 0.1 V and 1.5 V drain 27

voltages (linear and saturated case)

 xii

2.5 Transfer curves of Device γ for 0.1 V and 1.5 V drain 28

voltage (linear and saturated case)

2.6. The process sequence used in the fabrication of devices. 30

Power MOSFET cross section after (a) gate definition

and p-base formation, (b) the formation of shallow surface

p+-diffused region, (c) the formation of n+-source regions,

and (d) at the completion of device processing

2.7 Flowchart of research methodology 34

2.8 The terminal and Deckbuild:Atlas main window 37

2.9 Athena Mesh Define Tools (a) X direction 39

(b) Y direction

3.0 The mesh generate for planar power MOSFET 40

3.1 Athena Mesh Initialize Tools 41

3.2 Athena Epitaxy Tools for Epitaxy process 41

3.3 Athena Deposit Tools for depositing the materials 42

into device

3.4 Device structure after polysilicon deposition and 43

polysilicon oxidation with photoresist mask

3.5 Deckbuild Athena Etch Tools used to etch the oxide 44

3.6 Device structure after polysilicon and oxide etching 44

3.7 Deckbuild:Athena implant tools for boron implantation 45

3.8 Device structure after P-Body Implantation 46

 xiii

3.9 Nitride Deposition using Deckbuild:Athena Deposit 47

Tools

4.0 Device structure after nitride deposition 47

4.1 Defining the coordinate for rectangle that will need 49

to be etch (a)first coordinate (b)second coordinate

(c) Third coordinate (d) fourth coordinate

4.2 Device structure after nitride etching 50

4.3 Etching all Photoresist out using Deckbuild:Athena 51

Etch Tools

4.4 Device structure after photoresist etching 51

4.5 The implantation of N+source using Deckbuild:Athena 57

Implant Tools

4.6 Device structure after n+ source implantation 52

4.7 Device structure after full nitride etching 53

4.8 Device structure after polysilicon oxidation 54

4.9 The deposition of aluminium using Deckbuild:Athena 54

Deposit Tools

5.0 Device structure after aluminium deposition 55

5.1 Mirroring the structure using Deckbuild:Athena Mirror 55

Tools

5.2 The electrode definition of the device using the 57

Deckbuild:Athena Electrode Tools (a) Gate definition

(b) Source definition (c) Drain definition

 xiv

5.3 Final device structure after mirroring 57

5.4 Final device structure after mirroring with net doping 58

display

5.5 ATLAS input and output 59

5.6 The cross section of planar power MOSFETs 62

using Silvaco TCAD Athena

5.7 Graph of IDs VS VGS 63

5.8 IDs VS VDS curve 64

5.9 Extraction of DIBL 65

6.0 Extraction of S 65

6.1 Cross Section of N+ Source Region for Implant Dose 66

6.2 Cross Section of Variation of P-Body Implant Dose 69

6.3 Graph of The Pattern of Data 71

 xv

LIST OF ABBREVIATIONS

DIBL - Drain-Induced Barrier Lowering

MOSFET - Metal Oxide Semiconductor Field Effect Transistor

TCAD - Technology Computer Aided Design

Si - Silicon

NMOS - n-channel MOSFET

PMOS - p-channel MOSFET

FET - Field Effect Transistor

 xvi

LIST OF SYMBOLS

VTH - Threshold Voltage

VGS - Gate to Source Voltage

VDS - Drain to Source Voltage

S - Subthresahold Swing

Ion - On Current

Ioff - Off Current

- Drain voltage difference

- Lateral shift of the transfer curves in the subthreshold regime

Vdon - On voltage

Rs - Source resistance

Rch - Channel resistance

Racc - Resistance from the accumulation region

Repi - Resistance from the top layer of silicon

Rsubs - Resistance from the silicon substrate on which the epi is grown

Rjfet - Resistance from the JFET

- On Resistance

CGS - Gate-to-source capacitance

CGD - Gate-to-drain capacitance

CDS - Drain-to-source capacitances

 xvii

LIST OF APPENDICES

APPENDIX TITLE PAGE

A Silvaco TCAD Athena and Atlas 77

Program Listings
 1

CHAPTER 1

INTRODUCTION

1.1 Overview

Nowadays, in the electronic world that demands devices to be closer to their ideal
characteristics, the Power MOSFETs does give a glimpse of that situation. Power MOSFETs
are famous for their superior switching speed, which with further research and designing can
make it become “ideal switch”. Power MOSFETs does perform the same function as the
NPN, bipolar junction transistor (BJT) which is for amplifying and switching applications,
and come with additional benefits which is it can handle specific power levels . The first
power MOSFETs structure commercially introduced by the power semiconductor industry
was the double diffused which famously known as D-MOSFET structure. There is also other
type of Power MOSFETs structure such as U-MOSFET, SC-MOSFET, CC-MOSFET, GD-
MOSFET and SJ-MOSFET. There are all had their advantages and disadvantages.
 2

Most Power MOSFETs feature a vertical structure with Source and Drain on opposite
sides of the wafer in order to support higher current and voltage. By controlling the diffusion
depth of the P-base and N+ source region, the channel length of this device could be reduced
by sub-micron dimensions. This discovery does give an option to the industry to reduce their
cost since they could avoid the expensive lithography tools. The power MOSFETs also one
of the best when it comes to the high voltage applications. It can supported hundreds ampere
of drain current, compare to conventional MOSFETs which normally support miliampere of
drain current.

1.2 Objectives

The main objectives of this project to design and simulate Power MOSFETs with
vertical planar Silvaco TCAD Tools. The other objective also being described as guideline
for this project which is stated as below :

• To study, analyse, and investigate the electrical characteristics (I-V curve) of Planar
Power MOSFETs
• To investigate the characteristic of SCEs such as VT, Drain induced Barrier Lowering,
DIBL and Subthreshold Swing,S
• To have a good understanding of TCAD tools capabilities and the advantages of these
tools in the virtual fabrication process and the simulations process of a device.
 3

1.3 Scope of Project

The scope of this project presents the overview on the performance of Power
MOSFETS by using computer Silvaco TCAD Tools. The aim of the project was to
analyse and investigate the device electrical characteristic such as Ion, Ion/Ioff current ratio,
voltage threshold (Vth) and Subthreshold Swing.

The study of the device is on

• Design the structure of Planar Power MOSFET.
• Effect of varying doping dose for source and body implantation.
• Effect of varying the diffuse time for diffusion method.
• Effect of varying gate oxide thickness.

1.4 Problem Statement

A new structure of transistor based on conventional MOSFETs is required so it

can fulfil the need of high voltage devices since the usual candidates, bipolar junction
transistor did not perform well in the high voltage application. Many researchers in the
industry have started looking for a new type of device and mechanism to get some
improvement on device electrical characteristic. Power MOSFETs is one of a new type of
which gives better device electrical characteristic for high voltage applications especially
when it comes to the switching speed.
 4

1.5 Outline of Report

This thesis consists of five parts. The first chapter consist of the introduction to the
power MOSFET. This part also includes the objectives of the project, the scope of project
and the problem statements.

Second chapter is mostly discussing about the literature review. This section contains
the theories related to the project which is mostly about the characteristics of the power
MOSFET. The characteristics of the power MOSFET are discussed mostly because it is
important to understand it to further study the device.

Third chapter is on the method used on device design and simulation. This chapter
shows the chronology and the process flows from the beginning and the methodology used
for the project. The device design step will be shown in this chapter.

The fourth chapter will be focus on the results obtained from the software simulation.
The results were analysed and discussed in chapter 4. The electrical characteristics extracted
were compared and analysed. The fifth chapter is the conclusion of the project and some
recommendation for the future works
 5

CHAPTER 2

LITERATURE REVIEW

This chapter will briefly discuss about the founding research from other researcher
and theories related to the project. In this chapter we will discuss on the device characteristics
that‟s make it function as it should.

2.1 Introduction

To introduce and design the structure of a transistor, the i-v characteristic of the
device must be well known. This is a must as the designer need to control the output of the
device. Then, the study on the structure is also important as we must know how to improve
the device in certain way as it will be valid to be implement in other application.
 6

2.2 The Planar Power MOSFETs Structure

Figure 1.0 Planar Structure of Power MOSFETs with junction indicator [2]

The cross section of planar Power MOSFETs is shown in the figure 1.0 . From the
figure, the main difference compare to the lateral MOSFETs is the location of the source and
drain .In the lateral MOSFETs the source and drain appear side by side in horizontal but in
the power MOSFETs the source and drain area appear in vertical as to withstand the higher
voltage applied. The other reason for this is to makes possible lower on state resistances and
faster switching than the lateral MOSFETs. The existence of the epitaxial layer is mainly to
support the high voltage applied[1] .In most of Power MOSFETs structure, the N+ source
and P-body junction are shorted through source metallization to avoid accidental turn-on of
the parasitic bipolar transistor.
 7

This device structure is fabricated by starting with an N- type epitaxial layer grown
on a heavily doped N+ substrate. The channel is formed by the difference in lateral extension
of the P-base and N+ source regions produced by their diffusion cycles. Both regions are self-
aligned to the left-hand- side and right-hand- side of the gate region during ion-implantation
to introduce the respective dopants. Polysilicon, which will act as refractory gate electrode, is
required to allow diffusion of the dopants under the gate electrode at elevated temperatures.

The current path is created by inverting the p-layer underneath the gate by the
identical method in the lateral MOSFETs. Source current flows underneath this gate area and
then vertically through the drain, spreading out as it flows down[3] . A typical MOSFETs
consists of many thousands of N+ sources conducting in parallel as shown in Figure 1.1

Figure 1.1 The other representation of cross section of Planar Structure of Power MOSFETs.[1]

Figure 1.2 Another representation of cross section of Planar Structure of Power MOSFETs.[4]
 8

2.3 On State Characteristics

Basically, the planar power MOSFETs operates under two different mode of
operation which can be denoted as first quadrant and the third quadrant[3].

2.3.1 First Quadrant Operations

When the device is said to be operate in first quadrant operation, it means that the
device is supporting positive voltage to the drain. To understand this situation even more,
Figure 1.3 is referred.

Figure 1.3 I-V curves for 1st quadrant mode of operation [3]

From figure above, when the gate voltage (Vgs) is increase above the Threshold
voltage (Vth) ,the inversion layer will start to form and the device will start to conduct
current and the device will be turn on. The amount of current the channel conduct is depends
on the on-resistance ( ) of the MOSFETs, and can be defined in equation below

(1.0)
 9

For sufficiently large gate overdrive (Vg >> Vth), the curve appears linear
because the MOSFETs channel is fully turned on. Under low gate overdrive, the drain
current reaches saturation point when Vd > (Vg-Vth) due to a pinch-off effect of the
channel.

2.3.2 Third Quadrant Operations

Figure 1.4 I-V curve for third quadrant operation [3]

In the third quadrant operation, current flows in the reverse direction, oppositely
to the first quadrant operation. The value of is the same as the first quadrant. This
operation is common in the DC-DC buck converters, where the current conduction is under
at Vds.

Under relatively low current, the I-V curve appears to be symmetric to the first
quadrant operation. . Differences appear only under sufficient large current and therefore
sufficient large Vdon. When Vdon approaches the forward drop voltage of the body diode, the
body diode starts to conduct. As a result, the current increases and no current saturation
behaviour is observed.
 10

2.4 Threshold Voltage

Threshold voltage, Vth, is defined as the minimum gate electrode bias required to
strongly invert the surface of P-body under the polysilicon and form a conducting channel
between the source and the drain regions. Vth is usually measured at a drain-source current
of 250 µA[4]. Common values are 2-4V for high voltage devices with thicker gate oxides,
and 1-2V for lower voltage, logic-compatible devices with thinner gate oxides. With power
MOSFET finding increasing use in portable electronics and wireless communications where
battery power is at a premium, the trend is toward lower values of and Vth.

However, the low value of Vth is undesirable too based on the following reasons

1. Vth decreases with increased temperature.

2. The high gate impedance of a MOSFETs makes it susceptible to spurious turn-on due to
gate noise.
3. One of the more common modes of failure is gate-oxide voltage punch-through. Low Vth
requires thinner oxides, which lowers the gate oxide voltage rating.
 11

2.5 The On-Resistance ( )

The performance of power MOSFETs is restricted by the internal resistance. It is

useful to ascertain the minimum value for the internal resistance for a power MOSFET
structure that is capable of supporting a desired blocking voltage .

For a Planar power MOSFET, consists of the following components[3]:

- Rcs: source contact resistance
- RsN+: source resistance
- RCD : Drain contact resistance
- Rch: channel resistance
- RA: resistance from the accumulation region
- RD: resistance from the top layer of silicon (epitaxial silicon, also known as epi);
epi controls the amount of blocking voltage the MOSFETs can sustain
- Rsubs: resistance from the silicon substrate on which the epi is grown
- Rjfet: resistance from the JFET

Where = RCS + RN++ RCH + RA + RJFET + RD + RSUB + RCD (1.1)

Figure 1.5 Internal Resistance of planar power MOSFETs [1]

 12

Figure 1.6 vs. gate bias and temperature [3]

2.5.1 Source Contact Resistance

The contact to the N+ source region is made over a relatively small area in the power
MOSFET structure because the size of the window in the polysilicon must be minimized to
obtain the lowest possible specific on-resistance[1].

For computation of the contact resistance between the N+ source region and its
electrode, it is necessary to determine the contact area for the source region. The contact area
for the N+ source region is determined by the difference in width of the contact window (W C)
and the N+ source ion implant window (WS). The contact resistance to each of the N+ source
regions within the power MOSFET cell structure can be obtained by dividing the specific
contact resistance (ρC), which is determined by the work function of the contact metal and the
doping concentration at the surface of the N+ region.

(1.2)
 13

2.5.2 Source Region Resistance

Upon entering the N+ source region from the contact, the current must flow along the
source region until it reaches the channel. The resistance contributed by the source region is

determined by the sheet resistance of the N+ diffusion (ρSQN+) and its length (LN+):

(1.3)

2.5.3 Channel Resistance

The value of the channel resistance that contributed to the on-resistance of power
MOSFETs structure is given by

(1.4)

The increase of gate bias will reduce the value of channel resistance in case of the
same gate oxide thickness and inversion layer mobility.

2.5.4 Accumulation Resistance

In the power MOSFET structure, the current flowing through the inversion channel
enters the drift region at the edge of the P-base junction. The current then spreads from the
edge of the P-base junction into the JFET region. The current spreading phenomenon is aided
by the formation of an accumulation layer in the semiconductor below the gate oxide due to
 14

the positive gate bias applied to turn-on the device. The specific on-resistance contributed by
the accumulation layer in the power MOSFET structure is given by

(1.5)

KA has been introduced as for the current spreading from the accumulation layer into
the JFET region. A typical value for this coefficient is 0.6 based upon the current flow
observed from numerical simulations of power MOSFET structures. The threshold voltage in
the expression is for the on-set of formation of the accumulation layer. A zero threshold
voltage will be assumed in the process of performing the analytical computations. With the
increase of the gate bias, the specific resistance by the accumulation layer is reduced.

2.5.5 JFET Resistance

The electrons entering from the channel into the drift region are distributed into the
JFET region via the accumulation layer formed under the gate electrode. The spreading of
current in this region was accounted for by using a constant KA of 0.6 for the accumulation
layer resistance. Consequently, the current flow through the JFET region can be treated with
a uniform current density. In the power MOSFET structure, the cross-sectional area for the
JFET region increases with distance below the semiconductor surface due to the planar shape
of the P-base junction.

In practical devices, the P-base region is diffused into the N-drift region producing
a graded doping profile. However, these expressions based upon assuming a uniform doping
concentration for the P-base region are adequate for analytical computations. It is common
practice to enhance the doping concentration for the JFET region above that for the drift
region. It is therefore appropriate to use the enhanced doping concentration (NDJ) of the JFET
region.
 15

2.5.6 Drift Region Resistance

The resistance contributed by the drift region in the power MOSFET structure
is enhanced well above that for the ideal drift due to current spreading from the JFET region.
The cross-sectional area for the current flow in the drift region increases from the width a of
the JFET.

To increase the blocking voltage capability of the power MOSFET structure, it is

necessary to reduce the doping concentration and increase the thickness of the N-drift region
to support the voltage. The resistance of the drift region is now determined by two portions; a
first portion with a cross-sectional area that increases with the depth and a second portion
with a uniform cross-sectional area for the current flow.

2.5.7 N+ Substrate Resistance

When the current reaches the bottom of the N-drift region, it is very quickly
distributed throughout the heavily doped N+ substrate. The current flow through the substrate
can therefore be assumed to occur with a uniform cross-sectional area. Under this assumption,
the specific resistance contributed by the N+ substrate is given by :

RSUB,SP = ρSUBtSUB, (1.6)

where ρSUB and tSUB are the resistivity and thickness of the N+ substrate,respectively.
 16

2.6 Capacitance

The most important characteristics of power MOSFET which is switching behaviour

is mostly affected by the device parasitic capacitance. Although power MOSFET is unipolar
current transport, which mean the absence of minority carrier injection allows the interruption
of the current flow immediately after reduction of the gate bias below the threshold voltage,
in practice ,the switching speed still limited by the device capacitances. Analysis of this
capacitance requires taking into account the formation of a depletion layer in the
semiconductor under certain bias conditions. The rate at which the power MOSFET structure
can be switched between the on and off states is determined by the rate at which the input
capacitance can be charged or d is charged. In addition, the capacitance between the drain
and the gate electrodes has been found to play an important role in determining the drain
current and voltage transitions during the switching event.

The capacitance is located between the device three terminals that is, gate-to-source
(CGS), gate-to-drain (CGD) and drain-to-source (CDS) capacitances[1]. This parasitic
capacitances is is shown in figure below, figure 1.7.

Figure 1.7 Illustration of MOSFETs parasitic capacitances [3]

 17

During turn on, capacitors Cgd and Cgs are charged through the gate, so the gate
control circuit design must consider the variation in this capacitance. The power MOSFETs
capacitances are non-linear as well as a function of the dc bias voltage. Figure 1.8 shows how
capacitances vary with increased Vds voltage. All the MOSFETs capacitances come from a
series combination of a bias independent oxide capacitance and a bias dependent depletion
(Silicon) capacitance. The decrease in capacitances with V DS comes from the decrease in
depletion capacitance as the voltage increases and the depletion region widens.

Meanwhile, figure 1.9 shows that the planar power MOSFETs gate capacitance also
increases when the VGS voltage increases past the threshold voltage (for low VDS values)
because of the formation of an inversion layer of electrons in the MOS channel and an
accumulation layer of electrons under the trench bottom..

Figure 1.8 Capacitance vs Vds [3] Figure 1.9 Gate Capacitance vs Vgs [3]
 18

2.7 Breakdown voltage

Breakdown voltage, BVdss, is the voltage at which the reverse-biased body-drift diode
breaks down and significant current starts to flow between the source and drain by the
avalanche multiplication process, while the gate and source are shorted together. Current-
voltage characteristics of a power MOSFET are shown in Figure 2.1. BVdss is normally
measured at 250µA drain current. For drain voltages below BVdss and with no bias on the
gate, no channel is formed under the gate at the surface and the drain voltage is entirely
supported by the reverse-biased body-drift p-n junction. Two related phenomena can occur in
poorly designed and processed devices: punch-through and reach-through. Punch-through is
observed when the depletion region on the source side of the body-drift p-n junction reaches
the source region at drain voltages below the rated avalanche voltage of the device. This
provides a current path between source and drain and causes a soft breakdown characteristics
as shown in Figure 2.0. The leakage current flowing between source and drain is denoted by
IDSS. There are tradeoffs to be made between R DS(on) that requires shorter channel lengths
and punch-through avoidance that requires longer channel lengths. The reach-through
phenomenon occurs when the depletion region on the drift side of the body-drift p-n junction
reaches the epitaxy layer-substrate interface before avalanching takes place in the epitaxy
layer. Once the depletion edge enters the high carrier concentration substrate, a further
increase in drain voltage will cause the electric field to quickly reach the critical value of
2x10^5 V/cm where avalanching begins.

Figure 2.0 Power MOSFETs Soft Breakdown Characteristics [5]

 19

Figure 2.1 Current-Voltage Characteristics of Power MOSFETs [5]

 20

2.8 Blocking Voltage

The power MOSFET structure must be designed to support a high voltage in the first
quadrant when the drain bias voltage is positive[3]. During operation in the blocking mode,
the gate electrode is shorted to the source electrode by the external gate bias circuit. The
application of a positive drain bias voltage produces a reverse bias across junction J1 between
the P-base region and the N-drift region. Most of the applied voltage is supported across the
N-drift region. The doping concentration of donors in the N-epitaxial drift region and its
thickness must be chosen to attain the desired breakdown voltage. In devices designed to
support low voltages (less than 50 V), the doping concentration of the P-base region is
comparable to the doping concentration of the N-drift region leading to a graded doping
profile. Consequently, a significant fraction of the applied drain voltage is supported across a
depletion region formed in the P-base region. The highest doping concentration in the P-base
region is limited by the need to keep the threshold voltage around 2 V to achieve a low on-
resistance at a gate bias of 4.5 V as discussed in the previous section. For the allowable
maximum P-base doping concentration, it is desirable to make the depth of the P-base region
as small as possible to reduce the channel length in the power MOSFET structure. However,
if the junction depth of the P-base region is made too small, the depletion region in the P-base
region will reach through to the N+ source region leading to a reduced breakdown voltage. In
the power MOSFET structure, the gate region is not screened from the drain bias due to
cylindrical shape of the planar junctions. This results in significant depletion of the P-base
region making the channel length of this structure larger than that of the advanced power
MOSFET structures discussed in this monograph.
 21

2.9 Transconductance

Transconductance, gfs, is a measure of the sensitivity of drain current to changes in

gate-source bias. This parameter is normally quoted for a Vgs that gives a drain current equal
to about one half of the maximum current rating value and for a VDS that ensures operation in
the constant current region. Transconductance is influenced by gate width, which increases in
proportion to the active area as cell density increases. Cell density has increased over the
years from around half a million per square inch in 1980 to around eight million for planar
MOSFET and around 12 million for the trench technology. The limiting factor for even
higher cell densities is the photolithography process control and resolution that allows
contacts to be made to the source metallization in the center of the cells. Channel length also
affects transconductance. Reduced channel length is beneficial to both gfs and on-resistance,
with punch-through as a tradeoff. The lower limit of this length is set by the ability to control
the double-diffusion process and is around 1-2mm today. Finally the lower the gate oxide
thickness the higher gfs.

2.10 Dynamic Characteristics

When the MOSFET is used as a switch, its basic function is to control the drain
current by the gate voltage. Figure 2.2 (a) shows the transfer characteristics and Figure 2.2(b)
is an equivalent circuit model often used for the analysis of MOSFET switching performance.

The switching performance of a device is determined by the time required to establish

voltage changesacross capacitances. RG is the distributed resistance of the gate and is
approximately inversely proportional to active area. LS and LD are source and drain lead
inductances and are around a few tens of nH. Typical values of input (Ciss), output (Coss)
and reverse transfer (Crss) capacitances given in the data sheets are used by circuit designers
as a starting point in determining circuit component values. The capacitances are defined in
terms of the equivalent circuit capacitances as:
 22

Ciss = CGS + CGD, CDS shorted (1.7)

Crss = CGD (1.8)

Coss = CDS + CGD (1.9)

Gate-to-drain capacitance, CGD, is a nonlinear function of voltage and is the most

important parameter because it provides a feedback loop between the output and the
input of the circuit. CGD is also called the Miller capacitance because it causes the total
dynamic input capacitance to become greater than the sum of the static capacitances.

Figure 2.2 Power MOSFET (a) Transfer characteristics, (b) Equivalent Circuit Showing Components That Have
Greatest Effect on Switching
 23

2.11 Safe Operating Area

The Power MOSFET is not subjected to forward or reverse bias second breakdown,
which can easily occur in transistors. Second breakdown is a potentially catastrophic
condition in transistors caused by thermal hot spots in the silicon as the transistor turns on or
off. However in the MOSFET, the carriers travel through the device much as if it were a bulk
semiconductor, which exhibits positive temperature coefficient. If current attempts to self-
constrict to a localized area, the increasing temperature of the spot will raise the spot
resistance due to positive temperature coefficient of the bulk silicon[4]. The ensuing higher
voltage drop will tend to redistribute the current away from the hot spot. Figure 2.3 shows the
safe operating area of the power MOSFET.

Figure 2.3 Safe Operating Area of planar power MOSFET

 24

2.12 Avalanche Breakdown

As the voltage of a power MOSFET is increased, the electric field rises at the body-
epitaxy junction. When this field reaches a critical value Ec (about 3e5 V/cm in Si),
avalanche multiplication of carriers occurs, leading to an abrupt increase in current.
Avalanche multiplication is not a vicious process. However, since the current flow path
involves hole current flow IH (=ID), there is the possibility at high current density of turning
on the parasitic bipolar when VBE = IH * (Rp+Rc) > 0.7V. When this occurs, the gate can no
longer turn-off the FET current. Also, since the open base breakdown voltage ,BVceo is
typically lower than the MOSFET breakdown, current filaments into the weakest cell where
local non-uniformities first cause the parasitic bipolar to turn-on.

From this basic description it follows that:

• Failure occurs above a critical current density (even for short low energy high voltage
pulses)
• High values of Rp (body pinch resistance under the source) and Rc (contact resistance)
degrade UIS capability
• High density cell construction reduces the length of the current path. This decreases Rp,
and increases the critical current density at which failure occurs.
• Since both Rp and Rc increase with temperature, and the emitter-base turn on voltage VBE
decreases with temperature, UIS capability decreases with temperature.

If avalanche capability is tested at lower currents over a long duration, the energy
dissipated , heats the device. The failing current is therefore determined by the peak
temperature the device reaches during this event. Since large chips have a greater heat
capacity, they have higher capability in this mode of operation.
 25

2.13 Performance analysis

2.13.1 Ion / Ioff Current Ratio

Current ratio can be defined as ratio between drift and leakage current and both currents can
be defined respectively as below:

i. Drift current
The drain current that flows when VGS = VDS = VDD (in the strong inversion region) is called
Ion.

ii. Leakage current

The drain current that flows with VGS = 0 V is called Ioff (with VDS = VDD).

2.13.2 The Subthreshold Current

The current which flow when the voltage gate less than the voltage threshold is called
subthreshold current. In a MOSFETs (n-type) operating in subthreshold, the carriers are
emitted by the source, diffuse across the body of the device (under the gate oxide) and are
collected at the drain. The drain current of MOSFETs in the subthreshold region can be
written as

W
ID ID0 .eq(VGS -VTHN ) (n.kT) (2.0)
 26

Taking the log of both sides with VT = kT/q (the thermal voltage), we get

W VTHN 1
logID log +logID0 +- . log e + [ . log e] .VGS (2.1)
nVT VT .n

Where the subthreshold slope is

1
. log e (2.2)
VT .n

The reciprocal of the subthreshold slope is given by

VT .n
Subthreshold slope-1 (mV decade) (2.3)
log e

If the kT/q = 0.026 V = VT and the slope parameter, n = 1, the reciprocal of the
subthreshold slope is 60 mV/decade. In bulk CMOS n is around 1.6 and the subthreshold
slope is 100mV/decade at room temperature. The subthreshold slope can be a very important
MOSFETs parameter in many applications (the design of dynamic circuits). Not to forget,
subthreshold operation can be very useful for lower-power operation such as Solar-powered
calculators, CMOS imagers, or battery operated watches .
 27

2.13.3 DIBL and Punchtrough

Drain-induced barrier lowering (DIBL) determines proximity of surface diffusions and

qualifies as one of the fundamental electrical limitations for VLSI . DIBL effect can be
described as the lateral shift of the transfer curves in the subthreshold regime divided by
the drain voltage difference of the two curve and is given in units (mV/V) :

Vth
DIB (2.4)
Vd

When the inversion charge density is less than the magnitude of semiconductor doping
concentration, weak inversion occur and there will be a potential barrier between the source
and the channel region. The balance between drift and diffusion current between these two
regions produce the height of this barrier[6]. By applying high drain voltage, the barrier
height can decrease (Figure 2.4) and lead to high drain current. Consequently, not only gate
voltage controls the current, but drain voltage (Vd) also control the gate current. The
lowering potential barrier allows electron to flow between the source and the drain, even if
the gate-source voltage is lower than the threshold voltage. In this weak inversion condition,
the current flow through the channel is called the subthreshold current.
 28

Figure 2.4 Surface potential of Device γ for 0.1 V and 1.5 V drain voltages (linear and saturated case) [6]

The effect of DIBL becomes more obvious in the transfer curves of a MOS transistor
for the linear and saturated cases (Figure 2.5). The two curves would coincide in the
subthreshold region if there was no DIBL.

Figure 2.5 Transfer curves of Device γ for 0.1 V and 1.5 V drain voltage (linear and saturated case) [6]
 29

2.14 The Fabrication Process of Power MOSFET

Krishna Shenai, on his research titled „A High-Density, Self-Aligned Power MOSFET

Structure Fabricated Using Sacrificial Spacer Technology‟ which basically designing the
planar power MOSFET ,it can be summarised that the fabrication process used to fabricating
the devices is started by epitaxially grown phosphorus –doped silicon on the silicon substrate.
Then the polysilicon the deposited .Then the gate polysilicon was patterned in acid
hydrochloric plasma and the gate oxide was removed to define the p-base diffusion region
windows. Following the p-base diffusion, silicon oxide was deposited then to define the
sidewall oxide spacers. The next step is implanting arsenic to formed the doped n+ source
junctions for 30 minutes. A photoresist mask then used to provide the isolation between the
adjacent source diffusions. A sidewall oxide spacers were then formed by reactive ion
etching. The gate polysilicon and source contact regions were selectively silicide by
sputtering titanium and then forming Titanium silicide using a two step fumace anneal in the
forming gas.. The contacts to source regions were formed by plasma etching a double layer of
inter level dielectric. The drain contact to the substrate was formed after thinning the wafers
to 15 mils, implanting phosphorus, and annealing hydrogen at 450°C for 30 min, and
sintering nitrogen for 15 min. The sheet resistance of titanium silicide then increased at the
completion of device. Figure 2.6 show the process sequence used in the fabrication of
devices.

(a)
 30

(b)

(c)

(d)

Fig. 2.6. The process sequence used in the fabrication of devices. Power MOSFET cross section after (a) gate
definition and p-base formation, (b) the formation of shallow surface p+-diffused region, (c) the formation of
n+-source regions, and (d) at the completion of device processing
 31

CHAPTER 3

METHODOLOGY

3.1 Overview

This chapter will discuss about the steps taken in order to complete the project.
The main objective of this chapter is on understanding in handling the Silvaco TCAD
software, such as the steps taken to design and simulate a device and extract it electrical
characteristic. It is divided into a few parts that are methodology steps, process simulation,
and device simulation for this project

3.2 Silvaco TCAD Tools

The software is founded in 1984. The company recently spun out its circuit
simulation, parasitic extraction and IC CAD products as Simucad Design Automation so that
Silvaco can focus exclusively on TCAD. The company delivers its Stanford-based TCAD
products with support and engineering services to provide semiconductor process and device
simulation solutions. Worldwide customers include leading foundries, fabless semiconductor
companies, integrated semiconductor manufacturers, universities, and semiconductor
designers who require the broadest model support, highest accuracy and optimal
performance.
 32

Silvaco TCAD Tools consists of two main parts:

i. Process simulation / Design ( ATHENA)

In process simulation, semiconductor manufacturing processes was modelled. The

simulation starts with the bare wafer and finishes with device structures. Implantation,
diffusion, etching, growth, and deposition process are simulated on a microscopic
level. In this project, Athena Tools was used to design the planar power MOSFET.

ii. Device simulation (ATLAS)

In device simulation, semiconductor device operation on a microscopic level was

modelled. By integrating microscopic currents, the electrical behaviour is
characterized. The results of the process simulation will be displayed in Silvaco
Tonyplot and the device characteristics can be examined. This offers an easy way of
studying the effects of process parameters on the device performance and both the
device structure and the fabrication process can thus be optimized.

In order to complete the project using Silvaco TCAD Tools, an understanding on the
software tools and its flow on accomplishing the desire objective is crucial.
 33

3.3 Summary of Project’s Methodology

Methodology is generally a guideline for solving a problem, with specific components

such as phases, tasks, methods, techniques and tools. By applying the concept of the
methodology, it will give an overall overview of the whole project from the beginning until
the end of this project.

The project‟s flow can be divided into three major parts, the literature review part,
device simulation and design part and device analysis part. This project started with literature
review on research paper related to the power MOSFET. Then, by using Silvaco TCAD
Athena tool, a structure of planar power MOSFET will be designed. After that, the electrical
parameters will be determined by using Silvaco TCAD ATLAS tool during the device
simulation process. At this stage also, the output of I-V characteristic will be produced
automatically by Silvaco Tonyplot. Then, from the result obtained, the performance will be
analysed by using the Silvaco Tonyplot and Microsoft excel . Then, a decision will be made
either the result is valid or not based on the literature review and discussion with the other
researcher. If valid then the analysis will further be done by varying all the parameters stated
in the scope of the project but if the result not valid, there must be an error occurred in the
design structure or in simulation part and the designing process will be repeated until the
desired device is obtained. The flowchart of the whole project is shown in the Figure 2.7. The
table of parameters varied is shown in table 1.0.
 34

Start

iterature
study

Design structure Power MOSFETs

using using Silvaco TCAD Tools
(Athena)

Simulate device using Silvaco

TCAD Tools (Atlas)

Analysis of device
characteristics

NO
Is the
result
valid?

YES
Analysing the device by
varying desired
parameters

End

Figure 2.7 Flowchart of research methodology

 35

Table 1.0 Table of investigation parameters

No. Investigation Parameter Value

The effects on varying doping 3x1014
7x1014
implantation dose for source.
1x1015
1 Ns (cm-2) 3x1015
7x1015
1x1016
3x1016
The effects on varying doping 3x1014
1x1014
2 implantation dose for body Nd (cm-2) 7x1013
3x1013
1x1013
The effect of varying the diffuse time 20
for diffusion method of source doping 40
3 Td 60
80
100
The effects on varying gate oxide 20
thickness 40
5 tx (nm) 80
120
180
 36

3.4 Deckbuild

DeckBuild is an interactive runtime and input file development environment within

which all Silvaco‟s TCAD and several other EDA products can run and has numerous
simulator specific and general debugger style tools, such as powerful extract statements, GUI
based process file input, line by line runtime execution and intuitive input file syntactical
error messages. DeckBuild contains an extensive library of hundreds of pre-run examples
decks which cover many technologies and materials, and also allow the user to rapidly
become highly productive.In this project, the virtual fabrication process will be using
deckbuild to do all the process by inserting the input using the tools built in the deckbuild.
This program is divided into two part which is Athena and atlas which can run in the same
window. The command such as implant, creating mesh ,oxidation can be made by selecting
the right command tools in the interface. In general, deckbuild is called Graphic User
Interface(GUI) which will help the user to design the structure without need to type any
complex coding .

Deckbuild key features are listed below

 GUI based auto-creation of ATHENA process simulation input files

 Hundreds of fully run examples to jump-start new users to almost immediate
maximum productivity
 Extremely powerful, simulator specific, pre-written extract statements to extract all
manner of process and device characteristics at any stage during the runtime, like
layer thicknesses or device threshold voltages
 Extract statements are written in a general script language allowing user definable
functions
 Numerical results from previous extract statements can be used as inputs to
subsequent extract statements
 Extracted quantities can be used as targets in DeckBuild‟s internal optimizer, allowing
automatic cyclical optimization of any parameter
 Anything in the input file can be defined as a variable, even structure file names,
using a “set” statement
 37

 Any variables created using “set” statements can be used in DeckBuild‟s internal
Design Of Experiment (DOE) feature, allowing an entire DOE to be run using a
single input file
 Many input file creation and debug assist features, such as run, kill, pause, stop at, and
re-start
 Other tools can be invoked from the tool box or directly from the input file


The interface of deckbuild are shown in the right part of figure 2.8. The one in the left
part is the terminal in Linux based system. To view this interface, the terminal must be input
with certain code . To create Athena version of deckbuild, the code inserted are as below

> deckbuild – an&

Meanwhile,to create Atlas version of deckbuild,the code below need to be inserted to

the terminal

> deckbuild – as&

Figure 2.8 The terminal and Deckbuild:Atlas main window.

 38

3.5 Device Structure Design

In order to design the structure of the device, it specification must be define first.
Table 1.1 shows the device doping specification.

Table 1.1 Device doping specification

No. Region Material Doping Value

Source
1
Phosphorus 1x1018cm-3
Silicon
2 Drain
3 P-Body Boron 3x1014cm-3
7 N+ Source Arsenic 7x1016cm-3
8 Polysilicon N+ polysilicon Arsenic 5x1018cm-3

3.6 Process Development

The step by step fabrication process using Silvaco TCAD Athena tool will be shown
in this part. The device will be design only in the left side only as the device is symmetrical
and in the last step the device will be mirror, to get the actual device.

3.6.1 Generating Meshes

Generating mesh are required before a semiconductor device can be numerically solved for
its electrical properties. To create the mesh using deckbuild Athena GUI, clicking the menu
commands>define will generate the Athena Mesh Define Tools shown in figure 2.9 which
allows the user to create the desired mesh. The mesh for direction x and y are shown in
figure 2.9 (a) and 2.9 (b).
 39

(a)

(b)

Figure 2.9 Athena Mesh Define Tools (a) X direction (b) Y direction

The result of the mesh created are shown in figure 3.0. The more shallower the mesh,
the alteration of the device can be done more easily
 40

Figure 3.0 The mesh generate for planar power MOSFET

3.6.2 Adding a Substrate Region and Epitaxy Layer

The next step of fabrication is adding a silicon base region as a substrate. The silicon
impurities is phosphorus. The value of this concentration must fulfilled the whole area .
Hence, the phosphorus with 1x1018 cm-3 total doping concentrations were chosen .

Then, the epitaxy process is done to create the epitaxy layer which is used to support
most of the voltage applied to the device. To add the substrate in the Deckbuild Athena ,the
Athena Mesh Initilize Tools were used which can be found by clicking commands>mesh
initialize . The windows as shown in figure 3.1 will be generate which allow the user to
choose the impurity and others criteria desired.
 41

Figure 3.1 Athena Mesh Initialize Tools

To add an epitaxy layer the Athena Epitaxy Tools were used which can be found
when clicking command>process>epitaxy .Figure 3.2 below show the tools where the user
can define the scale such as time and temperature for the epitay process.

Figure 3.2 Athena Epitaxy Tools for Epitaxy process

 42

3.6.3 Polysilicon Deposition and Polysilicon Oxidation with Photoresist mask

The polysilicon is deposited as it will be used as gate contact to the planar power
MOSFET. The photoresist layer will be deposited with the polysilicon to act as mask which
provide the isolation between the adjacent source diffusions. The photoresist will be etch in
the further process. To deposit all the materials above ,the Athena Deposit tools will be used
which can be found by clicking commands>process>deposit>deposit .The material then can
be choose depend on the user need. The materials cannot be deposit in the same time, which
mean for three materials to be deposited, three separate process of deposition need to be done
using this tools. If the materials need to be deposited with impurities, like polysilicon, the
tools does provided the specifications as shown in figure 3.3 below

Figure 3.3 Athena Deposit Tools for depositing the materials into device
 43

The result after depositing all three materials stated above are shown below. The
materials are separated by the different colours which is indicated in the figure 3.4.

Figure 3.4 Device structure after polysilicon deposition and polysilicon oxidation with photoresist mask

3.6.4 Polysilicon and Oxide Etching

The polysilicon and oxide with the photoresist mask then will be etch as shown in
Figure 3.6 to follow the specification given in literature review. To do the etching process in
the Deckbuild Athena, the Athena Etch Tools will be used which will give the user to define
their etch region in the geometrical type option as shown in figure 3.5. The user then can
specify their etch location after choosing the geometrical type or for some cases like masking
which will be fully etch, geometrical type of all can be choose. To find this tools, the simplest
way is by clicking commands>process>etch>etch. Figure 3.5 show how the tools was used
to etch the oxide.
 44

Figure 3.5 Deckbuild Athena Etch Tools used to etch the oxide

Figure 3.6 Device structure after polysilicon and oxide etching

 45

3.6.5 P-Body Implantation

The next step is to implant the p-body of the device as shown in the literature review.
The impurity used is boron with dose of 3x1014 cm-2. . The implantation of p-body using
Deckbuild:Athena can be done using Deckbuild:Athena Implant Tools. The tools can be
access by clicking commands>process>implant .The tools will give the users option to
choose impurity ,the dose value and others parameters such as energy.For p-body
implantation,the impurity choose is boron. Figure 3.7 show the Deckbuild:Athena implant
tools for boron implantation. The result of the structure after running this process are show in
figure 3.8. The P-Body part can be seen clearly in the top left part of silicon.

Figure 3.7 Deckbuild:Athena implant tools for boron implantation.

 46

Figure 3.8 Device structure after P-Body Implantation

3.6.6 Nitride Deposition

Nitride deposition can be seen in Figure 4.0 .The nitride will be act as mask and will
be etch at all in the further process. The main reason for the nitride deposition as mask is to
create the contact between the source and the p-body so that the current can flow as normal
power MOSFET should. The nitride then is etched and as small part is left as to do what the
former sentence state .The nitride will be etch out at all when the N+ source is implant in the
device. The deposition of nitride using Deckbuild:Athena Deposit Tools are shown in figure
3.9.
 47

Figure 3.9 Nitride Deposition using Deckbuild:Athena Deposit Tools

Figure 4.0 Device structure after nitride deposition

 48

3.6.7 Nitride Etching

The nitride is etch and just a chunk part of it left as it will etch the n+ source area
under it and let the p-body part to have contact with the aluminium contact as shown in figure
4.2. To etch the nitride ,the Deckbuild:Athena Etch Tools will be used. This process is
different compare to the first etching process when etching the polysilicon since we need to
describe the area of the etching to using this tools.The figure 4.1 shown how the area of the
etching is described using the tools. The tools basically let the user decide the location of the
coordinate of the area that need to etch.

(a)

(b)
 49

(c)

(d)

Figure 4.1 Defining the coordinate for rectangle that will need to be etch (a)first coordinate
(b)second coordinate (c) Third coordinate (d) fourth coordinate
 50

The other way to do the etching process is by changing the following code .The code
is simply give out the coordinate of a rectangle area that need to be etch. For following code
,the etching of nitride will start at (1,0) then move to (10,0) ,and so on which will finally
create a rectangle that will be etch by the program

> etch nitride start x=1 y=0.0

>etch cont x=10 y=0.0
>etch cont x=10 y=-2.0
>etch done x=1 y=-2

Figure 4.2 Device structure after nitride etching

3.6.8 Photoresist Etching

The Photoresist is etch out after the implantation of the P-body. The process will be
used the same tools for etching which is Deckbuild:Athena Etch Tools. As mentioned before,
since all the photoresist need to be etched out, the selected geometrical type will be „All‟ .
This will let the program know that all the photoresist area will be etch out. Figure 4.3 show
how it done using is Deckbuild:Athena Etch Tools.
 51

Figure 4.3 Etching all Photoresist out using Deckbuild:Athena Etch Tools

Figure 4.4 Device structure after photoresist etching

 52

3.6.9 N+ Source Implantation

The implantation of N+ Source is using arsenic as the impurity. The dose is at 3x1015
cm-2 . Figure 4.6 show how the masking effect the structure after the implantation of the
arsenic dose. The source were connected to the other half of the device using the aluminium
contact . The implantation of N+source using Deckbuild:Athena Implant Tools are shown in
figure 4.5. The way of doing the process is all the same, with the difference only appear on
the parameters used.

Figure 4.5 The implantation of N+source using Deckbuild:Athena Implant Tools

 53

Figure 4.6 Device structure after n+ source implantation

3.6.10 The Etching of all Nitride

The nitride can be etch all out now as it will not be used anymore in the structure.
The main purpose of the nitride had been achieved, hence we can etch it all out so it will not
affect the structure in other ways. The same method as photoresist etching will be used.

Figure 4.7 Device structure after full nitride etching

 54

3.6.11 Polysilicon Oxidation

Since the etching process in the earlier part had make the oxidation of the polysilicon
did not complete, then again the polysilicon will be oxidise so that all part of the polysilicon
will be covered up with oxide. The same method as used before will be apply in this process
to oxidise the polysilicon.

Figure 4.8 Device structure after polysilicon oxidation

3.6.12 Aluminium Deposition

The main function of the aluminium is to connect the two source which is in the left
side and the right side. The right side will only appear after the mirroring process is done.
The current now can flow from one to the another as the literature review stated. The
deposition of aluminium using Deckbuild:Athena Deposit Tools are shown in figure 4.9 .The
same method of depositing as before when depositing polysilicon will be used in this process
but with the different material and thickness.Meanwhile,the cross section of device after the
process is shown in figure 5.0
 55

Figure 4.9 The deposition of aluminium using Deckbuild:Athena Deposit Tools

Figure 5.0 Device structure after aluminium deposition

 56

3.6.13 Mirroring the structure

The next step of fabricating the planar power MOSFET is the mirroring process. As
the device is symmetrical ,the mirroring process will create the a mirror image of the left side
to match with the left side and the designing of the device is finish up. The easiest way to
mirror the device is by typing expressions below in the Deckbuild:Athena windows. The
other ways to create the mirror structure is by clicking commands>strcture>mirror which
will generate Deckbuild:Athena Mirror Tools as shown in the figure 5.1. The usual way of
using it is when the structure is design in the right side, the mirror right option will be used
and vice versa .

> struct mirror right

Figure 5.1 Mirroring the structure using Deckbuild:Athena Mirror Tools

3.6.14 Adding Contacts to electrode

The final step is to locate the coordinate electrode of source, drain and gate. This can
be done by inserting a coordinate location of the electrode and the Athena Tools will detect
the material as the electrode.For example if the coordinate of gate given to the Athena Tools
is x=4 ,y=0 then it will assume the polysilicon as the gate.The figure 5.3 and 5.4 below show
the final device structure in two different representation. The simplest way to adding contacts
to the electrode is by inserting command below into the deckbuild.

> electrode name=source x=0

> electrode name=gate x=5 y=-0.2
> electrode name=drain backside
 57

There is another way to insert the contacts to the electrode which is by clicking
commands>structure>electrode and the following windows will be shown.The user need to
define the location in coordinate of the electrode in the Deckbuild:Athena Electrode Tools. If
any of the electrode is in the backside,in this project it is drain, the backside option will be
used to determine it.Electrode need to be named also.

(a)

(b)

(c)

Figure 5.2 The electrode definition of the device using the Deckbuild:Athena Electrode Tools (a) Gate definition
(b)Source definition (c) Drain definition
 58

Figure 5.3 Final device structure after mirroring

Figure 5.4 Final device structure after mirroring with net doping display
 59

3.7 Device simulation

ATLAS enables device technology engineers to simulate the electrical, optical, and
thermal behaviour of semiconductor devices. It provides a physics-based, modular, and
extensible platform to analyze DC, AC, and time domain responses for all semiconductor
based technologies in 2 and 3 dimensions.
Figure 5.5 shows the types of information that flow in and out of ATLAS. Most
ATLAS simulations use two inputs which are a text file that contains commands for ATLAS
to execute, and a structure file that defines the structure that will be simulated.
In this project, there are two outputs characteristic (I-V curve) can be obtained. First,
IDVDS graph and second, IDVGS graph. From these two characteristic, we can obtain the
threshold voltage, leakage current, maximum drain/source current, drain saturation slope and
also subthreshold slope [12].

Figure 5.5 ATLAS input and output [12]

 60

3.8 Summary

All steps to design the structure had explained earlier. It shows that nowadays there
are many easiest software in market that can use to fabricate the transistor. It will give a good
understanding before doing a real process of fabrication. All the results and output
characteristic will be shown and discuss in the next chapter.
 61

CHAPTER 4

RESULTS AND DISCUSSION

In this chapter, the results from the device simulation are discussed here. The
electrical performance of the device was performed by changing the desired parameters in the
Silvaco TCAD Atlas file. The analysis is done by using Silvaco Tonyplot where the graph
will be analyzed to get the desired parameters . The data of parameters taken from the Silvaco
Tonyplot will be plot using Microsoft Excel Tools.

4.1. Device Structure

Figure 5.6 shows the cross section of device structure of planar power MOSFETs
using Silvaco TCAD Athena. The inversion layer or channel can be seen in the p-body
region under the gate . The position of the drain ,gate and source has been described in the
figure.
 62

Figure 5.6 The cross section of planar power MOSFETs using Silvaco TCAD Athena.

4.2 Data Extraction

4.2.1 Threshold Voltage

Figure 5.7 and Figure 5.8 shows the output characteristic (I-V curve). Basically, there
are two types of graph have been obtained which are ID VS VGS and ID VS VDS.
 63

(a)

(b)

Figure 5.7 Graph of IDs VS VGS (a)In log scale (b)In linear scale

Threshold voltage is obtained from the ID-VGS curve as in Figure 5.7 (a). The
intersection between line that is between VDS=0.1V and VDS=1.0V will give the value of
threshold voltage, VTh.
 64

Figure 5.8 IDs VS VDS curve

4.2.2 Drain Induced Barrier Lowering (DIBL)

Theoretically, the values of DIBL can be calculate using equation 2.5, stated as
below. However, by using Silvaco Tonyplot, we can directly get the value of DIBL by using
the ruler tools. The tools will calculate the slope between the two curve of ID VS VGS graph,
which represent DIBL graphically. The figure 5.9 shows how the tools work to calculate the
DIBL.

( 2.5 )
 65

Figure 5.9 Extraction of DIBL

4.2.3 Subthreshol Swing

Meanwhile, the value of S is represent graphically by the nearest distance between

two curve of ID VS VGS graph, which is shown in figure 6.0.

Figure 6.0 Extraction of S

 66

4.3 Variation of N+ Source Implant Dose

Table 1.2 : Result of Variation of N+ Source Implant Dose

Implant Channel Vth (V) S(mV/dec) DIBL Ion (A) Ioff (A) Ion/Ioff
Dose Length(nm) Ratio
(cm-2 )
3e14 12.7 3.1 467 0.0978 1.033e-09 6.858e-15 150627
7e14 12.5 2.12 402 0.0732 3.029e-09 6.863e-15 441352.2
1e15 12.3 2.1 340 0.0817 3.446e-09 6.865e-15 501966.5
3e15 9.52 1.95 331 0.0787 6.746e-10 6.87e-15 98195.05
7e15 9.37 1.62 310 0.0579 5.441e-10 6.886e-15 79015.39
1e16 9.33 0.95 195 0.0522 1.687e-09 7.868e-15 24498.98
3e16 5.19 0.01 80 0.0505 4.578e-10 5.97e-11 7.668342

(a) (b) (c)

Figure 6.1 Cross Section of N+ Source Region for Implant Dose (a)3e14 (b)7e14 (c)1e15
 67

From table 1.2 , the data shown that as the implant dose increase, the channel length
decreased ,Vth decreased, S decreased and DIBL decreased. The Ion/Ioff Ratio is peak
501966.5 at the value of 1e15. Meanwhile in the figure 6.1 ,the figure shown that the depth
grows deeper as the concentration of arsenic increased . In this project, the planar power
MOSFET structure cannot have a of N+ source implant dose more than 3.0 x1016cm-3 as it
will make the device not function properly due to the punchthrough.

The reason for the increase in Vth is arsenic is donor atom. Increasing the
concentration will cause source having more electrons. Hence, more negative charges can be
used to form the channel when positive voltage is applied to gate. As a result, VTH decreases
as less VGS is needed.

4.4 Variation of Gate Oxide Thickness

Table 1.3 Result of Variation of Gate Oxide Thickness

Gate Oxide Channel Vth (V) S(mV/dec) DIBL Ion (A) Ioff (A)
Thickness, Length(nm)
Tox (Å )

20 9.63 0.5 132 0.0108 3.656e-09 4.35e-14

40 9.52 1.3 238 0.0357 3.515e-09 6.989e-15
60 9.34 2.5 423 0.108 3.297e-09 6.637e-15
80 9.21 3.75 596 0.193 7.25e-10 6.616e-15
100 9.01 4.8 733 0.28 1.36e-09 6.62e-15
180 9.05 5.15 817 0.315 9.889e-10 6.687e-15
 68

From table 1.3 , the data shown that as the gate oxide thickness increase, the channel
length decreased ,Vth increased, S increased and DIBL increased

Although decreasing the gate oxide does decrease the Vth, but device is more prone to
gate oxide punch throughIf the gate oxide of the device is too thick, it will be harder for the
gate voltage to attract the negative charges. Therefore, it will need a higher threshold voltage
in forming the effective n-channel. On the other hand, if the gate oxide is thin, the quantum
mechanics effect of electron tunnelling happened between the oxide and channel region will
lead to higher gate oxide leakage current. Thinner gate oxide will caused the channel to form
more easily and threshold voltage will be lower.

4.5 Variation of P-Body Implant Dose

Table 1.4 Result of Variation of P-Body Implant Dose

Implant Channel Vth (V) S(mV/dec) DIBL Ion (A) Ioff (A)
-2
Dose (cm ) Length(nm)

3e14 10.4 5.45 675 0.0862 6.008e-09 3.119e-14

1e14 9.52 1.95 331 0.0787 6.746e-10 6.87e-15

7e13 9.21 1.5 284 0.0546 2.339e-09 7.712e-15

3e13 8.05 0.55 153 0.0309 1.542e-10 6.663e-14

1e13 4.58 -0.2 65 0.0316 1.206e-10 6.3e-14

 69

(a) (b)

Figure 6.2 Cross Section of Variation of P-Body Implant Dose of (a)3e14 (b)1e14

From table 1.4 , the data shown that as the P-Body Implant Dose decrease, the
channel length decreased ,Vth decreased, S decreased and DIBL decreased.

P-body implant dose does have huge impact on the threshold voltage of the device .As
the result shown, slight change can alter the value of threshold voltage a lot. The designer
must be careful in choosing the P-body implant dose as it will affect the P-Body thickness. A
strong intention must be taken in designing because if under designed will cause depletion
region punch through to the N+ source region. Meanwhile if over designed, the channel
resistance and Vth will increase dramatically.
 70

4.6 Variation of Diffuse Time of Arsenic Doping

Table 1.5 Result of Variation of Diffuse Time of Arsenic Doping

Diffuse Time Channel Vth S(mV/dec) DIBL Ion Ioff

(minutes) Length(nm)

20 9.46 1.95 331 0.0636 6.746e-10 6.87e-15

40 9.6 1.8 324 0.0486 1.421e-09 1.844e-14
60 9.71 1.5 275 0.0287 1.165e-08 3.144e-14
80 9.94 0.65 171 0.0504 2.707e-10 3.377e-14
100 9.80 0.75 163 0.0502 4.752e-10 3.386e-14

From table 1.5 , the data shown that as the diffuse time of arsenic doping increase, the
channel length increased ,Vth decreased, S decreased and DIBL decreased. Diffuse stand for
a process that runs a time temperature step on the wafer and calculates oxidation, silicidation
and diffusion of impurities. It can be said that the increase in diffuse time does not affect the
channel length largely. But it does effect the Vth in some way. Lower diffuse time gave
higher Vth, while increasing diffuse time gave lower Vth. Hence, to design a device with
high Vth,the designer must considered the between 20 to 60 to not affect the Vth too much.
 71

4.7 The Pattern of data

(a) (b)

(c) (d)

Figure 6.3 Graph of The Pattern of Data of (a)Channel Length vs Vth (b) S VS Vth (c) DIBL vs S
(d)Ion/Ioff Ratio vs Vth
 72

From the data obtained, the pattern graph is drawn to compare how each parameters
related to each other. From figure 6.3 (a),channel length increase as the Vth increase for two
variables which is P-Body implant dose and N+ source implant dose. This show that how
implant dose can increase the Vth. The other two variables does show the opposite effects.

From figure 6.3 (b),the graph follow one pattern only which is as the subthreshold
swing (S) increase ,Vth increase ,or vice versa .This strongly show that any change happen to
any of the parameter will affect the other parameter too. This mean that we cannot control
any one of the parameters as the other one will follow. Compare to the lateral MOSFET, S
can be control by changing those parameters; The channel depletion depth, gate oxide
thickness, junction depth, the supply and substrate voltage.

For figure 6.3 (c),the same pattern apply as figure 6.3 (b).The DIBL will follow
Subthreshold Swing pattern or vice versa. For figure 6.3 (d),the different pattern can be seen
as the Ion/Ioff Ratios gave a peak value when the value of Vth is increase. The Ion/Ioff
Ratios is important parameter that can be used to see how fast the device switching and
smaller value is better.
 73

CHAPTER 5

CONCLUSION AND RECOMMENDATIONS

5.1. Conclusion

The planar power MOSFET has been designed and simulated successfully using Silvaco
TCAD Tools. This structure is investigated by varying the parameters such as it consists of:

a) N+ source implant dose with dose of 3x1014cm-2, 7x1014cm-2, 1x1015cm-2, 3x1015cm-

2
, 7x1015cm-2, 1x1016cm-2, 3x1016cm-2.
b) P-Body implant dose with dose of 3x1014cm-2, 1x1014cm-2, 7x1013cm-2, 3x1013cm-2,
1x1013cm-2.
c) Gate oxide thickness of 20 Å , 40 Å , 60 Å , 80 Å , 100 Å .
d) Diffuse time of arsenic doping with time of 20,40,60,80,and 100 minutes

The structure developed has shown that it have high Ion / Ioff ratio, which is the one of
the reason of designing power MOSFET,for the fast switching speed. The structure threshold
voltage can be vary but as it get higher or lower, the value of subthreshold swing and DIBL
also will follow the exact same path.

Finally, this research has been carried out on a simulation basics. Throughout this
project, it is found that Silvaco TCAD tools which are Athena and ATLAS has many useful
in industrial. It shows the steps on how to virtually fabricate a transistor in industry without
need to go to the fab houses which require high cost.
 74

5.2. Recommendations

Due to resource and time constrain, this project can still be improve. In this project,
the other type of power MOSFET structure which is trench can be design to be compare with
the planar design. Trench power MOSFET are mainly used for <200V voltage rating due to
their higher channel density and thus lower on-resistance.
 75

REFERENCES

[1] D-MOSFET Structure, Fundamentals of Power Semiconductor Devices ,B. Jayant

Baliga

[2] Introduction to Power MOSFETs and Their Applications , Ralph Locher,

December 1988

[3] Power MOSFET Basics ,Alpha and Omega semiconductor

[4] Power MOSFET Basics By Vrej Barkhordarian, International Rectifier, El

Segundo, Ca.

[5] Power MOSFET Tutorial,JonathanDodge, P.E.

[6] Michael Stockinger (2000). Optimization of Ultra-Low-Power CMOS Transistors.

Doctor Philosophy. Technical University Wien, Germany.

[7] Optimized Trench MOSFET Technologies for Power Devices Krishna Shenai,

Senior Member, IEEE,June 1992

[8] Investigation of Short Channel Effect on Vertical Structure in Nanoscales

MOSFETs by Munawar A. Riyadi, Ismail Saad,Razali Ismail,December 2009

[9] Short-Channel Effects in MOSFETs, December,2000, F. D‟Agostino, D. Quercia

[10] DeckBuild User‟s Manual, SILVACO, Inc

 76

[11] A High-Density, Self-Aligned Power MOSFET Structure Fapricated Using

Sacrificial Spacer Technology, Krishna Shenai

[12] ATHENA User‟s Manual, SILVACO, Inc

[13] http://www.silvaco.com
 77

APPENDIX A

Silvaco TCAD
Athena and Atlas Program Listings
 78

Planar Power MOSFET

Athena
go athena
#
line x loc=0.00 spac=0.25
line x loc=3.00 spac=0.10
line x loc=7.00 spac=1.0
#
line y loc=7.00 spac=0.5
line y loc=8.00 spac=0.5
#
init c.phosphor=1.0e18 orientation=100 space.mult=2
# Epitaxy Processs
epitaxy time=10 temp=1200 thickness=7 divisions=15 \
dy=0.10 ydy=0.00 c.phos=1.0e15

structure outfile=LateralPlanar1.str

#deposit poly first

deposit oxide thickness=0.02 div=1
deposit poly thickness=0.35 div=3 c.arsenic=5e18
deposit oxide thickness=0.35 div=3
deposit photores thickness=1 div=3

structure outfile=LateralPlanar2.str

etch photores p1.x=3 left

etch oxide p1.x=3 left
etch poly p1.x=3 left
etch oxide p1.x=3 left

structure outfile=LateralPlanar3.str
 79

#Dope P-Body
implant boron dose=3e14 energy=80
diffuse time=100 temp=1100
#implant boron dose=1e14 energy=80
#diffuse time=100 temp=1100

structure outfile=LateralPlanar4.str

deposit nitride thick=0.3 dy=0.1 ydy=0.3 division=10

structure outfile=LateralPlanar5.str

etch nitride start x=1 y=0.0

etch cont x=10 y=0.0
etch cont x=10 y=-2.0
etch done x=1 y=-2

structure outfile=LateralPlanar6.str

etch photores all

structure outfile=LateralPlanar7.str

#Dope N+ source
implant arsenic dose=7e16 energy=100
diffuse time=20 temp=1100
#implant arsenic dose=3e15 energy=100
#diffuse time=20 temp=1100

structure outfile=LateralPlanar8.str

etch nitride all

 80

structure outfile=LateralPlanar9.str

deposit oxide thickness=0.5 div=4

etch oxide thickness=0.5

structure outfile=LateralPlanar10.str

etch start x=0 y=-0.2

etch cont x=0 y=0.0 #y=0.8
etch cont x=2.5 y=0.0 #y=0.8
etch done x=2.5 y=-0.2

structure outfile=LateralPlanar11.str

diffuse time=1 temp=1100

deposit alum thickness=0.4 div=8

#etch alum right p1.x=3.5

structure outfile=LateralPlanar12.str

struct mirror right

electrode name=source x=0
electrode name=gate x=5 y=-0.2
electrode name=drain backside

structure outfile=LateralPlanar.str

tonyplot LateralPlanar.str -set LateralPlanar.set

 81

Atlas

go atlas
#
mesh infile=LateralPlanar.str
#
models cvt boltzman print temperature=300

#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000 cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5 gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4 mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17 csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71 betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14 delp.cvt=2.0546e+14
#
models srh cvt boltzman print temperature=300

#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000 cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5 gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4 mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17 csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71 betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14 delp.cvt=2.0546e+14
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4 autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03 maxinner=25
 82

#
contact name=gate n.poly

#
interface s.n=0.0 s.p=0.0 qf=3e10

solve init
solve vdrain=0.1 outfile=solve1

solve vdrain=1.0 outfile=solve2

load infile=solve1
log outf=ATHENA_NMOS_1_Vd_01.log
solve name=gate vgate=-0.1 vfinal=10 vstep=0.3

load infile=solve2
log outf=ATHENA_NMOS_1_Vd_10.log
solve name=gate vgate=-0.1 vfinal=10 vstep=0.3

extract name="vt" (xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) \

- abs(ave(v."drain"))/2.0)

Tonyplot -overlay ATHENA_NMOS_1_Vd_01.log ATHENA_NMOS_1_Vd_10.log

log off
solve vgate=1.1 outfile=solve4
solve vgate=2.2 outfile=solve5
solve vgate=3.3 outfile=solve6
 83

load infile=solve4
log outf=ATHENA_NMOS_1_Vg_11.log
solve name=drain vdrain=0 vfinal=10 vstep=3

load infile=solve5
log outf=ATHENA_NMOS_1_Vg_22.log
solve name=drain vdrain=0 vfinal=10 vstep=3

load infile=solve6
log outf=ATHENA_NMOS_1_Vg_33.log
solve name=drain vdrain=0 vfinal=10 vstep=3

tonyplot -overlay ATHENA_NMOS_1_Vg_11.log ATHENA_NMOS_1_Vg_22.log

ATHENA_NMOS_1_Vg_33.log
 84

Trench Power MOSFETs

go athena
#
line x loc=0.00 spac=0.2
line x loc=3.00 spac=0.10
line x loc=5.00 spac=0.10
#
line y loc=6.00 spac=0.1
line y loc=8.00 spac=0.3
#
init c.phosphor=1.0e18 orientation=100 space.mult=2

struct outfile=trenchpmos_1.str

# Epitaxy Processs
epitaxy time=10 temp=1200 thickness=6 \
dy=0.10 ydy=0.00 c.phos=1.0e15

struct outfile=trenchpmos_2.str

implant boron dose=1e14 energy=80

diffuse time=100 temp=1100

struct outfile=trenchpmos_3.str

deposit nitride thick=0.3 dy=0.1 ydy=0.3 division=10

etch nitride start x=1 y=0.0

etch cont x=10 y=0.0
etch cont x=10 y=-2.0
etch done x=1 y=-2
 85

struct outfile=trenchpmos_4.str

implant arsenic dose=3e15 energy=100

diffuse time=20 temp=1100

struct outfile=trenchpmos_5.str

etch nitride all

deposit oxide thickness=0.5 div=4

etch oxide thickness=0.5

struct outfile=trenchpmos_6.str

etch start x=3.5 y=-0.2

etch cont x=3.5 y=2.5
etch cont x=5.0 y=2.5
etch done x=5.0 y=2.3

struct outfile=trenchpmos_7.str

#Oxide Deposition
deposit oxide thick=0.15 divisions=10

#Polysilicon Deposition
deposit polysilicon thick=1 divisions=10 c.arsenic=1e18

#Poly Etching
etch polysilicon left p1.x=2.25

etch polysilicon start x=2 y=0

etch cont x=3.5 y=0
etch cont x=3.5 y=-2
etch done x=0 y=-2
 86

struct outfile=trenchpmos_8.str

etch oxide thickness=0.5

etch polysilicon start x=2 y=0

etch cont x=3.5 y=0
etch cont x=3.5 y=-2
etch done x=0 y=-2

struct outfile=trenchpmos_9.str

deposit alum thickness=0.5 div=8

etch alum start x=2.5 y=0

etch cont x=3.5 y=0
etch cont x=3.5 y=-0.5
etch done x=2.5 y=-0.5

etch alum start x=2.25 y=-0

etch cont x=5 y=-0
etch cont x=5 y=-2
etch done x=2.25 y=-2

struct mirror right

electrode name=source x=0 y=-0.2

electrode name=gate x=5 y=-0
electrode name=drain backside

struct outfile=trenchpmos.str
tonyplot trenchpmos.str -set trenchpmos.set
 87

extract init infile="trenchpmos"

extract name="1D Vt 0-20v" 1dvt ntype bias=0.5 bias.step=0.1

bias.stop=15.0 vb=0.2 temp.val=350.0 x.val=0.1
88
89