BUCK CONVERTER DESIGN -POWER STAGE

Vin = 9-32 V

Vout = 5 V

I load = 2 Amps

Fsw =
𝑉𝑜𝑢𝑡
𝐷= 𝑉𝑖𝑛
5𝑉
𝐷 = 32 𝑉

𝐷 = 0.15625

𝐼𝑟𝑖𝑝𝑝𝑙𝑒 = 0.3 𝑥 𝐼𝑙𝑜𝑎𝑑 for 40

The circuit show the basic topology of a simple buck converter.

For the design of the component values:

1st : DETERMINE THE SWITCHING FREQUENCY TO BE USED , based on an commercially available inductor

L = 33 uH ; commercially available
0.15625
5𝑉 ( )
𝑥
33𝑢𝐻 = 0.3(2)
X = 39.457 kHz = Fsw (Switching Frequency)

For a capacitor:

We define the ripple voltage : 50 mV

I ripple = 0.6 A

We have here an equation with multiple unknowns. ESR C and ESL

A reasonable approach here is to remove the terms that are not that significant.

We will make approximations right here.

ESL specification is usually not specified by the capacitor vendor

We will neglect this value of the ESL. We will be setting it as zero.

As the Fsw is increased, the ESL specification will become more important

ESR = 0.03 Ohms – selected form vendors catalog of SPS rated capacitors.

Given that:

Ripple current = 0.6A

ESR = 0.03 Ohms

ESL = 0

0.15625
𝛥𝑇 =
39.457 𝑘𝐻𝑧

𝜟𝑻 = 𝟑. 𝟗𝟔 𝒖𝒔𝒆𝒄

SELECTING THE OUTPUT CAPACITOR:

Through re -arranging:
 (0.6 𝐴 𝑥 3.96 𝑢𝑠𝑒𝑐 )
𝐶𝑜𝑢𝑡 =
50 𝑚𝑉 − (0.6𝐴 𝑥 0.03)
𝑪𝒐𝒖𝒕 = 𝟕𝟒. 𝟐𝟔 𝒖𝑭 − 𝒎𝒊𝒏𝒊𝒎𝒖𝒎

SELECTING THE INPUT CAPACITOR:

𝟑.𝟗𝟔𝒖𝒔𝒆𝒄
C = 𝟐𝟎𝟎𝒎𝑽
−𝟎.𝟏𝟐 𝒐𝒉𝒎𝒔
𝟏𝑨

C = 49.5 u F

But for the consult catalog 470uF electrolytic capacitors meets ESR and capacitance requirements.

We then used 470uF – 50 V input capacitor.

DIODE SELECTION:

Diode Current:

= (1-.15625) x 2 A

= 1.6875 A

WE basically select 1N5820 schottky diode since it meets the current requirements. (max rating : 3A)

WE selected a PMOS – IRF9530 as replacement for IRF9540

We used a PMOSFET – since it will simplify the design.

We can use an NMOS of PMOS-

The choice will depend on cost and complexity issues.

DESIGN OF THE CONTROLLER

 First design that was configured: To test the functionality of the ERROR AMP

This circuit is seen to be a linear voltage regulator. But as required, we basically need to make a PWM
control for the PMOS , thus acting as a switching voltage regulator.

The circuit gave us an initial concept on how an ERROR Amplifier works.

PREDESIGN STAGE:

DESIGN FOR THE RAMP GENERATOR:

The ramp generator’s component was simulated through multisim. It gave us desirable results (giving
an output of a ramp as portrayed on the virtual oscilloscope.

Combining the principles of the Error Amp and the triangle wave generator: we were able to combine
both inputs to a comparator that gives a PWM output.

Final circuit design:

Simulation results. – @ 2.5 Ohms

INPUT VOLTAGE OUTPUT

9 5.08 V
10 5.088 V
11 5.107 V
12 5.111 V
13 5.113 V
14 5.1 V
15 5.1 V
16 5.101 V
17 5.116 V
18 5.134 V
19 5.134 V
20 5.142 V
21 5.152 V
22 5.169 V
23 5.2 V
 24 5.233 V
25 5.353 V
26 5.36 V
27 5.338 V
28 5.342 V
29 5.534 V
30 5.542 v
31 5.587 V
32 5.598 V

VOLTAGE OUTPUT
5.7

5.6

5.5

5.4

5.3

5.2

5.1

5
0 5 10 15 20 25 30 35

Load current stayed at 2 Ampere. At varying Loads, the output current also varies.

Load Current @ 2.5 Ohms

2.023

2.034

2.045

2.047

2.043

2.037

2.042

2.043

2.044
2.048

2.052

2.059

2.057

2.064

2.065

2.071

2.082

2.103

2.13

2.117

2.119

2.124

2.161

2.182

2.261

PWM Output.

The circuit outputs a PWM, but there Is a noticeable change on its time of on and off.
 Triangle Wave Output

Efficiency Calculation:
𝑷𝒐𝒖𝒕
𝒙 𝟏𝟎𝟎
𝑷𝒊𝒏
@ 2.5 Ohms load

@ max 32 V = Idc = 625 mA

Pin = 32 x 625 mA =
𝟏𝟎. 𝟓 𝑾
𝒙 𝟏𝟎𝟎 = 𝟓𝟐. 𝟓 %
𝟐𝟎 𝑾

@ 5 Ohms Load

@ 32 V – Idc = 250 mA

𝟓. 𝟑𝟐 𝑾
𝒙 𝟏𝟎𝟎 = 𝟔𝟔. 𝟓 %
𝟎. 𝟐𝟓𝟎(𝟑𝟐)

@ 10 Ohms Load

@ 32 V - Idc = 150 mA
𝟐. 𝟕𝟖 𝑾
𝒙 𝟏𝟎𝟎 = 𝟓𝟕. 𝟗𝟐 %
𝟎. 𝟏𝟓𝟎(𝟑𝟐)