Pradyumna Hegade

RA1511004010352

Q1. Use IF statement to design positive edge triggered SR flip flop.

Main code: Testbench Code:

`timescale 1ns / 1ps [Grab your reader’s attention with a

great quote from the document or
module SRff_bh(S,R,clk,Q,Qb);
use this space to emphasize a key
input S,R,clk; point. To place this text box
output Q,Qb; anywhere on the page, just drag it.]

reg Q=0;
reg Qb=1;
always @(S or R or posedge(clk))
begin
if(clk==1)
begin
if(S==1&R==0)
begin
Q<=1; Qb<=0;
end
if (S==0&R==1)
begin
Q<=0; Q<=1;
end
end
end
endmodule

Output:

Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352

Q2. Use CASE statement to design negative edge triggered JK and T flip flop.

JK Flip Flop
Main code: Testbench Code:

module JKff_bh(Q,Q1,J,K,clk);
output Q,Q1;
input J,K,clk;
reg Q,Q1;
initial
begin
Q=1'b0; Q1=1'b1;
end
always @ (negedge clk)
begin
case({J,K})
{1'b0,1'b0}:begin Q=Q; Q1=Q1; end
{1'b0,1'b1}: begin Q=1'b0; Q1=1'b1; end
{1'b1,1'b0}:begin Q=1'b1; Q1=1'b0; end
{1'b1,1'b1}: begin Q=~Q; Q1=~Q1; end
endcase
end
endmodule

Output:

Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352

T Flip Flop
Main code: Testbench Code:

module Tff_bh(Q,Q1,T,clk);
output Q,Q1;
input T,clk;
reg Q,Q1;
initial
begin
Q=1'b0; Q1=1'b1;
end
always @ (negedge clk)
begin
case(T)
(1'b0):begin Q=Q; Q1=Q1; end
(1'b1):begin Q=~Q; Q1=~Q1; end
endcase
end
endmodule

Output:

Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352

Q3. Use T flip flop as a sub module to design 4-bit ripple counter.
4-bit Ripple Counter
Main code: Testbench Code:

`timescale 1ns / 1ps module RC_4bit_test;

// Inputs
module RC_4bit(Q,T,clk);
reg t;reg clk;
output [3:0]Q; // Outputswire [3:0] Q;
// Instantiate the Unit Under Test (UUT)
input T,clk; ripplecounter uut (.Q(Q), .T(T), .clk(clk));
wire w1,w2,w3; initial begin
// Initialize Inputs
Tff_bh g1(w1,T,clk); T = 1; clk = 0; #50;
T = 1;
Tff_bh g2(w2,T,w1); // Add stimulus here
Tff_bh g3(w3,T,w2); end
always begin
Tff_bh g4(Q[3],T,w3); #50 clk=~clk;
end
assign Q[0]=w1;
endmodule
assign Q[1]=w2;
assign Q[2]=w3;
endmodule

Output:

Q4. Use behavioral model to design Up-Down Counter. When Mode=1, do up counting for
Mode=0, do down counting.
Up-Down Counter
Main code: Testbench Code:

Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352

module UpDownCounter(Q,mode,clk); module UpDownCounter_test;

output reg [3:0] Q; // Inputs
input mode,clk; reg mode;reg clk;
initial Q=4'b 0000; // Outputs wire [3:0] Q;
always @(negedge clk) // Instantiate the Unit Under Test (UUT)
begin UpDownCounter uut
if(rst==1) (.Q(Q),.mode(mode), .clk(clk),);
Q=0; initial begin
else // Initialize Inputs
if(mode==1) mode = 0; clk = 0; #50;
Q=Q+1; mode = 0; #50;
else mode = 0; #50;
Q=Q-1; mode = 1; #50;
end mode = 1; #50;
endmodule mode = 1; #50;
end
always begin
#50 clk=~clk;
end
endmodule
Output:
Mode 0:

Mode 1:

Pradyumna Hegade
RA1511004010352