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Semiconductor Manufacturing in Austria

Topical Workshop on Electronics


for Particle Physics
Vienna, Sept. 26th, 2011

Rainer Minixhofer – Senior Manager R&D


austriamicrosystems AG
Outline

Introduction, Company Overview and some History

High Voltage Technology

More than Silicon

3D IC Integration

Conclusions
2 © 2010 austriamicrosystems
Company milestones
1981 Austria Mikro Systeme (AMS) founded as
joint venture by American Microsystems Inc. (AMI)
and Voest Alpine (Austria)
1993 AMS goes public on Vienna exchange
2000 AMS returns to private status
(major shareholder Permira Private Equity),
becomes austriamicrosystems
2002 New 200 mm (8”) fab goes on-line
2004 IPO on SIX Swiss Exchange in Zurich
2006 New test facility in Asia
2011 Acquisition of Texas Advanced Optoelectronic
Solutions (TAOS)
 A leader in high performance analog ICs:
1,100+ employees, 6 design centers,
19 offices worldwide

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Full supply chain under one roof

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Full Service Foundry

Full Service Foundry


Your one-stop-shop for turn-key high performance analog IC solutions

Specialty Processes Foundry Services More than Silicon ®

- 180nm, 350nm, 800nm - MPW service with cooperation partners - Custom processes
- CMOS, High-Voltage, SiGe, NVM - Benchmark design environment - 3D IC using TSVs
- Automotive and medical certified - Numerous digital & analog IP-cells - RGB & IR Color Coating
- Zero defect program - Standard package assembly service - Extended IP portfolio
- Extended temperature range - In-house mixed-signal test facility - Consultancy: ESD, DFM, DFY, …
- Second source capabilities - Qualification services - Adv. packages: WLCSP, Bumping, …

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austriamicrosystems at a glance

• Design and manufacture of high performance analog ICs


• Ultra-low power, high accuracy, high integration
• Power Management – Sensors & Sensor Interfaces – Mobile Infotainment
• Global customer base includes major OEMs
• Integrated manufacturer: world class design + best-in-class manufacturing

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Our business

Sensors &
Core expertise Power Management Mobile Infotainment
Sensor Interfaces

High performance analog ICs

CONSUMER &
INDUSTRY & MEDICAL AUTOMOTIVE
COMMUNICATIONS

Power management Sensors & sensor Sensors & sensor


interfaces interfaces
Lighting management
Target markets Bus systems
Mobile infotainment
Wireless

33% of revenues 2010 54% of revenues 2010 13% of revenues 2010

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Corporate responsibility
Total CO2 Emissions (tons eq)

• State-of-the-art abatement systems


57,500 - 54%
• Continuous energy saving and
Environment CO2 reduction measures
26,600

• Promoting FSC and MSC products


2005 2010

Strategic goal to become CO2 neutral as a company

Stakeholder • Participation in UN Global Compact for good business practices


Responsibility • Company Code of Conduct for stakeholder relations

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Worldwide network – design, sales, distribution

Headquarters & fab Design centers Sales offices


Distributor coverage Test center

• 6 design centers:
Distribution partnerships strengthened
Austria, Switzerland, 2x Italy, Spain, India
Global contracts
• 19 sales offices, over 30 distributors worldwide
with tier 1 players

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Austria – famous for

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austriamicrosystems
But Graz was home of famous scientists too

Johannes
Kepler Leopold
Gottlieb Ernst
Biwald Mach

Ludwig
Boltz-
mann Erwin
Schrödi
Viktor
nger
Franz
Hess

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Let‘s start with Ernst Mach

“Did you see an


atom personally?”
(Ernst Mach to his
physics students in
Vienna about 1900)

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Moore‘s Law
1958 (TI)
invention of IC

2011:

Tri-Gate(Intel 22nm):
10 Million Trans./mm²
1947 (Bell Labs) 1 Billion on 100mm².
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austriamicrosystems
Technology portfolio
800nm 350nm 180nm

CMOS • Mixed Signal CMOS


• High Perf. Analog

RF Technologies • RF CMOS

• BiCMOS (SiGe)

HV Technologies • HV CMOS

• Galvanic Isolation

Embedded NVM • Emb. EE / Flash

• OTP (Fuse)

3D integration • Through Silicon Via


• Backside RDL

Sensor • Hall
technologies • Opto

Rev. 3/2011 available in dev. intended


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High Voltage CMOS vs BCD Comparison
1000
NFETI120M
Rsp [mOhm*mm2]

PFET120M

PFET50T NFETI50M
100
NFET50MH
PFET25M NFETI25M
PFET20T

NFET20MH
10
-160 -120 -80 -40 0 40 80 120 160
BVdss [V]
0.18µm BCD (STM) 0.18µm BCD (Dongbu) 0.25µm BCD (TI) 0.25µm BCD (TSMC) 0.35µm HVCMOS (H35)
0.18µm HVCMOS (XFAB) 0.18µm HVCMOS (H18) one dimensional Silicon limit 0.18µm HVCMOS (TSMC)

Rdson vs. BVdss for HVCMOS (blue closed symbols) and BCD (white open symbols).
AMS 180nm HVCMOS shows largest BVdss range and very low Rdson
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Application Areas of Power Devices
1000 Served by monolithic power ICs

Motor Control
Power Converters/
100
Power Supplies
Current (A)

Lighting Ballast
Automotive
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Telecommunication
5V CMOS

350nm/180nm HVCMOS(e.g. SLIC)


20 V 120 V
50 V Systems is partioned into
control chip that drives a set
Display Electronics
of discrete power SC devices
 Hybrid integration
5 10 100 1000
Operating Voltage (V)
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Broad standard product portfolio
Power Mobile Entertainment Sensors & Sensor
Management Systems Audio
Interfaces
• PMUs • Mobile Entertainment • Audio • Magnetic Rotary
• Lighting Players Front-ends Encoder

• Supervisors & • High Performance • Amplifiers • Magnetic Linear


Comparators Microcontroller • Phones Position Encoder

• LDOs (Feature/Basic) • Automotive Rotary


Encoder
• DC-DC
Converters • Metering

Interfaces RF Products Data Converters


• Display and • High Frequency • A/D Converters
LED Drivers • Low Frequency • D/A Converters
• LVDS • Digital
• Industrial Bus Potentiometers
• FlexRay / • Analog Switches
Automotive • Data Acquisition
Bus Systems Front-ends

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Process modularity of 350nm technology
High flexibility through modularity:

Non-Volatile high sensitivity


SiGe BiCMOS High Voltage
Memory opto-process

hi- poly- &


caps: poly 5V LVT 3rd and
resistive Zener-
& MIM transistors transistors 4th metal
polysilicon fuses

350nm 3.3V analog/mixed signal polycide process

19 © 2010 austriamicrosystems
350nm vs. 180nm HV transistor comparison: 20V PMOS

AMS 350nm HVCMOS AMS/IBM 180nm HVCMOS

Additional 30% average HV area reduction by shrinking to 180nm

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Process modularity of 180nm technology
High flexibility through modularity:

Non-Volatile
High Voltage
Memory

up to 7 power hi-
metal- 5V OTP
layers of metal (Cu resistive
metal caps transistors (eFuse)
metal and/or Al) polysilicon

180nm 1.8V silicide process

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180nm CMOS-HV 20V & 50V
Full modularity with CMOS base process, low mask count
180nm CMOS + HVCMOS

Low-voltage CMOS

180nm HV = 180nm RFCMOS + 2 Mask Levels


(2 wells , no HV gate oxide)

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Gate Module of 180nm technology

52 nm

3.5 nm

12 nm

Only 180nm HV technology on the market with 3 gate oxides!

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Suite of FETs with three gate oxide thicknesses
– Low Voltage (LV) fets for standard 1.8 and 5V CMOS
– LV fets in HV well for high voltage isolation to substrate
– HV asymmetric fets for High Voltage applications
– 3 gate oxide thicknesses, 2 maximum drain bias choices
– HV symmetric fets for specialty applications (transmission gate)

LV fets LV fets in HV well HV asymmetric fets in HV HV symmetric fets


wells (nfet in Substrate)
Vds 1.8V 5.0V 1.8V 5.0V 20V** 50V 20V 50V
Vgs
1.8V nfet* nfeti* nfeti20t nfeti50t
(3.5nm) pfet* pfeti* pfet20t pfet50t
nfethvt nfetihvt
pfethvt pfetihvt
5.0V nfetm nfetim nfet20mh nfeti50m
(12nm) pfetm pfetim nfeti25m pfet50m
pfet25m
20V nfeti20h nfeti50h nfet20hs nfet50hs
(52nm) pfet20h pfet50h pfet20hs pfet50hs
* RF layout available ** 25V Vds for nfeti25m,pfeti25m

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Floating Logic
Substrate Logic – 350 and 180nm Floating Logic - only in HVCMOS

3.3V VDDF = GNDF+3.3V


• CORELIB (260 Cells) built up • CORELIB_HV has to be built with
with PMOS4 and NMOS4 PMOSI and NMOS4I
PMOSI
PMOS4 3.3V
• Bulk of NMOS always PSUB 0V • Bulk of NMOS 0V .. 46.7V
3.3V
• Bulk of PMOS maximum of 3.3V • PMOS maximum of GNDF+3.3V
NMOS4 (max. 50V) NMOSI

• Automatically generated form


GNDF
0V = PSUB CORELIB
0V … 46.7V
PSUB = 0V
PMOS4 NMOS4 PMOSI NMOSI

B S G D D G S B B S G D D G S B PSUB

DPTUB
NTUB

DNTUB
Net +2 additional alignments
PSUB

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CORELIB vs. CORELIB_HV Cell Layout
CORELIB Cell CORELIB_HV Cell
Same Cell Size

SNTUB DNTUB

NTUB

PSUB RPTUB = SPTUB + DPTUB

26 © 2010 austriamicrosystems
180nm HVCMOS metal stack options

AM Last Metal Option


# Levels 3 4 5 6 7
MT RF/analog
MT M5 AM add on
(4µm)
MT M4 M4 module
Standard
MT M3 M3 M3
Al wiring
MT M2 M2 M2 M2 MIM
Levels
M1 M1 M1 M1 M1 MT Standard
M3
M2
CMOS layers
K1 Res
M1

27 © 2010 austriamicrosystems
HV HSIM_HV Model to Hardware Results
Thin oxide NFET for 50V use Thin oxide PFET for 50V use
8,0E-03 6,0E-03

7,0E-03
5,0E-03

6,0E-03

4,0E-03
5,0E-03

-ID[A]
ID[A]

4,0E-03 3,0E-03

3,0E-03
2,0E-03
2,0E-03

1,0E-03
1,0E-03

0,0E+00 0,0E+00
10

20

25

30

45

50
0

15

35

40

10

15

20

25

30

35

40

45

50
VD[V] -VD[V]
ID(VG=0.45V) ID(VG=0.60V) ID(VG=0.75V) ID(VG=0.90V) ID(VG=1.05V) ID(VG=1.20V)
ID(VG=-0.45V) ID(VG=-0.60V) ID(VG=-0.75V) ID(VG=-0.90V) ID(VG=-1.05V) ID(VG=-1.20V)
ID(VG=1.35V) ID(VG=1.50V) ID(VG=1.65V ID(VG=1.80V)
ID(VG=-1.35V) ID(VG=-1.50V) ID(VG=-1.65V ID(VG=-1.80V)

Excellent agreement between measured results and HiSIM_HV SPICE model.


Model features include:
– Surface potential iterative calculation used for an accurate description of drift region
– Self-heating included
– Simulation speed and accuracy is improved compared BSIM (SPICE) + subcircuit.

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Layout for 50V ESD Protection

4kV ESD Cell 2kV ESD Cell

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More than Moore

International Technology Roadmap of Semiconductors, ITRS 2009


© 2010 austriamicrosystems
3D IC Integration
3D IC integration … stacking of semiconductor wafers or chips
using TSVs to provide electrical contact
between stacked layers

TSV … Through Silicon Via


3D TSV stack
electrical contact extending
through silicon

WLP … Wafer Level Package


UBM, bumping, test
IC packaging prior to wafer dicing

Form Factor reduction


Performance improvements
Reduced R, C
Reduced power consumption
Increased speed
Reduced signal losses (noise)
(Source: Yole Developpement, austriamicrosystems)

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More than Silicon: 3D-IC integration using Through Silicon Vias

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3D technology concept

Top wafer processed up to last metal layer (chip1)

Bottom wafer including bond oxide (chip2)

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3D technology concept

top wafer thinned to 250µm


Low temperature molecular wafer bonding
edge removal of top wafer

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3D technology concept

Final Bonded wafer stack

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3D technology concept

TSV and RDL Formation


Bumped wafer
Bump on pads - standard bump technology

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3D stacking by means of TSV, BRDL and µbumps 1/3

sensor chips with µbumps

Control and read out circuit with TSV and BRDL

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3D stacking by means of TSV, BRDL and µbumps 2/3

sensor chips

control and read out circuit with TSV and BRDL

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3D stacking by means of TSV, BRDL and µbumps 3/3

sensor chips

control and read out circuit

printed circuit board

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3D special integration tools

DRIE (STS PEGASUS)

Automated Wafer Bonder (EVG GEMINI®)

Scanning Acoustic Microscope (SONIX)


STS Pegasus SONIX CSAM
Resist Coating (EVG®150 NanoSpray)

EVG Gemini® EVG®150N


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TCAD environment set up

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Wafer surface

Key TSV reliability considerations TSV sidewall

Defect–related (extrinsic) problems


TSV base
Defect screening
Defect reduction
bottom top
2000

Intrinsic reliability
von Mises
1500

1000

vertical stress

Material set & construction


500

stress (MPa)
0
0.00 50.00 100.00 150.00 200.00 250.00
-500

Layer cracking/delamination -1000

-1500
tangential stress

e.g. TSV passivation integrity


-2000
depth (um)

42 Kraft IRPS/ESSDERC, Altman ISTFA, Cassidy ISTFA/IPFA/ESREF © 2010 austriamicrosystems


new developments: gas sensors using 3D integration

43 Teva Nanosense 2010 © 2010 austriamicrosystems


3D Integrated Photodiode Array
Detection and processing of visible light intensity in CT-Scanners

270um
64 pixel Photodiode

Green Transmitted x-rays


photons from patient
Analog-Digital Converter)
CMOS chip (64 channel

TSV
NMOS PMOS
Scintillator
PCB
p+ Photodiode

44 © 2010 austriamicrosystems
Summary and Conclusions

 austriamicrosystems offers a rich portfolio of technologies tailored to high


performance analog applications

 The high voltage technologies on the 350nm and 180nm node are ideally suited
for SoC applications

 The new 3D IC integration platform(s) provide completely new ways of sensor


and multiple chip solutions.

 We offer a long experience of High-Voltage CMOS/high performance analog


process development and design to our customers.

45 © 2010 austriamicrosystems
Some famous last words....

46 © 2010 austriamicrosystems
Benefits
Acknowledgements:

Cathal Cassidy
Heimo Gensinger
Ingrid Jonak
Martin Knaipp
Günter Koppitsch
Jochen Kraft Thank you for your attention!
Franz Schrank
Jörg Siegert
Jordi Teva
Ewald Wachmann

and to FELMI-ZFE
for the excellent co-
operation

47 © 2010 austriamicrosystems

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