A

45 Days Training
on

VLSI & Embedded System

(February 01 – March 15, 2018)

Delivered By:

Aditya Kumar Singh Pundir

LMISTE, MIEEE, MACM, LMCSI India
Contact: +91-9784637603/ 8209333973
Email: aditya.pundir@ieee.org/ aditya.pundir@acm.org
 Agenda
• Importance of VLSI & Embedded Systems
• Objective of the Training
• Contents to be covered
 Importance of VLSI & Embedded
Systems
• Difference between VLSI and Embedded System.
• The importance of VLSI & Embedded systems is growing
continuously
– hardware/software systems being embedded within everyday
products and places
• Today 90% of computing devices are in Embedded Systems
and not in PCs.
• Today 20% of the value of each car is attributed to VLSI
chips, SOCs and embedded electronics and this will increase
to an average of 35-50% by 2020
• The growth rate in embedded systems is more than 10% per
annum
– it is forecasted there will be over 40 billion devices (5 to 10
embedded devices per person on earth) worldwide by 2020.
List of Companies deals in VLSI & Embedded Area
 Objective
• To impart practical knowledge with the aim to
bridge the gap between theoretical and practical
world
• To provide platform and skills that could help
students
– to shape ideas which could lead to implementation of
innovative problem solving designs
• To motivate students to design VLSI and
embedded system based solutions .
• To work on the different simulation tools and
hardware platforms.
 Content Covered
Content Hrs.
Section I: VLSI Semi Custom Design
Introduction to VLSI Design and HDL languages 25
Various Simulator Software /Tools 20
VHDL Programming and Interfacing with
ALTERA CPLD, FPGA Kits: SPARTAN 3, CYCLONE 5
UP3 Kit
Section II: VLSI Full Custom Design
VLSI layout design and pre-layout and post
20
layout Simulation
 Content Covered
Content Hrs.
Section III: Embedded System Design
Introduction to Microcontrollers (AT89C51/52) 10
Live practical demonstration on ATMEL
5
89C51/ATMEGA 16 Universal Kit
Section IV: PCB Design
Introduction to PCB Design
5
PCB design
Total Hrs. 90
 References
• Books:
– Stephen Brown, Zvonko Vranesic, “Fundamentals of
Digital Logic with VHDL Design”, McGraw-Hill
Education; 3 edition, 16 April 2008.
– Jayaram Bhasker, “A VHDL primer”, PHI Learning, 3rd
Edition, 2009.
– Douglas L. Perry, “VHDL : Programming By Example”,
McGraw-Hill Education; 4 edition, June 2, 2002.
– James O. Hamblen, Tyson S. Hall, Michael D. Furman,
“Rapid prototyping of digital systems, Quartus II ed.”,
Springer Science+Busincss Media, Inc.,2006
 References
• Books:
– Muhammad Ali Mazidi, “The 8051 Microcontroller and
Embedded Systems: Using Assembly and C”, Pearson
Education India; 2 edition, 2007.
– Kai Qian, David Den Haring, Li Cao, “Embedded
Software Development with C”, PHI Learning, 3rd
Edition, 2009.
– Douglas A. Pucknell, “Basic VLSI Design”, Prentice Hall, ,
3rd Edition, 1995.
Section I: VLSI Semi Custom Design
Simulation and Synthesis Tools
• Xilinx Project Nevigator 9.2i
o Project Navigator organizes your design files
and runs processes to move the design from
design entry through implementation to
programming the targeted Xilinx® device.
• Modelsim 10
o Mentor Graphics was the first to combine
single kernel simulator (SKS) technology with a
unified debug environment for Verilog, VHDL,
and SystemC.
o ModelSim® the simulator of choice for both
ASIC and FPGA designs.
Simulation and Synthesis Tools
• Quartus 7.1
o Altera Quartus II is programmable logic device
design software produced by Altera.
o Quartus II enables analysis and synthesis of
HDL designs.
 FPGA Platform used
• Falcon SPARTAN III FPGA Trainer Kit XC3S400
PQ208-5
BASIC FUNCTION
FPGA Spartan-3 XC3S400 in PQ208 pin package
Serial Interface One RS232 channel using MAX3223
- LCD Interface ( optional )
Free I/Os 66
Clock Oscillator 4 Mhz ( Compatible upto 40MHz )
Configuration through JTAG Port, Flash PROM ( Optional )

USER INTERFACE
16 Digital Output LEDs
4 X 4 Matrix Keyboard
Four 7 Segment Display
16 Input switches
 FPGA Platform used
• Altera Cyclone University Program (UP3)
EP1C6Q240 Kit
 FPGA Platform used
• Altera MAX II CPLD ELT II board
• Powerful Development Board for FPGA designs
o Based on MAX II CPLD EPM240T100Cx
o Migration support from EPM240T100Cx to
EPM570T100Cx devices for higher density to
implement larger designs
• User Interfaces
o 4-Digit scanning 7-segment LED Display Interface
o 8x2 On-Off Push Button switches, shared with I/O
headers giving flexibility of additional 16 general
purpose (+5V tolerant) I/Os
o 4x4 Push Button Switch Matrix and 8 LEDs, shared and
configurable through 4 jumper selection options to
use them in any of the possible available combinations
• JTAG Configuration and debugging
o 41 General Purpose (+5V tolerant) I/Os, available on
the Altera standard Santa Cruz short expansion
connector
• On Board Global System Reset Circuitry
• On-board JTAG circuitry to configure MAX II
Design process for schematic or HDL entry in Quartus
Section II: VLSI Full Custom Design
 Introduction to VLSI Layout
Design
• VLSI Design - Full Custom
– Design Flow
– Design Methodology (Gaski-Y Chart & Types)
– Applications (Types of ICs, Layout styles and art work)
– Different types of CAD tools for front & back end
design like MAGIC and LASI
 Layout Design Tools used
• Microwind
– The DSCH (Digital Simulator and Schematic Editor)
– Microwind Layout tool
• Tanner tool
– Tspice (Simulation Program with Integrated Circuit
Emphasis)
– SEDIT
– LEDIT
– WEDIT
– LVS
Layout Design Tools used
Section III: Embedded System
Design
 IDE and ISP
• Hands-on-practice on various software & IDE
Keil C
EDSIM
Proteous
• Live project demonstration using ATMEL ISP
programmer
– A development platform that is used to develop
applications using Atmel 89C51/52 microcontroller
– Project building using Keil
 8051 & AVR DEVELOPMENT
BOARD WITH PROGRAMMER
• No external
Programmer required .
• On board Programmer
• 7 segment Display array
• LEDs to see result
• 4 x 4 matrix keypad
• Motor drive ULN2003
• EPROM
• I2C chips
• RS232
• Project building using
Keil
Section IV: PCB Design
 PCB Design
• PCB Design using Express PCB/ Ultiboard
• Mask Transfer on Copper Clad Laminate
• Etching
• Cleaning
• Drilling
• Component Mounting
• Testing
Why FPGAs
ASICs
 Degree of Integration
Name Signification Year Transistors number Logic gates
number
SSI Small-scale 1964 1 to 10 1 to 12
Integration
MSI Medium-scale 1968 10 to 500 13 to 99
Integration
LSI Large-scale 1971 500 to 20 000 100 to 9999
Integration
VLSI Very Large-scale 1980 20 000 to 1 000 10 000 to 99
Integration 000 999
ULSI Ultra-large-scale 1984 1 000 000 and 100 000 and
Integration more more
 Programmable ASICs
• PLDs - PLDs are low-density devices which
contain 1k – 10 k gates and are available both in
bipolar and CMOS technologies [PLA, PAL or GAL]
• CPLDs or FPLDs or FPGAs - FPGAs combine
architecture of gate arrays with programmability
of PLDs.
• User Configurable
• Contain Regular Structures - circuit elements such
as AND, OR, NAND/NOR gates, FFs, Mux, RAMs.
• Allow Different Programming Technologies
• Allow both Matrix and Row-based Architectures
 Why PLDs
Standard Chips

An implementation of f = x1x2 + x2’x3.

PLDs
Programmable Transistor Switches
Programmable Transistor Switches
Programmable Transistor Switches
PLDs
PLAs
PLAs
PALs
Macro Cells
In System Programming & Package
CPLDs
CPLDs Programming and Package
FPGA and its Packages
Why FPGA-based ASIC Design?
 Choice is based on Many Factors Requirement FPGA/FPLD Discrete Logic Custom Logic

 Speed Speed

 Gate Density
Gate Density

Cost

 Development Time
Development Time

 Prototyping and Simulation

Prototyping and Sim.
Time
Manufacturing

 Manufacturing Lead Time

Future Modification

 Future Modifications Inventory

 Inventory Risk Development Tools

 Cost
Very Effective Adequate Poor
Different Categorizations of FPGAs
 Based on Functional Unit/Logic
Cell Structure
 Transistor Pairs
 Basic Logic Gates: NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
 Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
 Gate Density
 Chip Architecture (Routing Style)
Different Types of Logic Cells –
Cont’d
To SUMMARIZE, FPGAs from various vendors differ in their
 Architecture (Row Based or Matrix Based Routing Mechanism)
 Gate Density (Cap. In Equiv. 2- Input NAND Gates)
 Basic Cell Structure
 Programming Technology
Vendor/ Product Architechture Capacity Basic Cell Programming Technology
Actel Gate Array 2-8 k MUX Antifuse
QuickLogic Matrix 1.2-1.8 k MUX Antifuse
Xilinx Matrix 2-10 k RAM Block SRAM
Altera Extended PLA 1- 5 k PLA EPROM
Concurrent Matrix 3-5 k XOR, AND SRAM
Plessy SOG 2-40 k NAND SRAM
Programming Technologies
 Three Programming Technologies
The Antifuse Technology
Static RAM Technology
EPROM and EEPROM Technology
THANK YOU