1064 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO.
3, SEPTEMBER 2016
Performance Comparison Study of Space-Vector
and Modified-Carrier-Based PWM Techniques
for a Three-Level Neutral-Point-Clamped
Traction Inverter Drive
Abhijit Choudhury, Member, IEEE, Pragasen Pillay, Fellow, IEEE,
and Sheldon S. Williamson, Senior Member, IEEE
Abstract— A performance comparison study between lower
switching loss-based space-vector pulsewidth modulation (PWM)
strategy for a three-level neutral-point-clamped inverter and a
proposed modified-carrier-based PWM strategy is carried out for
an electric vehicle propulsion application. The proposed carrier-
based strategy uses single carrier and reduces the switching
losses compared with the conventional carrier-based strategies
by eliminating the common modulation interval between the
upper and lower modulating signals. The inverter switching
and conduction losses, total inverter loss, and voltage and
current harmonic distortions are also compared with both the
control strategies. PLECS is used to simulate the inverter losses
with a 54-kW surface permanent magnet synchronous
machine (SPMSM). Detailed simulation and experimental
performances with the proposed carrier-based strategy and
the dc-link voltage balancing during the change in speed and
torque variations are carried out on a scaled-down prototype
of 6-kW SPMSM. Dspace is used for hardware verification.
Results show that, with the proposed carrier-based strategy, the
dc-link capacitors are balanced even during the change in speed
and torque.
Index Terms— Electric propulsion, motor drives, permanent
magnet motors, traction, transportation, vehicles.
I. I NTRODUCTION
M ULTILEVEL inverters have been widely employed
in medium- and low-power applications. The basic
topology was introduced in 1981 [2], after which multilevel
inverters were consistently considered for high-power appli-
cations. More recently, electric vehicles (EVs) and plug-in
Manuscript received July 28, 2015; revised December 15, 2015; accepted
February 12, 2016. Date of publication February 29, 2016; date of current
version July 29, 2016. This work was supported by the Natural Sciences
and Engineering Research Council (NSERC), Canada, within the Research
and Development Program through the Hydro-Québec Research Chair Project
entitled Design and Performance of Special Electrical Machines, Concordia
University. Recommended for publication by Associate Editor Juan C. Balda.
A. Choudhury was with the Department of Electrical and Computer
Engineering, Concordia University, Montreal, QC H4B 1R6, Canada.
He is now with the Experimental Power Grid Centre, Singapore (e-mail:
ab_ch@encs.concordia.ca).
P. Pillay is with the Department of Electrical and Computer Engineering,
Concordia University, Montreal, QC H4B 1R6, Canada, and also with
the University of Cape Town, Cape Town 7700, South Africa (e-mail:
pillay@encs.concordia.ca).
S. S. Williamson is with the Department of Electrical, Computer and
Software Engineering, University of Ontario Institute of Technology, Oshawa,
ON L1H 7K4, Canada (e-mail: sheldon.williamson@uoit.ca).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2016.2535406
2168-6777 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
hybrid EVs have become a sturdy driving option, to replace
internal combustion engine vehicles. This is because of the
unpredictable oil prices and stringent emission norms set up
by governments worldwide. As is well known, the main source
of energy in the EVs is the battery pack, which in turn propels
a traction system, comprised of a dc/ac inverter and a three-
phase ac motor. Most of the inverters used for EV applications
are of the standard, two-level/six-switch variety. The main
problem with this inverter topology is the larger amount of
switching losses that occur at higher switching frequencies.
However, to reduce the size of passive components (in order
to increase inverter power density), it is necessary to increase
the switching frequency of the converter itself. To overcome
this problem, a three-level neutral-point-clamped (NPC)
dc/ac inverter can be a possible solution moving for-
ward, especially for high-voltage EV traction applications.
Various modulation schemes have been developed for
three-level inverters, with neutral point voltage balancing
schemes. They can be mainly classified into two categories,
namely, space-vector pulsewidth modulation (SV-PWM) and
carrier-based PWM (CB-PWM). Among these options, the
CB-PWM is the simplest one to implement. It directly gen-
erates the duty cycles for the switches from the reference
voltage vector, instead of the sector identification and extensive
numeric calculations of the switching period, as in the case
for SV-PWM-based strategies. Moreover, this reduces the total
computation time of the controller, which in turn allows the
system switching frequency to increase.
A fast space-vector modulation scheme is proposed in [3].
Although some simulation studies are shown to validate the
proposed strategy, no experimental results with the proposed
control strategy or dc-link capacitor voltage balancing are
demonstrated. In [4], a space-vector-based strategy with cur-
rent direction is shown, which shares the duties of the redun-
dant voltage vectors [5]. However, if the duties are not selected
properly, it could unbalance the system. Moreover, no experi-
mental or simulation studies are shown to verify the results in
transients, such as in the change of speed–torque. An analytical
closed-form solution for total harmonic distortion (%THD) for
three-level inverter with centered SV-PWM and eight different
bus clamping PWM strategies are proposed in [6]. Results are
then validated by experimental studies.
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES
An SV-PWM strategy for three-level inverter is proposed
in [7]. As the NPC inverter distributes the power losses
asymmetrically in the different power switches, the proposed
strategy tried to distribute the power losses equally to different
power switches. However, loss distribution with the change in
modulation index is not shown, and the dc-link voltage bal-
ancing is also not considered. In [8], two three-level inverters
are used in back to back to reduce the low-order frequency
oscillations from the neutral point. Although, results show
reduction in low-frequency oscillations, however, it increases
the system space requirement. Conventional nearest-three-
vector (NTV) scheme [9] has different switching sequences
at different subsectors, which makes the switching asym-
metrical at different subsectors. To overcome this problem,
a symmetrical switching sequence strategy is proposed, where
the subsectors 1–2 were further divided into another two
subsectors. It makes the switching frequency constant at each
subsector; however, it increases the number of subsectors
to six. It also increases the low-frequency oscillation to some
extent. In [10], a carrier-based dc-link voltage balancing
strategy is proposed, where the difference between the two
capacitor voltages is passed through a proportional constant
block, and the output from this block is added with the
reference modulation signal. However, no transient simulation
studies during the change in load torque are shown, and
even the effect of the proposed control strategy on the phase
voltage or current harmonics are not demonstrated. In [11],
a hybrid PWM strategy is proposed, which uses both the
NTV and virtual space-vector strategy alternatively in each
switching cycle. The virtual space vector helps to keep the
neutral point fluctuation low at all power factor conditions,
and NTV can keep the harmonic distortion low. However, the
proposed strategy suffers from the fundamental problem of
virtual space vector, which is increased switching losses.
To overcome these problems with previously proposed
strategies, a new lower switching loss-based SV-PWM strategy
is proposed in [12] for three-level NPC inverter with
dc-link voltage balancing. This strategy uses reduced numbers
of vector in each switching cycle to reduce the inverter losses.
Moreover, it keeps the dc-link capacitor voltages balanced
even at speed–torque variations.
A carrier-based strategy with offset addition is proposed
in [13] and [14]. Simulation and experimental results are
shown to validate the strategy. Results showed required
steady-state stability; however, no transient performances are
demonstrated. In [15]–[17], a modified-carrier signal is pro-
posed based on the min–max control. It divides the main
carrier signal into two parts for upper and lower carrier signals.
It also proposed an analytical calculation of the duty ratio that
is required to add with the main modulating signal to keep
the dc-link capacitors balanced. However, it has a common
problem with the calculation of the proper dc-offset value.
If this generated dc-offset goes out of limit, it could unbalance
the capacitors.
A performance comparison study between the SV-PWM and
carrier-based strategies for a three- and six-phase machine
is shown in [18] and [19]. In these research works, differ-
ent types of available SV-PWM and carrier-based strategies
1065
Fig. 1. Three-level NPC inverter.
are compared with their total voltage harmonic distortion.
However, the effects of these control strategies on inverter
loss distribution (switching and conduction) in different power
switches, torque ripple, and capacitor voltage deviation, with
the change in switching frequencies are not considered.
Hence, to keep the advantages of both the carrier- and
space-vector-based strategies, a hybrid PWM technique is
proposed in [21]. In this strategy, duty cycles are generated by
the carrier-based strategy to reduce the computational time and
complexity of the system, and space-vector-based strategy is
used to keep the neutral point potential fluctuation low. Results
are then compared with the SV-PWM-based strategy. However,
the performance of the system with the proposed carrier-based
strategy was not demonstrated. A dc-link voltage balancing
strategy for leading power factor operation is shown in [22].
In this paper, a detailed performance analysis of the
single-carrier-based modulation strategy is carried out. Both
simulation and experimental studies are conducted to
demonstrate the performance of the proposed dc-link voltage
balancing strategy. Results are then compared with the
SV-PWM-based strategy [12]. Analytical derivation of both
the conduction and switching losses is carried out, and the
results are then compared with the simulation studies based
on PLECS-based simulation tool. Experimental validation of
the total inverter loss is also performed, and the results are
quite similar to the simulation studies.
II. P RINCIPLE OF O PERATION
A. Three-Level Neutral-Point-Clamped Inverter
Fig. 1 shows a three-level NPC inverter, used for EV traction
applications [12]. The inverter has four switches in each leg.
The topology includes two diodes in each leg, whose neutral
points are connected to the common connection point of
the two dc-link capacitors. Hence, a total of 27 switching
combinations are possible, out of which three are null or zero
vectors, and 24 are active vectors, as shown in [12].
B. Space-Vector PWM for the Three-Level Inverter
The control circuit diagram of the proposed SV-PWM
scheme with the dc-link capacitor voltage balancing strategy
is shown in [12]. Table I shows the switching sequence of the
1066 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016
TABLE I
DC-L INK V OLTAGE BALANCING A LGORITHM
proposed control strategy. In this strategy, only five switching
combinations are used instead of seven, generally being used
in other control techniques to reduce the switching losses.
The difference between the two capacitor voltages is passed
through a control logic block, which gives the command signal
for the SV-PWM. The command signal changes its state only
at the starting of each switching cycle to reduce the possibility
of asymmetrical switching. Based on the output from the logic
control block, the redundant voltage vectors are used to keep
the two capacitor voltages stable.
Compared with the earlier proposed strategy [24], one
switching sequence in sector one and subsector two is changed.
In the earlier published work, the switching sequence was
POO–PPO–PON–PPO–POO, where there was a direct tran-
sition of two vectors from PPO to PON. It will increase the
switching losses a bit high. To reduce this loss, the sequence
is now changed to PON–POO–PPO–POO–PON, where all
the vectors changed only by one state. Similarly, other sector
sequences can also be modified.
C. Carrier-Based PWM Technique
In this section, the different available carrier-based strate-
gies will be discussed, and the modified-single-carrier-based
strategy will be introduced.
1) Sinusoidal PWM With Triangular Signal Injection:
In this scheme, a common triangular signal is added to the
three reference phase voltages generated from the control loop,
as shown in [16]. It is also known as min–max control strategy.
This control strategy helps the modulation index to increase
to 1.15, compared with the typical sinusoidal PWM (SPWM)-
based schemes. Hence, there exists an additional 15% increase
in the modulation index.
Equation (1) shows the three reference voltage
vectors (Va,b,c_ min _ max ) generated from the three-phase
voltages (v abc ) using min–max control strategy. Zero-
sequence voltage (v z ) is generated from the minimum and
Fig. 2. Modulation and carrier signals for (a) min–max control and
(b) DS-PWM.
maximum values of the phase voltages
υa_min_max = υa − υz
υb_min_max = υb − υz
υc_min_max = υc − υz
min(υa , υb , υc ) + max(υa , υb , υc )
Here, υz = . (1)
2
Fig. 2(a) shows the simulated wave shape for SPWM with
min–max control. As shown, to implement this scheme for the
three-level inverter, two separate carrier signals are required,
which have to be in phase.
2) Double-Signal PWM: Double-signal PWM (DS-PWM)
is also referred to as fast-processing modulation [15]. This
scheme adopts two modulation signals: one positive and one
negative, as shown in Fig. 2(b). Equation (2) shows the two
duty cycles that are generated for the upper two switches of
each inverter phases
υi − min(υa , υb , υc )
υip =
2
υi − max(υa , υb , υc )
υin = . (2)
2
In order to calculate v ip and v in signals, a condition on the
neutral point current, i np , has to be imposed. Instantaneous
neutral point current, i np (t), can in fact be expressed, as
shown in
i np (t) = sao (t) · i a (t) + sbo (t) · i b (t) + sco (t) · i c (t). (3)
In order to preserve the dc-bus voltage balance, the locally
averaged neutral point current within a modulation period must
be zero. Thus
i np (t) = δao · i a + δbo · i b + δco · i c (4)
where δio = Sio is the duty cycle of the zero voltage conditions
for each NPC phase.
DS-PWM is equivalent to the previously presented
min–max-based SPWM as far as the maximum voltage range
for linear operation mode is considered. It also helps to
eliminate the low-frequency harmonic oscillations from the
neutral point, which helps to reduce the dc-link capacitor size.
However, it increases the number of switching of the inverter
to 33% more as compared with the typical SPWM scheme.
3) Single-Carrier-Based PWM Control Strategy: To over-
come the computational problem with the two carrier-based
strategies, a novel, modified-control strategy is proposed
in [20] and shown in Fig. 3(a). The proposed scheme is
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES 1067

Fig. 5. Duty cycle and phase current for the three-level inverter phase A.

Fig. 3. Modulation and carrier signals for (a) single-CB-PWM and δap = υa_ref , When, υa_ref > 0
(b) proposed control strategies.
= 0, When, υa_ref <= 0
δan = υa_ref + 1, When, υa_ref < 0
= 1, When, υa_ref >= 0. (8)
The three-phase modulating signals (v a,b,c_m ) are then
generated using the previously generated phase voltages from
the vector control block, as shown in (6). The dc-offset
voltage (v o ) is then subtracted from the each phase
modulating signals to generate the three-phase reference
voltages (v a,b,c_ref ) for the inverter switches in (7). The neg-
ative modulation signal is then shifted to the positive side,
as shown in (8), to compare it with a single-carrier signal, in
order to generate the suitable gate pulses for the dc/ac inverter.
Fig. 4. Three-level inverter with a single-CB-PWM control strategy model.
The reference voltage vectors generated in this case will look
similar to Fig. 3(b), with dc-offset voltage (v o ) added with it,
practically an extension of the DS-PWM scheme. As is clear which is not shown.
from (5), the negative modulating signal of v in is just shifted Similarly, reference voltages for the other two phases are
up by adding it with unity. Hence, this scheme gets rid of the also generated. δa,b,c_p and δa,b,c_n are the duties for upper
additional carrier signal. However, this scheme has a common and lower leg switches. Here, it can be observed that there
modulation signal between the positive and negative parts, is no common switching between the upper and lower duties,
as shown in Fig. 3(a). This introduces additional switching as shown in Fig. 3(b). The changes in dc-offset voltage (v o )
losses depend on the two capacitor voltage unbalances. When the
υi − min(υa , υb , υc ) upper capacitor voltage is higher than the lower capacitor
υip = voltage, a positive v o will be added with the three-phase
2
υi − max(υa , υb , υc ) modulation signal, and when the lower capacitor voltage is
υin = + 1. (5) higher than the higher capacitor voltage, a negative v o will
2
be added with the reference modulation signals. This addition
and subtraction of the dc-offset voltage will redistribute the
III. P ROPOSED M ODIFIED -C ARRIER -BASED T HIRD redundant voltage vectors to keep the neutral point potential
HARMONIC P ULSE WIDTH MODULATION (THPWM) fluctuation minimum. The effects of the different redundant
W ITH DC-L INK VOLTAGE BALANCING (small), medium, and large voltage vectors on the dc-link
The proposed control circuit with min–max PWM and capacitor voltages are already studied in [12]. The cutoff
single-carrier-based dc-link capacitor voltage balancing for frequency of the low-pass filter used was kept at 180 Hz, to
a three-level inverter driven permanent magnet synchronous allow both the dc-drift and the third harmonic component of
machine (PMSM) is shown in Fig. 4. The three-phase currents the fundamental frequency for the capacitors difference in to
and the machine speed are taken into the vector control block, the generated dc offset. As permanent magnet machine always
which generates the three reference phase voltages (v abc ). The works below 30° of the load power factor angle, the control
difference between the two capacitor voltages is then passed strategy is not tested with other power factors [23]. The PMSM
through a Proportional integral (PI) controller, to generate the is loaded with a separately exited dc generator, which works
dc-offset voltage (v o ) for the control circuit as a dynamometer. The output from the dc dynamometer is
connected to a resistive load bank, to load the machine at
υam = υa_ min _ max /(0.5 · υdc )
different speed and torque conditions.
υbm = υb_ min _ max /(0.5 · υdc )
IV. A NALYTICAL S WITCHING L OSS
υcm = υc_ min _ max /(0.5 · υdc ) (6)
C ALCULATION M ODEL
υa_ref = υam − υo
Fig. 5 shows the duty cycles for four power switches and
υb_ref = υbm − υo phase A current for three-level inverter. Instead of one modula-
υc_ref = υcm − υo (7) tion signal for two-level inverter, it has two modulating signals.
1068 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016

saturation voltage (v ce ) at a particular load current and

the load current (i ) itself, as shown in (9). The average
conduction loss (Pc_avg ) for one fundamental power cycle can
be represented by

PC (t) = v ce (t) · i (t) (9)

   π+ϕ
1
pc_avg = (M · v ce · i )dα. (10)
2π ϕ

The conduction losses for IGBT switches (IGBTSs),

T A1 , T A2 , T A3 , T A4 , D f A1 , and D f A2 , can be expressed as
follows:
  π
VceT
pc_avg_T A_1 = (m · sin (α) · i )dα
2π ϕ
 
VceT · Im · m
pc_avg_T A_1 = · {(π − ϕ) · cos(ϕ)+ sin(ϕ)}
4π
(11)
   π 
VceT (i · 1)dα
pc_avg_T A_2 =  π+ϕ
2π ϕ + π (i · (1 + m · sin(α)))dα
  
VceT · Im VceT · Im · m
Fig. 6. Current direction for three-level inverter for all four regions. pc_avg_T A_2 = +
π 4π

δap is for T A1 , and δan is for T A2 . T A3 and T A4 are complement × (ϕ · cos(α) −sin(α)) (12)
to T A1 and T A2 . Fig. 5 can be divided into four regions.   2π 
In region A, δan is clamped to one, so T A2 will always VceT (i · 1)dα
pc_avg_T A_3 = − ϕ
be ON. Hence, when T A1 will be turned ON, current will flow 2π ϕ+π+ 0 (i · (1− m · sin(α)))dα
according to state I in Fig. 6, through the antiparallel diodes   
VceT · Im VceT · Im · m
D A1 and D A2 , and when T A1 is OFF (T A3 is turned ON), current pc_avg_T A_3 = V+
π 4π
will flow according to state II, through T A3 and D f A2 . 
In region B, duties are similar to region A; however, current × (ϕ · cos(α) − sin(α))
is positive. Hence, when switch T A1 is turned ON, current flows
through T A1 and T A2 , as shown in state III, and when T A1 is (13)
  2π
turned OFF, current flows through D f A1 and T A2 , as shown VceT
in state IV. pc_avg_T A_4 =− (i · (1 − (1+ m · sin (α))))dα
2π ϕ+π
In state C, δap goes down to zero, which makes T A1 to  
switch OFF all the time, and T A2 starts switching. As current VceT · Im · m
pc_avg_T A_4 = · {(π − ϕ) · cos(ϕ)+ sin(ϕ)}
is positive, when T A2 is turned ON, current flows through 4π
D f A1 and T A2 , as shown in state IV, and when it is OFF, (14)
  π 
current flows through the antiparallel diodes D A3 and D A4 , as VceT (i · (1 − m · sin(α)))dα
pc_avg_D f A_1 =  π+ϕ
shown in state V. 2π ϕ + π (i · (1+ m · sin(α)))dα
Like region C, in region D, duties remain the same, but  
VceT · Im · m
current polarity has gone negative. Hence, when T A2 is ON, pc_avg_D f A_1 =
current flows through T A3 and D f A2 , as shown in state II, and 4π
when T A2 is turned OFF, current flows through T A3 and T A4 , · {4 + m · ((2ϕ − π) · cos(ϕ) − 2 sin(ϕ))}
as shown in state VI. (15)
Compared with the two-level inverter, in three-level inverter,   π
VceT (i · (1 − m · sin(α)))dα
the conduction time for the antiparallel diodes reduces dras- pc_avg_D f A_2 =−  2π
tically. This is basically due to the power shared by the 2π ϕ + π+ϕ (i · (1+m · sin(α)))dα
 
NPC diodes, which starts conducting whenever the power VceT · Im · m
switches are turned OFF. pc_avg_D f A_2 =
4π
· {4+ m · ((2ϕ − π) · cos(ϕ) − 2 sin(ϕ))}.
A. Conduction Loss Calculation (16)
For three-level inverter loss calculation, Infineon
F3L300R07PE4, 600 V NPC modules are used. Conduction In all these equations, the values of m are directly obtained
loss (Pc ) in power switches and diodes is the product of from Fig. 5. Similarly, the antiparallel diode conduction losses
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES 1069

generally provided by the device manufacturer. However, for

diodes, there are only reverse recovery losses (Err ) that are
present during turn OFF. Hence, average switching loss can be
represented by (21) and (22). Here, Vce is the rated voltage
across the power switches, Vnom is the nominal voltage where
the power switching losses are specified in the data sheet, and
f sw is the switching frequency
  π+ϕ    
1 Vce
psw_avg_IGBT = (E on + E off ) · · f sw dα
2π ϕ Vnom
(19)
   π+ϕ    
1 Vce
psw_avg_diode = Err · · f sw dα. (20)
2π ϕ Vnom
The quadratic interpolation for the IGBT, the antiparallel
diodes, and the NPC diode switching losses calculated from
the device data sheet is shown below
Fig. 7. Conduction loss distribution for IGBTSs (a) T A1 and T A4 E IGBT = −1 · e−8 · i 2 + 6 · e−5 · i + 31 · e−4 (21)
(b) T A2 and T A3 , (c) NPC diodes D f A1 and D Fa2 , and (d) antiparallel
−8 2 −5 −4
diode with the change in modulation index and power factor. E diode = −3 · e ·i +3·e · i + 11 · e . (22)

can also be obtained as follows: Here, it can be noted that the losses for the antiparallel
  ϕ diodes and the NPC diodes are similar, which is shown in (20).
VceD
pc_avg_D A_1 / pc_avg_D A_2 = − (i · m · sin(α))dα The switching losses for all the switches are shown below.
2π 0
  Here, Im is the peak load current, i is the instantaneous current,
VceD · Im · m and ϕ is the power factor angle
pc_avg_D A_1 / pc_avg_D A_2 =
4π
· {sin(ϕ) − ϕ · cos(ϕ)} (17) psw_avg_T A_1
   π+ϕ     π
VceD Vce 1
pc_avg_D A_3 / pc_avg_D A_4 = = · f sw · (E IGBT )dα
2π π
Vnom 2π ϕ
· (i · (1 − (1 + m · sin(α)))) dα psw_avg_T A_1
  1
2
VceD · Im · m = I · (5e−9 ϕ − 1.57e−8 − 25e−10 · sin(2ϕ)) + 6e−5
pc_avg_D A_3 / pc_avg_D A_4 = 2π m
4π 
· {sin(ϕ) − ϕ · cos(ϕ)}. (18) · Im (1 + cos(ϕ)) − 31e−4 · ϕ + 0.00973
 
Fig. 7 shows the conduction loss distribution for all the Vce
· · f sw (23)
power switches and the diodes. It can be observed that at Vnom
high power factor, which is the case for permanent magnet psw_avg_T A_2
machines, the conduction loss for the inner two IGBTSs,      π+ϕ
Vce 1
T A2 and T A3 , is higher than the outer most ones (T A1 and T A4 ). = · f sw · (E IGBT )dα
Moreover, the conduction loss for the antiparallel diodes are Vnom 2π π
psw_avg_T A_2
very low, as most of the power is shared by the NPC diodes
(D f A1 and D f A2 ), when IGBTSs are turned OFF. With an 1
2
= I · (25e−10 · sin(2ϕ) − 5e−9 ϕ) + 6e−5
increase in modulation index, the active Insulated gate bipolar 2π m
transistor (IGBTs) (T A1 and T A4 ) take more share of the load  
−4
 Vce
current, which make their conduction losses to increase, and · Im (1 − cos(ϕ)) + 31e · ϕ · · fsw
Vnom
the conduction losses for the NPC diodes go down.
(24)
In comparison with the conduction losses for two-level
inverter switches, the loss distributions between different psw_avg_T A_3
power switches are not symmetrical. This will overheat some     π
Vce 1
of the switches than the other. = · f sw · (E IGBT )dα
Vnom 2π 0
psw_avg_T A_3
B. Switching Loss Calculation 1
2
= I · (25e−10 · sin(2ϕ) − 5e−9 ϕ) − 6e−5
Switching losses in any device is a function of load current 2π m  
and the voltage across that power device. There are basi- −4
 Vce
· Im (1 − cos(ϕ)) + 31e · ϕ · · fsw
cally two kinds of switching losses observed in the IGBTSs: Vnom
turn-ON (E ON ) and turn-OFF (E OFF ) losses. Both of them are (25)
1070 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016

psw_avg_T A_4
     2π
Vce 1
= · fsw · (E IGBT )dα
Vnom 2π π+ϕ
psw_avg_T A_4
1
2
= I · (5e−9 ϕ − 1.57e−8 − 25e−10 · sin(2ϕ)) + 6e−5
2π m 
· Im (1 + cos(ϕ)) − 31e−4 · ϕ + 0.00973
 
Vce
· · fsw (26)
Vnom
psw_avg_d A_1 / psw_avg_d A_2
    π
Vce 1
= · fsw · (E diode)dα
Vnom 2π ϕ
psw_avg_d A_1 / psw_avg_d A_2
1
2 Fig. 8. Phase current and spectrum analysis for (a) and (b) SV-PWM and
= I · (75e−10 · sin(2ϕ) − 15e−9 ϕ) + 3e−5 (c) and (d) carrier-based control strategies.
2π m 
· Im (cos(ϕ) − 1) + 11e−4 · ϕ
 
Vce
· · fsw (27)
Vnom
psw_avg_d A_3 / psw_avg_d A_4
     2π
Vce 1
= · fsw · (E diode)dα
Vnom 2π π+ϕ
psw_avg_d A_3 / psw_avg_d A_4
1
2
= I · (75e−10 · sin(2ϕ) − 15e−9 ϕ) + 3e−5
2π m
· Im (cos(ϕ) − 1) + 11e−4 · ϕ}
 
Vce
· · fsw (28)
Vnom
psw_avg_D f d A_1
     π+ϕ
Vce 1
= · fsw · (E diode)dα
Vnom 2π ϕ
psw_avg_D f A_1
1
= {6e−5 · Im − 4.71e−8 Im + 0.0034}
2π 
Vce
· · fsw (29)
Vnom
psw_avg_D f d A_2
     2π
Vce 1
= · fsw · (E diode)dα
Vnom 2π π+ϕ Fig. 9. Performance results for three-level inverter with the change in speed
psw_avg_D f A_2 from 150 to 800 r/min, while the load torque was kept constant at 6 N · m.
1
−5  (a) Change in machine speed. (b) Phase voltage. (c) Difference between two
= 6e · Im − 4.71e−8 Im2 + 0.0034 dc-link capacitor voltages. (d) Stator current.
2π 
Vce
· · fsw . (30) Fig. 8 shows the simulation result for the stator phase cur-
Vnom rent [Fig. 8(a) and (c)] and current spectrum [Fig. 8(b) and (d)]
From the derived switching loss expressions, it can be seen of the two control strategies, while the machine was oper-
that the switching losses for IGBTSs T A1 and T A4 are similar, ating at 585 r/min (19.5 Hz). The results show the similar
T A2 and T A3 are almost similar, all antiparallel diodes have performance, and %THD is also at the required tolerance
similar losses, and the two NPC diodes will have also similar level. However, with the proposed carrier-based control strat-
switching losses as well. egy, harmonic distortions are comparatively lower than the
SV-PWM-based strategy.
V. S IMULATION R ESULTS Fig. 9 shows the simulation test results with the pro-
Detailed simulation studies were carried out on a 6-kW sur- posed carrier-based control strategy, depicting a change in
face PMSM (SPMSM). The dc-link voltage was kept constant speed from 150 to 800 r/min, while load torque was kept
at 270 V, and the machine is loaded with a dc dynamometer. constant at 6 N · m. Fig. 10 shows the machine performance
The switching frequency is kept constant at 3 kHz. with the change in load torque from 6 to 24 N · m., while the
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES
Fig. 10. Performance results for three-level inverter with the change in
torque from 6 to 24 N · m., while the speed was kept constant at 500 r/min.
(a) Machine speed. (b) Phase voltage. (c) Difference between two dc-link
capacitor voltages. (d) Stator current.
speed was kept constant at 500 r/min. It can be observed
that during the change in speed, the dc-link voltage difference
is balanced to its desired level. The maximum variation in
the dc-link capacitor voltage difference is 2 V, and during
the change in load torque, the maximum capacitor voltage
difference is ∼4.5 V, which is 1.66% of the total dc-link
voltage. Moreover, the performance of the system with the
change in speed and torque is also smooth, which shows the
required performance of the proposed scheme.
To compare the loss analysis with the two dc-link bal-
ancing strategies, a 54-kW SPMSM machine is considered
with a 600 V dc-link voltage, as generally being used for
EV propulsion applications. Detailed machine parameter is
included in Table III. All the IGBT modeling parameters are
taken from the Infineon F3L300RO7PE4, 650 V NPC module
data sheet, as explained in Section IV. To calculate the inverter
loss, PLECS simulation tool is used. During the simulation
studies for loss calculation machine, the torque and the speed
were kept constant at 60 N · m. and 5000 r/min, respectively.
In Fig. 11(a), the conduction loss distribution of the four
IGBTSs is shown. It can be observed that T A2 and T A3 con-
duction losses are constant. This is because of the continuous
conduction of these devices for each half cycle, as shown
in Fig. 7(b). However, T A1 and T A4 conduct only in proportion
to the duty ratio, and for this reason, the losses increase
linearly with modulation index. As the switching of IGBTSs,
T A2 and T A3 as shown, occurs when current is negative or
positive, respectively, only a small amount of switching losses
1071
happens due to the lagging power factor, as shown in Fig. 5
(region C, phase A). As the power factor goes more lagging,
it will introduce more losses in the inner switches. IGBTSs,
T A1 and T A4 , will produce more switching losses compared
with the inner ones, as they switch with active load current.
Fig. 11(c) and (d) shows the conduction and switching losses
of the antiparallel diodes. These diodes only conduct when the
IGBTSs are turned OFF ideally. However, in the case of three-
level inverter, because of the NPC diodes, they do not share
much load current. Hence, it shows very low conduction and
switching losses, as shown in the simulation results. Moreover,
when the modulation index increases, the reference voltage
vector goes to the outmost subsector, which uses mostly the
large and medium voltage vectors, and allows the flow of
current to increase on those diodes.
In Fig. 11(e) and (f), the conduction and switching losses for
the NPC diodes are shown. As already explained in the earlier
stage, when IGBTSs, T A1 and T A4 , are turned OFF, the load
current passes through the NPC diodes, and it introduces the
larger amount of conduction and switching losses on them.
However, as the modulation index increases and IGBTSs,
T A1 and T A4 , take the larger share of the load currents,
the losses on the NPC diodes reduce. All the results shown
in Fig. 11 follow the similar trend, such as the analytical
derivation in Section IV. It shows that the derived analytical
equations are properly derived.
Fig. 12 shows the loss distribution with the SV-PWM
strategy with the dc-link voltage balancing. Compared with the
earlier shown loss distribution, where a uniform modulation
index was generated, in SV-PWM strategies based on the
two-capacitor state of charge, duties are generated. Hence,
losses will not follow as symmetrical as carrier-based strat-
egy. Fig. 12(a) and (b) shows the conduction and switching
loss distributions for IGBTSs. Conduction losses for T A1 are
linear with the modulation index. Hence, the corresponding
switching loss is almost constant. Conduction loss for T A2
was increasing until modulation index reaches 0.56, where
the redundant voltage vectors are dominant and after that it
remains constant, as more medium and large vectors are used.
The change in conduction loss shows that T A2 was switch-
ing to keep the capacitors balanced. Hence, corresponding
switching losses were also high. However, after 0.56 when
the conduction losses went to a constant value, a very small
value of switching losses can be seen. This is because of the
reduced switching. T A3 conduction losses are quite constant,
as there was not much switching, and for this reason, switching
losses are also low. The conduction losses for T A4 are constant,
as there was not much switching, and switching losses for
that also are low. The inner switches T A2 and T A3 shows
the lowest switching losses compared with the outer switches,
as the duty cycle is constant for the carrier-based strategy.
As in the case of carrier-based strategy, the duty cycle is
symmetrically distributed and does not change as much as like
the SV-PWM strategy, where the duty of each switches can be
controlled individually, and the losses are low in the carrier-
based strategy compared with the SV-PWM-based strategy.
Fig. 12(c) and (d) shows the conduction and switching losses
for antiparallel diodes. Results showed a bit higher conduction
1072 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016

Fig. 11. Switching and conduction losses for each IGBT and diodes for each leg with single-CB-PWM strategy. (a) IGBT conduction loss. (b) IGBT switching
loss. (c) IGBT antiparallel diode conduction loss. (d) IGBT antiparallel diode switching loss. (e) NPC diode conduction loss. (f) NPC diode switching loss.

Fig. 12. Switching and conduction losses for each IGBT and diodes for each leg with SV-PWM-based control strategy. (a) IGBT conduction loss.
(b) IGBT switching loss. (c) IGBT antiparallel diode conduction loss. (d) IGBT antiparallel diode switching loss. (e) NPC diode conduction loss.
(f) NPC diode switching loss.

losses for lower two diodes until the modulation index of 0.56,
and then, it will reduce.
Fig. 12(e) and (f) shows the conduction and switching losses
for the NPC diodes. The losses are constant until 0.56, which
shows the continuous use of NPC diodes, to keep the neutral
point potential low, and after that losses will start to reduce.
However, above the modulation index of 0.6, because there
is not much redundant voltage vectors involved, it makes the
SV-PWM strategy to have bit lower %THD than the carrier-
based strategy. Here, it can be observed that with the earlier
proposed SV-PWM-based strategy, the total loss distribution
over a modulation cycle for each of the power switches is
almost equal [Fig. 13(a)], and with the carrier-based strat-
egy, the upper and lower IGBTS losses keep on increasing
with modulation indices [Fig. 13(b)]. Hence, with the
SV-PWM-based strategy, the distribution of total power loss
is more distributed compared with the carrier-based strategy.
Fig. 14 shows the total inverter loss with both the control
strategies with the change in switching frequencies. With the
SV-PWM-based control strategy, the total inverter loss is bit
lower than the carrier-based strategy. It is because of the
reduced number of switching sequence used to keep the two
capacitor voltages balanced. As in the analytical study, it is not
possible to separate the switching loss equation based on the
modulating strategy, and it is not possible to compare the total
loss between the carrier- and SV-PWM-based strategies from
the analytical study. Fig. 15 shows the %THD comparison
between both the control strategies for phase voltages. It can
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES
Fig. 13. IGBT and antiparallel diode total conduction and switching losses for each power switch. (a) SV-PWM strategy. (b) Carrier-based strategy.
Fig. 14. Total inverter loss comparison for both control strategies.
Fig. 15. Phase voltage harmonic distortion comparison for the two control
strategies.
be observed that although both the control strategies show
almost similar results, with carrier-based strategy, %THD is a
bit lower at high modulation indexes. In simulations, there are
not much transients involved like in the experimental studies,
which makes the generated waveform more cleaner than the
SV-PWM strategy, where a lot of switching is present. For this
reason, %THD with SV-PWM strategy is bit higher than the
carrier-based strategy at higher modulation indices than the
lower (>0.46).
VI. E XPERIMENTAL T EST V ERIFICATION
Hardware testing is performed with a 6-kW SPMSM and
270 V dc-bus voltage. The control strategy is implemented
with dSPACE DS1103-based real-time operating system. The
carrier frequency is kept constant at 3 kHz. Fig. 16 shows the
experimental setup used for hardware verification.
Fig. 17 shows the experimental results of the duty ratios
for both strategies. Compared with the SV-PWM-based duties,
where both the positive and negative redundant voltage vectors
1073
Fig. 16. Experimental dynamometer test setup [21].
Fig. 17. Experimental results of the duty ratios for each leg top two switches.
(a) and (b) For SV-PWM-based control strategy. (c) and (d) For CB-PWM
control strategy.
are used alternatively, in the carrier-based strategy, the addi-
tion of dc-offset voltage (v o ) makes the two duties little bit
different. Hence, where Fig. 17(a) and (b) looks symmetric,
in Fig. 17(c) and (d), duties look bit different, which is because
of the dc-offset voltage addition.
Fig. 18 shows the machine phase current harmonic dis-
tortion (%THD) when machine speed was kept constant
at 585 r/min (19.5 Hz). From the results, it can be observed
that with the SV-PWM control strategy, current harmonics
are quite low (2.84%), as also shown in the simulation
results. However, the carrier-based strategy corresponding
current harmonics are bit higher. As with the carrier-based
strategy, the difference between the two capacitor voltages is
directly passed through PI controller and output, from the
1074 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016
Fig. 18. Experimental results for the phase current and the %THD analysis
for (a) and (b) SV-PWM and (c) and (d) carrier-based control strategies.
Fig. 19. Experimental results for the phase voltage harmonic distortion
comparison between the two control strategies.
PI controller adds to the reference voltage, all harmonics
present in the dc-link capacitor-sensed voltages are also going
to affect the reference modulation signal. If the reference
modulation signals are distorted, it will also affect the machine
torque and current harmonics as well. Hence, a low-pass filter
can be used, to filter out the high-frequency noises from
the sensed dc-link voltage, before it is passed through the
PI controller.
Fig. 19 shows the %THD comparison between the two
control strategies for stator phase voltage. Results show a
reverse trend compared with the simulation results. At lower
modulation indices, the SV-PWM has a superior capacitor
voltage balancing ability compared with the carrier-based
strategy. In the case of carrier-based strategy, a dc-offset
voltage is generally being added with the reference modulation
signal to keep the two-capacitor voltages balanced. As it is
explained in the simulation studies, in steady-state, the value of
v o will have much more transients in the experimental results
compared with the simulation studies. Hence, it will affect
the generated voltage waveform. Thus, the %THD with the
carrier-based strategy will have bit higher harmonic distortion
than the SV-PWM strategy until the modulation index of 0.56,
and after that, as the reference voltage vector will use the outer
subsectors, the use of redundant voltage state will reduce. This
will help to reduce the %THD in the generated voltage with the
Fig. 20. Experimental results for the change in speed for the carrier-based
strategy from 150 to 800 r/min at 6-N · m. load torque. (a) Machine speed.
(b) Phase voltage. (c) Difference between two capacitor voltages. (d) Stator
current.
Fig. 21. Experimental results for the change in torque for the carrier-based
strategy from 6 to 24 N · m, while the speed is kept constant at 490 r/min.
(a) Machine speed. (b) Phase voltage. (c) Stator current. (d) Difference
between two dc-link capacitor voltages.
carrier-based strategy at higher modulation indices above 0.56,
compared with the SV-PWM-based strategy.
Fig. 20 shows the experimental results with the carrier-
based strategy when the machine speed changes from
150 to 800 r/min at no load. The maximum capacitor volt-
age deviation is ∼2.5 V, which is below 1% of the total
dc-link capacitor voltage. It shows the required controllability
of the proposed dc-link balancing algorithm. Fig. 21 shows the
machine performance during the change in load torque from
6 to 24 N · m., while the machine speed is kept constant at
490 r/min. During the change in load torque, the controller
was able to keep the machine speed constant at the required
level, and the two capacitor voltages were also balanced.
The maximum dc-link capacitor voltage deviation at full load
was ∼3 V, which is ∼1.11% of the total dc-link capacitor
voltage.
Fig. 22 shows the experimental results for the total
inverter loss comparison between the SV-PWM strategy and
the carrier-based strategy with 6-kW motor. The Powerex
CHOUDHURY et al.: PERFORMANCE COMPARISON STUDY OF SV-PWM AND MODIFIED-CB-PWM TECHNIQUES
Fig. 22. Experimental results for the total inverter loss comparison with
SV-PWM and carrier-based strategies.
TABLE II
E XPERIMENTAL -BASED P ERFORMANCE C OMPARISON B ETWEEN
THE SV-PWM AND THE P ROPOSED C ARRIER -B ASED
C ONTROL S TRATEGY
TABLE III
M ACHINE PARAMETERS
CM100DU-12F, 600 V IGBT modules are used to build the
three-level inverter. As, in this module, no port is available to
check the individual switch power loss, we are only able to
calculate the total inverter loss. To calculate the total inverter
loss, input and output inverter powers are measured, and then,
they are subtracted to calculate the total inverter loss. From the
results, it can be seen that the losses are following the similar
trend like the simulation results, and the carrier-based strategy
showed higher power loss compared with the SV-PWM-based
strategy. As, with the carrier-based strategy, we do not have
any control over the number of switching states, they produce
higher loss than the SV-PWM-based strategy.
1075
Table II shows the experimental results-based performance
comparison study for both the control strategies. It is very clear
from the results that the carrier-based control strategy is best
for digital implementation due to its computational simplicity.
However, a proper PI value calculation is required, to achieve
the required performance results.
Table III shows all the machine parameters used for the
simulation and experimental studies with their associated
values.
VII. C ONCLUSION
A simple modified-single-CB-PWM technique for a three-
level inverter with a dc-link voltage balancing strategy is pro-
posed. The proposed strategy uses only one carrier instead of
two carriers as it is used with the conventional strategies, and
also, in the generated modulating signals, there will not be any
common interval of duty which could increase the switching
losses. It also keeps the dc-link capacitor voltages balanced
by adding the dc offset with the reference modulating signals.
An analytic loss calculation model based on device parameter
from the data sheets is derived. The derived equations show the
change in device (IGBT and diodes) losses with the change
in modulation index and power factor. The results are then
compared with the simulation studies. The performance of
carrier-based strategy is then compared with the SV-PWM-
based strategy to show the loss distribution in each switches,
total inverter loss, computational time, voltage harmonic dis-
tortion, and performance of the system with rapid speed and
torque changes for EV propulsion applications. To validate the
simulation results, extensive experimental verification is also
carried out with a 6-kW SPMSM. Experimental results show
the similar performance as the simulation studies. Hence, it
can be concluded that the carrier-based strategy reduces the
computational time and complexity of the system as com-
pared with the space-vector-based strategy, while keeping the
machine performance similar to the SV-PWM-based strategy.
However, the switching losses with the carrier-based strategy
are higher than the SV-PWM-based strategy, as carrier-based
strategy cannot control the switching states individually.
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Abhijit Choudhury (S’11–M’16) received the
B.E. degree from the National Institute of Technol-
ogy Agartala, Agartala, India, in 2007, the M.Tech.
degree in electrical engineering from IIT Bombay,
Mumbai, India, in 2011, and the Ph.D. degree
from Concordia University, Montréal, QC, Canada,
in 2015.
He was a Management Trainee with ABB India
Ltd., Vadodara, India, from 2007 to 2008, and a
Graduate Trainee with General Motors, Bangalore,
India, in 2011. He was a Post-Doctoral Research
Fellow with the Department of Electrical and Computer Engineering,
Concordia University, in 2015. He is currently a Scientist I with the Experi-
mental Power Grid Centre, Singapore. His current research interests include
high power electronics, converter control techniques, electrical machine drives,
and electric vehicle architecture.
Pragasen Pillay (F’05) received the bachelor’s and
master’s degrees from the University of KwaZulu-
Natal, Durban, South Africa, in 1981 and 1983,
respectively, and the Ph.D. degree from the Virginia
Polytechnic Institute and State University,
Blacksburg, VA, USA, in 1987.
He is currently a Professor with the Department
of Electrical and Computer Engineering, Concordia
University, Montréal, QC, Canada, where he
holds the NSERC/Hydro-Québec Senior Industrial
Research Chair.
Sheldon S. Williamson (S’01–M’06–SM’13)
received the B.E. (Hons.) degree from the
University of Mumbai, Mumbai, India, in 1999,
and the M.S. and Ph.D. (Hons.) degrees from the
Illinois Institute of Technology, Chicago, IL, USA,
in 2002 and 2006, respectively, all in electrical
engineering.
He held a Tenure-Track Assistant Professor,
followed by a Tenured Associate Professor,
with the Department of Electrical and Computer
Engineering, Concordia University, Montréal, QC,
Canada, from 2006 to 2014. He is currently an Associate Professor with the
Department of Electrical, Computer, and Software Engineering, University of
Ontario Institute of Technology, Oshawa, ON, Canada. His current research
interests include transportation electrification, electric energy storage systems,
and automotive power electronics/motor drives.