FPGA EXERCISES COMPILATION

By

Nicko D. Casi/ ECE-4

MICROELECTRONICS TRACK 3

Bachelor of Science in
Electronics Engineering
EXERCISE I: LED AND PUSH BUTTON

The objective for this exercise is simple by knowing how to program so that
the LEDG0 on the FPGA board would light up and when the KEY0 is pressed, the
light on LEDG0 would turn off.

Verilog HDL Code:

module exercise1 (CLOCK_50, PB, LEDG);

input CLOCK_50;
input [3:0] PB;
reg [9:0] state;
output [7:0] LEDG;

assign LEDG = state;

always @ (posedge CLOCK_50)

if (PB[0] == 0)
state <= 10'b0000000000;
else
state[0] <= 1;

endmodule

TCL Script File:

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_U22 -to LEDG\[0\]
set_location_assignment PIN_U21 -to LEDG\[1\]
set_location_assignment PIN_V22 -to LEDG\[2\]
set_location_assignment PIN_V21 -to LEDG\[3\]
set_location_assignment PIN_W22 -to LEDG\[4\]
set_location_assignment PIN_W21 -to LEDG\[5\]
set_location_assignment PIN_Y22 -to LEDG\[6\]
set_location_assignment PIN_Y21 -to LEDG\[7\]
Photos:

Figure 1 The LEDG0 on the Photo is lit up and When the KEY0 is pressed, the LEDG0 would turn off

Figure 2 The LEDG0 was turned off

EXERCISE II: CONTROLLED LED

The exercise aims to design a Verilog program that controls the LEDG0
LED with the use of a push button specifically, the KEY1 push button. When KEY1
is pressed and LEDG0 LED is turned on, it will light up. However, when KEY0 is
pressed and LEDG0 is lit up, it will turn off.

Verilog HDL Code:

module exercise2 (CLOCK_50, PB, LEDG);
input CLOCK_50;
input [3:0] PB;
reg [9:0] state;
output [7:0] LEDG;
assign LEDG = state;
always @ (posedge CLOCK_50)
if (PB[0] == 0)
state <= 10'b0000000000;
else if (PB[1] == 0)
state[0] <= 1;
endmodule

TCL Script:
set_location_assignment PIN_R22 -to PB[0]
set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_U22 -to LEDG\[0\]
set_location_assignment PIN_U21 -to LEDG\[1\]
set_location_assignment PIN_V22 -to LEDG\[2\]
set_location_assignment PIN_V21 -to LEDG\[3\]
set_location_assignment PIN_W22 -to LEDG\[4\]
set_location_assignment PIN_W21 -to LEDG\[5\]
set_location_assignment PIN_Y22 -to LEDG\[6\]
set_location_assignment PIN_Y21 -to LEDG\[7\]
Photos:

Figure 3 When KEY1 is pressed, the LEDG0 lights up

Figure 4 When KEY0 is pressed, the LEDG0 turned off

EXERCISE III: BLINKING LEDS

This exercise aims to design a Verilog program that controls the blinking of
all the LEDs (LEDG0 – LEDG7) in the DE1 starter kit. The LEDs should blink every
half a second or 0.5 seconds at the same time.

Verilog HDL Code:

module exercise3 (CLOCK_50, PB, LEDG);

input CLOCK_50;
input [3:0] PB;
reg [7:0] state;
reg [23:0] counter;
output [7:0] LEDG;

assign LEDG = state;

always @ (posedge CLOCK_50)

if (PB[0] == 0)
counter <= 0;
else if (counter == 8000000)
counter <= 0;
else
counter <= counter+1;

always @ (posedge CLOCK_50)

if (PB[1] == 0)
state <= 8'b11111111;
else if (counter == 8000000)
state = ~state;

endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]

set_location_assignment PIN_U22 -to LEDG\[0\]

set_location_assignment PIN_U21 -to LEDG\[1\]
set_location_assignment PIN_V22 -to LEDG\[2\]
set_location_assignment PIN_V21 -to LEDG\[3\]
set_location_assignment PIN_W22 -to LEDG\[4\]
set_location_assignment PIN_W21 -to LEDG\[5\]
set_location_assignment PIN_Y22 -to LEDG\[6\]
set_location_assignment PIN_Y21 -to LEDG\[7\]

Photos:

Figure 5 All of the LEDG LEDs light up and blinking for 0.5 seconds
EXERCISE IV: LED PATTERN

This exercise aims to design a Verilog program that outputs the pattern below
using the LEDs.

The transition interval for each set is 0.5 seconds. A colored dot means that the
corresponding LED lights up.

Verilog HDL Code:

module exercise4 (CLOCK_50, PB, LEDG1, LEDG2);

input CLOCK_50;
input [3:0] PB;
reg [3:0] state_1;
reg [3:0] state_2;
reg [23:0] counter;
output [3:0] LEDG1;
output [7:4] LEDG2;

parameter case_01 = 4'b0000;

parameter case_02 = 4'b1000;
parameter case_03 = 4'b0100;
parameter case_04 = 4'b0010;
parameter case_05 = 4'b0001;
parameter case_11 = 4'b0000;
parameter case_12 = 4'b1000;
parameter case_13 = 4'b1100;
parameter case_14 = 4'b1110;
parameter case_15 = 4'b1111;
parameter case_16 = 4'b0001;

assign LEDG1 = state_1;

assign LEDG2 = state_2;

always @ (posedge CLOCK_50)

if (PB[0] == 0)
counter <= 0;
else if (counter == 8000000)
counter <= 0;
else
counter <= counter + 1;

always @ (posedge CLOCK_50)

if (counter == 8000000)
case (state_1)
case_01:state_1 <= case_02;
case_02:state_1 <= case_03;
case_03:state_1 <= case_04;
case_04:state_1 <= case_05;
case_05:state_1 <= case_01;

endcase

always @ (posedge CLOCK_50)

if (counter == 8000000)
 case (state_2)
case_11:state_2 <= case_12;
case_12:state_2 <= case_13;
case_13:state_2 <= case_14;
case_14:state_2 <= case_15;
case_15:state_2 <= case_16;
case_16:state_2 <= case_11;

endcase

endmodule

TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]

set_location_assignment PIN_U22 -to LEDG1[0]

set_location_assignment PIN_U21 -to LEDG1[1]
set_location_assignment PIN_V22 -to LEDG1[2]
set_location_assignment PIN_V21 -to LEDG1[3]
set_location_assignment PIN_W22 -to LEDG2[4]
set_location_assignment PIN_W21 -to LEDG2[5]
set_location_assignment PIN_Y22 -to LEDG2[6]
set_location_assignment PIN_Y21 -to LEDG2[7]
Photos:
Figure 6 The Following Photos show the combination of the LEDG pattern. Note that when KEY0 is pressed, the
transition pauses.
EXERCISE V: LED OPERATION USING A PUSH BUTTON
This exercise is the continuation of EXERCISE IV, but this time, the transition
of the LED patterns is controlled by a push button KEY1.
Verilog HDL Code:
module exercise5 (CLOCK_50, PB, LEDG1, LEDG2);

input CLOCK_50;
input [3:0] PB;
reg [3:0] state1;
reg [3:0] state2;
reg [23:0] counter;
output [3:0] LEDG1;
output [7:4] LEDG2;

parameter a0 = 4'b0000;
parameter a1 = 4'b1000;
parameter a2 = 4'b0100;
parameter a3 = 4'b0010;
parameter a4 = 4'b0001;

parameter b0 = 4'b0000;
parameter b1 = 4'b1000;
parameter b2 = 4'b1100;
parameter b3 = 4'b1110;
parameter b4 = 4'b1111;
parameter b5 = 4'b0001;
assign LEDG1 = state1;
assign LEDG2 = state2;

always @ (posedge CLOCK_50)

if (PB[0] == 0)
counter <= 0;
else if ( counter == 8000000)
counter <= 0;
else
 counter <= counter+1;

always @ (posedge CLOCK_50)

if(PB[0] == 0)
state1 <= a0;
else if (counter == 8000000)
case (state1)
a0:
if (PB[1] == 0)
state1 <= a1;
a1:
if (PB[1] == 0)
state1 <= a2;
a2:
if (PB[1] == 0)
state1 <= a3;
a3:
if (PB[1] == 0)
state1 <= a4;
a4:
if (PB[1] == 0)
state1 <= a0;
endcase

always @ (posedge CLOCK_50)

if(PB[0] == 0)
state2 <= b0;
else if (counter == 8000000)
case (state2)
b0:
if (PB[1] == 0)
state2 <= b1;
b1:
if (PB[1] == 0)
state2 <= b2;
b2:
if (PB[1] == 0)
 state2 <= b3;
b3:
if (PB[1] == 0)
state2 <= b4;
b4:
if (PB[1] == 0)
state2 <= b5;
b5:
if (PB[1] == 0)
state2 <= b0;
endcase

endmodule

TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]
set_location_assignment PIN_U22 -to LEDG1\[0\]
set_location_assignment PIN_U21 -to LEDG1\[1\]
set_location_assignment PIN_V22 -to LEDG1\[2\]
set_location_assignment PIN_V21 -to LEDG1\[3\]
set_location_assignment PIN_W22 -to LEDG2\[4\]
set_location_assignment PIN_W21 -to LEDG2\[5\]
set_location_assignment PIN_Y22 -to LEDG2\[6\]
set_location_assignment PIN_Y21 -to LEDG2\[7\]
Photos:
Figure 7 The LED Pattern Transition is being controlled by Pressing KEY1 Push Button

Figure 8 KEY0 is a Reset button. When pressed, the transition resets.

EXERCISE VI: 7-SEGMENT LED DISPLAY PART I

This exercise aims to design a Verilog program that outputs the number “4”
to the seven-segment display in the DE1 Starter Kit.

Verilog HDL Code:

module exercise6 (CLOCK_50, HEX0, HEX1, HEX2, HEX3, PB);

input CLOCK_50;
input [3:0] PB;
reg [6:0] number;
output [7:0] HEX0, HEX1, HEX2, HEX3;

parameter number4 = 7'b0011001;

assign HEX0 = {1'b1, number};

assign HEX1 = {7'b1111111};
assign HEX2 = {7'b1111111};
assign HEX3 = {7'b1111111};

always @ (posedge CLOCK_50)

if(PB[0] == 0)
number <= 7'h7F;
else
number <= number4;

endmodule

TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_J2 -to HEX0[0]

set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]

Photos:

Figure 9 The Number “4” is Displayed

EXERCISE VII: 7-SEGMENT LED DISPLAY PART 2

This exercise aims to design a Verilog program that outputs the numbers
letters “bESt” to the seven-segment display in the DE1 starter Kit.

Verilog HDL Code:

module exercise7(CLOCK_50, PB, HEX0, HEX1, HEX2, HEX3);

input CLOCK_50;
input[2:0] PB;
reg[6:0] lettera, letterb, letterc, letterd;
output[7:0] HEX0, HEX1, HEX2, HEX3;

parameter O = 7'b0000011;
parameter T = 7'b0000110;
parameter Th = 7'b0010010;
parameter F = 7'b0000111;

assign HEX0 = {1'b1, lettera};

assign HEX1 = {1'b1, letterb};
assign HEX2 = {1'b1, letterc};
assign HEX3 = {1'b1, letterd};

always @ (posedge CLOCK_50)

if(PB[0] == 0)

begin
lettera <= 7'h7F;
letterb <= 7'h7F;
letterc <= 7'h7F;
letterd <= 7'h7F; end
else
begin
lettera <= F;
letterb <= Th;
 letterc <= T;
letterd <= O; end
endmodule

TCL Script:
set_location_assignment PIN_D1 -to HEX1[6]

set_location_assignment PIN_G5 -to HEX2[0]

set_location_assignment PIN_G6 -to HEX2[1]
set_location_assignment PIN_C2 -to HEX2[2]
set_location_assignment PIN_C1 -to HEX2[3]
set_location_assignment PIN_E3 -to HEX2[4]
set_location_assignment PIN_E4 -to HEX2[5]
set_location_assignment PIN_D3 -to HEX2[6]

set_location_assignment PIN_F4 -to HEX3[0]

set_location_assignment PIN_D5 -to HEX3[1]
set_location_assignment PIN_D6 -to HEX3[2]
set_location_assignment PIN_J4 -to HEX3[3]
set_location_assignment PIN_L8 -to HEX3[4]
set_location_assignment PIN_F3 -to HEX3[5]
set_location_assignment PIN_D4 -to HEX3[6]

Photos:

Figure 10 The word "bESt" is displayed on the board.

EXERCISE VIII: COUNTER

This exercise aims to design a Verilog program that outputs 0000 to 9999 to
the seven-segment display in the DE1 Starter Kit with a 0.1 second interval.

Verilog HDL Code:

module exercise8(CLOCK_50, PB, HEX0, HEX1, HEX2, HEX3);

input CLOCK_50;
input[3:0] PB;
output[7:0] HEX0, HEX1, HEX2, HEX3;

reg[22:0] counter;
reg[6:0] number0, number1, number2, number3;

assign HEX0 = {1'b1, number0};

assign HEX1 = {1'b1, number0};
assign HEX2 = {1'b1, number0};
assign HEX3 = {1'b1, number0};

parameter n1 = 7'b1111001;
parameter n2 = 7'b0100100;
parameter n3 = 7'b0110000;
parameter n4 = 7'b0011001;
parameter n5 = 7'b0010010;
parameter n6 = 7'b0000010;
parameter n7 = 7'b1111000;
parameter n8 = 7'b0000000;
parameter n9 = 7'b0010000;
parameter n0 = 7'b1000000;

always @ (posedge CLOCK_50)

if(PB[0] == 0)
counter <= 0;
else if (counter == 10_000_000)
 counter <= 0;
else
counter <= counter + 1;

always @ (posedge CLOCK_50)

if (PB[0] == 0)
begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
number3 <= n0;
end
else if (counter == 5_000_000)
case (number0)
n0: number0 <= n1;
n1: number0 <= n2;
n2: number0 <= n3;
n3: number0 <= n4;
n4: number0 <= n5;
n5: number0 <= n6;
n6: number0 <= n7;
n7: number0 <= n8;
n8: number0 <= n9;
n9: number0 <= n0;
default: ;

endcase
endmodule

TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]

set_location_assignment PIN_J2 -to HEX0[0]

set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]

set_location_assignment PIN_E1 -to HEX1[0]

set_location_assignment PIN_H6 -to HEX1[1]
set_location_assignment PIN_H5 -to HEX1[2]
set_location_assignment PIN_H4 -to HEX1[3]
set_location_assignment PIN_G3 -to HEX1[4]
set_location_assignment PIN_D2 -to HEX1[5]
set_location_assignment PIN_D1 -to HEX1[6]

set_location_assignment PIN_G5 -to HEX2[0]

set_location_assignment PIN_G6 -to HEX2[1]
set_location_assignment PIN_C2 -to HEX2[2]
set_location_assignment PIN_C1 -to HEX2[3]
set_location_assignment PIN_E3 -to HEX2[4]
set_location_assignment PIN_E4 -to HEX2[5]
set_location_assignment PIN_D3 -to HEX2[6]

set_location_assignment PIN_F4 -to HEX3[0]

set_location_assignment PIN_D5 -to HEX3[1]
set_location_assignment PIN_D6 -to HEX3[2]
set_location_assignment PIN_J4 -to HEX3[3]
set_location_assignment PIN_L8 -to HEX3[4]
set_location_assignment PIN_F3 -to HEX3[5]
set_location_assignment PIN_D4 -to HEX3[6]
Photos:

Figure 11 The Counter counting from 0000 to 9999 in the four Seven-Segment Display with 0.1 second interval
EXERCISE IX: COUNTER WITH CONTROLS

This exercise aims to design a Verilog program that outputs 0000 to 9999 to
the seven-segment display in the DE1 Starter Kit with a 0.1 second interval when
the SW0 switch is off. When the SW0 is on, the output number will increment by 1
if SW1 is pressed and it will decrement by 1 if SW2 is pressed.

Verilog HDL Code:

module exercise9(CLOCK_50, PB, HEX0, HEX1, HEX2, HEX3,
SW);

input CLOCK_50;
input[3:0] PB;
input[9:0] SW;
output[7:0] HEX0, HEX1, HEX2, HEX3;

reg[22:0] counter;
reg[6:0] number0, number1, number2, number3;

reg hold;
reg add;
reg sub;
reg rst;

assign HEX0 = {1'b1, number0};

assign HEX1 = {1'b1, number1};
assign HEX2 = {1'b1, number2};
assign HEX3 = {1'b1, number3};

parameter n1 = 7'b1111001;
parameter n2 = 7'b0100100;
parameter n3 = 7'b0110000;
parameter n4 = 7'b0011001;
parameter n5 = 7'b0010010;
parameter n6 = 7'b0000010;
parameter n7 = 7'b1111000;
parameter n8 = 7'b0000000;
parameter n9 = 7'b0010000;
parameter n0 = 7'b1000000;

initial
begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
number3 <= n0;
rst = 0;
end

always @ (posedge CLOCK_50)

if(SW[0] == 1 && SW[1] == 0 && SW[2] == 0)
begin
hold = 1;
add = 0;
sub = 0;
end
else if(SW[0] == 0 && SW[1] == 1 && SW[2] == 0)
begin
hold = 0;
add = 1;
sub = 0;
end
else if(SW[0] == 0 && SW[1] == 0 && SW[2] == 1)
begin
hold = 0;
add = 0;
sub = 1;
end
else
begin
 hold = 0;
add = 0;
sub = 0;
end
always @ (posedge CLOCK_50)
if(PB[0] == 0)
counter <= 0;
else if (counter == 10_000_000)
counter <= 0;
else
counter <= counter +1;
always @ (posedge CLOCK_50)
if (PB[0] == 0)
begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
number3 <= n0;
end
else if (counter == 5_000_000 && hold == 1)
case (number0)
n0: number0 <= n1;
n1: number0 <= n2;
n2: number0 <= n3;
n3: number0 <= n4;
n4: number0 <= n5;
n5: number0 <= n6;
n6: number0 <= n7;
n7: number0 <= n8;
n8: number0 <= n9;
n9: begin
number0 <= n0;
case (number1)
n0: number1 <= n1;
n1: number1 <= n2;
n2: number1 <= n3;
n3: number1 <= n4;
n4: number1 <= n5;
n5: number1 <= n6;
n6: number1 <= n7;
n7: number1 <= n8;
n8: number1 <= n9;
n9: begin
number0 <= n0;
number1 <= n0;
case (number2)
n0: number2 <= n1;
n1: number2 <= n2;
n2: number2 <= n3;
n3: number2 <= n4;
n4: number2 <= n5;
n5: number2 <= n6;
n6: number2 <= n7;
n7: number2 <= n8;
n8: number2 <= n9;
n9: begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
case (number3)
n0: number3 <= n1;
n1: number3 <= n2;
n2: number3 <= n3;
n3: number3 <= n4;
n4: number3 <= n5;
n5: number3 <= n6;
n6: number3 <= n7;
n7: number3 <= n8;
n8: number3 <= n9;
n9: begin
 number0 <= n0;
number1 <= n0;
number2 <= n0;
number3 <= n0;
end
endcase
end
endcase
end
endcase
end
endcase
else if (counter == 5_000_000 && rst == 0 && hold ==
0 && add == 1)
case (number0)
n0: begin
number0 <= n1;
rst <= 1;
end
n1: begin
number0 <= n2;
rst <=1;
end
n2: begin
number0 <= n3;
rst <=1;
end
n3: begin
number0 <= n4;
rst <=1;
end
n4: begin
number0 <= n5;
rst <=1;
end
n5: begin
number0 <= n6;
rst <=1;
end
n6: begin
number0 <= n7;
rst<=1;
end
n7: begin
number0 <= n8;
rst<=1;
end
n8: begin
number0 <= n9;
rst<=1;
end
n9: begin
number0 <= n0;
case (number1)
n0: begin
number1 <= n1;
rst<=1;
end
n1: begin
number1 <= n2;
rst<=1;
end
n2: begin
number1 <= n3;
rst<=1;
end
n3: begin
number1 <= n4;
rst<=1;
end
n4: begin
number1 <= n5;
rst<=1;
end
n5: begin
number1 <= n6;
rst<=1;
end
n6: begin
number1 <= n7;
rst<=1;
end
n7: begin
number1 <= n8;
rst<=1;
end
n8: begin
number1 <= n9;
rst<=1;
end
n9: begin
number0 <= n0;
number1 <= n0;
case (number2)
n0: begin
number2 <= n1;
rst <=1;
end
n1: begin
number2 <= n2;
rst <=1;
end
n2: begin
number2 <= n3;
rst <=1;
 end
n3: begin
number2 <= n4;
rst <=1;
end
n4: begin
number2 <= n5;
rst <=1;
end
n5: begin
number2 <= n6;
rst <=1;
end
n6: begin
number2 <= n7;
rst <=1;
end
n7: begin
number2 <= n8;
rst <=1;
end
n8: begin
number2 <= n9;
rst <=1;
end
n9: begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
case (number3)
n0: begin
number3 <= n1;
rst<=1;
end
n1: begin
 number3 <= n2;
rst<=1;
end
n2: begin
number3 <= n3;
rst<=1;
end
n3: begin
number3 <= n4;
rst<=1;
end
n4: begin
number3 <= n5;
rst<=1;
end
n5: begin
number3 <= n6;
rst<=1;
end
n6: begin
number3 <= n7;
rst<=1;
end
n7: begin
number3 <= n8;
rst<=1;
end
n8: begin
number3 <= n9;
rst<=1;
end
n9: begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
 number3 <= n0;
end
endcase
end
endcase
end

endcase
end
endcase
else if (counter == 5_000_000 && rst == 0 && hold ==
0 && sub == 1)
case (number0)
n9: begin
number0 <= n8;
rst <= 1;
end
n8: begin
number0 <= n7;
rst <=1;
end
n7: begin
number0 <= n6;
rst <=1;
end
n6: begin
number0 <= n5;
rst <=1;
end
n5: begin
number0 <= n4;
rst <=1;
end
n4: begin
number0 <= n3;
 rst <=1;
end
n3: begin
number0 <= n2;
rst<=1;
end
n2: begin
number0 <= n1;
rst<=1;
end
n1: begin
number0 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
case (number1)
n9: begin
number1 <= n8;
rst<=1;
end
n8: begin
number1 <= n7;
rst<=1;
end
n7: begin
number1 <= n6;
rst<=1;
end
n6: begin
number1 <= n5;
rst<=1;
end
n5: begin
number1 <= n4;
 rst<=1;
end
n4: begin
number1 <= n3;
rst<=1;
end
n3: begin
number1 <= n2;
rst<=1;
end
n2: begin
number1 <= n1;
rst<=1;
end
n1: begin
number1 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
case (number2)
n9: begin
number2 <= n8;
rst <=1;
end
n8: begin
number2 <= n7;
rst <=1;
end
n7: begin
number2 <= n6;
rst <=1;
end
n6: begin
 number2 <= n5;
rst <=1;
end
n5: begin
number2 <= n4;
rst <=1;
end
n4: begin
number2 <= n3;
rst <=1;
end
n3: begin
number2 <= n2;
rst <=1;
end
n2: begin
number2 <= n1;
rst <=1;
end
n1: begin
number2 <= n0;
rst <=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
number2 <= n9;
case (number3)
n9: begin
number3 <= n8;
rst<=1;
end
n8: begin
number3 <= n7;
rst<=1;
 end
n7: begin
number3 <= n6;
rst<=1;
end
n6: begin
number3 <= n5;
rst<=1;
end
n5: begin
number3 <= n4;
rst<=1;
end
n4: begin
number3 <= n3;
rst<=1;
end
n3: begin
number3 <= n2;
rst<=1;
end
n2: begin
number3 <= n1;
rst<=1;
end
n1: begin
number3 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
number2 <= n9;
number3 <= n9;
end
 endcase
end
endcase
end

endcase
end
endcase

else if(counter == 5_000_000 && SW[1] == 0 && SW[2]

== 0)
rst <=0;

endmodule

TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_L22 -to SW[0]

set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]

set_location_assignment PIN_J2 -to HEX0[0]

set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
set_location_assignment PIN_E1 -to HEX1[0]
set_location_assignment PIN_H6 -to HEX1[1]
set_location_assignment PIN_H5 -to HEX1[2]
set_location_assignment PIN_H4 -to HEX1[3]
set_location_assignment PIN_G3 -to HEX1[4]
set_location_assignment PIN_D2 -to HEX1[5]
set_location_assignment PIN_D1 -to HEX1[6]
set_location_assignment PIN_G5 -to HEX2[0]
set_location_assignment PIN_G6 -to HEX2[1]
set_location_assignment PIN_C2 -to HEX2[2]
set_location_assignment PIN_C1 -to HEX2[3]
set_location_assignment PIN_E3 -to HEX2[4]
set_location_assignment PIN_E4 -to HEX2[5]
set_location_assignment PIN_D3 -to HEX2[6]
set_location_assignment PIN_F4 -to HEX3[0]
set_location_assignment PIN_D5 -to HEX3[1]
set_location_assignment PIN_D6 -to HEX3[2]
set_location_assignment PIN_J4 -to HEX3[3]
set_location_assignment PIN_L8 -to HEX3[4]
set_location_assignment PIN_F3 -to HEX3[5]
set_location_assignment PIN_D4 -to HEX3[6]

set_location_assignment PIN_R22 -to PB[0]

set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_T22 -to PB[2]
set_location_assignment PIN_T21 -to PB[3]
Photos:

Figure 12 When SW0 is turned ON, the Counter will count from 0000 to 9999 by 0.1 seconds interval. But When
SW0 is turned OFF, the counter pauses.
Figure 13 Increment of 1 if SW1 is turned ON while SW0 is turned off.
Figure 14 Decrement of 1 if SW2 is turned ON while SW0 is turned OFF
EXERCISE XI: VGA DISPLAY

This exercise aims to design a Verilog program that communicates to a

monitor via the VGA connector. The Verilog program should display any pattern
consisting of all possible color combinations.

Verilog HDL Code:

module exercise11 (CLOCK_50, VGA_HS, VGA_VS, VGA_R,
VGA_G, VGA_B);

input CLOCK_50;
output[3:0] VGA_R, VGA_G, VGA_B;
output VGA_HS, VGA_VS;

reg[9:0] counter_HS;
reg[8:0] counter_VS;
reg vga_HS, vga_VS, clk;
reg[3:0] VGA_R, VGA_G, VGA_B;

always @ (posedge CLOCK_50)

clk <= ~clk;

always @ (posedge clk) // the "clk" in this line is not

//originally "clk" but "CLOCK_50"
// Error if this was used ---> always @ (posedge CLOCK_50)
if(counter_HS == 767)
begin
counter_HS <= 0;
counter_VS <= counter_VS + 1;
end
else counter_HS <= counter_HS + 1;

always @ (posedge CLOCK_50)

begin
vga_HS <= (counter_HS[9:4] == 0);
 vga_VS <= (counter_VS == 0);
end

assign VGA_HS = ~vga_HS;

assign VGA_VS = ~vga_VS;

always @ (posedge CLOCK_50)

if(counter_VS<160)
begin
VGA_R <= ((counter_HS+1/10)%16);
if((counter_HS>159&&counter_HS<320)||(counter_HS>47
9))VGA_G<= 15;
else VGA_G <= 0;
if(counter_HS>319) VGA_B <= 15;
else VGA_B <=0;
end
else if(counter_VS<319)
begin
VGA_G <= ((counter_HS+1)/10)%16;
if((counter_HS>159&&counter_HS<320)||(counter_HS>47
9))VGA_B<= 15;
else VGA_B <= 0;
if(counter_HS>319) VGA_R <= 15;
else VGA_R <= 0;
end
else
begin
VGA_B <= ((counter_HS+1)/10)%16;
if((counter_HS>159&&counter_HS<320)||(counter_HS>47
9))VGA_R<= 15;
else VGA_R <= 0;
if(counter_HS>319) VGA_G <= 15;
else VGA_G <= 0;
end
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50

set_location_assignment PIN_D9 -to VGA_R\[0\]

set_location_assignment PIN_C9 -to VGA_R\[1\]
set_location_assignment PIN_A7 -to VGA_R\[2\]
set_location_assignment PIN_B7 -to VGA_R\[3\]
set_location_assignment PIN_B8 -to VGA_G\[0\]
set_location_assignment PIN_C10 -to VGA_G\[1\]
set_location_assignment PIN_B9 -to VGA_G\[2\]
set_location_assignment PIN_A8 -to VGA_G\[3\]
set_location_assignment PIN_A9 -to VGA_B\[0\]
set_location_assignment PIN_D11 -to VGA_B\[1\]
set_location_assignment PIN_A10 -to VGA_B\[2\]
set_location_assignment PIN_B10 -to VGA_B\[3\]
set_location_assignment PIN_A11 -to VGA_HS
set_location_assignment PIN_B11 -to VGA_VS

Photos:

Figure 15 The Default Screen Display of the FPGA Board connected to the Monitor Via the VGA port. This screen
will appear as a start-up configuration with no codes compiled and programmed to the board yet.
Figure 16 The output of the Verilog Code will all of the Possible Color Combination Was seen on the display.