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OBJECTIVES
Designing digital circuits at behavioral and RTL modeling of digital circuits using verilog HDL. verifying these
models, and synthesizing RTL models to standard cell libraries and FPGAs.
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Students gain practical experience by designing, modeling, implementing and verifying several digital circuits. This
course aims provide students with the understanding of different technologies related to HDLs, constructs,
compile and execute verilog HDL programs using provided software tools. Design digital components and circuits
that are testable, reusable and synthesizable.
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What is a data types? And what are those? Evaluate h
15.
Define scalars and vectors? Remember n
16.
Define parameters and memory operators? Remember n
17.
or
Define system tasks? Remember n
18.
UNIT-II
GATE LEVEL MODELING AND MODELING AT DATAFLOW LEVEL
What is gate level modeling? Evaluate h
1
4
What is AND gate primitive?
Evaluate
Remember
Evaluate
h
h
5
Define delay? Remember n
6
TU
Define strengths and content resolution? Remember n
7
What is a net data type? Evaluate h
8
How many types of net data types? Evaluate h
9
How many tri-state gates are there in verilog? Evaluate h
10
What is continuous assignment structure? Evaluate h
11.
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8 Explain multiple always blocks Understand i
9. Define blocking and non-blocking assignments Remember n
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13. Explain assign and de-assign construct. Understand i
Define repeat construct Remember n
14.
15. Write the syntax for a for loop Apply k
16. Write the syntax for a while loop and forever loop Apply k
17. Explain parallel blocks Understand i
18
1.
2.
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Explain force – release construct
Remember
i
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UNIT-V
SEQUENTIAL CIRCUIT DESCRIPTION, COMPONENT TEST VERIFICATION
What are the types of sequential models? Evaluate h
1
Explain Feedback model. Understand i
2
or
Explain capacitive model. Understand i
3
Explain implicit model. Understand i
4
What are the basic memory components? Evaluate h
5
8
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Explain functional register.
Remember
Understand
Evaluate
i
h
9
How to test a combinational circuit. Understand i
10
TU
What is sequential circuit testing? Evaluate h
11.
Explain test bench techniques. Understand i
12.
Define design verification. Remember n
13.
Define assertion verification. Remember n
14.
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(a) Concurrency
4
(b) Functional verification
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(a). Simulation versus synthesis.
5
(b). PLI
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what are the system tasks available in Verilog for making and controlling Evaluate h
6 simulation ?
(a). Module
8
(b). Test bench.
TU
12.
Give the surfaces for Verilog module and explain gate instantiations with create f
13. examples.
UNIT-II
GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING
Explain in brief built-in primitive gates that are available in Verilog HDL. Understand i
1
Explain NAND gate primitive with Verilog module. Understand i
2
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Write a Verilog code for tri-state devices. Apply k
7
Write Verilog HDL source code for a gate level description of 4 to 1 Apply k
8 multiplexer circuit. Draw the relevant logic diagram.
or
Implement Verilog HDL source code and draw the logic diagram of a 2-to-4 Evaluate b
9. decoder circuit. Give the gate level description.
12.
13.
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Explain simple latch with Verilog module.
Analyze
i
Design a D-Flip-flop with gate primitives and write its Verilog code. Analyze m
16.
20.
Design a JK flip flop using NAND gates. Create e
21.
Write a Verilog code for JK flip flop using NAND gates. Apply k
22.
Explain the design approach of a master slave flip-flop with gate primitives. Apply K
23. (OR) Design a master slave JK flip-flop using NAND gates.
Write a Verilog code for master slave JK flip flop using NAND gates. Apply K
24.
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Classify and explain strength and contention resolution. Creating K
29.
Design module to illustrate use if the wand-type net and test bench with Create M
30. stimulation results.
Draw the half adder circuits in terms of EX-OR and AND gates. Prepare the Evaluate b
or
31. half adder module and test bench in terms of and AND gate primitives.
34.
35.
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Write a Verilog HDL code for ripple-carry adder using generic specification?
Design a 4 bit full adder using gate level primitives and write its HDL code.
Apply
Create
k
Design a 1to 4 demultiplexer module by using 2 to 4 decoder, and white its Create b
36. Verilog code.
Explain about the concurrent statements in data flow level. Give one Understand I
38.
example to each one.
Explain net delay with assignment delay and effects of net delay with Understand I
39.
suitable example.
40. Explain combining assignment and net declarations with examples. Understand I
UNIT-III
BEHAVIORAL MODELING
Write a short note on, Apply k
1
(b). Intra-assignment delays.
Write the differences between begin-end and fork-blocks with examples. Apply K
2
Design up counter coding procedural assignment. Create M
3
Write up counter test bench, simulation results. Analysis B
4
Write the syntax for the following constructs and Apply k
5
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(c). wait construct.
What is the difference between an intra- statement delay and an inter- remembering M
6 statement delay? explain using an example.
or
(a). Intra-assignment delays
7
(b). Delay assignments
9
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What are the advantages of multiple always blocks? Explain with example.
Apply
Understand
M
I
10
Write a model using the behavioral modeling style to describe the behavior Apply K
11. of a JK flip- flop using an always statement.
TU
(a). Design Verilog module to identify the highest priority interrupts. Create M
12.
(b). Write test bench simulation results of above questions with explanation
Draw the flowchart for the simulation flow. OR Explain flowchart for the Understand I
16. simulation flow.
Write Verilog code using case statement for any one example. Apply k
17.
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UNIT-IV
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SWITCH LEVEL MODELING
1 Design half subtractor using CMOS switches. Create M
2 Write the Verilog code for half subtractor using CMOS switches. Apply K
3 Design code, test bench, results for CMOS switch with a single control line. Create M
4 Design CMOS flip-flop. Create M
5 Design Verilog module for CMOS flip-flop. Create M
or
Explain bi-directional gates with suitable logic diagrams and give their switch Understand I
6
level modeling
Design half -adder using CMOS switches. Create m
7
8 Write the Verilog code for half adder using CMOS switches. Apply K
9 Write about basic switch primitives. Apply K
10
11
modeling.
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Write notes on time delays with switch primitives relevant to switch level
modeling.
OR
Write notes on instantiations with strength and delays relevant to switch level
understanding
understanding
F
Define and explain the following terms relevant to Verilog HDL, Remember M
(a) Module parameters
TU
17
(b) Path delays.
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Explain cross-coupled NOR latch and ALL NAND clocked SR latch with the help Understand i
2
of neat sketches and write the Verilog cods for each of them.
Draw the block diagram of master-slave flip-flop constructed using latches analyze b
3
and write the Verilog code for the same.
4 Explain about sequential UDP with the help of an example. Understand i
Draw and explain the block diagram of master-slave flip-flop with two analyze b
ld
5 feedback blocks using assign statements. Also write the Verilog code for the
same.
Explain behavioral modeling for D-type latch and the use of non-blocking Understand i
6
assignments in latch modeling. Also with the Verilog code for each of them.
7 Write and explain the Verilog module for positive edge trigger flip-flop. Understanding h
Write a Verilog module for D flip-flop with synchronous control and Understanding h
or
8
asynchronous control. And compare the controls of both.
What is function of fork-join construct? Design a Verilog module for D flip- Evaluate h
9
flop using this construct.
10 Write a Verilog code for D flip-flop using assign and deassign statements. Understanding h
11 Define setup time. Write a Verilog code for D flip-flop setup time. Remember n
12 Define hold time. Design a Verilog module for D flip-flop with hold time. Remember n
13
14
(i)
(ii)
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Discuss about setup hold, width and period checks used in Verilog. Write a
Verilog module for D flip-flop using setup hold, width and period checks.
Design a Verilog module for the following,
8-bit transparent D-Latch
Create
n
How the memory initialization does is carried out in Verilog? Explain with the Create m
15
help of an example.
TU
What are the rules to be followed to declare and to use the bidirectional Evaluate h
16
lines?
17 Write a Verilog module for PLA. Understand i
What is functional register? Write and explain the Verilog module for basic Evaluate h
18
shift register?
19 Design and explain the Verilog module for universal shift register. Create m
Explain about shift register that uses separates combinational and Understand i
20
sequential blocks. Also write a Verilog code for the same.
21 Write a Verilog code for 4-binary up-down counter. Understanding h
Write a short notes on gray-code counter. Also design a Verilog module for Understanding h
22
the same.
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23 Explain about LFSR and design its Verilog module in structural model. Understand i
Explain MISR with the help of a neat sketch and also write the Verilog code Understand i
24
for the same.
25 Explain about FIFO Queue with the help of block diagram. Understand i
26 Write a Verilog code for FIFO Queue. Understanding h
Write a short notes on Moore 101 sequence detector. And write the Understanding h
27
Verilog code for the same.
28 Explain in brief about Mealy 101 sequence detector. Understand i
Explain how the state machine is designed for large number of input-output Understand i
29
line.
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Write a Verilog module for 4-bit ALU, also obtain its test bench and Understanding h
33
simulation results.
34 Write and explain the test bench for multi input signature register. Understanding h
or
Blooms Taxonomy Program
S.No QUESTIONS
Level Outcome
UNIT-I
INTRODUCTION TO VERILOG HDL
Using examples, explain about concurrent and procedural statement with Understand f
1 syntaxes.
3
W
Explain port declaration with an example using Verilog code.
Define the following terms relevant to Verilog HDL construct and onventions.
Understand
Understand
Remember
i
(a). Identifiers
4
(b). Strings
TU
Define the following terms relevant to Verilog HDL constructs and conventions. Remember n
(a). Keywords
5
(b). Strengths
(c). Parameters.
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Write about and differences scalars vectors in Verilog module with examples. Apply K
8
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11
(b). Operators.
Write about white space characters and variables with examples. Apply k
12
or
UNIT-II
GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING
Write a Verilog HDL code for n-bit right-to-left shift register using data flow Apply K
1
level.
Give the list of operations in data flow level and give one example for each one. Apply k
OR Comprehension
2
(a)
(b)
(c)
Unary operators
Binary operators
W
Write short notes for the following with examples.
Arithmetic operators
Write a data flow model for a 9-bit parity generator circuit. Use only two Apply k
7 assignment statements. Specify rise and fall delays as well.
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UNIT-III
BEHAVIORAL MODELING
Write the syntax for the following constructs and give one example for each Apply k
1
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Write the syntax for the following constructs and give one example for each Apply k
or
(b). While loop
5
W
What is the difference between a sequential block and a parallel block? Explain
using an example.
Evaluate h
(a) Design Verilog code of OR gate using for and disable. creating c
6
(b) Write simulation results of above question with explanation.
TU
Write syntax for ‘for while ’loop and write a Verilog code for n bit Johnson Evaluate h
7
counter.
UNIT-IV
SWITCH LEVEL MODELING
1 Explain automatic(re-entrant) tasks with example. Understand i
2 Explain and design Verilog module of timing related parameter with example. Understand i
3 Explain edge sensitive path using an example. Understand i
4 Explain overriding parameters. Understand i
5 Design Verilog module for left/right shifter. Create g
6 Design Verilog module using path delay. Create m
7 (a) Design Verilog module use of specify block to specify out rise end full time Create b
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UNIT-V
SEQUENTIAL CIRCUIT DESCRIPTION
1 Design a Verilog module for 101 moore detector and also obtain its test bench. Create m
How the simulation of test bench can be controlled? Explain with help of an Understanding h
2
example.
3 Write a test bench for moore detector for synchronized data input. Understand i
or
4 Write a test bench for moore detector to display the synchronization result. Understanding h
5 Write a test bench for moore detector to observe its states. Understanding h
Write a Verilog module for 1101 moore detector. Also obtain its test bench and Understanding h
6
simulation results.
7 Write an interactive test bench for 1101 moore detector using display tasks. Understanding h
8 Write a test bench for moore detector to control the delay. Understanding h
9
10
11
12
data.
W
Write a test bench for moore detector which makes uses of buffer to hold the
understand
Understanding
Evaluate
h
i
h
h
Explain the assert_change and assert_one_hot monitor with the help of an Understand i
13
example.
What is the use of assert_cycle_sequence and assert next? Explain using an Evaluate h
14
TU
example.
15 With the help of an example explain about the resetting sequqnce of controller. Evaluate h
Explain the following, Understand i
(i) Initial resetting
16
(ii) Assert_implication.
17 How the valid states of a machine can be checked? Explain using an example. Understand i
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