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DIGITAL DESIGN USING VERILOG HDL

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or
OBJECTIVES

Designing digital circuits at behavioral and RTL modeling of digital circuits using verilog HDL. verifying these
models, and synthesizing RTL models to standard cell libraries and FPGAs.

W
Students gain practical experience by designing, modeling, implementing and verifying several digital circuits. This
course aims provide students with the understanding of different technologies related to HDLs, constructs,
compile and execute verilog HDL programs using provided software tools. Design digital components and circuits
that are testable, reusable and synthesizable.

1. Group - A (Short Answer Questions)

Blooms Taxonomy Course


S. No QUESTION
Level Outcome
UNIT-I
TU
INTRODUCTION TO VERILOG HDL
Define verilog HDL? Remember n
1
List levels of design description in verilog HDL? Remember n
2
Describe is concurrency? Remember n
3
What is simulation and synthesis? Evaluate h
4
What is functional verification? Evaluate h
5
JN

What are system tasks? Evaluate h


6
Write short notes on programming language interface (PLI). Evaluate h
7
What is module? Evaluate h
8
What is a simulation and synthesis tool? Evaluate h
9
What is test bench? Evaluate h
10

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S. No QUESTION
Level Outcome
Define keywords and identifiers? Remember n
11.
What are white space characters? Evaluate h
12.
Define comments and numbers? Remember n
13.
Define strings and logic values? Remember n
14.

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What is a data types? And what are those? Evaluate h
15.
Define scalars and vectors? Remember n
16.
Define parameters and memory operators? Remember n
17.

or
Define system tasks? Remember n
18.
UNIT-II
GATE LEVEL MODELING AND MODELING AT DATAFLOW LEVEL
What is gate level modeling? Evaluate h
1

4
What is AND gate primitive?

Define tri-state gate?


W
What is module structure? Give the example of module structure.

What is array of instances of primitives?


Evaluate

Evaluate

Remember

Evaluate
h

h
5
Define delay? Remember n
6
TU
Define strengths and content resolution? Remember n
7
What is a net data type? Evaluate h
8
How many types of net data types? Evaluate h
9
How many tri-state gates are there in verilog? Evaluate h
10
What is continuous assignment structure? Evaluate h
11.
JN

What is assignment to vectors? Evaluate h


12.
Define operators in verilog? Remember n
13.
UNIT-III
BEHAVIORAL MODELING
1. What is behavioral modeling? Evaluate h
2. What are operations and assignments? Evaluate h
Define functional Bifurcation. Remember n
3.

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S. No QUESTION
Level Outcome
Define initial construct. Remember n
4.
Define always construct. Remember n
5.
6. Explain assignments with delays Understand i

Define wait construct Remember n


7.

ld
8 Explain multiple always blocks Understand i
9. Define blocking and non-blocking assignments Remember n

10. Explain the case statement Understand i


11. Draw a simulation flow chart Analyze i
12. Explain if and if-else construct Understand i

or
13. Explain assign and de-assign construct. Understand i
Define repeat construct Remember n
14.
15. Write the syntax for a for loop Apply k
16. Write the syntax for a while loop and forever loop Apply k
17. Explain parallel blocks Understand i
18

1.

2.
W
Explain force – release construct

Explain basic transistor switches.

Define basic switch primitive.


UNIT-IV
Understand

SWITCH LEVEL MODELING, SYSTEM TASKS FUNCTIONS AND COMPILER DIRECTIVES


Understand

Remember
i

3. Explain the operation of nmos switch. Understand i


TU
Explain the operation of pmos switch. Understand i
4.
Define resistive switches. Remember n
5.
Define cmos switch. Remember n
6.
Explain Bi-Directional gates. Understand i
7.
How to insatiate with strength and delays. Understand i
8.
9. Define system task. Remember n
JN

Define parameter. Remember n


10.
Explain parameter declaration and assignments. Understand i
11.
Define module paths. Remember n
12.
Define specify block. Remember n
13.
Define system function. Remember n
14.

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S. No QUESTION
Level Outcome
Explain $display Task. Understand i
15.
Explain file based tasks and functions. Understand i
16.
Explain compiler directives. Understand i
17.
Define hierarchical access. Remember n
18.

ld
UNIT-V
SEQUENTIAL CIRCUIT DESCRIPTION, COMPONENT TEST VERIFICATION
What are the types of sequential models? Evaluate h
1
Explain Feedback model. Understand i
2

or
Explain capacitive model. Understand i
3
Explain implicit model. Understand i
4
What are the basic memory components? Evaluate h
5

8
W
Explain functional register.

Define state machine coding.

How do you explain sequential synthesis?

What is test bench?


Understand

Remember

Understand

Evaluate
i

h
9
How to test a combinational circuit. Understand i
10
TU
What is sequential circuit testing? Evaluate h
11.
Explain test bench techniques. Understand i
12.
Define design verification. Remember n
13.
Define assertion verification. Remember n
14.

2. Group - II (Long Answer Questions)


JN

Blooms Taxonomy Program


S. No Question
Level Outcome
UNIT-I
INTRODUCTION TO VERILOG HDL
Write short note on “Verilog as HDL” Understanding h
1
Discuss Level of design description. Demonstrate e
2
Explain top-down design methodology with example. Understand i
3

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S. No Question
Level Outcome
Write short notes on, Apply k

(a) Concurrency
4
(b) Functional verification

Define the following terms relevant to Verilog HDL, Remember n

ld
(a). Simulation versus synthesis.
5
(b). PLI

(c). System tasks.

or
what are the system tasks available in Verilog for making and controlling Evaluate h
6 simulation ?

Explain about, Understand i

(a). Display tasks


7
(b). Strobe tasks W
(c). Monitor tasks with examples.

Define the following terms relevant to Verilog HDL. Remember n

(a). Module
8
(b). Test bench.
TU

Write a syntax functions and tasks with one example. Apply k


9

Write about $readmemb with example. Apply k


10.

Write value change dump file. Apply k


11.

Explain the synthesis procedure in Verilog HDL. Understand i


JN

12.
Give the surfaces for Verilog module and explain gate instantiations with create f
13. examples.

UNIT-II
GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING
Explain in brief built-in primitive gates that are available in Verilog HDL. Understand i
1
Explain NAND gate primitive with Verilog module. Understand i
2

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S. No Question
Level Outcome
Explain NOR gate primitive with Verilog module. Understand i
3
Design a module for addition of 16 bit words. Analyze M
4
Write Verilog module for addition 16 bit words. Apply k
5
What is a three-state gate and explain each type of three-state gate with Evaluate h
6 truth tables?

ld
Write a Verilog code for tri-state devices. Apply k
7
Write Verilog HDL source code for a gate level description of 4 to 1 Apply k
8 multiplexer circuit. Draw the relevant logic diagram.

or
Implement Verilog HDL source code and draw the logic diagram of a 2-to-4 Evaluate b
9. decoder circuit. Give the gate level description.

Design module and a test bench for a half-adder. Analyze m


10.
Design module and a test bench for a 4 to 1 multiples module. Analyze m
11.

12.

13.
W
Explain simple latch with Verilog module.

Design a RS-flip with NAND gates.


Understand

Analyze
i

Write a Verilog code for RS flip-flop with NAND gates. Apply k


14.
Explain clocked RS flip-flop Verilog module and test bench. Understand i
15.
TU

Design a D-Flip-flop with gate primitives and write its Verilog code. Analyze m
16.

Design a D flip flop using NAND gates. Create e


17.
Write a Verilog code for D flip flop using NAND gates. Apply k
18.
Classify delays and explain. Creating k
19.
Explain inertial and intra-assignment delays in Verilog. Understand i
JN

20.
Design a JK flip flop using NAND gates. Create e
21.
Write a Verilog code for JK flip flop using NAND gates. Apply k
22.
Explain the design approach of a master slave flip-flop with gate primitives. Apply K
23. (OR) Design a master slave JK flip-flop using NAND gates.

Write a Verilog code for master slave JK flip flop using NAND gates. Apply K
24.

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S. No Question
Level Outcome
Design a T flip flop using NAND gates. Create B
25.
Write a Verilog code for T flip flop using NAND gates. Apply K
26.
Write notes on gate delays with necessary instantiations. Apply K
27.
Explain delays with tristate gates. Apply K
28.

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Classify and explain strength and contention resolution. Creating K
29.
Design module to illustrate use if the wand-type net and test bench with Create M
30. stimulation results.

Draw the half adder circuits in terms of EX-OR and AND gates. Prepare the Evaluate b

or
31. half adder module and test bench in terms of and AND gate primitives.

Design a module and test bench for a full-adder. Create M


32.
Design a 4 X 4 multiplier circuit and write its Verilog HDL code. Create b
33.

34.

35.
W
Write a Verilog HDL code for ripple-carry adder using generic specification?

Design a 4 bit full adder using gate level primitives and write its HDL code.
Apply

Create
k

Design a 1to 4 demultiplexer module by using 2 to 4 decoder, and white its Create b
36. Verilog code.

37. Explain continuous assignment structures with examples. Understand I


TU

Explain about the concurrent statements in data flow level. Give one Understand I
38.
example to each one.
Explain net delay with assignment delay and effects of net delay with Understand I
39.
suitable example.
40. Explain combining assignment and net declarations with examples. Understand I
UNIT-III
BEHAVIORAL MODELING
Write a short note on, Apply k

(a). Functional bifurcation


JN

1
(b). Intra-assignment delays.

Write the differences between begin-end and fork-blocks with examples. Apply K
2
Design up counter coding procedural assignment. Create M
3
Write up counter test bench, simulation results. Analysis B
4
Write the syntax for the following constructs and Apply k
5

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S. No Question
Level Outcome
give one example for each relevant to behavioral

Verilog HDL modeling.

(a). initial construct,

(b). always construct

ld
(c). wait construct.

What is the difference between an intra- statement delay and an inter- remembering M
6 statement delay? explain using an example.

Write short notes on the following with examples, Apply h

or
(a). Intra-assignment delays
7
(b). Delay assignments

(c). Zero delay.

9
W
What are the advantages of multiple always blocks? Explain with example.

Write a Verilog module for a rudimentary serial transmitter module.

Explain multiple always blocks.


remembering

Apply

Understand
M

I
10
Write a model using the behavioral modeling style to describe the behavior Apply K
11. of a JK flip- flop using an always statement.
TU

(a). Design Verilog module to identify the highest priority interrupts. Create M
12.
(b). Write test bench simulation results of above questions with explanation

(a). Design module to convert angels in radians to one in degrees. Create M


13.
(b). Write Verilog code above question with explanation.
JN

Explain blocking and non-blocking statement with examples. Understand I


14.
. Write a Verilog HDL code for n-bit shift register with an enable input using Apply k
15. blocking assignments.

Draw the flowchart for the simulation flow. OR Explain flowchart for the Understand I
16. simulation flow.

Write Verilog code using case statement for any one example. Apply k
17.

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S. No Question
Level Outcome
Write the syntax for the following constructs and give one example for each Apply k
relevant to behavioral Verilog HDL modeling.

18. (a). The case statement

(b). If and if-else constructs.

UNIT-IV

ld
SWITCH LEVEL MODELING
1 Design half subtractor using CMOS switches. Create M
2 Write the Verilog code for half subtractor using CMOS switches. Apply K
3 Design code, test bench, results for CMOS switch with a single control line. Create M
4 Design CMOS flip-flop. Create M
5 Design Verilog module for CMOS flip-flop. Create M

or
Explain bi-directional gates with suitable logic diagrams and give their switch Understand I
6
level modeling
Design half -adder using CMOS switches. Create m
7
8 Write the Verilog code for half adder using CMOS switches. Apply K
9 Write about basic switch primitives. Apply K
10

11
modeling.
W
Write notes on time delays with switch primitives relevant to switch level

How strength and delays are instantiated? Explain.

modeling.
OR
Write notes on instantiations with strength and delays relevant to switch level
understanding

understanding
F

Define and explain the following terms relevant to Verilog HDL, Remember M
(a) Module parameters
TU

12 (b) File-based tasks and functions

(c) Compiler directives.

13 Explain parameter declaration and assignments. Understand I


14 Explain type declaration for parameters. Understand I
15 Explain automatic(recursive) function. Understand I
16 Explain about module paths. Understand I
Define and explain the following terms relevant to Verilog HDL, Remember M
(a) Hierarchical access
JN

17
(b) Path delays.

18 Explain $ finish task with example. Understand i


19 Explain $ random function with example. Understand i
20 Explain asymmetric sequence generator with example. Understand i
UNIT-V
SEQUENTIAL CIRCUIT DESCRIPTION
1 What are the various sequential memory storage models? Explain in detail Evaluate h

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S. No Question
Level Outcome
about each of them.

Explain cross-coupled NOR latch and ALL NAND clocked SR latch with the help Understand i
2
of neat sketches and write the Verilog cods for each of them.
Draw the block diagram of master-slave flip-flop constructed using latches analyze b
3
and write the Verilog code for the same.
4 Explain about sequential UDP with the help of an example. Understand i
Draw and explain the block diagram of master-slave flip-flop with two analyze b

ld
5 feedback blocks using assign statements. Also write the Verilog code for the
same.
Explain behavioral modeling for D-type latch and the use of non-blocking Understand i
6
assignments in latch modeling. Also with the Verilog code for each of them.
7 Write and explain the Verilog module for positive edge trigger flip-flop. Understanding h
Write a Verilog module for D flip-flop with synchronous control and Understanding h

or
8
asynchronous control. And compare the controls of both.
What is function of fork-join construct? Design a Verilog module for D flip- Evaluate h
9
flop using this construct.
10 Write a Verilog code for D flip-flop using assign and deassign statements. Understanding h
11 Define setup time. Write a Verilog code for D flip-flop setup time. Remember n
12 Define hold time. Design a Verilog module for D flip-flop with hold time. Remember n
13

14
(i)

(ii)
W
Discuss about setup hold, width and period checks used in Verilog. Write a
Verilog module for D flip-flop using setup hold, width and period checks.
Design a Verilog module for the following,
8-bit transparent D-Latch

8-bit register with tri-state output.


Remember

Create
n

How the memory initialization does is carried out in Verilog? Explain with the Create m
15
help of an example.
TU
What are the rules to be followed to declare and to use the bidirectional Evaluate h
16
lines?
17 Write a Verilog module for PLA. Understand i
What is functional register? Write and explain the Verilog module for basic Evaluate h
18
shift register?
19 Design and explain the Verilog module for universal shift register. Create m
Explain about shift register that uses separates combinational and Understand i
20
sequential blocks. Also write a Verilog code for the same.
21 Write a Verilog code for 4-binary up-down counter. Understanding h
Write a short notes on gray-code counter. Also design a Verilog module for Understanding h
22
the same.
JN

23 Explain about LFSR and design its Verilog module in structural model. Understand i
Explain MISR with the help of a neat sketch and also write the Verilog code Understand i
24
for the same.
25 Explain about FIFO Queue with the help of block diagram. Understand i
26 Write a Verilog code for FIFO Queue. Understanding h
Write a short notes on Moore 101 sequence detector. And write the Understanding h
27
Verilog code for the same.
28 Explain in brief about Mealy 101 sequence detector. Understand i
Explain how the state machine is designed for large number of input-output Understand i
29
line.

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S. No Question
Level Outcome
Write a Verilog code for moore detector using Huffman model. Also explain Understanding h
30
it.
31 Explain about ROM-based controller. Write the Verilog code for the same. Understand i
Explain about the following with the help of neat block diagram, Understand i
(a) Implementation of FPGA latch
32
(b) Implementation of FPGA flip-flop.

ld
Write a Verilog module for 4-bit ALU, also obtain its test bench and Understanding h
33
simulation results.
34 Write and explain the test bench for multi input signature register. Understanding h

3. Group - III (Analytical Questions)

or
Blooms Taxonomy Program
S.No QUESTIONS
Level Outcome
UNIT-I
INTRODUCTION TO VERILOG HDL
Using examples, explain about concurrent and procedural statement with Understand f
1 syntaxes.

3
W
Explain port declaration with an example using Verilog code.

Explain the components of a Verilog module with block diagram.

Define the following terms relevant to Verilog HDL construct and onventions.
Understand

Understand

Remember
i

(a). Identifiers
4
(b). Strings
TU

(c). Data types.

Define the following terms relevant to Verilog HDL constructs and conventions. Remember n

(a). Keywords
5
(b). Strengths

(c). Parameters.
JN

Explain about number system used in Verilog. Understand i


6
Define the following terms relevant to Verilog HDL construct and conventions. Remember n

(a). Comments, (b). Scalars and vectors.


7
(b). Scalars and vectors.

Write about and differences scalars vectors in Verilog module with examples. Apply K
8

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S.No QUESTIONS
Level Outcome
Using examples, explain about concurrent and procedural statement with comprehension f
9 syntaxes.

Explain port declaration with an example using Verilog code. Understand I


10
Define the following terms relevant to Verilog HDL constructs and conventions. Remember N

(a). Logic values

ld
11
(b). Operators.

Write about white space characters and variables with examples. Apply k
12

or
UNIT-II
GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING
Write a Verilog HDL code for n-bit right-to-left shift register using data flow Apply K
1
level.
Give the list of operations in data flow level and give one example for each one. Apply k
OR Comprehension

2
(a)

(b)

(c)
Unary operators

Binary operators
W
Write short notes for the following with examples.

Arithmetic operators

(d) Logical operators.

3 Explain about operator priority with examples. Understand i


TU
4 Explain bit widths of expressions. Understand i
Design a Verilog module for a 4 to 1 vector multiplexer or module at data flow Create m
5
level.
Give the block diagram of one digit BCD adder and write its Verilog HDL code. Create e, b
OR
6 Design a Verilog module for a BCD adder module at the data flow level.

Write a data flow model for a 9-bit parity generator circuit. Use only two Apply k
7 assignment statements. Specify rise and fall delays as well.
JN

8 Explain NMOS enhancement with conditions. Understand I


Design a Verilog module of a 4-bit bus switcher at the data flow level. Create m
9
Design Verilog module of an edge triggered flip-flop built with the latch at the Create m
10
data flow level.

UNIT-III
BEHAVIORAL MODELING
Write the syntax for the following constructs and give one example for each Apply k
1

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S.No QUESTIONS
Level Outcome
relevant to behavioral Verilog HDL modeling.

(a). assign-deassign construct

(b). repeat construct

(c). for loop.

ld
Write the syntax for the following constructs and give one example for each Apply k

relevant to behavioural Verilog HDL modeling.

(a). The disable construct


2

or
(b). While loop

(c). force-release construct.

Explain about forever loop. Apply k


3
Define while loop, write syntax with flow chart. Remembering m
4

5
W
What is the difference between a sequential block and a parallel block? Explain

using an example.
Evaluate h

(a) Design Verilog code of OR gate using for and disable. creating c
6
(b) Write simulation results of above question with explanation.
TU

Write syntax for ‘for while ’loop and write a Verilog code for n bit Johnson Evaluate h
7
counter.

Explain event construct in a module. Understand i


8
Explain stratified event queue. Understand i
9
Design Verilog module event construct for a serial data receive and test bench Create m
10 for the same.
JN

UNIT-IV
SWITCH LEVEL MODELING
1 Explain automatic(re-entrant) tasks with example. Understand i
2 Explain and design Verilog module of timing related parameter with example. Understand i
3 Explain edge sensitive path using an example. Understand i
4 Explain overriding parameters. Understand i
5 Design Verilog module for left/right shifter. Create g
6 Design Verilog module using path delay. Create m
7 (a) Design Verilog module use of specify block to specify out rise end full time Create b

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S.No QUESTIONS
Level Outcome
separation for spin delays.
(b)Write test bench and simulation for the above.
(a) Design the use of group delay with an ALU module. Create m
8
(b) Write test bench and simulation results for the above.
What do you mean by User Defined Primitives (UDP) and explain the types with understand h
9
examples
Give the syntax for function and write a program for 16-to-1 multiplexer using unserstand a
10
function.

ld
UNIT-V
SEQUENTIAL CIRCUIT DESCRIPTION
1 Design a Verilog module for 101 moore detector and also obtain its test bench. Create m
How the simulation of test bench can be controlled? Explain with help of an Understanding h
2
example.
3 Write a test bench for moore detector for synchronized data input. Understand i

or
4 Write a test bench for moore detector to display the synchronization result. Understanding h
5 Write a test bench for moore detector to observe its states. Understanding h
Write a Verilog module for 1101 moore detector. Also obtain its test bench and Understanding h
6
simulation results.
7 Write an interactive test bench for 1101 moore detector using display tasks. Understanding h
8 Write a test bench for moore detector to control the delay. Understanding h
9
10
11
12
data.
W
Write a test bench for moore detector which makes uses of buffer to hold the

Explain in detail about formal verification of a system.


Write in detail about assertion verification. Also give its benefits.
What is the function of assert_always monitor? Explain with the help of an
example.
Understanding

understand
Understanding
Evaluate
h

i
h
h

Explain the assert_change and assert_one_hot monitor with the help of an Understand i
13
example.
What is the use of assert_cycle_sequence and assert next? Explain using an Evaluate h
14
TU
example.
15 With the help of an example explain about the resetting sequqnce of controller. Evaluate h
Explain the following, Understand i
(i) Initial resetting
16
(ii) Assert_implication.

17 How the valid states of a machine can be checked? Explain using an example. Understand i
JN

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