3/27/2017

ECE6025
DrVSKB

Low Power IC Design

Low-Power Static RAM

Architectures
Class II

ECE6025/Low Power IC Design

Reduced Bit Line Voltage Swing

 Can end sense amplifier read operation as soon as
differential voltage detection is complete
 Saves fraction of DrVSKB
power needed to accomplish
read
 DV = bit line voltage swing
 Vcore = core supply voltage
 r = operation fraction that is read
 f = frequency of core operations
 Read power: ½ Ceff Vcore DV r f
 Reducing DV often fails: increases noise
sensitivity, sense amp complexity, reduces RAM
performance

ECE6025/Low Power IC Design

1
 3/27/2017

Early Word Line Termination

 Reduces bit line swings

DrVSKB

ECE6025/Low Power IC Design

Pulsed Word Lines

Enable word lines only for precise time:
 Needed to develop bit cell voltage discharge
DrVSKB
Use pulse generator:
 Gates word line and sense amplifier
 Need margin for worst-case pulse width:
 Must estimate actual RAM access time

ECE6025/Low Power IC Design

2
 3/27/2017

Self-Timed RAM Core

 Different rows have different access speeds
 Row closest to sense amps is fastest
 Columns closest to word line drivers enabled first
 Tailor pulse width to RAM access time
DrVSKB
 Use dummy column to time signal flow
 Forced to known state by shorting one internal node
 Set SR flip-flop to trigger word line
 By time dummy column sense amp generates high:
 Rest of columns have been sensed
 Dummy column sense amp resets SR flip-flop, turns off word
line
 Dummy column adds insignificant chip area/power
overhead
 Called word line kill circuit
ECE6025/Low Power IC Design

Dummy Column for Self-Timing

DrVSKB

ECE6025/Low Power IC Design

3
 3/27/2017

Bit Line Precharge Voltage

Two methods:
 Uses MOS device static load – enhancement nMOS,
depletion nMOS, standard
DrVSKB pMOS
 Use precharger transistor – no static power
consumed
» Needs more power to drive clocked precharger
Lower precharge V lowers power consumption
(less bit line voltage swing)
 Enhancement nMOS most effective:
(precharge to VCC – Vtn)
 Optimal precharge voltage: VCC / 2

ECE6025/Low Power IC Design

Problems with Lower Precharge V

Read forces SRAM internal nodes
towards bit line voltage
 Bit line precharges
DrVSKB to V
CC – Vtp
 Forces cell internal nodes low –
counteracted by weak cell pMOS
 Read may destroy old cell data
Avoid this problem –- use different
bit line voltages for read/write

ECE6025/Low Power IC Design

4
 3/27/2017

Half Swing Mode AND Gate

DrVSKB

Power due to full voltage swing =

Power due to half voltage swing =
ECE6025/Low Power IC Design

Write Driver Power Reduction

Reduce power in word line decoders and
drivers
Write line driver only drives 1 word line at a
time DrVSKB

 Small contribution to overall power

Want fast row decoding
NAND decoder only changes word line output
of 1 row
 Slower
NOR decoder changes word line output of all
but 1 row
 Faster but very bad for power
ECE6025/Low Power IC Design

5
 3/27/2017

Domino NAND Decoder

DrVSKB

ECE6025/Low Power IC Design

Improve NAND Decoder Speed

Do not decode A address lines into 1 of 2A
word lines
Split decoding process
DrVSKB
Decode A1 < A address lines:
 Use 2A1 lines to activate one of second stage
decoders
Second stage decodes A – A1 lines into
2(A – A1) word lines
 Get total of: 2A1 x 2(A – A1) = 2A lines
Recursively repeat to get a tree of
intermediate decoders – extreme is to decode
1 address line/stage
ECE6025/Low Power IC Design

6
 3/27/2017

Multistage NAND Decoder

DrVSKB

ECE6025/Low Power IC Design

NOR Decoder

DrVSKB

ECE6025/Low Power IC Design

7
 3/27/2017

Sense Amp Power Reduction

 Larger currents improve speed
Becomes significant fraction of total power
 Have a sense amplifierDrVSKB
enable signal
 Power reduction:
 Limit current by enabling sense amp for minimum needed
period
 Use self-timed RAM core
 Use sense amp that automatically cuts off after
sensing
 Sets SR flip-flop, once dummy sense amp finished, resets SR
flip-flop, turns off sense amplifier enable
 Alternative: shape tail current of amp by activating
pull-down transistors of differential amps in sequence
ECE6025/Low Power IC Design

Single- Ended Differential Sense Amplifier

DrVSKB

ECE6025/Low Power IC Design

8
 3/27/2017

Differential Sense Amp

DrVSKB

ECE6025/Low Power IC Design

Differential Charge Sense Amp

DrVSKB

ECE6025/Low Power IC Design

9
 3/27/2017

Self-Timed Sense Amp

DrVSKB

ECE6025/Low Power IC Design

Self-Latching Sense Amp

Self-latching sense amp

automatically DrVSKB
limits currents after
sense
Cross-coupled amplifying inverter
loop
Extra transistors transfer bit line
voltages to inverter loop

ECE6025/Low Power IC Design

10
 3/27/2017

Latched Sense Amp

DrVSKB

ECE6025/Low Power IC Design

Low Core Voltage from Single Supply

Memory core:
 Square law relationship for both standby and
dynamic power with respect to core voltage
DrVSKB
Commodity RAM: Have single external
supply voltage
 Step this down to get lower core voltage
Sakata method: Achieve ½ core supply
voltage
 Place 2 identical DRAM cores in series
 If average power consumption fairly constant:
» Results in potential divider
» Top and bottom core supplies: VCC / 2
ECE6025/Low Power IC Design

11
 3/27/2017

Voltage Supply Step-Down Circuits

Step-down circuit design with low DC voltage,

significant current drain is hard
 Cannot use inductors and pulse width control circuits
DrVSKB

Implement by charging N series capacitors

from VCC
 Achieve parallel capacitor connection by
opening/closing switches
 Steps voltage down to VCC / N
 Run at high rate, to get smooth supply waveform
 Need near-ideal switches and capacitors – hard to
get in CMOS

ECE6025/Low Power IC Design

Cross-coupled nMOS Sense Amplifier

DrVSKB

ECE6025/Low Power IC Design

12
 3/27/2017

4-Transistor DRAM cell

DrVSKB

ECE6025/Low Power IC Design

Three and One Transistor DRAM Cells

DrVSKB

Three Transistor DRAM Cell One Transistor DRAM Cell

ECE6025/Low Power IC Design

13
 3/27/2017

Multi-divided DRAM Architecture

DrVSKB

ECE6025/Low Power IC Design

Multi-divided bit-line Schemes

(a) Conventional and (b) Shared Amplifier

DrVSKB

ECE6025/Low Power IC Design

14
 3/27/2017

Refresh Time Increase

Busy refresh-rate β =[t(REFmax)/n]/ t(RCmin)
Iact= (mnCDVp β)/t (REFmax)
DrVSKB

Vp –bit-line precharge voltage

CD –total bit-line capacitance
m=no. of cells connected to the bit-
line
n=no. rows of the memory
t(REFmax) = maximum refresh time needed
ECE6025/Low Power IC Design

On-Chip Voltage-Down Converter Scheme

DrVSKB

ECE6025/Low Power IC Design

15
 3/27/2017

Summary
Switched capacitance reduction
techniques:
 Reduces power
DrVSKB
 Also improves performance
 Banked SRAM and DRAM Organization
 Divided word lines
 Change decoder design (useful for
DRAMS, too)
Voltage swing reduction techniques:
 Early word line cutoff
 Reduced bit line swings for SRAM/DRAM
 Self-timed RAM cores
ECE6025/Low Power IC Design

16